cpu.hh revision 9919
14120Sgblack@eecs.umich.edu/* 24120Sgblack@eecs.umich.edu * Copyright (c) 2011-2013 ARM Limited 34120Sgblack@eecs.umich.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 44120Sgblack@eecs.umich.edu * All rights reserved 54120Sgblack@eecs.umich.edu * 64120Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 74120Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 84120Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 94120Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 104120Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 114120Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 124120Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 134120Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 144120Sgblack@eecs.umich.edu * 154120Sgblack@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 164120Sgblack@eecs.umich.edu * Copyright (c) 2011 Regents of the University of California 174120Sgblack@eecs.umich.edu * All rights reserved. 184120Sgblack@eecs.umich.edu * 194120Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 204120Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 214120Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 224120Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 234120Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 244120Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 254120Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 264120Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 274120Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 284120Sgblack@eecs.umich.edu * this software without specific prior written permission. 294120Sgblack@eecs.umich.edu * 304120Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 315334Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 324120Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 334120Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 344120Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 354120Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 364120Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 374120Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 384120Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 394120Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 404120Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 414120Sgblack@eecs.umich.edu * 424120Sgblack@eecs.umich.edu * Authors: Kevin Lim 434120Sgblack@eecs.umich.edu * Korey Sewell 444120Sgblack@eecs.umich.edu * Rick Strong 454120Sgblack@eecs.umich.edu */ 464120Sgblack@eecs.umich.edu 474120Sgblack@eecs.umich.edu#ifndef __CPU_O3_CPU_HH__ 484120Sgblack@eecs.umich.edu#define __CPU_O3_CPU_HH__ 494120Sgblack@eecs.umich.edu 504120Sgblack@eecs.umich.edu#include <iostream> 514120Sgblack@eecs.umich.edu#include <list> 524120Sgblack@eecs.umich.edu#include <queue> 534120Sgblack@eecs.umich.edu#include <set> 544120Sgblack@eecs.umich.edu#include <vector> 554120Sgblack@eecs.umich.edu 564120Sgblack@eecs.umich.edu#include "arch/types.hh" 574120Sgblack@eecs.umich.edu#include "base/statistics.hh" 584120Sgblack@eecs.umich.edu#include "config/the_isa.hh" 594120Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 604120Sgblack@eecs.umich.edu#include "cpu/o3/cpu_policy.hh" 614120Sgblack@eecs.umich.edu#include "cpu/o3/scoreboard.hh" 624120Sgblack@eecs.umich.edu#include "cpu/o3/thread_state.hh" 634120Sgblack@eecs.umich.edu#include "cpu/activity.hh" 644120Sgblack@eecs.umich.edu#include "cpu/base.hh" 654120Sgblack@eecs.umich.edu#include "cpu/simple_thread.hh" 664120Sgblack@eecs.umich.edu#include "cpu/timebuf.hh" 674120Sgblack@eecs.umich.edu//#include "cpu/o3/thread_context.hh" 684120Sgblack@eecs.umich.edu#include "params/DerivO3CPU.hh" 694120Sgblack@eecs.umich.edu#include "sim/process.hh" 704120Sgblack@eecs.umich.edu 714120Sgblack@eecs.umich.edutemplate <class> 724120Sgblack@eecs.umich.educlass Checker; 734120Sgblack@eecs.umich.educlass ThreadContext; 744120Sgblack@eecs.umich.edutemplate <class> 754120Sgblack@eecs.umich.educlass O3ThreadContext; 764120Sgblack@eecs.umich.edu 774120Sgblack@eecs.umich.educlass Checkpoint; 784120Sgblack@eecs.umich.educlass MemObject; 794120Sgblack@eecs.umich.educlass Process; 804120Sgblack@eecs.umich.edu 814120Sgblack@eecs.umich.edustruct BaseCPUParams; 824120Sgblack@eecs.umich.edu 834120Sgblack@eecs.umich.educlass BaseO3CPU : public BaseCPU 844120Sgblack@eecs.umich.edu{ 854120Sgblack@eecs.umich.edu //Stuff that's pretty ISA independent will go here. 864202Sbinkertn@umich.edu public: 875069Sgblack@eecs.umich.edu BaseO3CPU(BaseCPUParams *params); 884202Sbinkertn@umich.edu 895659Sgblack@eecs.umich.edu void regStats(); 904601Sgblack@eecs.umich.edu}; 914202Sbinkertn@umich.edu 925124Sgblack@eecs.umich.edu/** 935083Sgblack@eecs.umich.edu * FullO3CPU class, has each of the stages (fetch through commit) 944679Sgblack@eecs.umich.edu * within it, as well as all of the time buffers between stages. The 955083Sgblack@eecs.umich.edu * tick() function for the CPU is defined here. 964679Sgblack@eecs.umich.edu */ 974679Sgblack@eecs.umich.edutemplate <class Impl> 984202Sbinkertn@umich.educlass FullO3CPU : public BaseO3CPU 994202Sbinkertn@umich.edu{ 1005124Sgblack@eecs.umich.edu public: 1014249Sgblack@eecs.umich.edu // Typedefs from the Impl here. 1024240Sgblack@eecs.umich.edu typedef typename Impl::CPUPol CPUPolicy; 1034202Sbinkertn@umich.edu typedef typename Impl::DynInstPtr DynInstPtr; 1044202Sbinkertn@umich.edu typedef typename Impl::O3CPU O3CPU; 1054997Sgblack@eecs.umich.edu 1065135Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> ImplState; 1074997Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> Thread; 1084997Sgblack@eecs.umich.edu 1095800Snate@binkert.org typedef typename std::list<DynInstPtr>::iterator ListIt; 1105800Snate@binkert.org 1114120Sgblack@eecs.umich.edu friend class O3ThreadContext<Impl>; 1124202Sbinkertn@umich.edu 1135800Snate@binkert.org public: 1145649Sgblack@eecs.umich.edu enum Status { 1155647Sgblack@eecs.umich.edu Running, 1165132Sgblack@eecs.umich.edu Idle, 1175132Sgblack@eecs.umich.edu Halted, 1184202Sbinkertn@umich.edu Blocked, 1195647Sgblack@eecs.umich.edu SwitchedOut 1205299Sgblack@eecs.umich.edu }; 1215245Sgblack@eecs.umich.edu 1225132Sgblack@eecs.umich.edu TheISA::TLB * itb; 1235086Sgblack@eecs.umich.edu TheISA::TLB * dtb; 1245086Sgblack@eecs.umich.edu 1254202Sbinkertn@umich.edu /** Overall CPU status. */ 1264202Sbinkertn@umich.edu Status _status; 1274120Sgblack@eecs.umich.edu 1284202Sbinkertn@umich.edu private: 1294202Sbinkertn@umich.edu 1304202Sbinkertn@umich.edu /** 1314120Sgblack@eecs.umich.edu * IcachePort class for instruction fetch. 1325069Sgblack@eecs.umich.edu */ 1335081Sgblack@eecs.umich.edu class IcachePort : public MasterPort 1345081Sgblack@eecs.umich.edu { 1355081Sgblack@eecs.umich.edu protected: 1365081Sgblack@eecs.umich.edu /** Pointer to fetch. */ 1375081Sgblack@eecs.umich.edu DefaultFetch<Impl> *fetch; 1385081Sgblack@eecs.umich.edu 1395081Sgblack@eecs.umich.edu public: 1405081Sgblack@eecs.umich.edu /** Default constructor. */ 1415081Sgblack@eecs.umich.edu IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 1425081Sgblack@eecs.umich.edu : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 1435081Sgblack@eecs.umich.edu { } 1445081Sgblack@eecs.umich.edu 1455081Sgblack@eecs.umich.edu protected: 1465081Sgblack@eecs.umich.edu 1475081Sgblack@eecs.umich.edu /** Timing version of receive. Handles setting fetch to the 1485081Sgblack@eecs.umich.edu * proper status to start fetching. */ 1495081Sgblack@eecs.umich.edu virtual bool recvTimingResp(PacketPtr pkt); 1505081Sgblack@eecs.umich.edu virtual void recvTimingSnoopReq(PacketPtr pkt) { } 1515081Sgblack@eecs.umich.edu 1525081Sgblack@eecs.umich.edu /** Handles doing a retry of a failed fetch. */ 1535081Sgblack@eecs.umich.edu virtual void recvRetry(); 1545081Sgblack@eecs.umich.edu }; 1555081Sgblack@eecs.umich.edu 1565081Sgblack@eecs.umich.edu /** 1575081Sgblack@eecs.umich.edu * DcachePort class for the load/store queue. 1585081Sgblack@eecs.umich.edu */ 1595081Sgblack@eecs.umich.edu class DcachePort : public MasterPort 1605081Sgblack@eecs.umich.edu { 1615081Sgblack@eecs.umich.edu protected: 1625081Sgblack@eecs.umich.edu 1635081Sgblack@eecs.umich.edu /** Pointer to LSQ. */ 1645081Sgblack@eecs.umich.edu LSQ<Impl> *lsq; 1655081Sgblack@eecs.umich.edu 1665081Sgblack@eecs.umich.edu public: 1675081Sgblack@eecs.umich.edu /** Default constructor. */ 1685081Sgblack@eecs.umich.edu DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 1695081Sgblack@eecs.umich.edu : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq) 1705081Sgblack@eecs.umich.edu { } 1715081Sgblack@eecs.umich.edu 1725081Sgblack@eecs.umich.edu protected: 1735081Sgblack@eecs.umich.edu 1745081Sgblack@eecs.umich.edu /** Timing version of receive. Handles writing back and 1755081Sgblack@eecs.umich.edu * completing the load or store that has returned from 1765081Sgblack@eecs.umich.edu * memory. */ 1775081Sgblack@eecs.umich.edu virtual bool recvTimingResp(PacketPtr pkt); 1785081Sgblack@eecs.umich.edu virtual void recvTimingSnoopReq(PacketPtr pkt); 1795081Sgblack@eecs.umich.edu 1805081Sgblack@eecs.umich.edu virtual void recvFunctionalSnoop(PacketPtr pkt) 1815081Sgblack@eecs.umich.edu { 1825081Sgblack@eecs.umich.edu // @todo: Is there a need for potential invalidation here? 1835081Sgblack@eecs.umich.edu } 1845081Sgblack@eecs.umich.edu 1855081Sgblack@eecs.umich.edu /** Handles doing a retry of the previous send. */ 1865081Sgblack@eecs.umich.edu virtual void recvRetry(); 1875081Sgblack@eecs.umich.edu 1885680Sgblack@eecs.umich.edu /** 1895081Sgblack@eecs.umich.edu * As this CPU requires snooping to maintain the load store queue 1905173Sgblack@eecs.umich.edu * change the behaviour from the base CPU port. 1915359Sgblack@eecs.umich.edu * 1925081Sgblack@eecs.umich.edu * @return true since we have to snoop 1935149Sgblack@eecs.umich.edu */ 1945298Sgblack@eecs.umich.edu virtual bool isSnooping() const { return true; } 1955081Sgblack@eecs.umich.edu }; 1965081Sgblack@eecs.umich.edu 1975081Sgblack@eecs.umich.edu class TickEvent : public Event 1985081Sgblack@eecs.umich.edu { 1995081Sgblack@eecs.umich.edu private: 2005081Sgblack@eecs.umich.edu /** Pointer to the CPU. */ 2015081Sgblack@eecs.umich.edu FullO3CPU<Impl> *cpu; 2025081Sgblack@eecs.umich.edu 2035081Sgblack@eecs.umich.edu public: 2045081Sgblack@eecs.umich.edu /** Constructs a tick event. */ 2055081Sgblack@eecs.umich.edu TickEvent(FullO3CPU<Impl> *c); 2065081Sgblack@eecs.umich.edu 2075081Sgblack@eecs.umich.edu /** Processes a tick event, calling tick() on the CPU. */ 2085081Sgblack@eecs.umich.edu void process(); 2095081Sgblack@eecs.umich.edu /** Returns the description of the tick event. */ 2105081Sgblack@eecs.umich.edu const char *description() const; 2115081Sgblack@eecs.umich.edu }; 2125081Sgblack@eecs.umich.edu 2135081Sgblack@eecs.umich.edu /** The tick event used for scheduling CPU ticks. */ 2145081Sgblack@eecs.umich.edu TickEvent tickEvent; 2155081Sgblack@eecs.umich.edu 2165081Sgblack@eecs.umich.edu /** Schedule tick event, regardless of its current state. */ 2175081Sgblack@eecs.umich.edu void scheduleTickEvent(Cycles delay) 2185081Sgblack@eecs.umich.edu { 2195081Sgblack@eecs.umich.edu if (tickEvent.squashed()) 2205081Sgblack@eecs.umich.edu reschedule(tickEvent, clockEdge(delay)); 2215081Sgblack@eecs.umich.edu else if (!tickEvent.scheduled()) 2225081Sgblack@eecs.umich.edu schedule(tickEvent, clockEdge(delay)); 2235081Sgblack@eecs.umich.edu } 2245081Sgblack@eecs.umich.edu 2255081Sgblack@eecs.umich.edu /** Unschedule tick event, regardless of its current state. */ 2265081Sgblack@eecs.umich.edu void unscheduleTickEvent() 2275081Sgblack@eecs.umich.edu { 2285081Sgblack@eecs.umich.edu if (tickEvent.scheduled()) 2295081Sgblack@eecs.umich.edu tickEvent.squash(); 2305081Sgblack@eecs.umich.edu } 2315081Sgblack@eecs.umich.edu 2325081Sgblack@eecs.umich.edu class ActivateThreadEvent : public Event 2335081Sgblack@eecs.umich.edu { 2345081Sgblack@eecs.umich.edu private: 2355081Sgblack@eecs.umich.edu /** Number of Thread to Activate */ 2365081Sgblack@eecs.umich.edu ThreadID tid; 2375081Sgblack@eecs.umich.edu 2385081Sgblack@eecs.umich.edu /** Pointer to the CPU. */ 2395081Sgblack@eecs.umich.edu FullO3CPU<Impl> *cpu; 2405081Sgblack@eecs.umich.edu 2415081Sgblack@eecs.umich.edu public: 2425081Sgblack@eecs.umich.edu /** Constructs the event. */ 2435081Sgblack@eecs.umich.edu ActivateThreadEvent(); 2445081Sgblack@eecs.umich.edu 2455081Sgblack@eecs.umich.edu /** Initialize Event */ 2465081Sgblack@eecs.umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 2475081Sgblack@eecs.umich.edu 2485081Sgblack@eecs.umich.edu /** Processes the event, calling activateThread() on the CPU. */ 2495081Sgblack@eecs.umich.edu void process(); 2505081Sgblack@eecs.umich.edu 2515081Sgblack@eecs.umich.edu /** Returns the description of the event. */ 2525081Sgblack@eecs.umich.edu const char *description() const; 2535081Sgblack@eecs.umich.edu }; 2545081Sgblack@eecs.umich.edu 2555081Sgblack@eecs.umich.edu /** Schedule thread to activate , regardless of its current state. */ 2565081Sgblack@eecs.umich.edu void 2575081Sgblack@eecs.umich.edu scheduleActivateThreadEvent(ThreadID tid, Cycles delay) 2585081Sgblack@eecs.umich.edu { 2595081Sgblack@eecs.umich.edu // Schedule thread to activate, regardless of its current state. 2605081Sgblack@eecs.umich.edu if (activateThreadEvent[tid].squashed()) 2615081Sgblack@eecs.umich.edu reschedule(activateThreadEvent[tid], 2625081Sgblack@eecs.umich.edu clockEdge(delay)); 2635081Sgblack@eecs.umich.edu else if (!activateThreadEvent[tid].scheduled()) { 2645081Sgblack@eecs.umich.edu Tick when = clockEdge(delay); 2655081Sgblack@eecs.umich.edu 2665081Sgblack@eecs.umich.edu // Check if the deallocateEvent is also scheduled, and make 2675081Sgblack@eecs.umich.edu // sure they do not happen at same time causing a sleep that 2685081Sgblack@eecs.umich.edu // is never woken from. 2695081Sgblack@eecs.umich.edu if (deallocateContextEvent[tid].scheduled() && 2705081Sgblack@eecs.umich.edu deallocateContextEvent[tid].when() == when) { 2715081Sgblack@eecs.umich.edu when++; 2725081Sgblack@eecs.umich.edu } 2735081Sgblack@eecs.umich.edu 2745081Sgblack@eecs.umich.edu schedule(activateThreadEvent[tid], when); 2755081Sgblack@eecs.umich.edu } 2765081Sgblack@eecs.umich.edu } 2775081Sgblack@eecs.umich.edu 2785081Sgblack@eecs.umich.edu /** Unschedule actiavte thread event, regardless of its current state. */ 2795081Sgblack@eecs.umich.edu void 2805081Sgblack@eecs.umich.edu unscheduleActivateThreadEvent(ThreadID tid) 2815081Sgblack@eecs.umich.edu { 2825081Sgblack@eecs.umich.edu if (activateThreadEvent[tid].scheduled()) 2835081Sgblack@eecs.umich.edu activateThreadEvent[tid].squash(); 2845081Sgblack@eecs.umich.edu } 2855081Sgblack@eecs.umich.edu 2865081Sgblack@eecs.umich.edu /** The tick event used for scheduling CPU ticks. */ 2875081Sgblack@eecs.umich.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 2885081Sgblack@eecs.umich.edu 2895081Sgblack@eecs.umich.edu class DeallocateContextEvent : public Event 2905081Sgblack@eecs.umich.edu { 2915081Sgblack@eecs.umich.edu private: 2925081Sgblack@eecs.umich.edu /** Number of Thread to deactivate */ 2935081Sgblack@eecs.umich.edu ThreadID tid; 2945081Sgblack@eecs.umich.edu 2955081Sgblack@eecs.umich.edu /** Should the thread be removed from the CPU? */ 2965081Sgblack@eecs.umich.edu bool remove; 2975081Sgblack@eecs.umich.edu 2985081Sgblack@eecs.umich.edu /** Pointer to the CPU. */ 2995081Sgblack@eecs.umich.edu FullO3CPU<Impl> *cpu; 3005081Sgblack@eecs.umich.edu 3015081Sgblack@eecs.umich.edu public: 3025081Sgblack@eecs.umich.edu /** Constructs the event. */ 3035081Sgblack@eecs.umich.edu DeallocateContextEvent(); 3045081Sgblack@eecs.umich.edu 3055081Sgblack@eecs.umich.edu /** Initialize Event */ 3065081Sgblack@eecs.umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 3075081Sgblack@eecs.umich.edu 3085081Sgblack@eecs.umich.edu /** Processes the event, calling activateThread() on the CPU. */ 3095081Sgblack@eecs.umich.edu void process(); 3105081Sgblack@eecs.umich.edu 3115081Sgblack@eecs.umich.edu /** Sets whether the thread should also be removed from the CPU. */ 3125081Sgblack@eecs.umich.edu void setRemove(bool _remove) { remove = _remove; } 3135081Sgblack@eecs.umich.edu 3145081Sgblack@eecs.umich.edu /** Returns the description of the event. */ 3155081Sgblack@eecs.umich.edu const char *description() const; 3165081Sgblack@eecs.umich.edu }; 3175081Sgblack@eecs.umich.edu 3185081Sgblack@eecs.umich.edu /** Schedule cpu to deallocate thread context.*/ 3195081Sgblack@eecs.umich.edu void 3205081Sgblack@eecs.umich.edu scheduleDeallocateContextEvent(ThreadID tid, bool remove, Cycles delay) 3215081Sgblack@eecs.umich.edu { 3225081Sgblack@eecs.umich.edu // Schedule thread to activate, regardless of its current state. 3235081Sgblack@eecs.umich.edu if (deallocateContextEvent[tid].squashed()) 3245081Sgblack@eecs.umich.edu reschedule(deallocateContextEvent[tid], 3255081Sgblack@eecs.umich.edu clockEdge(delay)); 3265081Sgblack@eecs.umich.edu else if (!deallocateContextEvent[tid].scheduled()) 3275081Sgblack@eecs.umich.edu schedule(deallocateContextEvent[tid], 3285081Sgblack@eecs.umich.edu clockEdge(delay)); 3295081Sgblack@eecs.umich.edu } 3305081Sgblack@eecs.umich.edu 3315081Sgblack@eecs.umich.edu /** Unschedule thread deallocation in CPU */ 3325081Sgblack@eecs.umich.edu void 3335081Sgblack@eecs.umich.edu unscheduleDeallocateContextEvent(ThreadID tid) 3345081Sgblack@eecs.umich.edu { 3355081Sgblack@eecs.umich.edu if (deallocateContextEvent[tid].scheduled()) 3365081Sgblack@eecs.umich.edu deallocateContextEvent[tid].squash(); 3375081Sgblack@eecs.umich.edu } 3385081Sgblack@eecs.umich.edu 3395081Sgblack@eecs.umich.edu /** The tick event used for scheduling CPU ticks. */ 3405081Sgblack@eecs.umich.edu DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 3415081Sgblack@eecs.umich.edu 3425081Sgblack@eecs.umich.edu /** 3435081Sgblack@eecs.umich.edu * Check if the pipeline has drained and signal the DrainManager. 3445081Sgblack@eecs.umich.edu * 3455081Sgblack@eecs.umich.edu * This method checks if a drain has been requested and if the CPU 3465081Sgblack@eecs.umich.edu * has drained successfully (i.e., there are no instructions in 3475081Sgblack@eecs.umich.edu * the pipeline). If the CPU has drained, it deschedules the tick 3485081Sgblack@eecs.umich.edu * event and signals the drain manager. 3495081Sgblack@eecs.umich.edu * 3505069Sgblack@eecs.umich.edu * @return False if a drain hasn't been requested or the CPU 3514202Sbinkertn@umich.edu * hasn't drained, true otherwise. 3524202Sbinkertn@umich.edu */ 3534202Sbinkertn@umich.edu bool tryDrain(); 3545069Sgblack@eecs.umich.edu 3555069Sgblack@eecs.umich.edu /** 3565069Sgblack@eecs.umich.edu * Perform sanity checks after a drain. 3575069Sgblack@eecs.umich.edu * 3584202Sbinkertn@umich.edu * This method is called from drain() when it has determined that 3594202Sbinkertn@umich.edu * the CPU is fully drained when gem5 is compiled with the NDEBUG 360 * macro undefined. The intention of this method is to do more 361 * extensive tests than the isDrained() method to weed out any 362 * draining bugs. 363 */ 364 void drainSanityCheck() const; 365 366 /** Check if a system is in a drained state. */ 367 bool isDrained() const; 368 369 public: 370 /** Constructs a CPU with the given parameters. */ 371 FullO3CPU(DerivO3CPUParams *params); 372 /** Destructor. */ 373 ~FullO3CPU(); 374 375 /** Registers statistics. */ 376 void regStats(); 377 378 void demapPage(Addr vaddr, uint64_t asn) 379 { 380 this->itb->demapPage(vaddr, asn); 381 this->dtb->demapPage(vaddr, asn); 382 } 383 384 void demapInstPage(Addr vaddr, uint64_t asn) 385 { 386 this->itb->demapPage(vaddr, asn); 387 } 388 389 void demapDataPage(Addr vaddr, uint64_t asn) 390 { 391 this->dtb->demapPage(vaddr, asn); 392 } 393 394 /** Ticks CPU, calling tick() on each stage, and checking the overall 395 * activity to see if the CPU should deschedule itself. 396 */ 397 void tick(); 398 399 /** Initialize the CPU */ 400 void init(); 401 402 void startup(); 403 404 /** Returns the Number of Active Threads in the CPU */ 405 int numActiveThreads() 406 { return activeThreads.size(); } 407 408 /** Add Thread to Active Threads List */ 409 void activateThread(ThreadID tid); 410 411 /** Remove Thread from Active Threads List */ 412 void deactivateThread(ThreadID tid); 413 414 /** Setup CPU to insert a thread's context */ 415 void insertThread(ThreadID tid); 416 417 /** Remove all of a thread's context from CPU */ 418 void removeThread(ThreadID tid); 419 420 /** Count the Total Instructions Committed in the CPU. */ 421 virtual Counter totalInsts() const; 422 423 /** Count the Total Ops (including micro ops) committed in the CPU. */ 424 virtual Counter totalOps() const; 425 426 /** Add Thread to Active Threads List. */ 427 void activateContext(ThreadID tid, Cycles delay); 428 429 /** Remove Thread from Active Threads List */ 430 void suspendContext(ThreadID tid); 431 432 /** Remove Thread from Active Threads List && 433 * Possibly Remove Thread Context from CPU. 434 */ 435 bool scheduleDeallocateContext(ThreadID tid, bool remove, 436 Cycles delay = Cycles(1)); 437 438 /** Remove Thread from Active Threads List && 439 * Remove Thread Context from CPU. 440 */ 441 void haltContext(ThreadID tid); 442 443 /** Activate a Thread When CPU Resources are Available. */ 444 void activateWhenReady(ThreadID tid); 445 446 /** Add or Remove a Thread Context in the CPU. */ 447 void doContextSwitch(); 448 449 /** Update The Order In Which We Process Threads. */ 450 void updateThreadPriority(); 451 452 /** Is the CPU draining? */ 453 bool isDraining() const { return getDrainState() == Drainable::Draining; } 454 455 void serializeThread(std::ostream &os, ThreadID tid); 456 457 void unserializeThread(Checkpoint *cp, const std::string §ion, 458 ThreadID tid); 459 460 public: 461 /** Executes a syscall. 462 * @todo: Determine if this needs to be virtual. 463 */ 464 void syscall(int64_t callnum, ThreadID tid); 465 466 /** Starts draining the CPU's pipeline of all instructions in 467 * order to stop all memory accesses. */ 468 unsigned int drain(DrainManager *drain_manager); 469 470 /** Resumes execution after a drain. */ 471 void drainResume(); 472 473 /** 474 * Commit has reached a safe point to drain a thread. 475 * 476 * Commit calls this method to inform the pipeline that it has 477 * reached a point where it is not executed microcode and is about 478 * to squash uncommitted instructions to fully drain the pipeline. 479 */ 480 void commitDrained(ThreadID tid); 481 482 /** Switches out this CPU. */ 483 virtual void switchOut(); 484 485 /** Takes over from another CPU. */ 486 virtual void takeOverFrom(BaseCPU *oldCPU); 487 488 void verifyMemoryMode() const; 489 490 /** Get the current instruction sequence number, and increment it. */ 491 InstSeqNum getAndIncrementInstSeq() 492 { return globalSeqNum++; } 493 494 /** Traps to handle given fault. */ 495 void trap(Fault fault, ThreadID tid, StaticInstPtr inst); 496 497 /** HW return from error interrupt. */ 498 Fault hwrei(ThreadID tid); 499 500 bool simPalCheck(int palFunc, ThreadID tid); 501 502 /** Returns the Fault for any valid interrupt. */ 503 Fault getInterrupts(); 504 505 /** Processes any an interrupt fault. */ 506 void processInterrupts(Fault interrupt); 507 508 /** Halts the CPU. */ 509 void halt() { panic("Halt not implemented!\n"); } 510 511 /** Check if this address is a valid instruction address. */ 512 bool validInstAddr(Addr addr) { return true; } 513 514 /** Check if this address is a valid data address. */ 515 bool validDataAddr(Addr addr) { return true; } 516 517 /** Register accessors. Index refers to the physical register index. */ 518 519 /** Reads a miscellaneous register. */ 520 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 521 522 /** Reads a misc. register, including any side effects the read 523 * might have as defined by the architecture. 524 */ 525 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 526 527 /** Sets a miscellaneous register. */ 528 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 529 ThreadID tid); 530 531 /** Sets a misc. register, including any side effects the write 532 * might have as defined by the architecture. 533 */ 534 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 535 ThreadID tid); 536 537 uint64_t readIntReg(int reg_idx); 538 539 TheISA::FloatReg readFloatReg(int reg_idx); 540 541 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 542 543 void setIntReg(int reg_idx, uint64_t val); 544 545 void setFloatReg(int reg_idx, TheISA::FloatReg val); 546 547 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 548 549 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 550 551 float readArchFloatReg(int reg_idx, ThreadID tid); 552 553 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 554 555 /** Architectural register accessors. Looks up in the commit 556 * rename table to obtain the true physical index of the 557 * architected register first, then accesses that physical 558 * register. 559 */ 560 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 561 562 void setArchFloatReg(int reg_idx, float val, ThreadID tid); 563 564 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 565 566 /** Sets the commit PC state of a specific thread. */ 567 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 568 569 /** Reads the commit PC state of a specific thread. */ 570 TheISA::PCState pcState(ThreadID tid); 571 572 /** Reads the commit PC of a specific thread. */ 573 Addr instAddr(ThreadID tid); 574 575 /** Reads the commit micro PC of a specific thread. */ 576 MicroPC microPC(ThreadID tid); 577 578 /** Reads the next PC of a specific thread. */ 579 Addr nextInstAddr(ThreadID tid); 580 581 /** Initiates a squash of all in-flight instructions for a given 582 * thread. The source of the squash is an external update of 583 * state through the TC. 584 */ 585 void squashFromTC(ThreadID tid); 586 587 /** Function to add instruction onto the head of the list of the 588 * instructions. Used when new instructions are fetched. 589 */ 590 ListIt addInst(DynInstPtr &inst); 591 592 /** Function to tell the CPU that an instruction has completed. */ 593 void instDone(ThreadID tid, DynInstPtr &inst); 594 595 /** Remove an instruction from the front end of the list. There's 596 * no restriction on location of the instruction. 597 */ 598 void removeFrontInst(DynInstPtr &inst); 599 600 /** Remove all instructions that are not currently in the ROB. 601 * There's also an option to not squash delay slot instructions.*/ 602 void removeInstsNotInROB(ThreadID tid); 603 604 /** Remove all instructions younger than the given sequence number. */ 605 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 606 607 /** Removes the instruction pointed to by the iterator. */ 608 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 609 610 /** Cleans up all instructions on the remove list. */ 611 void cleanUpRemovedInsts(); 612 613 /** Debug function to print all instructions on the list. */ 614 void dumpInsts(); 615 616 public: 617#ifndef NDEBUG 618 /** Count of total number of dynamic instructions in flight. */ 619 int instcount; 620#endif 621 622 /** List of all the instructions in flight. */ 623 std::list<DynInstPtr> instList; 624 625 /** List of all the instructions that will be removed at the end of this 626 * cycle. 627 */ 628 std::queue<ListIt> removeList; 629 630#ifdef DEBUG 631 /** Debug structure to keep track of the sequence numbers still in 632 * flight. 633 */ 634 std::set<InstSeqNum> snList; 635#endif 636 637 /** Records if instructions need to be removed this cycle due to 638 * being retired or squashed. 639 */ 640 bool removeInstsThisCycle; 641 642 protected: 643 /** The fetch stage. */ 644 typename CPUPolicy::Fetch fetch; 645 646 /** The decode stage. */ 647 typename CPUPolicy::Decode decode; 648 649 /** The dispatch stage. */ 650 typename CPUPolicy::Rename rename; 651 652 /** The issue/execute/writeback stages. */ 653 typename CPUPolicy::IEW iew; 654 655 /** The commit stage. */ 656 typename CPUPolicy::Commit commit; 657 658 /** The register file. */ 659 PhysRegFile regFile; 660 661 /** The free list. */ 662 typename CPUPolicy::FreeList freeList; 663 664 /** The rename map. */ 665 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 666 667 /** The commit rename map. */ 668 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 669 670 /** The re-order buffer. */ 671 typename CPUPolicy::ROB rob; 672 673 /** Active Threads List */ 674 std::list<ThreadID> activeThreads; 675 676 /** Integer Register Scoreboard */ 677 Scoreboard scoreboard; 678 679 std::vector<TheISA::ISA *> isa; 680 681 /** Instruction port. Note that it has to appear after the fetch stage. */ 682 IcachePort icachePort; 683 684 /** Data port. Note that it has to appear after the iew stages */ 685 DcachePort dcachePort; 686 687 public: 688 /** Enum to give each stage a specific index, so when calling 689 * activateStage() or deactivateStage(), they can specify which stage 690 * is being activated/deactivated. 691 */ 692 enum StageIdx { 693 FetchIdx, 694 DecodeIdx, 695 RenameIdx, 696 IEWIdx, 697 CommitIdx, 698 NumStages }; 699 700 /** Typedefs from the Impl to get the structs that each of the 701 * time buffers should use. 702 */ 703 typedef typename CPUPolicy::TimeStruct TimeStruct; 704 705 typedef typename CPUPolicy::FetchStruct FetchStruct; 706 707 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 708 709 typedef typename CPUPolicy::RenameStruct RenameStruct; 710 711 typedef typename CPUPolicy::IEWStruct IEWStruct; 712 713 /** The main time buffer to do backwards communication. */ 714 TimeBuffer<TimeStruct> timeBuffer; 715 716 /** The fetch stage's instruction queue. */ 717 TimeBuffer<FetchStruct> fetchQueue; 718 719 /** The decode stage's instruction queue. */ 720 TimeBuffer<DecodeStruct> decodeQueue; 721 722 /** The rename stage's instruction queue. */ 723 TimeBuffer<RenameStruct> renameQueue; 724 725 /** The IEW stage's instruction queue. */ 726 TimeBuffer<IEWStruct> iewQueue; 727 728 private: 729 /** The activity recorder; used to tell if the CPU has any 730 * activity remaining or if it can go to idle and deschedule 731 * itself. 732 */ 733 ActivityRecorder activityRec; 734 735 public: 736 /** Records that there was time buffer activity this cycle. */ 737 void activityThisCycle() { activityRec.activity(); } 738 739 /** Changes a stage's status to active within the activity recorder. */ 740 void activateStage(const StageIdx idx) 741 { activityRec.activateStage(idx); } 742 743 /** Changes a stage's status to inactive within the activity recorder. */ 744 void deactivateStage(const StageIdx idx) 745 { activityRec.deactivateStage(idx); } 746 747 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 748 void wakeCPU(); 749 750 virtual void wakeup(); 751 752 /** Gets a free thread id. Use if thread ids change across system. */ 753 ThreadID getFreeTid(); 754 755 public: 756 /** Returns a pointer to a thread context. */ 757 ThreadContext * 758 tcBase(ThreadID tid) 759 { 760 return thread[tid]->getTC(); 761 } 762 763 /** The global sequence number counter. */ 764 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 765 766 /** Pointer to the checker, which can dynamically verify 767 * instruction results at run time. This can be set to NULL if it 768 * is not being used. 769 */ 770 Checker<Impl> *checker; 771 772 /** Pointer to the system. */ 773 System *system; 774 775 /** DrainManager to notify when draining has completed. */ 776 DrainManager *drainManager; 777 778 /** Pointers to all of the threads in the CPU. */ 779 std::vector<Thread *> thread; 780 781 /** Is there a context switch pending? */ 782 bool contextSwitch; 783 784 /** Threads Scheduled to Enter CPU */ 785 std::list<int> cpuWaitList; 786 787 /** The cycle that the CPU was last running, used for statistics. */ 788 Cycles lastRunningCycle; 789 790 /** The cycle that the CPU was last activated by a new thread*/ 791 Tick lastActivatedCycle; 792 793 /** Mapping for system thread id to cpu id */ 794 std::map<ThreadID, unsigned> threadMap; 795 796 /** Available thread ids in the cpu*/ 797 std::vector<ThreadID> tids; 798 799 /** CPU read function, forwards read to LSQ. */ 800 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 801 uint8_t *data, int load_idx) 802 { 803 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 804 data, load_idx); 805 } 806 807 /** CPU write function, forwards write to LSQ. */ 808 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 809 uint8_t *data, int store_idx) 810 { 811 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 812 data, store_idx); 813 } 814 815 /** Used by the fetch unit to get a hold of the instruction port. */ 816 virtual MasterPort &getInstPort() { return icachePort; } 817 818 /** Get the dcache port (used to find block size for translations). */ 819 virtual MasterPort &getDataPort() { return dcachePort; } 820 821 /** Stat for total number of times the CPU is descheduled. */ 822 Stats::Scalar timesIdled; 823 /** Stat for total number of cycles the CPU spends descheduled. */ 824 Stats::Scalar idleCycles; 825 /** Stat for total number of cycles the CPU spends descheduled due to a 826 * quiesce operation or waiting for an interrupt. */ 827 Stats::Scalar quiesceCycles; 828 /** Stat for the number of committed instructions per thread. */ 829 Stats::Vector committedInsts; 830 /** Stat for the number of committed ops (including micro ops) per thread. */ 831 Stats::Vector committedOps; 832 /** Stat for the total number of committed instructions. */ 833 Stats::Scalar totalCommittedInsts; 834 /** Stat for the CPI per thread. */ 835 Stats::Formula cpi; 836 /** Stat for the total CPI. */ 837 Stats::Formula totalCpi; 838 /** Stat for the IPC per thread. */ 839 Stats::Formula ipc; 840 /** Stat for the total IPC. */ 841 Stats::Formula totalIpc; 842 843 //number of integer register file accesses 844 Stats::Scalar intRegfileReads; 845 Stats::Scalar intRegfileWrites; 846 //number of float register file accesses 847 Stats::Scalar fpRegfileReads; 848 Stats::Scalar fpRegfileWrites; 849 //number of misc 850 Stats::Scalar miscRegfileReads; 851 Stats::Scalar miscRegfileWrites; 852}; 853 854#endif // __CPU_O3_CPU_HH__ 855