cpu.hh revision 8711
11689SN/A/* 28707Sandreas.hansson@arm.com * Copyright (c) 2011 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422756Sksewell@umich.edu * Korey Sewell 437897Shestness@cs.utexas.edu * Rick Strong 441689SN/A */ 451689SN/A 462325SN/A#ifndef __CPU_O3_CPU_HH__ 472325SN/A#define __CPU_O3_CPU_HH__ 481060SN/A 491060SN/A#include <iostream> 501060SN/A#include <list> 512292SN/A#include <queue> 522292SN/A#include <set> 531681SN/A#include <vector> 541060SN/A 552980Sgblack@eecs.umich.edu#include "arch/types.hh" 561060SN/A#include "base/statistics.hh" 571858SN/A#include "config/full_system.hh" 586658Snate@binkert.org#include "config/the_isa.hh" 594598Sbinkertn@umich.edu#include "config/use_checker.hh" 601717SN/A#include "cpu/o3/comm.hh" 611717SN/A#include "cpu/o3/cpu_policy.hh" 622292SN/A#include "cpu/o3/scoreboard.hh" 632292SN/A#include "cpu/o3/thread_state.hh" 648229Snate@binkert.org#include "cpu/activity.hh" 658229Snate@binkert.org#include "cpu/base.hh" 668229Snate@binkert.org#include "cpu/simple_thread.hh" 678229Snate@binkert.org#include "cpu/timebuf.hh" 682817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 698229Snate@binkert.org#include "params/DerivO3CPU.hh" 701060SN/A#include "sim/process.hh" 711060SN/A 722316SN/Atemplate <class> 732316SN/Aclass Checker; 742680Sktlim@umich.educlass ThreadContext; 752817Sksewell@umich.edutemplate <class> 762817Sksewell@umich.educlass O3ThreadContext; 772843Sktlim@umich.edu 782843Sktlim@umich.educlass Checkpoint; 792669Sktlim@umich.educlass MemObject; 801060SN/Aclass Process; 811060SN/A 825529Snate@binkert.orgclass BaseCPUParams; 835529Snate@binkert.org 842733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 851060SN/A{ 861060SN/A //Stuff that's pretty ISA independent will go here. 871060SN/A public: 885529Snate@binkert.org BaseO3CPU(BaseCPUParams *params); 892292SN/A 902292SN/A void regStats(); 911060SN/A}; 921060SN/A 932348SN/A/** 942348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 952348SN/A * within it, as well as all of the time buffers between stages. The 962348SN/A * tick() function for the CPU is defined here. 972348SN/A */ 981060SN/Atemplate <class Impl> 992733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 1001060SN/A{ 1011060SN/A public: 1022325SN/A // Typedefs from the Impl here. 1031060SN/A typedef typename Impl::CPUPol CPUPolicy; 1041061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1054329Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 1061060SN/A 1075595Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> ImplState; 1082292SN/A typedef O3ThreadState<Impl> Thread; 1092292SN/A 1102292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1112292SN/A 1122817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1132829Sksewell@umich.edu 1141060SN/A public: 1151060SN/A enum Status { 1161060SN/A Running, 1171060SN/A Idle, 1181060SN/A Halted, 1192307SN/A Blocked, 1202307SN/A SwitchedOut 1211060SN/A }; 1221060SN/A 1236022Sgblack@eecs.umich.edu TheISA::TLB * itb; 1246022Sgblack@eecs.umich.edu TheISA::TLB * dtb; 1253781Sgblack@eecs.umich.edu 1262292SN/A /** Overall CPU status. */ 1271060SN/A Status _status; 1281060SN/A 1292829Sksewell@umich.edu /** Per-thread status in CPU, used for SMT. */ 1302829Sksewell@umich.edu Status _threadStatus[Impl::MaxThreads]; 1312829Sksewell@umich.edu 1321060SN/A private: 1338707Sandreas.hansson@arm.com 1348707Sandreas.hansson@arm.com /** 1358707Sandreas.hansson@arm.com * IcachePort class for instruction fetch. 1368707Sandreas.hansson@arm.com */ 1378707Sandreas.hansson@arm.com class IcachePort : public CpuPort 1388707Sandreas.hansson@arm.com { 1398707Sandreas.hansson@arm.com protected: 1408707Sandreas.hansson@arm.com /** Pointer to fetch. */ 1418707Sandreas.hansson@arm.com DefaultFetch<Impl> *fetch; 1428707Sandreas.hansson@arm.com 1438707Sandreas.hansson@arm.com public: 1448707Sandreas.hansson@arm.com /** Default constructor. */ 1458707Sandreas.hansson@arm.com IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 1468707Sandreas.hansson@arm.com : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch) 1478707Sandreas.hansson@arm.com { } 1488707Sandreas.hansson@arm.com 1498707Sandreas.hansson@arm.com protected: 1508707Sandreas.hansson@arm.com 1518707Sandreas.hansson@arm.com /** Timing version of receive. Handles setting fetch to the 1528707Sandreas.hansson@arm.com * proper status to start fetching. */ 1538707Sandreas.hansson@arm.com virtual bool recvTiming(PacketPtr pkt); 1548707Sandreas.hansson@arm.com 1558707Sandreas.hansson@arm.com /** Handles doing a retry of a failed fetch. */ 1568707Sandreas.hansson@arm.com virtual void recvRetry(); 1578707Sandreas.hansson@arm.com }; 1588707Sandreas.hansson@arm.com 1598707Sandreas.hansson@arm.com /** 1608707Sandreas.hansson@arm.com * DcachePort class for the load/store queue. 1618707Sandreas.hansson@arm.com */ 1628707Sandreas.hansson@arm.com class DcachePort : public CpuPort 1638707Sandreas.hansson@arm.com { 1648707Sandreas.hansson@arm.com protected: 1658707Sandreas.hansson@arm.com 1668707Sandreas.hansson@arm.com /** Pointer to LSQ. */ 1678707Sandreas.hansson@arm.com LSQ<Impl> *lsq; 1688707Sandreas.hansson@arm.com 1698707Sandreas.hansson@arm.com public: 1708707Sandreas.hansson@arm.com /** Default constructor. */ 1718707Sandreas.hansson@arm.com DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 1728707Sandreas.hansson@arm.com : CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq) 1738707Sandreas.hansson@arm.com { } 1748707Sandreas.hansson@arm.com 1758707Sandreas.hansson@arm.com protected: 1768707Sandreas.hansson@arm.com 1778707Sandreas.hansson@arm.com /** Timing version of receive. Handles writing back and 1788707Sandreas.hansson@arm.com * completing the load or store that has returned from 1798707Sandreas.hansson@arm.com * memory. */ 1808707Sandreas.hansson@arm.com virtual bool recvTiming(PacketPtr pkt); 1818707Sandreas.hansson@arm.com 1828707Sandreas.hansson@arm.com /** Handles doing a retry of the previous send. */ 1838707Sandreas.hansson@arm.com virtual void recvRetry(); 1848707Sandreas.hansson@arm.com 1858707Sandreas.hansson@arm.com /** 1868707Sandreas.hansson@arm.com * As this CPU requires snooping to maintain the load store queue 1878707Sandreas.hansson@arm.com * change the behaviour from the base CPU port. 1888707Sandreas.hansson@arm.com * 1898711Sandreas.hansson@arm.com * @return true since we have to snoop 1908707Sandreas.hansson@arm.com */ 1918711Sandreas.hansson@arm.com virtual bool isSnooping() 1928711Sandreas.hansson@arm.com { return true; } 1938707Sandreas.hansson@arm.com }; 1948707Sandreas.hansson@arm.com 1951060SN/A class TickEvent : public Event 1961060SN/A { 1971060SN/A private: 1982292SN/A /** Pointer to the CPU. */ 1991755SN/A FullO3CPU<Impl> *cpu; 2001060SN/A 2011060SN/A public: 2022292SN/A /** Constructs a tick event. */ 2031755SN/A TickEvent(FullO3CPU<Impl> *c); 2042292SN/A 2052292SN/A /** Processes a tick event, calling tick() on the CPU. */ 2061060SN/A void process(); 2072292SN/A /** Returns the description of the tick event. */ 2085336Shines@cs.fsu.edu const char *description() const; 2091060SN/A }; 2101060SN/A 2112292SN/A /** The tick event used for scheduling CPU ticks. */ 2121060SN/A TickEvent tickEvent; 2131060SN/A 2142292SN/A /** Schedule tick event, regardless of its current state. */ 2151060SN/A void scheduleTickEvent(int delay) 2161060SN/A { 2171060SN/A if (tickEvent.squashed()) 2187823Ssteve.reinhardt@amd.com reschedule(tickEvent, nextCycle(curTick() + ticks(delay))); 2191060SN/A else if (!tickEvent.scheduled()) 2207823Ssteve.reinhardt@amd.com schedule(tickEvent, nextCycle(curTick() + ticks(delay))); 2211060SN/A } 2221060SN/A 2232292SN/A /** Unschedule tick event, regardless of its current state. */ 2241060SN/A void unscheduleTickEvent() 2251060SN/A { 2261060SN/A if (tickEvent.scheduled()) 2271060SN/A tickEvent.squash(); 2281060SN/A } 2291060SN/A 2302829Sksewell@umich.edu class ActivateThreadEvent : public Event 2312829Sksewell@umich.edu { 2322829Sksewell@umich.edu private: 2332829Sksewell@umich.edu /** Number of Thread to Activate */ 2346221Snate@binkert.org ThreadID tid; 2352829Sksewell@umich.edu 2362829Sksewell@umich.edu /** Pointer to the CPU. */ 2372829Sksewell@umich.edu FullO3CPU<Impl> *cpu; 2382829Sksewell@umich.edu 2392829Sksewell@umich.edu public: 2402829Sksewell@umich.edu /** Constructs the event. */ 2412829Sksewell@umich.edu ActivateThreadEvent(); 2422829Sksewell@umich.edu 2432829Sksewell@umich.edu /** Initialize Event */ 2442829Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 2452829Sksewell@umich.edu 2462829Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 2472829Sksewell@umich.edu void process(); 2482829Sksewell@umich.edu 2492829Sksewell@umich.edu /** Returns the description of the event. */ 2505336Shines@cs.fsu.edu const char *description() const; 2512829Sksewell@umich.edu }; 2522829Sksewell@umich.edu 2532829Sksewell@umich.edu /** Schedule thread to activate , regardless of its current state. */ 2546221Snate@binkert.org void 2556221Snate@binkert.org scheduleActivateThreadEvent(ThreadID tid, int delay) 2562829Sksewell@umich.edu { 2572829Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 2582829Sksewell@umich.edu if (activateThreadEvent[tid].squashed()) 2595606Snate@binkert.org reschedule(activateThreadEvent[tid], 2607823Ssteve.reinhardt@amd.com nextCycle(curTick() + ticks(delay))); 2618518Sgeoffrey.blake@arm.com else if (!activateThreadEvent[tid].scheduled()) { 2628518Sgeoffrey.blake@arm.com Tick when = nextCycle(curTick() + ticks(delay)); 2638518Sgeoffrey.blake@arm.com 2648518Sgeoffrey.blake@arm.com // Check if the deallocateEvent is also scheduled, and make 2658518Sgeoffrey.blake@arm.com // sure they do not happen at same time causing a sleep that 2668518Sgeoffrey.blake@arm.com // is never woken from. 2678518Sgeoffrey.blake@arm.com if (deallocateContextEvent[tid].scheduled() && 2688518Sgeoffrey.blake@arm.com deallocateContextEvent[tid].when() == when) { 2698518Sgeoffrey.blake@arm.com when++; 2708518Sgeoffrey.blake@arm.com } 2718518Sgeoffrey.blake@arm.com 2728518Sgeoffrey.blake@arm.com schedule(activateThreadEvent[tid], when); 2738518Sgeoffrey.blake@arm.com } 2742829Sksewell@umich.edu } 2752829Sksewell@umich.edu 2762829Sksewell@umich.edu /** Unschedule actiavte thread event, regardless of its current state. */ 2776221Snate@binkert.org void 2786221Snate@binkert.org unscheduleActivateThreadEvent(ThreadID tid) 2792829Sksewell@umich.edu { 2802829Sksewell@umich.edu if (activateThreadEvent[tid].scheduled()) 2812829Sksewell@umich.edu activateThreadEvent[tid].squash(); 2822829Sksewell@umich.edu } 2832829Sksewell@umich.edu 2842829Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2852829Sksewell@umich.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 2862829Sksewell@umich.edu 2872875Sksewell@umich.edu class DeallocateContextEvent : public Event 2882875Sksewell@umich.edu { 2892875Sksewell@umich.edu private: 2903221Sktlim@umich.edu /** Number of Thread to deactivate */ 2916221Snate@binkert.org ThreadID tid; 2922875Sksewell@umich.edu 2933221Sktlim@umich.edu /** Should the thread be removed from the CPU? */ 2943221Sktlim@umich.edu bool remove; 2953221Sktlim@umich.edu 2962875Sksewell@umich.edu /** Pointer to the CPU. */ 2972875Sksewell@umich.edu FullO3CPU<Impl> *cpu; 2982875Sksewell@umich.edu 2992875Sksewell@umich.edu public: 3002875Sksewell@umich.edu /** Constructs the event. */ 3012875Sksewell@umich.edu DeallocateContextEvent(); 3022875Sksewell@umich.edu 3032875Sksewell@umich.edu /** Initialize Event */ 3042875Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 3052875Sksewell@umich.edu 3062875Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 3072875Sksewell@umich.edu void process(); 3082875Sksewell@umich.edu 3093221Sktlim@umich.edu /** Sets whether the thread should also be removed from the CPU. */ 3103221Sktlim@umich.edu void setRemove(bool _remove) { remove = _remove; } 3113221Sktlim@umich.edu 3122875Sksewell@umich.edu /** Returns the description of the event. */ 3135336Shines@cs.fsu.edu const char *description() const; 3142875Sksewell@umich.edu }; 3152875Sksewell@umich.edu 3162875Sksewell@umich.edu /** Schedule cpu to deallocate thread context.*/ 3176221Snate@binkert.org void 3186221Snate@binkert.org scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay) 3192875Sksewell@umich.edu { 3202875Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 3212875Sksewell@umich.edu if (deallocateContextEvent[tid].squashed()) 3225606Snate@binkert.org reschedule(deallocateContextEvent[tid], 3237823Ssteve.reinhardt@amd.com nextCycle(curTick() + ticks(delay))); 3242875Sksewell@umich.edu else if (!deallocateContextEvent[tid].scheduled()) 3255606Snate@binkert.org schedule(deallocateContextEvent[tid], 3267823Ssteve.reinhardt@amd.com nextCycle(curTick() + ticks(delay))); 3272875Sksewell@umich.edu } 3282875Sksewell@umich.edu 3292875Sksewell@umich.edu /** Unschedule thread deallocation in CPU */ 3306221Snate@binkert.org void 3316221Snate@binkert.org unscheduleDeallocateContextEvent(ThreadID tid) 3322875Sksewell@umich.edu { 3332875Sksewell@umich.edu if (deallocateContextEvent[tid].scheduled()) 3342875Sksewell@umich.edu deallocateContextEvent[tid].squash(); 3352875Sksewell@umich.edu } 3362875Sksewell@umich.edu 3372875Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 3382875Sksewell@umich.edu DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 3392875Sksewell@umich.edu 3401060SN/A public: 3412292SN/A /** Constructs a CPU with the given parameters. */ 3425595Sgblack@eecs.umich.edu FullO3CPU(DerivO3CPUParams *params); 3432292SN/A /** Destructor. */ 3441755SN/A ~FullO3CPU(); 3451060SN/A 3462292SN/A /** Registers statistics. */ 3475595Sgblack@eecs.umich.edu void regStats(); 3481684SN/A 3495358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3505358Sgblack@eecs.umich.edu { 3515358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3525358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3535358Sgblack@eecs.umich.edu } 3545358Sgblack@eecs.umich.edu 3555358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3565358Sgblack@eecs.umich.edu { 3575358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3585358Sgblack@eecs.umich.edu } 3595358Sgblack@eecs.umich.edu 3605358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3615358Sgblack@eecs.umich.edu { 3625358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3635358Sgblack@eecs.umich.edu } 3645358Sgblack@eecs.umich.edu 3652871Sktlim@umich.edu /** Returns a specific port. */ 3662871Sktlim@umich.edu Port *getPort(const std::string &if_name, int idx); 3672871Sktlim@umich.edu 3682292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 3692292SN/A * activity to see if the CPU should deschedule itself. 3702292SN/A */ 3711684SN/A void tick(); 3721684SN/A 3732292SN/A /** Initialize the CPU */ 3741060SN/A void init(); 3751060SN/A 3762834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 3772834Sksewell@umich.edu int numActiveThreads() 3782834Sksewell@umich.edu { return activeThreads.size(); } 3792834Sksewell@umich.edu 3802829Sksewell@umich.edu /** Add Thread to Active Threads List */ 3816221Snate@binkert.org void activateThread(ThreadID tid); 3822875Sksewell@umich.edu 3832875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 3846221Snate@binkert.org void deactivateThread(ThreadID tid); 3852829Sksewell@umich.edu 3862292SN/A /** Setup CPU to insert a thread's context */ 3876221Snate@binkert.org void insertThread(ThreadID tid); 3881060SN/A 3892292SN/A /** Remove all of a thread's context from CPU */ 3906221Snate@binkert.org void removeThread(ThreadID tid); 3912292SN/A 3922292SN/A /** Count the Total Instructions Committed in the CPU. */ 3936221Snate@binkert.org virtual Counter totalInstructions() const; 3942292SN/A 3952292SN/A /** Add Thread to Active Threads List. */ 3966221Snate@binkert.org void activateContext(ThreadID tid, int delay); 3972292SN/A 3982292SN/A /** Remove Thread from Active Threads List */ 3996221Snate@binkert.org void suspendContext(ThreadID tid); 4002292SN/A 4012292SN/A /** Remove Thread from Active Threads List && 4023221Sktlim@umich.edu * Possibly Remove Thread Context from CPU. 4032292SN/A */ 4046221Snate@binkert.org bool deallocateContext(ThreadID tid, bool remove, int delay = 1); 4052292SN/A 4062292SN/A /** Remove Thread from Active Threads List && 4072292SN/A * Remove Thread Context from CPU. 4082292SN/A */ 4096221Snate@binkert.org void haltContext(ThreadID tid); 4102292SN/A 4112292SN/A /** Activate a Thread When CPU Resources are Available. */ 4126221Snate@binkert.org void activateWhenReady(ThreadID tid); 4132292SN/A 4142292SN/A /** Add or Remove a Thread Context in the CPU. */ 4152292SN/A void doContextSwitch(); 4162292SN/A 4172292SN/A /** Update The Order In Which We Process Threads. */ 4182292SN/A void updateThreadPriority(); 4192292SN/A 4202864Sktlim@umich.edu /** Serialize state. */ 4212864Sktlim@umich.edu virtual void serialize(std::ostream &os); 4222864Sktlim@umich.edu 4232864Sktlim@umich.edu /** Unserialize from a checkpoint. */ 4242864Sktlim@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 4252864Sktlim@umich.edu 4262864Sktlim@umich.edu public: 4275595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 4285595Sgblack@eecs.umich.edu /** Executes a syscall. 4295595Sgblack@eecs.umich.edu * @todo: Determine if this needs to be virtual. 4302292SN/A */ 4316221Snate@binkert.org void syscall(int64_t callnum, ThreadID tid); 4325595Sgblack@eecs.umich.edu#endif 4332292SN/A 4342843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 4352843Sktlim@umich.edu * order to stop all memory accesses. */ 4362905Sktlim@umich.edu virtual unsigned int drain(Event *drain_event); 4372843Sktlim@umich.edu 4382843Sktlim@umich.edu /** Resumes execution after a drain. */ 4392843Sktlim@umich.edu virtual void resume(); 4402292SN/A 4412348SN/A /** Signals to this CPU that a stage has completed switching out. */ 4422843Sktlim@umich.edu void signalDrained(); 4432843Sktlim@umich.edu 4442843Sktlim@umich.edu /** Switches out this CPU. */ 4452843Sktlim@umich.edu virtual void switchOut(); 4462316SN/A 4472348SN/A /** Takes over from another CPU. */ 4482843Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *oldCPU); 4491060SN/A 4501060SN/A /** Get the current instruction sequence number, and increment it. */ 4512316SN/A InstSeqNum getAndIncrementInstSeq() 4522316SN/A { return globalSeqNum++; } 4531060SN/A 4545595Sgblack@eecs.umich.edu /** Traps to handle given fault. */ 4557684Sgblack@eecs.umich.edu void trap(Fault fault, ThreadID tid, StaticInstPtr inst); 4565595Sgblack@eecs.umich.edu 4571858SN/A#if FULL_SYSTEM 4585702Ssaidi@eecs.umich.edu /** HW return from error interrupt. */ 4596221Snate@binkert.org Fault hwrei(ThreadID tid); 4605702Ssaidi@eecs.umich.edu 4616221Snate@binkert.org bool simPalCheck(int palFunc, ThreadID tid); 4625702Ssaidi@eecs.umich.edu 4635595Sgblack@eecs.umich.edu /** Returns the Fault for any valid interrupt. */ 4645595Sgblack@eecs.umich.edu Fault getInterrupts(); 4655595Sgblack@eecs.umich.edu 4665595Sgblack@eecs.umich.edu /** Processes any an interrupt fault. */ 4675595Sgblack@eecs.umich.edu void processInterrupts(Fault interrupt); 4685595Sgblack@eecs.umich.edu 4695595Sgblack@eecs.umich.edu /** Halts the CPU. */ 4705595Sgblack@eecs.umich.edu void halt() { panic("Halt not implemented!\n"); } 4715595Sgblack@eecs.umich.edu 4721060SN/A /** Check if this address is a valid instruction address. */ 4731060SN/A bool validInstAddr(Addr addr) { return true; } 4741060SN/A 4751060SN/A /** Check if this address is a valid data address. */ 4761060SN/A bool validDataAddr(Addr addr) { return true; } 4771060SN/A#endif 4781060SN/A 4792348SN/A /** Register accessors. Index refers to the physical register index. */ 4805595Sgblack@eecs.umich.edu 4815595Sgblack@eecs.umich.edu /** Reads a miscellaneous register. */ 4826221Snate@binkert.org TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 4835595Sgblack@eecs.umich.edu 4845595Sgblack@eecs.umich.edu /** Reads a misc. register, including any side effects the read 4855595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4865595Sgblack@eecs.umich.edu */ 4876221Snate@binkert.org TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 4885595Sgblack@eecs.umich.edu 4895595Sgblack@eecs.umich.edu /** Sets a miscellaneous register. */ 4906221Snate@binkert.org void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 4916221Snate@binkert.org ThreadID tid); 4925595Sgblack@eecs.umich.edu 4935595Sgblack@eecs.umich.edu /** Sets a misc. register, including any side effects the write 4945595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4955595Sgblack@eecs.umich.edu */ 4965595Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 4976221Snate@binkert.org ThreadID tid); 4985595Sgblack@eecs.umich.edu 4991060SN/A uint64_t readIntReg(int reg_idx); 5001060SN/A 5013781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx); 5021060SN/A 5033781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx); 5042455SN/A 5051060SN/A void setIntReg(int reg_idx, uint64_t val); 5061060SN/A 5073781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val); 5081060SN/A 5093781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 5102455SN/A 5116221Snate@binkert.org uint64_t readArchIntReg(int reg_idx, ThreadID tid); 5121060SN/A 5136314Sgblack@eecs.umich.edu float readArchFloatReg(int reg_idx, ThreadID tid); 5142292SN/A 5156221Snate@binkert.org uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 5162292SN/A 5172348SN/A /** Architectural register accessors. Looks up in the commit 5182348SN/A * rename table to obtain the true physical index of the 5192348SN/A * architected register first, then accesses that physical 5202348SN/A * register. 5212348SN/A */ 5226221Snate@binkert.org void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 5232292SN/A 5246314Sgblack@eecs.umich.edu void setArchFloatReg(int reg_idx, float val, ThreadID tid); 5252292SN/A 5266221Snate@binkert.org void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 5272292SN/A 5287720Sgblack@eecs.umich.edu /** Sets the commit PC state of a specific thread. */ 5297720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &newPCState, ThreadID tid); 5307720Sgblack@eecs.umich.edu 5317720Sgblack@eecs.umich.edu /** Reads the commit PC state of a specific thread. */ 5327720Sgblack@eecs.umich.edu TheISA::PCState pcState(ThreadID tid); 5337720Sgblack@eecs.umich.edu 5342348SN/A /** Reads the commit PC of a specific thread. */ 5357720Sgblack@eecs.umich.edu Addr instAddr(ThreadID tid); 5362292SN/A 5374636Sgblack@eecs.umich.edu /** Reads the commit micro PC of a specific thread. */ 5387720Sgblack@eecs.umich.edu MicroPC microPC(ThreadID tid); 5394636Sgblack@eecs.umich.edu 5402348SN/A /** Reads the next PC of a specific thread. */ 5417720Sgblack@eecs.umich.edu Addr nextInstAddr(ThreadID tid); 5422756Sksewell@umich.edu 5435595Sgblack@eecs.umich.edu /** Initiates a squash of all in-flight instructions for a given 5445595Sgblack@eecs.umich.edu * thread. The source of the squash is an external update of 5455595Sgblack@eecs.umich.edu * state through the TC. 5465595Sgblack@eecs.umich.edu */ 5476221Snate@binkert.org void squashFromTC(ThreadID tid); 5485595Sgblack@eecs.umich.edu 5491060SN/A /** Function to add instruction onto the head of the list of the 5501060SN/A * instructions. Used when new instructions are fetched. 5511060SN/A */ 5522292SN/A ListIt addInst(DynInstPtr &inst); 5531060SN/A 5541060SN/A /** Function to tell the CPU that an instruction has completed. */ 5556221Snate@binkert.org void instDone(ThreadID tid); 5561060SN/A 5572325SN/A /** Remove an instruction from the front end of the list. There's 5582325SN/A * no restriction on location of the instruction. 5591060SN/A */ 5601061SN/A void removeFrontInst(DynInstPtr &inst); 5611060SN/A 5622935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 5632935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 5646221Snate@binkert.org void removeInstsNotInROB(ThreadID tid); 5651060SN/A 5661062SN/A /** Remove all instructions younger than the given sequence number. */ 5676221Snate@binkert.org void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 5682292SN/A 5692348SN/A /** Removes the instruction pointed to by the iterator. */ 5706221Snate@binkert.org inline void squashInstIt(const ListIt &instIt, ThreadID tid); 5712292SN/A 5722348SN/A /** Cleans up all instructions on the remove list. */ 5732292SN/A void cleanUpRemovedInsts(); 5741062SN/A 5752348SN/A /** Debug function to print all instructions on the list. */ 5761060SN/A void dumpInsts(); 5771060SN/A 5781060SN/A public: 5795737Scws3k@cs.virginia.edu#ifndef NDEBUG 5805737Scws3k@cs.virginia.edu /** Count of total number of dynamic instructions in flight. */ 5815737Scws3k@cs.virginia.edu int instcount; 5825737Scws3k@cs.virginia.edu#endif 5835737Scws3k@cs.virginia.edu 5841060SN/A /** List of all the instructions in flight. */ 5852292SN/A std::list<DynInstPtr> instList; 5861060SN/A 5872292SN/A /** List of all the instructions that will be removed at the end of this 5882292SN/A * cycle. 5892292SN/A */ 5902292SN/A std::queue<ListIt> removeList; 5912292SN/A 5922325SN/A#ifdef DEBUG 5932348SN/A /** Debug structure to keep track of the sequence numbers still in 5942348SN/A * flight. 5952348SN/A */ 5962292SN/A std::set<InstSeqNum> snList; 5972325SN/A#endif 5982292SN/A 5992325SN/A /** Records if instructions need to be removed this cycle due to 6002325SN/A * being retired or squashed. 6012292SN/A */ 6022292SN/A bool removeInstsThisCycle; 6032292SN/A 6041060SN/A protected: 6051060SN/A /** The fetch stage. */ 6061060SN/A typename CPUPolicy::Fetch fetch; 6071060SN/A 6081060SN/A /** The decode stage. */ 6091060SN/A typename CPUPolicy::Decode decode; 6101060SN/A 6111060SN/A /** The dispatch stage. */ 6121060SN/A typename CPUPolicy::Rename rename; 6131060SN/A 6141060SN/A /** The issue/execute/writeback stages. */ 6151060SN/A typename CPUPolicy::IEW iew; 6161060SN/A 6171060SN/A /** The commit stage. */ 6181060SN/A typename CPUPolicy::Commit commit; 6191060SN/A 6201060SN/A /** The register file. */ 6211060SN/A typename CPUPolicy::RegFile regFile; 6221060SN/A 6231060SN/A /** The free list. */ 6241060SN/A typename CPUPolicy::FreeList freeList; 6251060SN/A 6261060SN/A /** The rename map. */ 6272292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 6282292SN/A 6292292SN/A /** The commit rename map. */ 6302292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 6311060SN/A 6321060SN/A /** The re-order buffer. */ 6331060SN/A typename CPUPolicy::ROB rob; 6341060SN/A 6352292SN/A /** Active Threads List */ 6366221Snate@binkert.org std::list<ThreadID> activeThreads; 6372292SN/A 6382292SN/A /** Integer Register Scoreboard */ 6392292SN/A Scoreboard scoreboard; 6402292SN/A 6416313Sgblack@eecs.umich.edu TheISA::ISA isa[Impl::MaxThreads]; 6426313Sgblack@eecs.umich.edu 6438707Sandreas.hansson@arm.com /** Instruction port. Note that it has to appear after the fetch stage. */ 6448707Sandreas.hansson@arm.com IcachePort icachePort; 6458707Sandreas.hansson@arm.com 6468707Sandreas.hansson@arm.com /** Data port. Note that it has to appear after the iew stages */ 6478707Sandreas.hansson@arm.com DcachePort dcachePort; 6488707Sandreas.hansson@arm.com 6491060SN/A public: 6502292SN/A /** Enum to give each stage a specific index, so when calling 6512292SN/A * activateStage() or deactivateStage(), they can specify which stage 6522292SN/A * is being activated/deactivated. 6532292SN/A */ 6542292SN/A enum StageIdx { 6552292SN/A FetchIdx, 6562292SN/A DecodeIdx, 6572292SN/A RenameIdx, 6582292SN/A IEWIdx, 6592292SN/A CommitIdx, 6602292SN/A NumStages }; 6612292SN/A 6621060SN/A /** Typedefs from the Impl to get the structs that each of the 6631060SN/A * time buffers should use. 6641060SN/A */ 6651061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 6661060SN/A 6671061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 6681060SN/A 6691061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 6701060SN/A 6711061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 6721060SN/A 6731061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 6741060SN/A 6751060SN/A /** The main time buffer to do backwards communication. */ 6761060SN/A TimeBuffer<TimeStruct> timeBuffer; 6771060SN/A 6781060SN/A /** The fetch stage's instruction queue. */ 6791060SN/A TimeBuffer<FetchStruct> fetchQueue; 6801060SN/A 6811060SN/A /** The decode stage's instruction queue. */ 6821060SN/A TimeBuffer<DecodeStruct> decodeQueue; 6831060SN/A 6841060SN/A /** The rename stage's instruction queue. */ 6851060SN/A TimeBuffer<RenameStruct> renameQueue; 6861060SN/A 6871060SN/A /** The IEW stage's instruction queue. */ 6881060SN/A TimeBuffer<IEWStruct> iewQueue; 6891060SN/A 6902348SN/A private: 6912348SN/A /** The activity recorder; used to tell if the CPU has any 6922348SN/A * activity remaining or if it can go to idle and deschedule 6932348SN/A * itself. 6942348SN/A */ 6952325SN/A ActivityRecorder activityRec; 6961060SN/A 6972348SN/A public: 6982348SN/A /** Records that there was time buffer activity this cycle. */ 6992325SN/A void activityThisCycle() { activityRec.activity(); } 7002292SN/A 7012348SN/A /** Changes a stage's status to active within the activity recorder. */ 7022325SN/A void activateStage(const StageIdx idx) 7032325SN/A { activityRec.activateStage(idx); } 7042292SN/A 7052348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 7062325SN/A void deactivateStage(const StageIdx idx) 7072325SN/A { activityRec.deactivateStage(idx); } 7082292SN/A 7092292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 7102292SN/A void wakeCPU(); 7112260SN/A 7125807Snate@binkert.org#if FULL_SYSTEM 7135807Snate@binkert.org virtual void wakeup(); 7145807Snate@binkert.org#endif 7155807Snate@binkert.org 7162292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 7176221Snate@binkert.org ThreadID getFreeTid(); 7182292SN/A 7192292SN/A public: 7202680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 7216221Snate@binkert.org ThreadContext * 7226221Snate@binkert.org tcBase(ThreadID tid) 7231681SN/A { 7242680Sktlim@umich.edu return thread[tid]->getTC(); 7252190SN/A } 7262190SN/A 7272292SN/A /** The global sequence number counter. */ 7283093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 7291060SN/A 7304598Sbinkertn@umich.edu#if USE_CHECKER 7312348SN/A /** Pointer to the checker, which can dynamically verify 7322348SN/A * instruction results at run time. This can be set to NULL if it 7332348SN/A * is not being used. 7342348SN/A */ 7352316SN/A Checker<DynInstPtr> *checker; 7364598Sbinkertn@umich.edu#endif 7372316SN/A 7382292SN/A /** Pointer to the system. */ 7391060SN/A System *system; 7401060SN/A 7412843Sktlim@umich.edu /** Event to call process() on once draining has completed. */ 7422843Sktlim@umich.edu Event *drainEvent; 7432843Sktlim@umich.edu 7442843Sktlim@umich.edu /** Counter of how many stages have completed draining. */ 7452843Sktlim@umich.edu int drainCount; 7462316SN/A 7472348SN/A /** Pointers to all of the threads in the CPU. */ 7482292SN/A std::vector<Thread *> thread; 7492260SN/A 7502292SN/A /** Whether or not the CPU should defer its registration. */ 7511060SN/A bool deferRegistration; 7521060SN/A 7532292SN/A /** Is there a context switch pending? */ 7542292SN/A bool contextSwitch; 7551060SN/A 7562292SN/A /** Threads Scheduled to Enter CPU */ 7572292SN/A std::list<int> cpuWaitList; 7582292SN/A 7592292SN/A /** The cycle that the CPU was last running, used for statistics. */ 7602292SN/A Tick lastRunningCycle; 7612292SN/A 7622829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 7632829Sksewell@umich.edu Tick lastActivatedCycle; 7642829Sksewell@umich.edu 7652292SN/A /** Mapping for system thread id to cpu id */ 7666221Snate@binkert.org std::map<ThreadID, unsigned> threadMap; 7672292SN/A 7682292SN/A /** Available thread ids in the cpu*/ 7696221Snate@binkert.org std::vector<ThreadID> tids; 7702292SN/A 7715595Sgblack@eecs.umich.edu /** CPU read function, forwards read to LSQ. */ 7726974Stjones1@inf.ed.ac.uk Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 7737520Sgblack@eecs.umich.edu uint8_t *data, int load_idx) 7745595Sgblack@eecs.umich.edu { 7756974Stjones1@inf.ed.ac.uk return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 7766974Stjones1@inf.ed.ac.uk data, load_idx); 7775595Sgblack@eecs.umich.edu } 7785595Sgblack@eecs.umich.edu 7795595Sgblack@eecs.umich.edu /** CPU write function, forwards write to LSQ. */ 7806974Stjones1@inf.ed.ac.uk Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 7817520Sgblack@eecs.umich.edu uint8_t *data, int store_idx) 7825595Sgblack@eecs.umich.edu { 7836974Stjones1@inf.ed.ac.uk return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 7846974Stjones1@inf.ed.ac.uk data, store_idx); 7855595Sgblack@eecs.umich.edu } 7865595Sgblack@eecs.umich.edu 7878707Sandreas.hansson@arm.com /** Used by the fetch unit to get a hold of the instruction port. */ 7888707Sandreas.hansson@arm.com Port* getIcachePort() { return &icachePort; } 7898707Sandreas.hansson@arm.com 7906974Stjones1@inf.ed.ac.uk /** Get the dcache port (used to find block size for translations). */ 7918707Sandreas.hansson@arm.com Port* getDcachePort() { return &dcachePort; } 7926974Stjones1@inf.ed.ac.uk 7935595Sgblack@eecs.umich.edu Addr lockAddr; 7945595Sgblack@eecs.umich.edu 7955595Sgblack@eecs.umich.edu /** Temporary fix for the lock flag, works in the UP case. */ 7965595Sgblack@eecs.umich.edu bool lockFlag; 7975595Sgblack@eecs.umich.edu 7982292SN/A /** Stat for total number of times the CPU is descheduled. */ 7995999Snate@binkert.org Stats::Scalar timesIdled; 8002292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 8015999Snate@binkert.org Stats::Scalar idleCycles; 8028627SAli.Saidi@ARM.com /** Stat for total number of cycles the CPU spends descheduled due to a 8038627SAli.Saidi@ARM.com * quiesce operation or waiting for an interrupt. */ 8048627SAli.Saidi@ARM.com Stats::Scalar quiesceCycles; 8052292SN/A /** Stat for the number of committed instructions per thread. */ 8065999Snate@binkert.org Stats::Vector committedInsts; 8072292SN/A /** Stat for the total number of committed instructions. */ 8085999Snate@binkert.org Stats::Scalar totalCommittedInsts; 8092292SN/A /** Stat for the CPI per thread. */ 8102292SN/A Stats::Formula cpi; 8112292SN/A /** Stat for the total CPI. */ 8122292SN/A Stats::Formula totalCpi; 8132292SN/A /** Stat for the IPC per thread. */ 8142292SN/A Stats::Formula ipc; 8152292SN/A /** Stat for the total IPC. */ 8162292SN/A Stats::Formula totalIpc; 8177897Shestness@cs.utexas.edu 8187897Shestness@cs.utexas.edu //number of integer register file accesses 8197897Shestness@cs.utexas.edu Stats::Scalar intRegfileReads; 8207897Shestness@cs.utexas.edu Stats::Scalar intRegfileWrites; 8217897Shestness@cs.utexas.edu //number of float register file accesses 8227897Shestness@cs.utexas.edu Stats::Scalar fpRegfileReads; 8237897Shestness@cs.utexas.edu Stats::Scalar fpRegfileWrites; 8247897Shestness@cs.utexas.edu //number of misc 8257897Shestness@cs.utexas.edu Stats::Scalar miscRegfileReads; 8267897Shestness@cs.utexas.edu Stats::Scalar miscRegfileWrites; 8271060SN/A}; 8281060SN/A 8292325SN/A#endif // __CPU_O3_CPU_HH__ 830