cpu.hh revision 7813
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322325SN/A#ifndef __CPU_O3_CPU_HH__ 332325SN/A#define __CPU_O3_CPU_HH__ 341060SN/A 351060SN/A#include <iostream> 361060SN/A#include <list> 372292SN/A#include <queue> 382292SN/A#include <set> 391681SN/A#include <vector> 401060SN/A 412980Sgblack@eecs.umich.edu#include "arch/types.hh" 421060SN/A#include "base/statistics.hh" 437813Ssteve.reinhardt@amd.com#include "cpu/timebuf.hh" 441858SN/A#include "config/full_system.hh" 456658Snate@binkert.org#include "config/the_isa.hh" 464598Sbinkertn@umich.edu#include "config/use_checker.hh" 472325SN/A#include "cpu/activity.hh" 481717SN/A#include "cpu/base.hh" 492683Sktlim@umich.edu#include "cpu/simple_thread.hh" 501717SN/A#include "cpu/o3/comm.hh" 511717SN/A#include "cpu/o3/cpu_policy.hh" 522292SN/A#include "cpu/o3/scoreboard.hh" 532292SN/A#include "cpu/o3/thread_state.hh" 542817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 551060SN/A#include "sim/process.hh" 561060SN/A 575529Snate@binkert.org#include "params/DerivO3CPU.hh" 585529Snate@binkert.org 592316SN/Atemplate <class> 602316SN/Aclass Checker; 612680Sktlim@umich.educlass ThreadContext; 622817Sksewell@umich.edutemplate <class> 632817Sksewell@umich.educlass O3ThreadContext; 642843Sktlim@umich.edu 652843Sktlim@umich.educlass Checkpoint; 662669Sktlim@umich.educlass MemObject; 671060SN/Aclass Process; 681060SN/A 695529Snate@binkert.orgclass BaseCPUParams; 705529Snate@binkert.org 712733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 721060SN/A{ 731060SN/A //Stuff that's pretty ISA independent will go here. 741060SN/A public: 755529Snate@binkert.org BaseO3CPU(BaseCPUParams *params); 762292SN/A 772292SN/A void regStats(); 781060SN/A}; 791060SN/A 802348SN/A/** 812348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 822348SN/A * within it, as well as all of the time buffers between stages. The 832348SN/A * tick() function for the CPU is defined here. 842348SN/A */ 851060SN/Atemplate <class Impl> 862733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 871060SN/A{ 881060SN/A public: 892325SN/A // Typedefs from the Impl here. 901060SN/A typedef typename Impl::CPUPol CPUPolicy; 911061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 924329Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 931060SN/A 945595Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> ImplState; 952292SN/A typedef O3ThreadState<Impl> Thread; 962292SN/A 972292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 982292SN/A 992817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1002829Sksewell@umich.edu 1011060SN/A public: 1021060SN/A enum Status { 1031060SN/A Running, 1041060SN/A Idle, 1051060SN/A Halted, 1062307SN/A Blocked, 1072307SN/A SwitchedOut 1081060SN/A }; 1091060SN/A 1106022Sgblack@eecs.umich.edu TheISA::TLB * itb; 1116022Sgblack@eecs.umich.edu TheISA::TLB * dtb; 1123781Sgblack@eecs.umich.edu 1132292SN/A /** Overall CPU status. */ 1141060SN/A Status _status; 1151060SN/A 1162829Sksewell@umich.edu /** Per-thread status in CPU, used for SMT. */ 1172829Sksewell@umich.edu Status _threadStatus[Impl::MaxThreads]; 1182829Sksewell@umich.edu 1191060SN/A private: 1201060SN/A class TickEvent : public Event 1211060SN/A { 1221060SN/A private: 1232292SN/A /** Pointer to the CPU. */ 1241755SN/A FullO3CPU<Impl> *cpu; 1251060SN/A 1261060SN/A public: 1272292SN/A /** Constructs a tick event. */ 1281755SN/A TickEvent(FullO3CPU<Impl> *c); 1292292SN/A 1302292SN/A /** Processes a tick event, calling tick() on the CPU. */ 1311060SN/A void process(); 1322292SN/A /** Returns the description of the tick event. */ 1335336Shines@cs.fsu.edu const char *description() const; 1341060SN/A }; 1351060SN/A 1362292SN/A /** The tick event used for scheduling CPU ticks. */ 1371060SN/A TickEvent tickEvent; 1381060SN/A 1392292SN/A /** Schedule tick event, regardless of its current state. */ 1401060SN/A void scheduleTickEvent(int delay) 1411060SN/A { 1421060SN/A if (tickEvent.squashed()) 1435606Snate@binkert.org reschedule(tickEvent, nextCycle(curTick + ticks(delay))); 1441060SN/A else if (!tickEvent.scheduled()) 1455606Snate@binkert.org schedule(tickEvent, nextCycle(curTick + ticks(delay))); 1461060SN/A } 1471060SN/A 1482292SN/A /** Unschedule tick event, regardless of its current state. */ 1491060SN/A void unscheduleTickEvent() 1501060SN/A { 1511060SN/A if (tickEvent.scheduled()) 1521060SN/A tickEvent.squash(); 1531060SN/A } 1541060SN/A 1552829Sksewell@umich.edu class ActivateThreadEvent : public Event 1562829Sksewell@umich.edu { 1572829Sksewell@umich.edu private: 1582829Sksewell@umich.edu /** Number of Thread to Activate */ 1596221Snate@binkert.org ThreadID tid; 1602829Sksewell@umich.edu 1612829Sksewell@umich.edu /** Pointer to the CPU. */ 1622829Sksewell@umich.edu FullO3CPU<Impl> *cpu; 1632829Sksewell@umich.edu 1642829Sksewell@umich.edu public: 1652829Sksewell@umich.edu /** Constructs the event. */ 1662829Sksewell@umich.edu ActivateThreadEvent(); 1672829Sksewell@umich.edu 1682829Sksewell@umich.edu /** Initialize Event */ 1692829Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 1702829Sksewell@umich.edu 1712829Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 1722829Sksewell@umich.edu void process(); 1732829Sksewell@umich.edu 1742829Sksewell@umich.edu /** Returns the description of the event. */ 1755336Shines@cs.fsu.edu const char *description() const; 1762829Sksewell@umich.edu }; 1772829Sksewell@umich.edu 1782829Sksewell@umich.edu /** Schedule thread to activate , regardless of its current state. */ 1796221Snate@binkert.org void 1806221Snate@binkert.org scheduleActivateThreadEvent(ThreadID tid, int delay) 1812829Sksewell@umich.edu { 1822829Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 1832829Sksewell@umich.edu if (activateThreadEvent[tid].squashed()) 1845606Snate@binkert.org reschedule(activateThreadEvent[tid], 1855606Snate@binkert.org nextCycle(curTick + ticks(delay))); 1862829Sksewell@umich.edu else if (!activateThreadEvent[tid].scheduled()) 1875606Snate@binkert.org schedule(activateThreadEvent[tid], 1885606Snate@binkert.org nextCycle(curTick + ticks(delay))); 1892829Sksewell@umich.edu } 1902829Sksewell@umich.edu 1912829Sksewell@umich.edu /** Unschedule actiavte thread event, regardless of its current state. */ 1926221Snate@binkert.org void 1936221Snate@binkert.org unscheduleActivateThreadEvent(ThreadID tid) 1942829Sksewell@umich.edu { 1952829Sksewell@umich.edu if (activateThreadEvent[tid].scheduled()) 1962829Sksewell@umich.edu activateThreadEvent[tid].squash(); 1972829Sksewell@umich.edu } 1982829Sksewell@umich.edu 1992829Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2002829Sksewell@umich.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 2012829Sksewell@umich.edu 2022875Sksewell@umich.edu class DeallocateContextEvent : public Event 2032875Sksewell@umich.edu { 2042875Sksewell@umich.edu private: 2053221Sktlim@umich.edu /** Number of Thread to deactivate */ 2066221Snate@binkert.org ThreadID tid; 2072875Sksewell@umich.edu 2083221Sktlim@umich.edu /** Should the thread be removed from the CPU? */ 2093221Sktlim@umich.edu bool remove; 2103221Sktlim@umich.edu 2112875Sksewell@umich.edu /** Pointer to the CPU. */ 2122875Sksewell@umich.edu FullO3CPU<Impl> *cpu; 2132875Sksewell@umich.edu 2142875Sksewell@umich.edu public: 2152875Sksewell@umich.edu /** Constructs the event. */ 2162875Sksewell@umich.edu DeallocateContextEvent(); 2172875Sksewell@umich.edu 2182875Sksewell@umich.edu /** Initialize Event */ 2192875Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 2202875Sksewell@umich.edu 2212875Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 2222875Sksewell@umich.edu void process(); 2232875Sksewell@umich.edu 2243221Sktlim@umich.edu /** Sets whether the thread should also be removed from the CPU. */ 2253221Sktlim@umich.edu void setRemove(bool _remove) { remove = _remove; } 2263221Sktlim@umich.edu 2272875Sksewell@umich.edu /** Returns the description of the event. */ 2285336Shines@cs.fsu.edu const char *description() const; 2292875Sksewell@umich.edu }; 2302875Sksewell@umich.edu 2312875Sksewell@umich.edu /** Schedule cpu to deallocate thread context.*/ 2326221Snate@binkert.org void 2336221Snate@binkert.org scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay) 2342875Sksewell@umich.edu { 2352875Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 2362875Sksewell@umich.edu if (deallocateContextEvent[tid].squashed()) 2375606Snate@binkert.org reschedule(deallocateContextEvent[tid], 2385606Snate@binkert.org nextCycle(curTick + ticks(delay))); 2392875Sksewell@umich.edu else if (!deallocateContextEvent[tid].scheduled()) 2405606Snate@binkert.org schedule(deallocateContextEvent[tid], 2415606Snate@binkert.org nextCycle(curTick + ticks(delay))); 2422875Sksewell@umich.edu } 2432875Sksewell@umich.edu 2442875Sksewell@umich.edu /** Unschedule thread deallocation in CPU */ 2456221Snate@binkert.org void 2466221Snate@binkert.org unscheduleDeallocateContextEvent(ThreadID tid) 2472875Sksewell@umich.edu { 2482875Sksewell@umich.edu if (deallocateContextEvent[tid].scheduled()) 2492875Sksewell@umich.edu deallocateContextEvent[tid].squash(); 2502875Sksewell@umich.edu } 2512875Sksewell@umich.edu 2522875Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2532875Sksewell@umich.edu DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 2542875Sksewell@umich.edu 2551060SN/A public: 2562292SN/A /** Constructs a CPU with the given parameters. */ 2575595Sgblack@eecs.umich.edu FullO3CPU(DerivO3CPUParams *params); 2582292SN/A /** Destructor. */ 2591755SN/A ~FullO3CPU(); 2601060SN/A 2612292SN/A /** Registers statistics. */ 2625595Sgblack@eecs.umich.edu void regStats(); 2631684SN/A 2645358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 2655358Sgblack@eecs.umich.edu { 2665358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2675358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2685358Sgblack@eecs.umich.edu } 2695358Sgblack@eecs.umich.edu 2705358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 2715358Sgblack@eecs.umich.edu { 2725358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2735358Sgblack@eecs.umich.edu } 2745358Sgblack@eecs.umich.edu 2755358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 2765358Sgblack@eecs.umich.edu { 2775358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2785358Sgblack@eecs.umich.edu } 2795358Sgblack@eecs.umich.edu 2802871Sktlim@umich.edu /** Returns a specific port. */ 2812871Sktlim@umich.edu Port *getPort(const std::string &if_name, int idx); 2822871Sktlim@umich.edu 2832292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 2842292SN/A * activity to see if the CPU should deschedule itself. 2852292SN/A */ 2861684SN/A void tick(); 2871684SN/A 2882292SN/A /** Initialize the CPU */ 2891060SN/A void init(); 2901060SN/A 2912834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 2922834Sksewell@umich.edu int numActiveThreads() 2932834Sksewell@umich.edu { return activeThreads.size(); } 2942834Sksewell@umich.edu 2952829Sksewell@umich.edu /** Add Thread to Active Threads List */ 2966221Snate@binkert.org void activateThread(ThreadID tid); 2972875Sksewell@umich.edu 2982875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 2996221Snate@binkert.org void deactivateThread(ThreadID tid); 3002829Sksewell@umich.edu 3012292SN/A /** Setup CPU to insert a thread's context */ 3026221Snate@binkert.org void insertThread(ThreadID tid); 3031060SN/A 3042292SN/A /** Remove all of a thread's context from CPU */ 3056221Snate@binkert.org void removeThread(ThreadID tid); 3062292SN/A 3072292SN/A /** Count the Total Instructions Committed in the CPU. */ 3086221Snate@binkert.org virtual Counter totalInstructions() const; 3092292SN/A 3102292SN/A /** Add Thread to Active Threads List. */ 3116221Snate@binkert.org void activateContext(ThreadID tid, int delay); 3122292SN/A 3132292SN/A /** Remove Thread from Active Threads List */ 3146221Snate@binkert.org void suspendContext(ThreadID tid); 3152292SN/A 3162292SN/A /** Remove Thread from Active Threads List && 3173221Sktlim@umich.edu * Possibly Remove Thread Context from CPU. 3182292SN/A */ 3196221Snate@binkert.org bool deallocateContext(ThreadID tid, bool remove, int delay = 1); 3202292SN/A 3212292SN/A /** Remove Thread from Active Threads List && 3222292SN/A * Remove Thread Context from CPU. 3232292SN/A */ 3246221Snate@binkert.org void haltContext(ThreadID tid); 3252292SN/A 3262292SN/A /** Activate a Thread When CPU Resources are Available. */ 3276221Snate@binkert.org void activateWhenReady(ThreadID tid); 3282292SN/A 3292292SN/A /** Add or Remove a Thread Context in the CPU. */ 3302292SN/A void doContextSwitch(); 3312292SN/A 3322292SN/A /** Update The Order In Which We Process Threads. */ 3332292SN/A void updateThreadPriority(); 3342292SN/A 3352864Sktlim@umich.edu /** Serialize state. */ 3362864Sktlim@umich.edu virtual void serialize(std::ostream &os); 3372864Sktlim@umich.edu 3382864Sktlim@umich.edu /** Unserialize from a checkpoint. */ 3392864Sktlim@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 3402864Sktlim@umich.edu 3412864Sktlim@umich.edu public: 3425595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 3435595Sgblack@eecs.umich.edu /** Executes a syscall. 3445595Sgblack@eecs.umich.edu * @todo: Determine if this needs to be virtual. 3452292SN/A */ 3466221Snate@binkert.org void syscall(int64_t callnum, ThreadID tid); 3475595Sgblack@eecs.umich.edu#endif 3482292SN/A 3492843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 3502843Sktlim@umich.edu * order to stop all memory accesses. */ 3512905Sktlim@umich.edu virtual unsigned int drain(Event *drain_event); 3522843Sktlim@umich.edu 3532843Sktlim@umich.edu /** Resumes execution after a drain. */ 3542843Sktlim@umich.edu virtual void resume(); 3552292SN/A 3562348SN/A /** Signals to this CPU that a stage has completed switching out. */ 3572843Sktlim@umich.edu void signalDrained(); 3582843Sktlim@umich.edu 3592843Sktlim@umich.edu /** Switches out this CPU. */ 3602843Sktlim@umich.edu virtual void switchOut(); 3612316SN/A 3622348SN/A /** Takes over from another CPU. */ 3632843Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *oldCPU); 3641060SN/A 3651060SN/A /** Get the current instruction sequence number, and increment it. */ 3662316SN/A InstSeqNum getAndIncrementInstSeq() 3672316SN/A { return globalSeqNum++; } 3681060SN/A 3695595Sgblack@eecs.umich.edu /** Traps to handle given fault. */ 3707684Sgblack@eecs.umich.edu void trap(Fault fault, ThreadID tid, StaticInstPtr inst); 3715595Sgblack@eecs.umich.edu 3721858SN/A#if FULL_SYSTEM 3735702Ssaidi@eecs.umich.edu /** HW return from error interrupt. */ 3746221Snate@binkert.org Fault hwrei(ThreadID tid); 3755702Ssaidi@eecs.umich.edu 3766221Snate@binkert.org bool simPalCheck(int palFunc, ThreadID tid); 3775702Ssaidi@eecs.umich.edu 3785595Sgblack@eecs.umich.edu /** Returns the Fault for any valid interrupt. */ 3795595Sgblack@eecs.umich.edu Fault getInterrupts(); 3805595Sgblack@eecs.umich.edu 3815595Sgblack@eecs.umich.edu /** Processes any an interrupt fault. */ 3825595Sgblack@eecs.umich.edu void processInterrupts(Fault interrupt); 3835595Sgblack@eecs.umich.edu 3845595Sgblack@eecs.umich.edu /** Halts the CPU. */ 3855595Sgblack@eecs.umich.edu void halt() { panic("Halt not implemented!\n"); } 3865595Sgblack@eecs.umich.edu 3874192Sktlim@umich.edu /** Update the Virt and Phys ports of all ThreadContexts to 3884192Sktlim@umich.edu * reflect change in memory connections. */ 3894192Sktlim@umich.edu void updateMemPorts(); 3904192Sktlim@umich.edu 3911060SN/A /** Check if this address is a valid instruction address. */ 3921060SN/A bool validInstAddr(Addr addr) { return true; } 3931060SN/A 3941060SN/A /** Check if this address is a valid data address. */ 3951060SN/A bool validDataAddr(Addr addr) { return true; } 3961060SN/A#endif 3971060SN/A 3982348SN/A /** Register accessors. Index refers to the physical register index. */ 3995595Sgblack@eecs.umich.edu 4005595Sgblack@eecs.umich.edu /** Reads a miscellaneous register. */ 4016221Snate@binkert.org TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 4025595Sgblack@eecs.umich.edu 4035595Sgblack@eecs.umich.edu /** Reads a misc. register, including any side effects the read 4045595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4055595Sgblack@eecs.umich.edu */ 4066221Snate@binkert.org TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 4075595Sgblack@eecs.umich.edu 4085595Sgblack@eecs.umich.edu /** Sets a miscellaneous register. */ 4096221Snate@binkert.org void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 4106221Snate@binkert.org ThreadID tid); 4115595Sgblack@eecs.umich.edu 4125595Sgblack@eecs.umich.edu /** Sets a misc. register, including any side effects the write 4135595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4145595Sgblack@eecs.umich.edu */ 4155595Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 4166221Snate@binkert.org ThreadID tid); 4175595Sgblack@eecs.umich.edu 4181060SN/A uint64_t readIntReg(int reg_idx); 4191060SN/A 4203781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx); 4211060SN/A 4223781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx); 4232455SN/A 4241060SN/A void setIntReg(int reg_idx, uint64_t val); 4251060SN/A 4263781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val); 4271060SN/A 4283781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 4292455SN/A 4306221Snate@binkert.org uint64_t readArchIntReg(int reg_idx, ThreadID tid); 4311060SN/A 4326314Sgblack@eecs.umich.edu float readArchFloatReg(int reg_idx, ThreadID tid); 4332292SN/A 4346221Snate@binkert.org uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 4352292SN/A 4362348SN/A /** Architectural register accessors. Looks up in the commit 4372348SN/A * rename table to obtain the true physical index of the 4382348SN/A * architected register first, then accesses that physical 4392348SN/A * register. 4402348SN/A */ 4416221Snate@binkert.org void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 4422292SN/A 4436314Sgblack@eecs.umich.edu void setArchFloatReg(int reg_idx, float val, ThreadID tid); 4442292SN/A 4456221Snate@binkert.org void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 4462292SN/A 4477720Sgblack@eecs.umich.edu /** Sets the commit PC state of a specific thread. */ 4487720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &newPCState, ThreadID tid); 4497720Sgblack@eecs.umich.edu 4507720Sgblack@eecs.umich.edu /** Reads the commit PC state of a specific thread. */ 4517720Sgblack@eecs.umich.edu TheISA::PCState pcState(ThreadID tid); 4527720Sgblack@eecs.umich.edu 4532348SN/A /** Reads the commit PC of a specific thread. */ 4547720Sgblack@eecs.umich.edu Addr instAddr(ThreadID tid); 4552292SN/A 4564636Sgblack@eecs.umich.edu /** Reads the commit micro PC of a specific thread. */ 4577720Sgblack@eecs.umich.edu MicroPC microPC(ThreadID tid); 4584636Sgblack@eecs.umich.edu 4592348SN/A /** Reads the next PC of a specific thread. */ 4607720Sgblack@eecs.umich.edu Addr nextInstAddr(ThreadID tid); 4612756Sksewell@umich.edu 4625595Sgblack@eecs.umich.edu /** Initiates a squash of all in-flight instructions for a given 4635595Sgblack@eecs.umich.edu * thread. The source of the squash is an external update of 4645595Sgblack@eecs.umich.edu * state through the TC. 4655595Sgblack@eecs.umich.edu */ 4666221Snate@binkert.org void squashFromTC(ThreadID tid); 4675595Sgblack@eecs.umich.edu 4681060SN/A /** Function to add instruction onto the head of the list of the 4691060SN/A * instructions. Used when new instructions are fetched. 4701060SN/A */ 4712292SN/A ListIt addInst(DynInstPtr &inst); 4721060SN/A 4731060SN/A /** Function to tell the CPU that an instruction has completed. */ 4746221Snate@binkert.org void instDone(ThreadID tid); 4751060SN/A 4762292SN/A /** Add Instructions to the CPU Remove List*/ 4772292SN/A void addToRemoveList(DynInstPtr &inst); 4781060SN/A 4792325SN/A /** Remove an instruction from the front end of the list. There's 4802325SN/A * no restriction on location of the instruction. 4811060SN/A */ 4821061SN/A void removeFrontInst(DynInstPtr &inst); 4831060SN/A 4842935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 4852935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 4866221Snate@binkert.org void removeInstsNotInROB(ThreadID tid); 4871060SN/A 4881062SN/A /** Remove all instructions younger than the given sequence number. */ 4896221Snate@binkert.org void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 4902292SN/A 4912348SN/A /** Removes the instruction pointed to by the iterator. */ 4926221Snate@binkert.org inline void squashInstIt(const ListIt &instIt, ThreadID tid); 4932292SN/A 4942348SN/A /** Cleans up all instructions on the remove list. */ 4952292SN/A void cleanUpRemovedInsts(); 4961062SN/A 4972348SN/A /** Debug function to print all instructions on the list. */ 4981060SN/A void dumpInsts(); 4991060SN/A 5001060SN/A public: 5015737Scws3k@cs.virginia.edu#ifndef NDEBUG 5025737Scws3k@cs.virginia.edu /** Count of total number of dynamic instructions in flight. */ 5035737Scws3k@cs.virginia.edu int instcount; 5045737Scws3k@cs.virginia.edu#endif 5055737Scws3k@cs.virginia.edu 5061060SN/A /** List of all the instructions in flight. */ 5072292SN/A std::list<DynInstPtr> instList; 5081060SN/A 5092292SN/A /** List of all the instructions that will be removed at the end of this 5102292SN/A * cycle. 5112292SN/A */ 5122292SN/A std::queue<ListIt> removeList; 5132292SN/A 5142325SN/A#ifdef DEBUG 5152348SN/A /** Debug structure to keep track of the sequence numbers still in 5162348SN/A * flight. 5172348SN/A */ 5182292SN/A std::set<InstSeqNum> snList; 5192325SN/A#endif 5202292SN/A 5212325SN/A /** Records if instructions need to be removed this cycle due to 5222325SN/A * being retired or squashed. 5232292SN/A */ 5242292SN/A bool removeInstsThisCycle; 5252292SN/A 5261060SN/A protected: 5271060SN/A /** The fetch stage. */ 5281060SN/A typename CPUPolicy::Fetch fetch; 5291060SN/A 5301060SN/A /** The decode stage. */ 5311060SN/A typename CPUPolicy::Decode decode; 5321060SN/A 5331060SN/A /** The dispatch stage. */ 5341060SN/A typename CPUPolicy::Rename rename; 5351060SN/A 5361060SN/A /** The issue/execute/writeback stages. */ 5371060SN/A typename CPUPolicy::IEW iew; 5381060SN/A 5391060SN/A /** The commit stage. */ 5401060SN/A typename CPUPolicy::Commit commit; 5411060SN/A 5421060SN/A /** The register file. */ 5431060SN/A typename CPUPolicy::RegFile regFile; 5441060SN/A 5451060SN/A /** The free list. */ 5461060SN/A typename CPUPolicy::FreeList freeList; 5471060SN/A 5481060SN/A /** The rename map. */ 5492292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 5502292SN/A 5512292SN/A /** The commit rename map. */ 5522292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 5531060SN/A 5541060SN/A /** The re-order buffer. */ 5551060SN/A typename CPUPolicy::ROB rob; 5561060SN/A 5572292SN/A /** Active Threads List */ 5586221Snate@binkert.org std::list<ThreadID> activeThreads; 5592292SN/A 5602292SN/A /** Integer Register Scoreboard */ 5612292SN/A Scoreboard scoreboard; 5622292SN/A 5636313Sgblack@eecs.umich.edu TheISA::ISA isa[Impl::MaxThreads]; 5646313Sgblack@eecs.umich.edu 5651060SN/A public: 5662292SN/A /** Enum to give each stage a specific index, so when calling 5672292SN/A * activateStage() or deactivateStage(), they can specify which stage 5682292SN/A * is being activated/deactivated. 5692292SN/A */ 5702292SN/A enum StageIdx { 5712292SN/A FetchIdx, 5722292SN/A DecodeIdx, 5732292SN/A RenameIdx, 5742292SN/A IEWIdx, 5752292SN/A CommitIdx, 5762292SN/A NumStages }; 5772292SN/A 5781060SN/A /** Typedefs from the Impl to get the structs that each of the 5791060SN/A * time buffers should use. 5801060SN/A */ 5811061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 5821060SN/A 5831061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 5841060SN/A 5851061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 5861060SN/A 5871061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 5881060SN/A 5891061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 5901060SN/A 5911060SN/A /** The main time buffer to do backwards communication. */ 5921060SN/A TimeBuffer<TimeStruct> timeBuffer; 5931060SN/A 5941060SN/A /** The fetch stage's instruction queue. */ 5951060SN/A TimeBuffer<FetchStruct> fetchQueue; 5961060SN/A 5971060SN/A /** The decode stage's instruction queue. */ 5981060SN/A TimeBuffer<DecodeStruct> decodeQueue; 5991060SN/A 6001060SN/A /** The rename stage's instruction queue. */ 6011060SN/A TimeBuffer<RenameStruct> renameQueue; 6021060SN/A 6031060SN/A /** The IEW stage's instruction queue. */ 6041060SN/A TimeBuffer<IEWStruct> iewQueue; 6051060SN/A 6062348SN/A private: 6072348SN/A /** The activity recorder; used to tell if the CPU has any 6082348SN/A * activity remaining or if it can go to idle and deschedule 6092348SN/A * itself. 6102348SN/A */ 6112325SN/A ActivityRecorder activityRec; 6121060SN/A 6132348SN/A public: 6142348SN/A /** Records that there was time buffer activity this cycle. */ 6152325SN/A void activityThisCycle() { activityRec.activity(); } 6162292SN/A 6172348SN/A /** Changes a stage's status to active within the activity recorder. */ 6182325SN/A void activateStage(const StageIdx idx) 6192325SN/A { activityRec.activateStage(idx); } 6202292SN/A 6212348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 6222325SN/A void deactivateStage(const StageIdx idx) 6232325SN/A { activityRec.deactivateStage(idx); } 6242292SN/A 6252292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 6262292SN/A void wakeCPU(); 6272260SN/A 6285807Snate@binkert.org#if FULL_SYSTEM 6295807Snate@binkert.org virtual void wakeup(); 6305807Snate@binkert.org#endif 6315807Snate@binkert.org 6322292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 6336221Snate@binkert.org ThreadID getFreeTid(); 6342292SN/A 6352292SN/A public: 6362680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 6376221Snate@binkert.org ThreadContext * 6386221Snate@binkert.org tcBase(ThreadID tid) 6391681SN/A { 6402680Sktlim@umich.edu return thread[tid]->getTC(); 6412190SN/A } 6422190SN/A 6432292SN/A /** The global sequence number counter. */ 6443093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 6451060SN/A 6464598Sbinkertn@umich.edu#if USE_CHECKER 6472348SN/A /** Pointer to the checker, which can dynamically verify 6482348SN/A * instruction results at run time. This can be set to NULL if it 6492348SN/A * is not being used. 6502348SN/A */ 6512316SN/A Checker<DynInstPtr> *checker; 6524598Sbinkertn@umich.edu#endif 6532316SN/A 6541858SN/A#if FULL_SYSTEM 6552292SN/A /** Pointer to the system. */ 6561060SN/A System *system; 6572292SN/A#endif 6581060SN/A 6592843Sktlim@umich.edu /** Event to call process() on once draining has completed. */ 6602843Sktlim@umich.edu Event *drainEvent; 6612843Sktlim@umich.edu 6622843Sktlim@umich.edu /** Counter of how many stages have completed draining. */ 6632843Sktlim@umich.edu int drainCount; 6642316SN/A 6652348SN/A /** Pointers to all of the threads in the CPU. */ 6662292SN/A std::vector<Thread *> thread; 6672260SN/A 6682292SN/A /** Whether or not the CPU should defer its registration. */ 6691060SN/A bool deferRegistration; 6701060SN/A 6712292SN/A /** Is there a context switch pending? */ 6722292SN/A bool contextSwitch; 6731060SN/A 6742292SN/A /** Threads Scheduled to Enter CPU */ 6752292SN/A std::list<int> cpuWaitList; 6762292SN/A 6772292SN/A /** The cycle that the CPU was last running, used for statistics. */ 6782292SN/A Tick lastRunningCycle; 6792292SN/A 6802829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 6812829Sksewell@umich.edu Tick lastActivatedCycle; 6822829Sksewell@umich.edu 6832292SN/A /** Mapping for system thread id to cpu id */ 6846221Snate@binkert.org std::map<ThreadID, unsigned> threadMap; 6852292SN/A 6862292SN/A /** Available thread ids in the cpu*/ 6876221Snate@binkert.org std::vector<ThreadID> tids; 6882292SN/A 6895595Sgblack@eecs.umich.edu /** CPU read function, forwards read to LSQ. */ 6906974Stjones1@inf.ed.ac.uk Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 6917520Sgblack@eecs.umich.edu uint8_t *data, int load_idx) 6925595Sgblack@eecs.umich.edu { 6936974Stjones1@inf.ed.ac.uk return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 6946974Stjones1@inf.ed.ac.uk data, load_idx); 6955595Sgblack@eecs.umich.edu } 6965595Sgblack@eecs.umich.edu 6975595Sgblack@eecs.umich.edu /** CPU write function, forwards write to LSQ. */ 6986974Stjones1@inf.ed.ac.uk Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 6997520Sgblack@eecs.umich.edu uint8_t *data, int store_idx) 7005595Sgblack@eecs.umich.edu { 7016974Stjones1@inf.ed.ac.uk return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 7026974Stjones1@inf.ed.ac.uk data, store_idx); 7035595Sgblack@eecs.umich.edu } 7045595Sgblack@eecs.umich.edu 7056974Stjones1@inf.ed.ac.uk /** Get the dcache port (used to find block size for translations). */ 7066974Stjones1@inf.ed.ac.uk Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); } 7076974Stjones1@inf.ed.ac.uk 7085595Sgblack@eecs.umich.edu Addr lockAddr; 7095595Sgblack@eecs.umich.edu 7105595Sgblack@eecs.umich.edu /** Temporary fix for the lock flag, works in the UP case. */ 7115595Sgblack@eecs.umich.edu bool lockFlag; 7125595Sgblack@eecs.umich.edu 7132292SN/A /** Stat for total number of times the CPU is descheduled. */ 7145999Snate@binkert.org Stats::Scalar timesIdled; 7152292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 7165999Snate@binkert.org Stats::Scalar idleCycles; 7172292SN/A /** Stat for the number of committed instructions per thread. */ 7185999Snate@binkert.org Stats::Vector committedInsts; 7192292SN/A /** Stat for the total number of committed instructions. */ 7205999Snate@binkert.org Stats::Scalar totalCommittedInsts; 7212292SN/A /** Stat for the CPI per thread. */ 7222292SN/A Stats::Formula cpi; 7232292SN/A /** Stat for the total CPI. */ 7242292SN/A Stats::Formula totalCpi; 7252292SN/A /** Stat for the IPC per thread. */ 7262292SN/A Stats::Formula ipc; 7272292SN/A /** Stat for the total IPC. */ 7282292SN/A Stats::Formula totalIpc; 7291060SN/A}; 7301060SN/A 7312325SN/A#endif // __CPU_O3_CPU_HH__ 732