cpu.hh revision 6022
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322325SN/A#ifndef __CPU_O3_CPU_HH__ 332325SN/A#define __CPU_O3_CPU_HH__ 341060SN/A 351060SN/A#include <iostream> 361060SN/A#include <list> 372292SN/A#include <queue> 382292SN/A#include <set> 391681SN/A#include <vector> 401060SN/A 412980Sgblack@eecs.umich.edu#include "arch/types.hh" 421060SN/A#include "base/statistics.hh" 431060SN/A#include "base/timebuf.hh" 441858SN/A#include "config/full_system.hh" 454598Sbinkertn@umich.edu#include "config/use_checker.hh" 462325SN/A#include "cpu/activity.hh" 471717SN/A#include "cpu/base.hh" 482683Sktlim@umich.edu#include "cpu/simple_thread.hh" 491717SN/A#include "cpu/o3/comm.hh" 501717SN/A#include "cpu/o3/cpu_policy.hh" 512292SN/A#include "cpu/o3/scoreboard.hh" 522292SN/A#include "cpu/o3/thread_state.hh" 532817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 541060SN/A#include "sim/process.hh" 551060SN/A 565529Snate@binkert.org#include "params/DerivO3CPU.hh" 575529Snate@binkert.org 582316SN/Atemplate <class> 592316SN/Aclass Checker; 602680Sktlim@umich.educlass ThreadContext; 612817Sksewell@umich.edutemplate <class> 622817Sksewell@umich.educlass O3ThreadContext; 632843Sktlim@umich.edu 642843Sktlim@umich.educlass Checkpoint; 652669Sktlim@umich.educlass MemObject; 661060SN/Aclass Process; 671060SN/A 685529Snate@binkert.orgclass BaseCPUParams; 695529Snate@binkert.org 702733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 711060SN/A{ 721060SN/A //Stuff that's pretty ISA independent will go here. 731060SN/A public: 745529Snate@binkert.org BaseO3CPU(BaseCPUParams *params); 752292SN/A 762292SN/A void regStats(); 771060SN/A}; 781060SN/A 792348SN/A/** 802348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 812348SN/A * within it, as well as all of the time buffers between stages. The 822348SN/A * tick() function for the CPU is defined here. 832348SN/A */ 841060SN/Atemplate <class Impl> 852733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 861060SN/A{ 871060SN/A public: 882325SN/A // Typedefs from the Impl here. 891060SN/A typedef typename Impl::CPUPol CPUPolicy; 901061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 914329Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 921060SN/A 935595Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> ImplState; 942292SN/A typedef O3ThreadState<Impl> Thread; 952292SN/A 962292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 972292SN/A 982817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 992829Sksewell@umich.edu 1001060SN/A public: 1011060SN/A enum Status { 1021060SN/A Running, 1031060SN/A Idle, 1041060SN/A Halted, 1052307SN/A Blocked, 1062307SN/A SwitchedOut 1071060SN/A }; 1081060SN/A 1096022Sgblack@eecs.umich.edu TheISA::TLB * itb; 1106022Sgblack@eecs.umich.edu TheISA::TLB * dtb; 1113781Sgblack@eecs.umich.edu 1122292SN/A /** Overall CPU status. */ 1131060SN/A Status _status; 1141060SN/A 1152829Sksewell@umich.edu /** Per-thread status in CPU, used for SMT. */ 1162829Sksewell@umich.edu Status _threadStatus[Impl::MaxThreads]; 1172829Sksewell@umich.edu 1181060SN/A private: 1191060SN/A class TickEvent : public Event 1201060SN/A { 1211060SN/A private: 1222292SN/A /** Pointer to the CPU. */ 1231755SN/A FullO3CPU<Impl> *cpu; 1241060SN/A 1251060SN/A public: 1262292SN/A /** Constructs a tick event. */ 1271755SN/A TickEvent(FullO3CPU<Impl> *c); 1282292SN/A 1292292SN/A /** Processes a tick event, calling tick() on the CPU. */ 1301060SN/A void process(); 1312292SN/A /** Returns the description of the tick event. */ 1325336Shines@cs.fsu.edu const char *description() const; 1331060SN/A }; 1341060SN/A 1352292SN/A /** The tick event used for scheduling CPU ticks. */ 1361060SN/A TickEvent tickEvent; 1371060SN/A 1382292SN/A /** Schedule tick event, regardless of its current state. */ 1391060SN/A void scheduleTickEvent(int delay) 1401060SN/A { 1411060SN/A if (tickEvent.squashed()) 1425606Snate@binkert.org reschedule(tickEvent, nextCycle(curTick + ticks(delay))); 1431060SN/A else if (!tickEvent.scheduled()) 1445606Snate@binkert.org schedule(tickEvent, nextCycle(curTick + ticks(delay))); 1451060SN/A } 1461060SN/A 1472292SN/A /** Unschedule tick event, regardless of its current state. */ 1481060SN/A void unscheduleTickEvent() 1491060SN/A { 1501060SN/A if (tickEvent.scheduled()) 1511060SN/A tickEvent.squash(); 1521060SN/A } 1531060SN/A 1542829Sksewell@umich.edu class ActivateThreadEvent : public Event 1552829Sksewell@umich.edu { 1562829Sksewell@umich.edu private: 1572829Sksewell@umich.edu /** Number of Thread to Activate */ 1582829Sksewell@umich.edu int tid; 1592829Sksewell@umich.edu 1602829Sksewell@umich.edu /** Pointer to the CPU. */ 1612829Sksewell@umich.edu FullO3CPU<Impl> *cpu; 1622829Sksewell@umich.edu 1632829Sksewell@umich.edu public: 1642829Sksewell@umich.edu /** Constructs the event. */ 1652829Sksewell@umich.edu ActivateThreadEvent(); 1662829Sksewell@umich.edu 1672829Sksewell@umich.edu /** Initialize Event */ 1682829Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 1692829Sksewell@umich.edu 1702829Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 1712829Sksewell@umich.edu void process(); 1722829Sksewell@umich.edu 1732829Sksewell@umich.edu /** Returns the description of the event. */ 1745336Shines@cs.fsu.edu const char *description() const; 1752829Sksewell@umich.edu }; 1762829Sksewell@umich.edu 1772829Sksewell@umich.edu /** Schedule thread to activate , regardless of its current state. */ 1782829Sksewell@umich.edu void scheduleActivateThreadEvent(int tid, int delay) 1792829Sksewell@umich.edu { 1802829Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 1812829Sksewell@umich.edu if (activateThreadEvent[tid].squashed()) 1825606Snate@binkert.org reschedule(activateThreadEvent[tid], 1835606Snate@binkert.org nextCycle(curTick + ticks(delay))); 1842829Sksewell@umich.edu else if (!activateThreadEvent[tid].scheduled()) 1855606Snate@binkert.org schedule(activateThreadEvent[tid], 1865606Snate@binkert.org nextCycle(curTick + ticks(delay))); 1872829Sksewell@umich.edu } 1882829Sksewell@umich.edu 1892829Sksewell@umich.edu /** Unschedule actiavte thread event, regardless of its current state. */ 1902829Sksewell@umich.edu void unscheduleActivateThreadEvent(int tid) 1912829Sksewell@umich.edu { 1922829Sksewell@umich.edu if (activateThreadEvent[tid].scheduled()) 1932829Sksewell@umich.edu activateThreadEvent[tid].squash(); 1942829Sksewell@umich.edu } 1952829Sksewell@umich.edu 1962829Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 1972829Sksewell@umich.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 1982829Sksewell@umich.edu 1992875Sksewell@umich.edu class DeallocateContextEvent : public Event 2002875Sksewell@umich.edu { 2012875Sksewell@umich.edu private: 2023221Sktlim@umich.edu /** Number of Thread to deactivate */ 2032875Sksewell@umich.edu int tid; 2042875Sksewell@umich.edu 2053221Sktlim@umich.edu /** Should the thread be removed from the CPU? */ 2063221Sktlim@umich.edu bool remove; 2073221Sktlim@umich.edu 2082875Sksewell@umich.edu /** Pointer to the CPU. */ 2092875Sksewell@umich.edu FullO3CPU<Impl> *cpu; 2102875Sksewell@umich.edu 2112875Sksewell@umich.edu public: 2122875Sksewell@umich.edu /** Constructs the event. */ 2132875Sksewell@umich.edu DeallocateContextEvent(); 2142875Sksewell@umich.edu 2152875Sksewell@umich.edu /** Initialize Event */ 2162875Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 2172875Sksewell@umich.edu 2182875Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 2192875Sksewell@umich.edu void process(); 2202875Sksewell@umich.edu 2213221Sktlim@umich.edu /** Sets whether the thread should also be removed from the CPU. */ 2223221Sktlim@umich.edu void setRemove(bool _remove) { remove = _remove; } 2233221Sktlim@umich.edu 2242875Sksewell@umich.edu /** Returns the description of the event. */ 2255336Shines@cs.fsu.edu const char *description() const; 2262875Sksewell@umich.edu }; 2272875Sksewell@umich.edu 2282875Sksewell@umich.edu /** Schedule cpu to deallocate thread context.*/ 2293221Sktlim@umich.edu void scheduleDeallocateContextEvent(int tid, bool remove, int delay) 2302875Sksewell@umich.edu { 2312875Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 2322875Sksewell@umich.edu if (deallocateContextEvent[tid].squashed()) 2335606Snate@binkert.org reschedule(deallocateContextEvent[tid], 2345606Snate@binkert.org nextCycle(curTick + ticks(delay))); 2352875Sksewell@umich.edu else if (!deallocateContextEvent[tid].scheduled()) 2365606Snate@binkert.org schedule(deallocateContextEvent[tid], 2375606Snate@binkert.org nextCycle(curTick + ticks(delay))); 2382875Sksewell@umich.edu } 2392875Sksewell@umich.edu 2402875Sksewell@umich.edu /** Unschedule thread deallocation in CPU */ 2412875Sksewell@umich.edu void unscheduleDeallocateContextEvent(int tid) 2422875Sksewell@umich.edu { 2432875Sksewell@umich.edu if (deallocateContextEvent[tid].scheduled()) 2442875Sksewell@umich.edu deallocateContextEvent[tid].squash(); 2452875Sksewell@umich.edu } 2462875Sksewell@umich.edu 2472875Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2482875Sksewell@umich.edu DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 2492875Sksewell@umich.edu 2501060SN/A public: 2512292SN/A /** Constructs a CPU with the given parameters. */ 2525595Sgblack@eecs.umich.edu FullO3CPU(DerivO3CPUParams *params); 2532292SN/A /** Destructor. */ 2541755SN/A ~FullO3CPU(); 2551060SN/A 2562292SN/A /** Registers statistics. */ 2575595Sgblack@eecs.umich.edu void regStats(); 2581684SN/A 2595358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 2605358Sgblack@eecs.umich.edu { 2615358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2625358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2635358Sgblack@eecs.umich.edu } 2645358Sgblack@eecs.umich.edu 2655358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 2665358Sgblack@eecs.umich.edu { 2675358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2685358Sgblack@eecs.umich.edu } 2695358Sgblack@eecs.umich.edu 2705358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 2715358Sgblack@eecs.umich.edu { 2725358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2735358Sgblack@eecs.umich.edu } 2745358Sgblack@eecs.umich.edu 2752871Sktlim@umich.edu /** Returns a specific port. */ 2762871Sktlim@umich.edu Port *getPort(const std::string &if_name, int idx); 2772871Sktlim@umich.edu 2782292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 2792292SN/A * activity to see if the CPU should deschedule itself. 2802292SN/A */ 2811684SN/A void tick(); 2821684SN/A 2832292SN/A /** Initialize the CPU */ 2841060SN/A void init(); 2851060SN/A 2862834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 2872834Sksewell@umich.edu int numActiveThreads() 2882834Sksewell@umich.edu { return activeThreads.size(); } 2892834Sksewell@umich.edu 2902829Sksewell@umich.edu /** Add Thread to Active Threads List */ 2912875Sksewell@umich.edu void activateThread(unsigned tid); 2922875Sksewell@umich.edu 2932875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 2942875Sksewell@umich.edu void deactivateThread(unsigned tid); 2952829Sksewell@umich.edu 2962292SN/A /** Setup CPU to insert a thread's context */ 2972292SN/A void insertThread(unsigned tid); 2981060SN/A 2992292SN/A /** Remove all of a thread's context from CPU */ 3002292SN/A void removeThread(unsigned tid); 3012292SN/A 3022292SN/A /** Count the Total Instructions Committed in the CPU. */ 3032292SN/A virtual Counter totalInstructions() const 3042292SN/A { 3052292SN/A Counter total(0); 3062292SN/A 3072292SN/A for (int i=0; i < thread.size(); i++) 3082292SN/A total += thread[i]->numInst; 3092292SN/A 3102292SN/A return total; 3112292SN/A } 3122292SN/A 3132292SN/A /** Add Thread to Active Threads List. */ 3142292SN/A void activateContext(int tid, int delay); 3152292SN/A 3162292SN/A /** Remove Thread from Active Threads List */ 3172292SN/A void suspendContext(int tid); 3182292SN/A 3192292SN/A /** Remove Thread from Active Threads List && 3203221Sktlim@umich.edu * Possibly Remove Thread Context from CPU. 3212292SN/A */ 3223221Sktlim@umich.edu bool deallocateContext(int tid, bool remove, int delay = 1); 3232292SN/A 3242292SN/A /** Remove Thread from Active Threads List && 3252292SN/A * Remove Thread Context from CPU. 3262292SN/A */ 3272292SN/A void haltContext(int tid); 3282292SN/A 3292292SN/A /** Activate a Thread When CPU Resources are Available. */ 3302292SN/A void activateWhenReady(int tid); 3312292SN/A 3322292SN/A /** Add or Remove a Thread Context in the CPU. */ 3332292SN/A void doContextSwitch(); 3342292SN/A 3352292SN/A /** Update The Order In Which We Process Threads. */ 3362292SN/A void updateThreadPriority(); 3372292SN/A 3382864Sktlim@umich.edu /** Serialize state. */ 3392864Sktlim@umich.edu virtual void serialize(std::ostream &os); 3402864Sktlim@umich.edu 3412864Sktlim@umich.edu /** Unserialize from a checkpoint. */ 3422864Sktlim@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 3432864Sktlim@umich.edu 3442864Sktlim@umich.edu public: 3455595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 3465595Sgblack@eecs.umich.edu /** Executes a syscall. 3475595Sgblack@eecs.umich.edu * @todo: Determine if this needs to be virtual. 3482292SN/A */ 3495595Sgblack@eecs.umich.edu void syscall(int64_t callnum, int tid); 3505595Sgblack@eecs.umich.edu#endif 3512292SN/A 3522843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 3532843Sktlim@umich.edu * order to stop all memory accesses. */ 3542905Sktlim@umich.edu virtual unsigned int drain(Event *drain_event); 3552843Sktlim@umich.edu 3562843Sktlim@umich.edu /** Resumes execution after a drain. */ 3572843Sktlim@umich.edu virtual void resume(); 3582292SN/A 3592348SN/A /** Signals to this CPU that a stage has completed switching out. */ 3602843Sktlim@umich.edu void signalDrained(); 3612843Sktlim@umich.edu 3622843Sktlim@umich.edu /** Switches out this CPU. */ 3632843Sktlim@umich.edu virtual void switchOut(); 3642316SN/A 3652348SN/A /** Takes over from another CPU. */ 3662843Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *oldCPU); 3671060SN/A 3681060SN/A /** Get the current instruction sequence number, and increment it. */ 3692316SN/A InstSeqNum getAndIncrementInstSeq() 3702316SN/A { return globalSeqNum++; } 3711060SN/A 3725595Sgblack@eecs.umich.edu /** Traps to handle given fault. */ 3735595Sgblack@eecs.umich.edu void trap(Fault fault, unsigned tid); 3745595Sgblack@eecs.umich.edu 3751858SN/A#if FULL_SYSTEM 3765702Ssaidi@eecs.umich.edu /** HW return from error interrupt. */ 3775702Ssaidi@eecs.umich.edu Fault hwrei(unsigned tid); 3785702Ssaidi@eecs.umich.edu 3795702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc, unsigned tid); 3805702Ssaidi@eecs.umich.edu 3815595Sgblack@eecs.umich.edu /** Returns the Fault for any valid interrupt. */ 3825595Sgblack@eecs.umich.edu Fault getInterrupts(); 3835595Sgblack@eecs.umich.edu 3845595Sgblack@eecs.umich.edu /** Processes any an interrupt fault. */ 3855595Sgblack@eecs.umich.edu void processInterrupts(Fault interrupt); 3865595Sgblack@eecs.umich.edu 3875595Sgblack@eecs.umich.edu /** Halts the CPU. */ 3885595Sgblack@eecs.umich.edu void halt() { panic("Halt not implemented!\n"); } 3895595Sgblack@eecs.umich.edu 3904192Sktlim@umich.edu /** Update the Virt and Phys ports of all ThreadContexts to 3914192Sktlim@umich.edu * reflect change in memory connections. */ 3924192Sktlim@umich.edu void updateMemPorts(); 3934192Sktlim@umich.edu 3941060SN/A /** Check if this address is a valid instruction address. */ 3951060SN/A bool validInstAddr(Addr addr) { return true; } 3961060SN/A 3971060SN/A /** Check if this address is a valid data address. */ 3981060SN/A bool validDataAddr(Addr addr) { return true; } 3991060SN/A 4001060SN/A /** Get instruction asid. */ 4012292SN/A int getInstAsid(unsigned tid) 4022292SN/A { return regFile.miscRegs[tid].getInstAsid(); } 4031060SN/A 4041060SN/A /** Get data asid. */ 4052292SN/A int getDataAsid(unsigned tid) 4062292SN/A { return regFile.miscRegs[tid].getDataAsid(); } 4071060SN/A#else 4082292SN/A /** Get instruction asid. */ 4092292SN/A int getInstAsid(unsigned tid) 4102683Sktlim@umich.edu { return thread[tid]->getInstAsid(); } 4111060SN/A 4122292SN/A /** Get data asid. */ 4132292SN/A int getDataAsid(unsigned tid) 4142683Sktlim@umich.edu { return thread[tid]->getDataAsid(); } 4151060SN/A 4161060SN/A#endif 4171060SN/A 4182348SN/A /** Register accessors. Index refers to the physical register index. */ 4195595Sgblack@eecs.umich.edu 4205595Sgblack@eecs.umich.edu /** Reads a miscellaneous register. */ 4215595Sgblack@eecs.umich.edu TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid); 4225595Sgblack@eecs.umich.edu 4235595Sgblack@eecs.umich.edu /** Reads a misc. register, including any side effects the read 4245595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4255595Sgblack@eecs.umich.edu */ 4265595Sgblack@eecs.umich.edu TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); 4275595Sgblack@eecs.umich.edu 4285595Sgblack@eecs.umich.edu /** Sets a miscellaneous register. */ 4295595Sgblack@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid); 4305595Sgblack@eecs.umich.edu 4315595Sgblack@eecs.umich.edu /** Sets a misc. register, including any side effects the write 4325595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4335595Sgblack@eecs.umich.edu */ 4345595Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 4355595Sgblack@eecs.umich.edu unsigned tid); 4365595Sgblack@eecs.umich.edu 4371060SN/A uint64_t readIntReg(int reg_idx); 4381060SN/A 4393781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx); 4401060SN/A 4413781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx, int width); 4421060SN/A 4433781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx); 4442455SN/A 4453781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width); 4461060SN/A 4471060SN/A void setIntReg(int reg_idx, uint64_t val); 4481060SN/A 4493781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val); 4501060SN/A 4513781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val, int width); 4521060SN/A 4533781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 4542455SN/A 4553781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width); 4561060SN/A 4572292SN/A uint64_t readArchIntReg(int reg_idx, unsigned tid); 4581060SN/A 4592292SN/A float readArchFloatRegSingle(int reg_idx, unsigned tid); 4601060SN/A 4612292SN/A double readArchFloatRegDouble(int reg_idx, unsigned tid); 4622292SN/A 4632292SN/A uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 4642292SN/A 4652348SN/A /** Architectural register accessors. Looks up in the commit 4662348SN/A * rename table to obtain the true physical index of the 4672348SN/A * architected register first, then accesses that physical 4682348SN/A * register. 4692348SN/A */ 4702292SN/A void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 4712292SN/A 4722292SN/A void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 4732292SN/A 4742292SN/A void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 4752292SN/A 4762292SN/A void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 4772292SN/A 4782348SN/A /** Reads the commit PC of a specific thread. */ 4794636Sgblack@eecs.umich.edu Addr readPC(unsigned tid); 4802292SN/A 4812348SN/A /** Sets the commit PC of a specific thread. */ 4822348SN/A void setPC(Addr new_PC, unsigned tid); 4832292SN/A 4844636Sgblack@eecs.umich.edu /** Reads the commit micro PC of a specific thread. */ 4854636Sgblack@eecs.umich.edu Addr readMicroPC(unsigned tid); 4864636Sgblack@eecs.umich.edu 4874636Sgblack@eecs.umich.edu /** Sets the commmit micro PC of a specific thread. */ 4884636Sgblack@eecs.umich.edu void setMicroPC(Addr new_microPC, unsigned tid); 4894636Sgblack@eecs.umich.edu 4902348SN/A /** Reads the next PC of a specific thread. */ 4914636Sgblack@eecs.umich.edu Addr readNextPC(unsigned tid); 4922292SN/A 4932348SN/A /** Sets the next PC of a specific thread. */ 4944636Sgblack@eecs.umich.edu void setNextPC(Addr val, unsigned tid); 4951060SN/A 4962756Sksewell@umich.edu /** Reads the next NPC of a specific thread. */ 4974636Sgblack@eecs.umich.edu Addr readNextNPC(unsigned tid); 4982756Sksewell@umich.edu 4992756Sksewell@umich.edu /** Sets the next NPC of a specific thread. */ 5004636Sgblack@eecs.umich.edu void setNextNPC(Addr val, unsigned tid); 5014636Sgblack@eecs.umich.edu 5024636Sgblack@eecs.umich.edu /** Reads the commit next micro PC of a specific thread. */ 5034636Sgblack@eecs.umich.edu Addr readNextMicroPC(unsigned tid); 5044636Sgblack@eecs.umich.edu 5054636Sgblack@eecs.umich.edu /** Sets the commit next micro PC of a specific thread. */ 5064636Sgblack@eecs.umich.edu void setNextMicroPC(Addr val, unsigned tid); 5072756Sksewell@umich.edu 5085595Sgblack@eecs.umich.edu /** Initiates a squash of all in-flight instructions for a given 5095595Sgblack@eecs.umich.edu * thread. The source of the squash is an external update of 5105595Sgblack@eecs.umich.edu * state through the TC. 5115595Sgblack@eecs.umich.edu */ 5125595Sgblack@eecs.umich.edu void squashFromTC(unsigned tid); 5135595Sgblack@eecs.umich.edu 5141060SN/A /** Function to add instruction onto the head of the list of the 5151060SN/A * instructions. Used when new instructions are fetched. 5161060SN/A */ 5172292SN/A ListIt addInst(DynInstPtr &inst); 5181060SN/A 5191060SN/A /** Function to tell the CPU that an instruction has completed. */ 5202292SN/A void instDone(unsigned tid); 5211060SN/A 5222292SN/A /** Add Instructions to the CPU Remove List*/ 5232292SN/A void addToRemoveList(DynInstPtr &inst); 5241060SN/A 5252325SN/A /** Remove an instruction from the front end of the list. There's 5262325SN/A * no restriction on location of the instruction. 5271060SN/A */ 5281061SN/A void removeFrontInst(DynInstPtr &inst); 5291060SN/A 5302935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 5312935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 5324632Sgblack@eecs.umich.edu void removeInstsNotInROB(unsigned tid); 5331060SN/A 5341062SN/A /** Remove all instructions younger than the given sequence number. */ 5352292SN/A void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 5362292SN/A 5372348SN/A /** Removes the instruction pointed to by the iterator. */ 5382292SN/A inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 5392292SN/A 5402348SN/A /** Cleans up all instructions on the remove list. */ 5412292SN/A void cleanUpRemovedInsts(); 5421062SN/A 5432348SN/A /** Debug function to print all instructions on the list. */ 5441060SN/A void dumpInsts(); 5451060SN/A 5461060SN/A public: 5475737Scws3k@cs.virginia.edu#ifndef NDEBUG 5485737Scws3k@cs.virginia.edu /** Count of total number of dynamic instructions in flight. */ 5495737Scws3k@cs.virginia.edu int instcount; 5505737Scws3k@cs.virginia.edu#endif 5515737Scws3k@cs.virginia.edu 5521060SN/A /** List of all the instructions in flight. */ 5532292SN/A std::list<DynInstPtr> instList; 5541060SN/A 5552292SN/A /** List of all the instructions that will be removed at the end of this 5562292SN/A * cycle. 5572292SN/A */ 5582292SN/A std::queue<ListIt> removeList; 5592292SN/A 5602325SN/A#ifdef DEBUG 5612348SN/A /** Debug structure to keep track of the sequence numbers still in 5622348SN/A * flight. 5632348SN/A */ 5642292SN/A std::set<InstSeqNum> snList; 5652325SN/A#endif 5662292SN/A 5672325SN/A /** Records if instructions need to be removed this cycle due to 5682325SN/A * being retired or squashed. 5692292SN/A */ 5702292SN/A bool removeInstsThisCycle; 5712292SN/A 5721060SN/A protected: 5731060SN/A /** The fetch stage. */ 5741060SN/A typename CPUPolicy::Fetch fetch; 5751060SN/A 5761060SN/A /** The decode stage. */ 5771060SN/A typename CPUPolicy::Decode decode; 5781060SN/A 5791060SN/A /** The dispatch stage. */ 5801060SN/A typename CPUPolicy::Rename rename; 5811060SN/A 5821060SN/A /** The issue/execute/writeback stages. */ 5831060SN/A typename CPUPolicy::IEW iew; 5841060SN/A 5851060SN/A /** The commit stage. */ 5861060SN/A typename CPUPolicy::Commit commit; 5871060SN/A 5881060SN/A /** The register file. */ 5891060SN/A typename CPUPolicy::RegFile regFile; 5901060SN/A 5911060SN/A /** The free list. */ 5921060SN/A typename CPUPolicy::FreeList freeList; 5931060SN/A 5941060SN/A /** The rename map. */ 5952292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 5962292SN/A 5972292SN/A /** The commit rename map. */ 5982292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 5991060SN/A 6001060SN/A /** The re-order buffer. */ 6011060SN/A typename CPUPolicy::ROB rob; 6021060SN/A 6032292SN/A /** Active Threads List */ 6042292SN/A std::list<unsigned> activeThreads; 6052292SN/A 6062292SN/A /** Integer Register Scoreboard */ 6072292SN/A Scoreboard scoreboard; 6082292SN/A 6091060SN/A public: 6102292SN/A /** Enum to give each stage a specific index, so when calling 6112292SN/A * activateStage() or deactivateStage(), they can specify which stage 6122292SN/A * is being activated/deactivated. 6132292SN/A */ 6142292SN/A enum StageIdx { 6152292SN/A FetchIdx, 6162292SN/A DecodeIdx, 6172292SN/A RenameIdx, 6182292SN/A IEWIdx, 6192292SN/A CommitIdx, 6202292SN/A NumStages }; 6212292SN/A 6221060SN/A /** Typedefs from the Impl to get the structs that each of the 6231060SN/A * time buffers should use. 6241060SN/A */ 6251061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 6261060SN/A 6271061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 6281060SN/A 6291061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 6301060SN/A 6311061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 6321060SN/A 6331061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 6341060SN/A 6351060SN/A /** The main time buffer to do backwards communication. */ 6361060SN/A TimeBuffer<TimeStruct> timeBuffer; 6371060SN/A 6381060SN/A /** The fetch stage's instruction queue. */ 6391060SN/A TimeBuffer<FetchStruct> fetchQueue; 6401060SN/A 6411060SN/A /** The decode stage's instruction queue. */ 6421060SN/A TimeBuffer<DecodeStruct> decodeQueue; 6431060SN/A 6441060SN/A /** The rename stage's instruction queue. */ 6451060SN/A TimeBuffer<RenameStruct> renameQueue; 6461060SN/A 6471060SN/A /** The IEW stage's instruction queue. */ 6481060SN/A TimeBuffer<IEWStruct> iewQueue; 6491060SN/A 6502348SN/A private: 6512348SN/A /** The activity recorder; used to tell if the CPU has any 6522348SN/A * activity remaining or if it can go to idle and deschedule 6532348SN/A * itself. 6542348SN/A */ 6552325SN/A ActivityRecorder activityRec; 6561060SN/A 6572348SN/A public: 6582348SN/A /** Records that there was time buffer activity this cycle. */ 6592325SN/A void activityThisCycle() { activityRec.activity(); } 6602292SN/A 6612348SN/A /** Changes a stage's status to active within the activity recorder. */ 6622325SN/A void activateStage(const StageIdx idx) 6632325SN/A { activityRec.activateStage(idx); } 6642292SN/A 6652348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 6662325SN/A void deactivateStage(const StageIdx idx) 6672325SN/A { activityRec.deactivateStage(idx); } 6682292SN/A 6692292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 6702292SN/A void wakeCPU(); 6712260SN/A 6725807Snate@binkert.org#if FULL_SYSTEM 6735807Snate@binkert.org virtual void wakeup(); 6745807Snate@binkert.org#endif 6755807Snate@binkert.org 6762292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 6772292SN/A int getFreeTid(); 6782292SN/A 6792292SN/A public: 6802680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 6812680Sktlim@umich.edu ThreadContext *tcBase(unsigned tid) 6821681SN/A { 6832680Sktlim@umich.edu return thread[tid]->getTC(); 6842190SN/A } 6852190SN/A 6862292SN/A /** The global sequence number counter. */ 6873093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 6881060SN/A 6894598Sbinkertn@umich.edu#if USE_CHECKER 6902348SN/A /** Pointer to the checker, which can dynamically verify 6912348SN/A * instruction results at run time. This can be set to NULL if it 6922348SN/A * is not being used. 6932348SN/A */ 6942316SN/A Checker<DynInstPtr> *checker; 6954598Sbinkertn@umich.edu#endif 6962316SN/A 6971858SN/A#if FULL_SYSTEM 6982292SN/A /** Pointer to the system. */ 6991060SN/A System *system; 7001060SN/A 7012292SN/A /** Pointer to physical memory. */ 7021060SN/A PhysicalMemory *physmem; 7032292SN/A#endif 7041060SN/A 7052843Sktlim@umich.edu /** Event to call process() on once draining has completed. */ 7062843Sktlim@umich.edu Event *drainEvent; 7072843Sktlim@umich.edu 7082843Sktlim@umich.edu /** Counter of how many stages have completed draining. */ 7092843Sktlim@umich.edu int drainCount; 7102316SN/A 7112348SN/A /** Pointers to all of the threads in the CPU. */ 7122292SN/A std::vector<Thread *> thread; 7132260SN/A 7142292SN/A /** Whether or not the CPU should defer its registration. */ 7151060SN/A bool deferRegistration; 7161060SN/A 7172292SN/A /** Is there a context switch pending? */ 7182292SN/A bool contextSwitch; 7191060SN/A 7202292SN/A /** Threads Scheduled to Enter CPU */ 7212292SN/A std::list<int> cpuWaitList; 7222292SN/A 7232292SN/A /** The cycle that the CPU was last running, used for statistics. */ 7242292SN/A Tick lastRunningCycle; 7252292SN/A 7262829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 7272829Sksewell@umich.edu Tick lastActivatedCycle; 7282829Sksewell@umich.edu 7292292SN/A /** Number of Threads CPU can process */ 7302292SN/A unsigned numThreads; 7312292SN/A 7322292SN/A /** Mapping for system thread id to cpu id */ 7332292SN/A std::map<unsigned,unsigned> threadMap; 7342292SN/A 7352292SN/A /** Available thread ids in the cpu*/ 7362292SN/A std::vector<unsigned> tids; 7372292SN/A 7385595Sgblack@eecs.umich.edu /** CPU read function, forwards read to LSQ. */ 7395595Sgblack@eecs.umich.edu template <class T> 7405595Sgblack@eecs.umich.edu Fault read(RequestPtr &req, T &data, int load_idx) 7415595Sgblack@eecs.umich.edu { 7425595Sgblack@eecs.umich.edu return this->iew.ldstQueue.read(req, data, load_idx); 7435595Sgblack@eecs.umich.edu } 7445595Sgblack@eecs.umich.edu 7455595Sgblack@eecs.umich.edu /** CPU write function, forwards write to LSQ. */ 7465595Sgblack@eecs.umich.edu template <class T> 7475595Sgblack@eecs.umich.edu Fault write(RequestPtr &req, T &data, int store_idx) 7485595Sgblack@eecs.umich.edu { 7495595Sgblack@eecs.umich.edu return this->iew.ldstQueue.write(req, data, store_idx); 7505595Sgblack@eecs.umich.edu } 7515595Sgblack@eecs.umich.edu 7525595Sgblack@eecs.umich.edu Addr lockAddr; 7535595Sgblack@eecs.umich.edu 7545595Sgblack@eecs.umich.edu /** Temporary fix for the lock flag, works in the UP case. */ 7555595Sgblack@eecs.umich.edu bool lockFlag; 7565595Sgblack@eecs.umich.edu 7572292SN/A /** Stat for total number of times the CPU is descheduled. */ 7585999Snate@binkert.org Stats::Scalar timesIdled; 7592292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 7605999Snate@binkert.org Stats::Scalar idleCycles; 7612292SN/A /** Stat for the number of committed instructions per thread. */ 7625999Snate@binkert.org Stats::Vector committedInsts; 7632292SN/A /** Stat for the total number of committed instructions. */ 7645999Snate@binkert.org Stats::Scalar totalCommittedInsts; 7652292SN/A /** Stat for the CPI per thread. */ 7662292SN/A Stats::Formula cpi; 7672292SN/A /** Stat for the total CPI. */ 7682292SN/A Stats::Formula totalCpi; 7692292SN/A /** Stat for the IPC per thread. */ 7702292SN/A Stats::Formula ipc; 7712292SN/A /** Stat for the total IPC. */ 7722292SN/A Stats::Formula totalIpc; 7731060SN/A}; 7741060SN/A 7752325SN/A#endif // __CPU_O3_CPU_HH__ 776