cpu.hh revision 5336
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322325SN/A#ifndef __CPU_O3_CPU_HH__ 332325SN/A#define __CPU_O3_CPU_HH__ 341060SN/A 351060SN/A#include <iostream> 361060SN/A#include <list> 372292SN/A#include <queue> 382292SN/A#include <set> 391681SN/A#include <vector> 401060SN/A 412980Sgblack@eecs.umich.edu#include "arch/types.hh" 421060SN/A#include "base/statistics.hh" 431060SN/A#include "base/timebuf.hh" 441858SN/A#include "config/full_system.hh" 454598Sbinkertn@umich.edu#include "config/use_checker.hh" 462325SN/A#include "cpu/activity.hh" 471717SN/A#include "cpu/base.hh" 482683Sktlim@umich.edu#include "cpu/simple_thread.hh" 491717SN/A#include "cpu/o3/comm.hh" 501717SN/A#include "cpu/o3/cpu_policy.hh" 512292SN/A#include "cpu/o3/scoreboard.hh" 522292SN/A#include "cpu/o3/thread_state.hh" 532817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 541060SN/A#include "sim/process.hh" 551060SN/A 562316SN/Atemplate <class> 572316SN/Aclass Checker; 582680Sktlim@umich.educlass ThreadContext; 592817Sksewell@umich.edutemplate <class> 602817Sksewell@umich.educlass O3ThreadContext; 612843Sktlim@umich.edu 622843Sktlim@umich.educlass Checkpoint; 632669Sktlim@umich.educlass MemObject; 641060SN/Aclass Process; 651060SN/A 662733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 671060SN/A{ 681060SN/A //Stuff that's pretty ISA independent will go here. 691060SN/A public: 701464SN/A typedef BaseCPU::Params Params; 711061SN/A 722733Sktlim@umich.edu BaseO3CPU(Params *params); 732292SN/A 742292SN/A void regStats(); 752632Sstever@eecs.umich.edu 762817Sksewell@umich.edu /** Sets this CPU's ID. */ 772817Sksewell@umich.edu void setCpuId(int id) { cpu_id = id; } 782817Sksewell@umich.edu 792817Sksewell@umich.edu /** Reads this CPU's ID. */ 802669Sktlim@umich.edu int readCpuId() { return cpu_id; } 811681SN/A 821685SN/A protected: 831681SN/A int cpu_id; 841060SN/A}; 851060SN/A 862348SN/A/** 872348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 882348SN/A * within it, as well as all of the time buffers between stages. The 892348SN/A * tick() function for the CPU is defined here. 902348SN/A */ 911060SN/Atemplate <class Impl> 922733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 931060SN/A{ 941060SN/A public: 952325SN/A // Typedefs from the Impl here. 961060SN/A typedef typename Impl::CPUPol CPUPolicy; 971061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 984329Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 994988Sgblack@eecs.umich.edu typedef typename Impl::Params Params; 1001060SN/A 1012292SN/A typedef O3ThreadState<Impl> Thread; 1022292SN/A 1032292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1042292SN/A 1052817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1062829Sksewell@umich.edu 1071060SN/A public: 1081060SN/A enum Status { 1091060SN/A Running, 1101060SN/A Idle, 1111060SN/A Halted, 1122307SN/A Blocked, 1132307SN/A SwitchedOut 1141060SN/A }; 1151060SN/A 1163781Sgblack@eecs.umich.edu TheISA::ITB * itb; 1173781Sgblack@eecs.umich.edu TheISA::DTB * dtb; 1183781Sgblack@eecs.umich.edu 1192292SN/A /** Overall CPU status. */ 1201060SN/A Status _status; 1211060SN/A 1222829Sksewell@umich.edu /** Per-thread status in CPU, used for SMT. */ 1232829Sksewell@umich.edu Status _threadStatus[Impl::MaxThreads]; 1242829Sksewell@umich.edu 1251060SN/A private: 1261060SN/A class TickEvent : public Event 1271060SN/A { 1281060SN/A private: 1292292SN/A /** Pointer to the CPU. */ 1301755SN/A FullO3CPU<Impl> *cpu; 1311060SN/A 1321060SN/A public: 1332292SN/A /** Constructs a tick event. */ 1341755SN/A TickEvent(FullO3CPU<Impl> *c); 1352292SN/A 1362292SN/A /** Processes a tick event, calling tick() on the CPU. */ 1371060SN/A void process(); 1382292SN/A /** Returns the description of the tick event. */ 1395336Shines@cs.fsu.edu const char *description() const; 1401060SN/A }; 1411060SN/A 1422292SN/A /** The tick event used for scheduling CPU ticks. */ 1431060SN/A TickEvent tickEvent; 1441060SN/A 1452292SN/A /** Schedule tick event, regardless of its current state. */ 1461060SN/A void scheduleTickEvent(int delay) 1471060SN/A { 1481060SN/A if (tickEvent.squashed()) 1495100Ssaidi@eecs.umich.edu tickEvent.reschedule(nextCycle(curTick + ticks(delay))); 1501060SN/A else if (!tickEvent.scheduled()) 1515100Ssaidi@eecs.umich.edu tickEvent.schedule(nextCycle(curTick + ticks(delay))); 1521060SN/A } 1531060SN/A 1542292SN/A /** Unschedule tick event, regardless of its current state. */ 1551060SN/A void unscheduleTickEvent() 1561060SN/A { 1571060SN/A if (tickEvent.scheduled()) 1581060SN/A tickEvent.squash(); 1591060SN/A } 1601060SN/A 1612829Sksewell@umich.edu class ActivateThreadEvent : public Event 1622829Sksewell@umich.edu { 1632829Sksewell@umich.edu private: 1642829Sksewell@umich.edu /** Number of Thread to Activate */ 1652829Sksewell@umich.edu int tid; 1662829Sksewell@umich.edu 1672829Sksewell@umich.edu /** Pointer to the CPU. */ 1682829Sksewell@umich.edu FullO3CPU<Impl> *cpu; 1692829Sksewell@umich.edu 1702829Sksewell@umich.edu public: 1712829Sksewell@umich.edu /** Constructs the event. */ 1722829Sksewell@umich.edu ActivateThreadEvent(); 1732829Sksewell@umich.edu 1742829Sksewell@umich.edu /** Initialize Event */ 1752829Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 1762829Sksewell@umich.edu 1772829Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 1782829Sksewell@umich.edu void process(); 1792829Sksewell@umich.edu 1802829Sksewell@umich.edu /** Returns the description of the event. */ 1815336Shines@cs.fsu.edu const char *description() const; 1822829Sksewell@umich.edu }; 1832829Sksewell@umich.edu 1842829Sksewell@umich.edu /** Schedule thread to activate , regardless of its current state. */ 1852829Sksewell@umich.edu void scheduleActivateThreadEvent(int tid, int delay) 1862829Sksewell@umich.edu { 1872829Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 1882829Sksewell@umich.edu if (activateThreadEvent[tid].squashed()) 1894030Sktlim@umich.edu activateThreadEvent[tid]. 1905100Ssaidi@eecs.umich.edu reschedule(nextCycle(curTick + ticks(delay))); 1912829Sksewell@umich.edu else if (!activateThreadEvent[tid].scheduled()) 1924030Sktlim@umich.edu activateThreadEvent[tid]. 1935100Ssaidi@eecs.umich.edu schedule(nextCycle(curTick + ticks(delay))); 1942829Sksewell@umich.edu } 1952829Sksewell@umich.edu 1962829Sksewell@umich.edu /** Unschedule actiavte thread event, regardless of its current state. */ 1972829Sksewell@umich.edu void unscheduleActivateThreadEvent(int tid) 1982829Sksewell@umich.edu { 1992829Sksewell@umich.edu if (activateThreadEvent[tid].scheduled()) 2002829Sksewell@umich.edu activateThreadEvent[tid].squash(); 2012829Sksewell@umich.edu } 2022829Sksewell@umich.edu 2032829Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2042829Sksewell@umich.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 2052829Sksewell@umich.edu 2062875Sksewell@umich.edu class DeallocateContextEvent : public Event 2072875Sksewell@umich.edu { 2082875Sksewell@umich.edu private: 2093221Sktlim@umich.edu /** Number of Thread to deactivate */ 2102875Sksewell@umich.edu int tid; 2112875Sksewell@umich.edu 2123221Sktlim@umich.edu /** Should the thread be removed from the CPU? */ 2133221Sktlim@umich.edu bool remove; 2143221Sktlim@umich.edu 2152875Sksewell@umich.edu /** Pointer to the CPU. */ 2162875Sksewell@umich.edu FullO3CPU<Impl> *cpu; 2172875Sksewell@umich.edu 2182875Sksewell@umich.edu public: 2192875Sksewell@umich.edu /** Constructs the event. */ 2202875Sksewell@umich.edu DeallocateContextEvent(); 2212875Sksewell@umich.edu 2222875Sksewell@umich.edu /** Initialize Event */ 2232875Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 2242875Sksewell@umich.edu 2252875Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 2262875Sksewell@umich.edu void process(); 2272875Sksewell@umich.edu 2283221Sktlim@umich.edu /** Sets whether the thread should also be removed from the CPU. */ 2293221Sktlim@umich.edu void setRemove(bool _remove) { remove = _remove; } 2303221Sktlim@umich.edu 2312875Sksewell@umich.edu /** Returns the description of the event. */ 2325336Shines@cs.fsu.edu const char *description() const; 2332875Sksewell@umich.edu }; 2342875Sksewell@umich.edu 2352875Sksewell@umich.edu /** Schedule cpu to deallocate thread context.*/ 2363221Sktlim@umich.edu void scheduleDeallocateContextEvent(int tid, bool remove, int delay) 2372875Sksewell@umich.edu { 2382875Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 2392875Sksewell@umich.edu if (deallocateContextEvent[tid].squashed()) 2404030Sktlim@umich.edu deallocateContextEvent[tid]. 2415100Ssaidi@eecs.umich.edu reschedule(nextCycle(curTick + ticks(delay))); 2422875Sksewell@umich.edu else if (!deallocateContextEvent[tid].scheduled()) 2434030Sktlim@umich.edu deallocateContextEvent[tid]. 2445100Ssaidi@eecs.umich.edu schedule(nextCycle(curTick + ticks(delay))); 2452875Sksewell@umich.edu } 2462875Sksewell@umich.edu 2472875Sksewell@umich.edu /** Unschedule thread deallocation in CPU */ 2482875Sksewell@umich.edu void unscheduleDeallocateContextEvent(int tid) 2492875Sksewell@umich.edu { 2502875Sksewell@umich.edu if (deallocateContextEvent[tid].scheduled()) 2512875Sksewell@umich.edu deallocateContextEvent[tid].squash(); 2522875Sksewell@umich.edu } 2532875Sksewell@umich.edu 2542875Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2552875Sksewell@umich.edu DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 2562875Sksewell@umich.edu 2571060SN/A public: 2582292SN/A /** Constructs a CPU with the given parameters. */ 2594329Sktlim@umich.edu FullO3CPU(O3CPU *o3_cpu, Params *params); 2602292SN/A /** Destructor. */ 2611755SN/A ~FullO3CPU(); 2621060SN/A 2632292SN/A /** Registers statistics. */ 2641684SN/A void fullCPURegStats(); 2651684SN/A 2664988Sgblack@eecs.umich.edu /** Translates instruction requestion. */ 2674988Sgblack@eecs.umich.edu Fault translateInstReq(RequestPtr &req, Thread *thread) 2684988Sgblack@eecs.umich.edu { 2694988Sgblack@eecs.umich.edu return this->itb->translate(req, thread->getTC()); 2704988Sgblack@eecs.umich.edu } 2714988Sgblack@eecs.umich.edu 2724988Sgblack@eecs.umich.edu /** Translates data read request. */ 2734988Sgblack@eecs.umich.edu Fault translateDataReadReq(RequestPtr &req, Thread *thread) 2744988Sgblack@eecs.umich.edu { 2754988Sgblack@eecs.umich.edu return this->dtb->translate(req, thread->getTC(), false); 2764988Sgblack@eecs.umich.edu } 2774988Sgblack@eecs.umich.edu 2784988Sgblack@eecs.umich.edu /** Translates data write request. */ 2794988Sgblack@eecs.umich.edu Fault translateDataWriteReq(RequestPtr &req, Thread *thread) 2804988Sgblack@eecs.umich.edu { 2814988Sgblack@eecs.umich.edu return this->dtb->translate(req, thread->getTC(), true); 2824988Sgblack@eecs.umich.edu } 2834988Sgblack@eecs.umich.edu 2842871Sktlim@umich.edu /** Returns a specific port. */ 2852871Sktlim@umich.edu Port *getPort(const std::string &if_name, int idx); 2862871Sktlim@umich.edu 2872292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 2882292SN/A * activity to see if the CPU should deschedule itself. 2892292SN/A */ 2901684SN/A void tick(); 2911684SN/A 2922292SN/A /** Initialize the CPU */ 2931060SN/A void init(); 2941060SN/A 2952834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 2962834Sksewell@umich.edu int numActiveThreads() 2972834Sksewell@umich.edu { return activeThreads.size(); } 2982834Sksewell@umich.edu 2992829Sksewell@umich.edu /** Add Thread to Active Threads List */ 3002875Sksewell@umich.edu void activateThread(unsigned tid); 3012875Sksewell@umich.edu 3022875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 3032875Sksewell@umich.edu void deactivateThread(unsigned tid); 3042829Sksewell@umich.edu 3052292SN/A /** Setup CPU to insert a thread's context */ 3062292SN/A void insertThread(unsigned tid); 3071060SN/A 3082292SN/A /** Remove all of a thread's context from CPU */ 3092292SN/A void removeThread(unsigned tid); 3102292SN/A 3112292SN/A /** Count the Total Instructions Committed in the CPU. */ 3122292SN/A virtual Counter totalInstructions() const 3132292SN/A { 3142292SN/A Counter total(0); 3152292SN/A 3162292SN/A for (int i=0; i < thread.size(); i++) 3172292SN/A total += thread[i]->numInst; 3182292SN/A 3192292SN/A return total; 3202292SN/A } 3212292SN/A 3222292SN/A /** Add Thread to Active Threads List. */ 3232292SN/A void activateContext(int tid, int delay); 3242292SN/A 3252292SN/A /** Remove Thread from Active Threads List */ 3262292SN/A void suspendContext(int tid); 3272292SN/A 3282292SN/A /** Remove Thread from Active Threads List && 3293221Sktlim@umich.edu * Possibly Remove Thread Context from CPU. 3302292SN/A */ 3313221Sktlim@umich.edu bool deallocateContext(int tid, bool remove, int delay = 1); 3322292SN/A 3332292SN/A /** Remove Thread from Active Threads List && 3342292SN/A * Remove Thread Context from CPU. 3352292SN/A */ 3362292SN/A void haltContext(int tid); 3372292SN/A 3382292SN/A /** Activate a Thread When CPU Resources are Available. */ 3392292SN/A void activateWhenReady(int tid); 3402292SN/A 3412292SN/A /** Add or Remove a Thread Context in the CPU. */ 3422292SN/A void doContextSwitch(); 3432292SN/A 3442292SN/A /** Update The Order In Which We Process Threads. */ 3452292SN/A void updateThreadPriority(); 3462292SN/A 3472864Sktlim@umich.edu /** Serialize state. */ 3482864Sktlim@umich.edu virtual void serialize(std::ostream &os); 3492864Sktlim@umich.edu 3502864Sktlim@umich.edu /** Unserialize from a checkpoint. */ 3512864Sktlim@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 3522864Sktlim@umich.edu 3532864Sktlim@umich.edu public: 3542292SN/A /** Executes a syscall on this cycle. 3552292SN/A * --------------------------------------- 3562292SN/A * Note: this is a virtual function. CPU-Specific 3572292SN/A * functionality defined in derived classes 3582292SN/A */ 3592325SN/A virtual void syscall(int tid) { panic("Unimplemented!"); } 3602292SN/A 3612843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 3622843Sktlim@umich.edu * order to stop all memory accesses. */ 3632905Sktlim@umich.edu virtual unsigned int drain(Event *drain_event); 3642843Sktlim@umich.edu 3652843Sktlim@umich.edu /** Resumes execution after a drain. */ 3662843Sktlim@umich.edu virtual void resume(); 3672292SN/A 3682348SN/A /** Signals to this CPU that a stage has completed switching out. */ 3692843Sktlim@umich.edu void signalDrained(); 3702843Sktlim@umich.edu 3712843Sktlim@umich.edu /** Switches out this CPU. */ 3722843Sktlim@umich.edu virtual void switchOut(); 3732316SN/A 3742348SN/A /** Takes over from another CPU. */ 3752843Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *oldCPU); 3761060SN/A 3771060SN/A /** Get the current instruction sequence number, and increment it. */ 3782316SN/A InstSeqNum getAndIncrementInstSeq() 3792316SN/A { return globalSeqNum++; } 3801060SN/A 3811858SN/A#if FULL_SYSTEM 3824192Sktlim@umich.edu /** Update the Virt and Phys ports of all ThreadContexts to 3834192Sktlim@umich.edu * reflect change in memory connections. */ 3844192Sktlim@umich.edu void updateMemPorts(); 3854192Sktlim@umich.edu 3861060SN/A /** Check if this address is a valid instruction address. */ 3871060SN/A bool validInstAddr(Addr addr) { return true; } 3881060SN/A 3891060SN/A /** Check if this address is a valid data address. */ 3901060SN/A bool validDataAddr(Addr addr) { return true; } 3911060SN/A 3921060SN/A /** Get instruction asid. */ 3932292SN/A int getInstAsid(unsigned tid) 3942292SN/A { return regFile.miscRegs[tid].getInstAsid(); } 3951060SN/A 3961060SN/A /** Get data asid. */ 3972292SN/A int getDataAsid(unsigned tid) 3982292SN/A { return regFile.miscRegs[tid].getDataAsid(); } 3991060SN/A#else 4002292SN/A /** Get instruction asid. */ 4012292SN/A int getInstAsid(unsigned tid) 4022683Sktlim@umich.edu { return thread[tid]->getInstAsid(); } 4031060SN/A 4042292SN/A /** Get data asid. */ 4052292SN/A int getDataAsid(unsigned tid) 4062683Sktlim@umich.edu { return thread[tid]->getDataAsid(); } 4071060SN/A 4081060SN/A#endif 4091060SN/A 4102348SN/A /** Register accessors. Index refers to the physical register index. */ 4111060SN/A uint64_t readIntReg(int reg_idx); 4121060SN/A 4133781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx); 4141060SN/A 4153781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx, int width); 4161060SN/A 4173781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx); 4182455SN/A 4193781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width); 4201060SN/A 4211060SN/A void setIntReg(int reg_idx, uint64_t val); 4221060SN/A 4233781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val); 4241060SN/A 4253781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val, int width); 4261060SN/A 4273781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 4282455SN/A 4293781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width); 4301060SN/A 4312292SN/A uint64_t readArchIntReg(int reg_idx, unsigned tid); 4321060SN/A 4332292SN/A float readArchFloatRegSingle(int reg_idx, unsigned tid); 4341060SN/A 4352292SN/A double readArchFloatRegDouble(int reg_idx, unsigned tid); 4362292SN/A 4372292SN/A uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 4382292SN/A 4392348SN/A /** Architectural register accessors. Looks up in the commit 4402348SN/A * rename table to obtain the true physical index of the 4412348SN/A * architected register first, then accesses that physical 4422348SN/A * register. 4432348SN/A */ 4442292SN/A void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 4452292SN/A 4462292SN/A void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 4472292SN/A 4482292SN/A void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 4492292SN/A 4502292SN/A void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 4512292SN/A 4522348SN/A /** Reads the commit PC of a specific thread. */ 4534636Sgblack@eecs.umich.edu Addr readPC(unsigned tid); 4542292SN/A 4552348SN/A /** Sets the commit PC of a specific thread. */ 4562348SN/A void setPC(Addr new_PC, unsigned tid); 4572292SN/A 4584636Sgblack@eecs.umich.edu /** Reads the commit micro PC of a specific thread. */ 4594636Sgblack@eecs.umich.edu Addr readMicroPC(unsigned tid); 4604636Sgblack@eecs.umich.edu 4614636Sgblack@eecs.umich.edu /** Sets the commmit micro PC of a specific thread. */ 4624636Sgblack@eecs.umich.edu void setMicroPC(Addr new_microPC, unsigned tid); 4634636Sgblack@eecs.umich.edu 4642348SN/A /** Reads the next PC of a specific thread. */ 4654636Sgblack@eecs.umich.edu Addr readNextPC(unsigned tid); 4662292SN/A 4672348SN/A /** Sets the next PC of a specific thread. */ 4684636Sgblack@eecs.umich.edu void setNextPC(Addr val, unsigned tid); 4691060SN/A 4702756Sksewell@umich.edu /** Reads the next NPC of a specific thread. */ 4714636Sgblack@eecs.umich.edu Addr readNextNPC(unsigned tid); 4722756Sksewell@umich.edu 4732756Sksewell@umich.edu /** Sets the next NPC of a specific thread. */ 4744636Sgblack@eecs.umich.edu void setNextNPC(Addr val, unsigned tid); 4754636Sgblack@eecs.umich.edu 4764636Sgblack@eecs.umich.edu /** Reads the commit next micro PC of a specific thread. */ 4774636Sgblack@eecs.umich.edu Addr readNextMicroPC(unsigned tid); 4784636Sgblack@eecs.umich.edu 4794636Sgblack@eecs.umich.edu /** Sets the commit next micro PC of a specific thread. */ 4804636Sgblack@eecs.umich.edu void setNextMicroPC(Addr val, unsigned tid); 4812756Sksewell@umich.edu 4821060SN/A /** Function to add instruction onto the head of the list of the 4831060SN/A * instructions. Used when new instructions are fetched. 4841060SN/A */ 4852292SN/A ListIt addInst(DynInstPtr &inst); 4861060SN/A 4871060SN/A /** Function to tell the CPU that an instruction has completed. */ 4882292SN/A void instDone(unsigned tid); 4891060SN/A 4902292SN/A /** Add Instructions to the CPU Remove List*/ 4912292SN/A void addToRemoveList(DynInstPtr &inst); 4921060SN/A 4932325SN/A /** Remove an instruction from the front end of the list. There's 4942325SN/A * no restriction on location of the instruction. 4951060SN/A */ 4961061SN/A void removeFrontInst(DynInstPtr &inst); 4971060SN/A 4982935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 4992935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 5004632Sgblack@eecs.umich.edu void removeInstsNotInROB(unsigned tid); 5011060SN/A 5021062SN/A /** Remove all instructions younger than the given sequence number. */ 5032292SN/A void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 5042292SN/A 5052348SN/A /** Removes the instruction pointed to by the iterator. */ 5062292SN/A inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 5072292SN/A 5082348SN/A /** Cleans up all instructions on the remove list. */ 5092292SN/A void cleanUpRemovedInsts(); 5101062SN/A 5112348SN/A /** Debug function to print all instructions on the list. */ 5121060SN/A void dumpInsts(); 5131060SN/A 5141060SN/A public: 5151060SN/A /** List of all the instructions in flight. */ 5162292SN/A std::list<DynInstPtr> instList; 5171060SN/A 5182292SN/A /** List of all the instructions that will be removed at the end of this 5192292SN/A * cycle. 5202292SN/A */ 5212292SN/A std::queue<ListIt> removeList; 5222292SN/A 5232325SN/A#ifdef DEBUG 5242348SN/A /** Debug structure to keep track of the sequence numbers still in 5252348SN/A * flight. 5262348SN/A */ 5272292SN/A std::set<InstSeqNum> snList; 5282325SN/A#endif 5292292SN/A 5302325SN/A /** Records if instructions need to be removed this cycle due to 5312325SN/A * being retired or squashed. 5322292SN/A */ 5332292SN/A bool removeInstsThisCycle; 5342292SN/A 5351060SN/A protected: 5361060SN/A /** The fetch stage. */ 5371060SN/A typename CPUPolicy::Fetch fetch; 5381060SN/A 5391060SN/A /** The decode stage. */ 5401060SN/A typename CPUPolicy::Decode decode; 5411060SN/A 5421060SN/A /** The dispatch stage. */ 5431060SN/A typename CPUPolicy::Rename rename; 5441060SN/A 5451060SN/A /** The issue/execute/writeback stages. */ 5461060SN/A typename CPUPolicy::IEW iew; 5471060SN/A 5481060SN/A /** The commit stage. */ 5491060SN/A typename CPUPolicy::Commit commit; 5501060SN/A 5511060SN/A /** The register file. */ 5521060SN/A typename CPUPolicy::RegFile regFile; 5531060SN/A 5541060SN/A /** The free list. */ 5551060SN/A typename CPUPolicy::FreeList freeList; 5561060SN/A 5571060SN/A /** The rename map. */ 5582292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 5592292SN/A 5602292SN/A /** The commit rename map. */ 5612292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 5621060SN/A 5631060SN/A /** The re-order buffer. */ 5641060SN/A typename CPUPolicy::ROB rob; 5651060SN/A 5662292SN/A /** Active Threads List */ 5672292SN/A std::list<unsigned> activeThreads; 5682292SN/A 5692292SN/A /** Integer Register Scoreboard */ 5702292SN/A Scoreboard scoreboard; 5712292SN/A 5721060SN/A public: 5732292SN/A /** Enum to give each stage a specific index, so when calling 5742292SN/A * activateStage() or deactivateStage(), they can specify which stage 5752292SN/A * is being activated/deactivated. 5762292SN/A */ 5772292SN/A enum StageIdx { 5782292SN/A FetchIdx, 5792292SN/A DecodeIdx, 5802292SN/A RenameIdx, 5812292SN/A IEWIdx, 5822292SN/A CommitIdx, 5832292SN/A NumStages }; 5842292SN/A 5851060SN/A /** Typedefs from the Impl to get the structs that each of the 5861060SN/A * time buffers should use. 5871060SN/A */ 5881061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 5891060SN/A 5901061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 5911060SN/A 5921061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 5931060SN/A 5941061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 5951060SN/A 5961061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 5971060SN/A 5981060SN/A /** The main time buffer to do backwards communication. */ 5991060SN/A TimeBuffer<TimeStruct> timeBuffer; 6001060SN/A 6011060SN/A /** The fetch stage's instruction queue. */ 6021060SN/A TimeBuffer<FetchStruct> fetchQueue; 6031060SN/A 6041060SN/A /** The decode stage's instruction queue. */ 6051060SN/A TimeBuffer<DecodeStruct> decodeQueue; 6061060SN/A 6071060SN/A /** The rename stage's instruction queue. */ 6081060SN/A TimeBuffer<RenameStruct> renameQueue; 6091060SN/A 6101060SN/A /** The IEW stage's instruction queue. */ 6111060SN/A TimeBuffer<IEWStruct> iewQueue; 6121060SN/A 6132348SN/A private: 6142348SN/A /** The activity recorder; used to tell if the CPU has any 6152348SN/A * activity remaining or if it can go to idle and deschedule 6162348SN/A * itself. 6172348SN/A */ 6182325SN/A ActivityRecorder activityRec; 6191060SN/A 6202348SN/A public: 6212348SN/A /** Records that there was time buffer activity this cycle. */ 6222325SN/A void activityThisCycle() { activityRec.activity(); } 6232292SN/A 6242348SN/A /** Changes a stage's status to active within the activity recorder. */ 6252325SN/A void activateStage(const StageIdx idx) 6262325SN/A { activityRec.activateStage(idx); } 6272292SN/A 6282348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 6292325SN/A void deactivateStage(const StageIdx idx) 6302325SN/A { activityRec.deactivateStage(idx); } 6312292SN/A 6322292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 6332292SN/A void wakeCPU(); 6342260SN/A 6352292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 6362292SN/A int getFreeTid(); 6372292SN/A 6382292SN/A public: 6392680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 6402680Sktlim@umich.edu ThreadContext *tcBase(unsigned tid) 6411681SN/A { 6422680Sktlim@umich.edu return thread[tid]->getTC(); 6432190SN/A } 6442190SN/A 6452292SN/A /** The global sequence number counter. */ 6463093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 6471060SN/A 6484598Sbinkertn@umich.edu#if USE_CHECKER 6492348SN/A /** Pointer to the checker, which can dynamically verify 6502348SN/A * instruction results at run time. This can be set to NULL if it 6512348SN/A * is not being used. 6522348SN/A */ 6532316SN/A Checker<DynInstPtr> *checker; 6544598Sbinkertn@umich.edu#endif 6552316SN/A 6561858SN/A#if FULL_SYSTEM 6572292SN/A /** Pointer to the system. */ 6581060SN/A System *system; 6591060SN/A 6602292SN/A /** Pointer to physical memory. */ 6611060SN/A PhysicalMemory *physmem; 6622292SN/A#endif 6631060SN/A 6642843Sktlim@umich.edu /** Event to call process() on once draining has completed. */ 6652843Sktlim@umich.edu Event *drainEvent; 6662843Sktlim@umich.edu 6672843Sktlim@umich.edu /** Counter of how many stages have completed draining. */ 6682843Sktlim@umich.edu int drainCount; 6692316SN/A 6702348SN/A /** Pointers to all of the threads in the CPU. */ 6712292SN/A std::vector<Thread *> thread; 6722260SN/A 6732292SN/A /** Whether or not the CPU should defer its registration. */ 6741060SN/A bool deferRegistration; 6751060SN/A 6762292SN/A /** Is there a context switch pending? */ 6772292SN/A bool contextSwitch; 6781060SN/A 6792292SN/A /** Threads Scheduled to Enter CPU */ 6802292SN/A std::list<int> cpuWaitList; 6812292SN/A 6822292SN/A /** The cycle that the CPU was last running, used for statistics. */ 6832292SN/A Tick lastRunningCycle; 6842292SN/A 6852829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 6862829Sksewell@umich.edu Tick lastActivatedCycle; 6872829Sksewell@umich.edu 6882292SN/A /** Number of Threads CPU can process */ 6892292SN/A unsigned numThreads; 6902292SN/A 6912292SN/A /** Mapping for system thread id to cpu id */ 6922292SN/A std::map<unsigned,unsigned> threadMap; 6932292SN/A 6942292SN/A /** Available thread ids in the cpu*/ 6952292SN/A std::vector<unsigned> tids; 6962292SN/A 6972292SN/A /** Stat for total number of times the CPU is descheduled. */ 6982292SN/A Stats::Scalar<> timesIdled; 6992292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 7002292SN/A Stats::Scalar<> idleCycles; 7012292SN/A /** Stat for the number of committed instructions per thread. */ 7022292SN/A Stats::Vector<> committedInsts; 7032292SN/A /** Stat for the total number of committed instructions. */ 7042292SN/A Stats::Scalar<> totalCommittedInsts; 7052292SN/A /** Stat for the CPI per thread. */ 7062292SN/A Stats::Formula cpi; 7072292SN/A /** Stat for the total CPI. */ 7082292SN/A Stats::Formula totalCpi; 7092292SN/A /** Stat for the IPC per thread. */ 7102292SN/A Stats::Formula ipc; 7112292SN/A /** Stat for the total IPC. */ 7122292SN/A Stats::Formula totalIpc; 7131060SN/A}; 7141060SN/A 7152325SN/A#endif // __CPU_O3_CPU_HH__ 716