cpu.hh revision 4988
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322325SN/A#ifndef __CPU_O3_CPU_HH__ 332325SN/A#define __CPU_O3_CPU_HH__ 341060SN/A 351060SN/A#include <iostream> 361060SN/A#include <list> 372292SN/A#include <queue> 382292SN/A#include <set> 391681SN/A#include <vector> 401060SN/A 412980Sgblack@eecs.umich.edu#include "arch/types.hh" 421060SN/A#include "base/statistics.hh" 431060SN/A#include "base/timebuf.hh" 441858SN/A#include "config/full_system.hh" 454598Sbinkertn@umich.edu#include "config/use_checker.hh" 462325SN/A#include "cpu/activity.hh" 471717SN/A#include "cpu/base.hh" 482683Sktlim@umich.edu#include "cpu/simple_thread.hh" 491717SN/A#include "cpu/o3/comm.hh" 501717SN/A#include "cpu/o3/cpu_policy.hh" 512292SN/A#include "cpu/o3/scoreboard.hh" 522292SN/A#include "cpu/o3/thread_state.hh" 532817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 541060SN/A#include "sim/process.hh" 551060SN/A 562316SN/Atemplate <class> 572316SN/Aclass Checker; 582680Sktlim@umich.educlass ThreadContext; 592817Sksewell@umich.edutemplate <class> 602817Sksewell@umich.educlass O3ThreadContext; 612843Sktlim@umich.edu 622843Sktlim@umich.educlass Checkpoint; 632669Sktlim@umich.educlass MemObject; 641060SN/Aclass Process; 651060SN/A 662733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 671060SN/A{ 681060SN/A //Stuff that's pretty ISA independent will go here. 691060SN/A public: 701464SN/A typedef BaseCPU::Params Params; 711061SN/A 722733Sktlim@umich.edu BaseO3CPU(Params *params); 732292SN/A 742292SN/A void regStats(); 752632Sstever@eecs.umich.edu 762817Sksewell@umich.edu /** Sets this CPU's ID. */ 772817Sksewell@umich.edu void setCpuId(int id) { cpu_id = id; } 782817Sksewell@umich.edu 792817Sksewell@umich.edu /** Reads this CPU's ID. */ 802669Sktlim@umich.edu int readCpuId() { return cpu_id; } 811681SN/A 821685SN/A protected: 831681SN/A int cpu_id; 841060SN/A}; 851060SN/A 862348SN/A/** 872348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 882348SN/A * within it, as well as all of the time buffers between stages. The 892348SN/A * tick() function for the CPU is defined here. 902348SN/A */ 911060SN/Atemplate <class Impl> 922733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 931060SN/A{ 941060SN/A public: 952325SN/A // Typedefs from the Impl here. 961060SN/A typedef typename Impl::CPUPol CPUPolicy; 971061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 984329Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 994988Sgblack@eecs.umich.edu typedef typename Impl::Params Params; 1001060SN/A 1012292SN/A typedef O3ThreadState<Impl> Thread; 1022292SN/A 1032292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1042292SN/A 1052817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1062829Sksewell@umich.edu 1071060SN/A public: 1081060SN/A enum Status { 1091060SN/A Running, 1101060SN/A Idle, 1111060SN/A Halted, 1122307SN/A Blocked, 1132307SN/A SwitchedOut 1141060SN/A }; 1151060SN/A 1163781Sgblack@eecs.umich.edu#if FULL_SYSTEM 1173781Sgblack@eecs.umich.edu TheISA::ITB * itb; 1183781Sgblack@eecs.umich.edu TheISA::DTB * dtb; 1193781Sgblack@eecs.umich.edu#endif 1203781Sgblack@eecs.umich.edu 1212292SN/A /** Overall CPU status. */ 1221060SN/A Status _status; 1231060SN/A 1242829Sksewell@umich.edu /** Per-thread status in CPU, used for SMT. */ 1252829Sksewell@umich.edu Status _threadStatus[Impl::MaxThreads]; 1262829Sksewell@umich.edu 1271060SN/A private: 1281060SN/A class TickEvent : public Event 1291060SN/A { 1301060SN/A private: 1312292SN/A /** Pointer to the CPU. */ 1321755SN/A FullO3CPU<Impl> *cpu; 1331060SN/A 1341060SN/A public: 1352292SN/A /** Constructs a tick event. */ 1361755SN/A TickEvent(FullO3CPU<Impl> *c); 1372292SN/A 1382292SN/A /** Processes a tick event, calling tick() on the CPU. */ 1391060SN/A void process(); 1402292SN/A /** Returns the description of the tick event. */ 1411060SN/A const char *description(); 1421060SN/A }; 1431060SN/A 1442292SN/A /** The tick event used for scheduling CPU ticks. */ 1451060SN/A TickEvent tickEvent; 1461060SN/A 1472292SN/A /** Schedule tick event, regardless of its current state. */ 1481060SN/A void scheduleTickEvent(int delay) 1491060SN/A { 1501060SN/A if (tickEvent.squashed()) 1514030Sktlim@umich.edu tickEvent.reschedule(nextCycle(curTick + cycles(delay))); 1521060SN/A else if (!tickEvent.scheduled()) 1534030Sktlim@umich.edu tickEvent.schedule(nextCycle(curTick + cycles(delay))); 1541060SN/A } 1551060SN/A 1562292SN/A /** Unschedule tick event, regardless of its current state. */ 1571060SN/A void unscheduleTickEvent() 1581060SN/A { 1591060SN/A if (tickEvent.scheduled()) 1601060SN/A tickEvent.squash(); 1611060SN/A } 1621060SN/A 1632829Sksewell@umich.edu class ActivateThreadEvent : public Event 1642829Sksewell@umich.edu { 1652829Sksewell@umich.edu private: 1662829Sksewell@umich.edu /** Number of Thread to Activate */ 1672829Sksewell@umich.edu int tid; 1682829Sksewell@umich.edu 1692829Sksewell@umich.edu /** Pointer to the CPU. */ 1702829Sksewell@umich.edu FullO3CPU<Impl> *cpu; 1712829Sksewell@umich.edu 1722829Sksewell@umich.edu public: 1732829Sksewell@umich.edu /** Constructs the event. */ 1742829Sksewell@umich.edu ActivateThreadEvent(); 1752829Sksewell@umich.edu 1762829Sksewell@umich.edu /** Initialize Event */ 1772829Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 1782829Sksewell@umich.edu 1792829Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 1802829Sksewell@umich.edu void process(); 1812829Sksewell@umich.edu 1822829Sksewell@umich.edu /** Returns the description of the event. */ 1832829Sksewell@umich.edu const char *description(); 1842829Sksewell@umich.edu }; 1852829Sksewell@umich.edu 1862829Sksewell@umich.edu /** Schedule thread to activate , regardless of its current state. */ 1872829Sksewell@umich.edu void scheduleActivateThreadEvent(int tid, int delay) 1882829Sksewell@umich.edu { 1892829Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 1902829Sksewell@umich.edu if (activateThreadEvent[tid].squashed()) 1914030Sktlim@umich.edu activateThreadEvent[tid]. 1924030Sktlim@umich.edu reschedule(nextCycle(curTick + cycles(delay))); 1932829Sksewell@umich.edu else if (!activateThreadEvent[tid].scheduled()) 1944030Sktlim@umich.edu activateThreadEvent[tid]. 1954030Sktlim@umich.edu schedule(nextCycle(curTick + cycles(delay))); 1962829Sksewell@umich.edu } 1972829Sksewell@umich.edu 1982829Sksewell@umich.edu /** Unschedule actiavte thread event, regardless of its current state. */ 1992829Sksewell@umich.edu void unscheduleActivateThreadEvent(int tid) 2002829Sksewell@umich.edu { 2012829Sksewell@umich.edu if (activateThreadEvent[tid].scheduled()) 2022829Sksewell@umich.edu activateThreadEvent[tid].squash(); 2032829Sksewell@umich.edu } 2042829Sksewell@umich.edu 2052829Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2062829Sksewell@umich.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 2072829Sksewell@umich.edu 2082875Sksewell@umich.edu class DeallocateContextEvent : public Event 2092875Sksewell@umich.edu { 2102875Sksewell@umich.edu private: 2113221Sktlim@umich.edu /** Number of Thread to deactivate */ 2122875Sksewell@umich.edu int tid; 2132875Sksewell@umich.edu 2143221Sktlim@umich.edu /** Should the thread be removed from the CPU? */ 2153221Sktlim@umich.edu bool remove; 2163221Sktlim@umich.edu 2172875Sksewell@umich.edu /** Pointer to the CPU. */ 2182875Sksewell@umich.edu FullO3CPU<Impl> *cpu; 2192875Sksewell@umich.edu 2202875Sksewell@umich.edu public: 2212875Sksewell@umich.edu /** Constructs the event. */ 2222875Sksewell@umich.edu DeallocateContextEvent(); 2232875Sksewell@umich.edu 2242875Sksewell@umich.edu /** Initialize Event */ 2252875Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 2262875Sksewell@umich.edu 2272875Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 2282875Sksewell@umich.edu void process(); 2292875Sksewell@umich.edu 2303221Sktlim@umich.edu /** Sets whether the thread should also be removed from the CPU. */ 2313221Sktlim@umich.edu void setRemove(bool _remove) { remove = _remove; } 2323221Sktlim@umich.edu 2332875Sksewell@umich.edu /** Returns the description of the event. */ 2342875Sksewell@umich.edu const char *description(); 2352875Sksewell@umich.edu }; 2362875Sksewell@umich.edu 2372875Sksewell@umich.edu /** Schedule cpu to deallocate thread context.*/ 2383221Sktlim@umich.edu void scheduleDeallocateContextEvent(int tid, bool remove, int delay) 2392875Sksewell@umich.edu { 2402875Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 2412875Sksewell@umich.edu if (deallocateContextEvent[tid].squashed()) 2424030Sktlim@umich.edu deallocateContextEvent[tid]. 2434030Sktlim@umich.edu reschedule(nextCycle(curTick + cycles(delay))); 2442875Sksewell@umich.edu else if (!deallocateContextEvent[tid].scheduled()) 2454030Sktlim@umich.edu deallocateContextEvent[tid]. 2464030Sktlim@umich.edu schedule(nextCycle(curTick + cycles(delay))); 2472875Sksewell@umich.edu } 2482875Sksewell@umich.edu 2492875Sksewell@umich.edu /** Unschedule thread deallocation in CPU */ 2502875Sksewell@umich.edu void unscheduleDeallocateContextEvent(int tid) 2512875Sksewell@umich.edu { 2522875Sksewell@umich.edu if (deallocateContextEvent[tid].scheduled()) 2532875Sksewell@umich.edu deallocateContextEvent[tid].squash(); 2542875Sksewell@umich.edu } 2552875Sksewell@umich.edu 2562875Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2572875Sksewell@umich.edu DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 2582875Sksewell@umich.edu 2591060SN/A public: 2602292SN/A /** Constructs a CPU with the given parameters. */ 2614329Sktlim@umich.edu FullO3CPU(O3CPU *o3_cpu, Params *params); 2622292SN/A /** Destructor. */ 2631755SN/A ~FullO3CPU(); 2641060SN/A 2652292SN/A /** Registers statistics. */ 2661684SN/A void fullCPURegStats(); 2671684SN/A 2684988Sgblack@eecs.umich.edu#if FULL_SYSTEM 2694988Sgblack@eecs.umich.edu /** Translates instruction requestion. */ 2704988Sgblack@eecs.umich.edu Fault translateInstReq(RequestPtr &req, Thread *thread) 2714988Sgblack@eecs.umich.edu { 2724988Sgblack@eecs.umich.edu return this->itb->translate(req, thread->getTC()); 2734988Sgblack@eecs.umich.edu } 2744988Sgblack@eecs.umich.edu 2754988Sgblack@eecs.umich.edu /** Translates data read request. */ 2764988Sgblack@eecs.umich.edu Fault translateDataReadReq(RequestPtr &req, Thread *thread) 2774988Sgblack@eecs.umich.edu { 2784988Sgblack@eecs.umich.edu return this->dtb->translate(req, thread->getTC(), false); 2794988Sgblack@eecs.umich.edu } 2804988Sgblack@eecs.umich.edu 2814988Sgblack@eecs.umich.edu /** Translates data write request. */ 2824988Sgblack@eecs.umich.edu Fault translateDataWriteReq(RequestPtr &req, Thread *thread) 2834988Sgblack@eecs.umich.edu { 2844988Sgblack@eecs.umich.edu return this->dtb->translate(req, thread->getTC(), true); 2854988Sgblack@eecs.umich.edu } 2864988Sgblack@eecs.umich.edu 2874988Sgblack@eecs.umich.edu#else 2884988Sgblack@eecs.umich.edu /** Translates instruction requestion in syscall emulation mode. */ 2894988Sgblack@eecs.umich.edu Fault translateInstReq(RequestPtr &req, Thread *thread) 2904988Sgblack@eecs.umich.edu { 2914988Sgblack@eecs.umich.edu return thread->getProcessPtr()->pTable->translate(req); 2924988Sgblack@eecs.umich.edu } 2934988Sgblack@eecs.umich.edu 2944988Sgblack@eecs.umich.edu /** Translates data read request in syscall emulation mode. */ 2954988Sgblack@eecs.umich.edu Fault translateDataReadReq(RequestPtr &req, Thread *thread) 2964988Sgblack@eecs.umich.edu { 2974988Sgblack@eecs.umich.edu return thread->getProcessPtr()->pTable->translate(req); 2984988Sgblack@eecs.umich.edu } 2994988Sgblack@eecs.umich.edu 3004988Sgblack@eecs.umich.edu /** Translates data write request in syscall emulation mode. */ 3014988Sgblack@eecs.umich.edu Fault translateDataWriteReq(RequestPtr &req, Thread *thread) 3024988Sgblack@eecs.umich.edu { 3034988Sgblack@eecs.umich.edu return thread->getProcessPtr()->pTable->translate(req); 3044988Sgblack@eecs.umich.edu } 3054988Sgblack@eecs.umich.edu 3064988Sgblack@eecs.umich.edu#endif 3074988Sgblack@eecs.umich.edu 3082871Sktlim@umich.edu /** Returns a specific port. */ 3092871Sktlim@umich.edu Port *getPort(const std::string &if_name, int idx); 3102871Sktlim@umich.edu 3112292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 3122292SN/A * activity to see if the CPU should deschedule itself. 3132292SN/A */ 3141684SN/A void tick(); 3151684SN/A 3162292SN/A /** Initialize the CPU */ 3171060SN/A void init(); 3181060SN/A 3192834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 3202834Sksewell@umich.edu int numActiveThreads() 3212834Sksewell@umich.edu { return activeThreads.size(); } 3222834Sksewell@umich.edu 3232829Sksewell@umich.edu /** Add Thread to Active Threads List */ 3242875Sksewell@umich.edu void activateThread(unsigned tid); 3252875Sksewell@umich.edu 3262875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 3272875Sksewell@umich.edu void deactivateThread(unsigned tid); 3282829Sksewell@umich.edu 3292292SN/A /** Setup CPU to insert a thread's context */ 3302292SN/A void insertThread(unsigned tid); 3311060SN/A 3322292SN/A /** Remove all of a thread's context from CPU */ 3332292SN/A void removeThread(unsigned tid); 3342292SN/A 3352292SN/A /** Count the Total Instructions Committed in the CPU. */ 3362292SN/A virtual Counter totalInstructions() const 3372292SN/A { 3382292SN/A Counter total(0); 3392292SN/A 3402292SN/A for (int i=0; i < thread.size(); i++) 3412292SN/A total += thread[i]->numInst; 3422292SN/A 3432292SN/A return total; 3442292SN/A } 3452292SN/A 3462292SN/A /** Add Thread to Active Threads List. */ 3472292SN/A void activateContext(int tid, int delay); 3482292SN/A 3492292SN/A /** Remove Thread from Active Threads List */ 3502292SN/A void suspendContext(int tid); 3512292SN/A 3522292SN/A /** Remove Thread from Active Threads List && 3533221Sktlim@umich.edu * Possibly Remove Thread Context from CPU. 3542292SN/A */ 3553221Sktlim@umich.edu bool deallocateContext(int tid, bool remove, int delay = 1); 3562292SN/A 3572292SN/A /** Remove Thread from Active Threads List && 3582292SN/A * Remove Thread Context from CPU. 3592292SN/A */ 3602292SN/A void haltContext(int tid); 3612292SN/A 3622292SN/A /** Activate a Thread When CPU Resources are Available. */ 3632292SN/A void activateWhenReady(int tid); 3642292SN/A 3652292SN/A /** Add or Remove a Thread Context in the CPU. */ 3662292SN/A void doContextSwitch(); 3672292SN/A 3682292SN/A /** Update The Order In Which We Process Threads. */ 3692292SN/A void updateThreadPriority(); 3702292SN/A 3712864Sktlim@umich.edu /** Serialize state. */ 3722864Sktlim@umich.edu virtual void serialize(std::ostream &os); 3732864Sktlim@umich.edu 3742864Sktlim@umich.edu /** Unserialize from a checkpoint. */ 3752864Sktlim@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 3762864Sktlim@umich.edu 3772864Sktlim@umich.edu public: 3782292SN/A /** Executes a syscall on this cycle. 3792292SN/A * --------------------------------------- 3802292SN/A * Note: this is a virtual function. CPU-Specific 3812292SN/A * functionality defined in derived classes 3822292SN/A */ 3832325SN/A virtual void syscall(int tid) { panic("Unimplemented!"); } 3842292SN/A 3852843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 3862843Sktlim@umich.edu * order to stop all memory accesses. */ 3872905Sktlim@umich.edu virtual unsigned int drain(Event *drain_event); 3882843Sktlim@umich.edu 3892843Sktlim@umich.edu /** Resumes execution after a drain. */ 3902843Sktlim@umich.edu virtual void resume(); 3912292SN/A 3922348SN/A /** Signals to this CPU that a stage has completed switching out. */ 3932843Sktlim@umich.edu void signalDrained(); 3942843Sktlim@umich.edu 3952843Sktlim@umich.edu /** Switches out this CPU. */ 3962843Sktlim@umich.edu virtual void switchOut(); 3972316SN/A 3982348SN/A /** Takes over from another CPU. */ 3992843Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *oldCPU); 4001060SN/A 4011060SN/A /** Get the current instruction sequence number, and increment it. */ 4022316SN/A InstSeqNum getAndIncrementInstSeq() 4032316SN/A { return globalSeqNum++; } 4041060SN/A 4051858SN/A#if FULL_SYSTEM 4064192Sktlim@umich.edu /** Update the Virt and Phys ports of all ThreadContexts to 4074192Sktlim@umich.edu * reflect change in memory connections. */ 4084192Sktlim@umich.edu void updateMemPorts(); 4094192Sktlim@umich.edu 4101060SN/A /** Check if this address is a valid instruction address. */ 4111060SN/A bool validInstAddr(Addr addr) { return true; } 4121060SN/A 4131060SN/A /** Check if this address is a valid data address. */ 4141060SN/A bool validDataAddr(Addr addr) { return true; } 4151060SN/A 4161060SN/A /** Get instruction asid. */ 4172292SN/A int getInstAsid(unsigned tid) 4182292SN/A { return regFile.miscRegs[tid].getInstAsid(); } 4191060SN/A 4201060SN/A /** Get data asid. */ 4212292SN/A int getDataAsid(unsigned tid) 4222292SN/A { return regFile.miscRegs[tid].getDataAsid(); } 4231060SN/A#else 4242292SN/A /** Get instruction asid. */ 4252292SN/A int getInstAsid(unsigned tid) 4262683Sktlim@umich.edu { return thread[tid]->getInstAsid(); } 4271060SN/A 4282292SN/A /** Get data asid. */ 4292292SN/A int getDataAsid(unsigned tid) 4302683Sktlim@umich.edu { return thread[tid]->getDataAsid(); } 4311060SN/A 4321060SN/A#endif 4331060SN/A 4342348SN/A /** Register accessors. Index refers to the physical register index. */ 4351060SN/A uint64_t readIntReg(int reg_idx); 4361060SN/A 4373781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx); 4381060SN/A 4393781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx, int width); 4401060SN/A 4413781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx); 4422455SN/A 4433781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width); 4441060SN/A 4451060SN/A void setIntReg(int reg_idx, uint64_t val); 4461060SN/A 4473781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val); 4481060SN/A 4493781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val, int width); 4501060SN/A 4513781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 4522455SN/A 4533781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width); 4541060SN/A 4552292SN/A uint64_t readArchIntReg(int reg_idx, unsigned tid); 4561060SN/A 4572292SN/A float readArchFloatRegSingle(int reg_idx, unsigned tid); 4581060SN/A 4592292SN/A double readArchFloatRegDouble(int reg_idx, unsigned tid); 4602292SN/A 4612292SN/A uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 4622292SN/A 4632348SN/A /** Architectural register accessors. Looks up in the commit 4642348SN/A * rename table to obtain the true physical index of the 4652348SN/A * architected register first, then accesses that physical 4662348SN/A * register. 4672348SN/A */ 4682292SN/A void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 4692292SN/A 4702292SN/A void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 4712292SN/A 4722292SN/A void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 4732292SN/A 4742292SN/A void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 4752292SN/A 4762348SN/A /** Reads the commit PC of a specific thread. */ 4774636Sgblack@eecs.umich.edu Addr readPC(unsigned tid); 4782292SN/A 4792348SN/A /** Sets the commit PC of a specific thread. */ 4802348SN/A void setPC(Addr new_PC, unsigned tid); 4812292SN/A 4824636Sgblack@eecs.umich.edu /** Reads the commit micro PC of a specific thread. */ 4834636Sgblack@eecs.umich.edu Addr readMicroPC(unsigned tid); 4844636Sgblack@eecs.umich.edu 4854636Sgblack@eecs.umich.edu /** Sets the commmit micro PC of a specific thread. */ 4864636Sgblack@eecs.umich.edu void setMicroPC(Addr new_microPC, unsigned tid); 4874636Sgblack@eecs.umich.edu 4882348SN/A /** Reads the next PC of a specific thread. */ 4894636Sgblack@eecs.umich.edu Addr readNextPC(unsigned tid); 4902292SN/A 4912348SN/A /** Sets the next PC of a specific thread. */ 4924636Sgblack@eecs.umich.edu void setNextPC(Addr val, unsigned tid); 4931060SN/A 4942756Sksewell@umich.edu /** Reads the next NPC of a specific thread. */ 4954636Sgblack@eecs.umich.edu Addr readNextNPC(unsigned tid); 4962756Sksewell@umich.edu 4972756Sksewell@umich.edu /** Sets the next NPC of a specific thread. */ 4984636Sgblack@eecs.umich.edu void setNextNPC(Addr val, unsigned tid); 4994636Sgblack@eecs.umich.edu 5004636Sgblack@eecs.umich.edu /** Reads the commit next micro PC of a specific thread. */ 5014636Sgblack@eecs.umich.edu Addr readNextMicroPC(unsigned tid); 5024636Sgblack@eecs.umich.edu 5034636Sgblack@eecs.umich.edu /** Sets the commit next micro PC of a specific thread. */ 5044636Sgblack@eecs.umich.edu void setNextMicroPC(Addr val, unsigned tid); 5052756Sksewell@umich.edu 5061060SN/A /** Function to add instruction onto the head of the list of the 5071060SN/A * instructions. Used when new instructions are fetched. 5081060SN/A */ 5092292SN/A ListIt addInst(DynInstPtr &inst); 5101060SN/A 5111060SN/A /** Function to tell the CPU that an instruction has completed. */ 5122292SN/A void instDone(unsigned tid); 5131060SN/A 5142292SN/A /** Add Instructions to the CPU Remove List*/ 5152292SN/A void addToRemoveList(DynInstPtr &inst); 5161060SN/A 5172325SN/A /** Remove an instruction from the front end of the list. There's 5182325SN/A * no restriction on location of the instruction. 5191060SN/A */ 5201061SN/A void removeFrontInst(DynInstPtr &inst); 5211060SN/A 5222935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 5232935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 5244632Sgblack@eecs.umich.edu void removeInstsNotInROB(unsigned tid); 5251060SN/A 5261062SN/A /** Remove all instructions younger than the given sequence number. */ 5272292SN/A void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 5282292SN/A 5292348SN/A /** Removes the instruction pointed to by the iterator. */ 5302292SN/A inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 5312292SN/A 5322348SN/A /** Cleans up all instructions on the remove list. */ 5332292SN/A void cleanUpRemovedInsts(); 5341062SN/A 5352348SN/A /** Debug function to print all instructions on the list. */ 5361060SN/A void dumpInsts(); 5371060SN/A 5381060SN/A public: 5391060SN/A /** List of all the instructions in flight. */ 5402292SN/A std::list<DynInstPtr> instList; 5411060SN/A 5422292SN/A /** List of all the instructions that will be removed at the end of this 5432292SN/A * cycle. 5442292SN/A */ 5452292SN/A std::queue<ListIt> removeList; 5462292SN/A 5472325SN/A#ifdef DEBUG 5482348SN/A /** Debug structure to keep track of the sequence numbers still in 5492348SN/A * flight. 5502348SN/A */ 5512292SN/A std::set<InstSeqNum> snList; 5522325SN/A#endif 5532292SN/A 5542325SN/A /** Records if instructions need to be removed this cycle due to 5552325SN/A * being retired or squashed. 5562292SN/A */ 5572292SN/A bool removeInstsThisCycle; 5582292SN/A 5591060SN/A protected: 5601060SN/A /** The fetch stage. */ 5611060SN/A typename CPUPolicy::Fetch fetch; 5621060SN/A 5631060SN/A /** The decode stage. */ 5641060SN/A typename CPUPolicy::Decode decode; 5651060SN/A 5661060SN/A /** The dispatch stage. */ 5671060SN/A typename CPUPolicy::Rename rename; 5681060SN/A 5691060SN/A /** The issue/execute/writeback stages. */ 5701060SN/A typename CPUPolicy::IEW iew; 5711060SN/A 5721060SN/A /** The commit stage. */ 5731060SN/A typename CPUPolicy::Commit commit; 5741060SN/A 5751060SN/A /** The register file. */ 5761060SN/A typename CPUPolicy::RegFile regFile; 5771060SN/A 5781060SN/A /** The free list. */ 5791060SN/A typename CPUPolicy::FreeList freeList; 5801060SN/A 5811060SN/A /** The rename map. */ 5822292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 5832292SN/A 5842292SN/A /** The commit rename map. */ 5852292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 5861060SN/A 5871060SN/A /** The re-order buffer. */ 5881060SN/A typename CPUPolicy::ROB rob; 5891060SN/A 5902292SN/A /** Active Threads List */ 5912292SN/A std::list<unsigned> activeThreads; 5922292SN/A 5932292SN/A /** Integer Register Scoreboard */ 5942292SN/A Scoreboard scoreboard; 5952292SN/A 5961060SN/A public: 5972292SN/A /** Enum to give each stage a specific index, so when calling 5982292SN/A * activateStage() or deactivateStage(), they can specify which stage 5992292SN/A * is being activated/deactivated. 6002292SN/A */ 6012292SN/A enum StageIdx { 6022292SN/A FetchIdx, 6032292SN/A DecodeIdx, 6042292SN/A RenameIdx, 6052292SN/A IEWIdx, 6062292SN/A CommitIdx, 6072292SN/A NumStages }; 6082292SN/A 6091060SN/A /** Typedefs from the Impl to get the structs that each of the 6101060SN/A * time buffers should use. 6111060SN/A */ 6121061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 6131060SN/A 6141061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 6151060SN/A 6161061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 6171060SN/A 6181061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 6191060SN/A 6201061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 6211060SN/A 6221060SN/A /** The main time buffer to do backwards communication. */ 6231060SN/A TimeBuffer<TimeStruct> timeBuffer; 6241060SN/A 6251060SN/A /** The fetch stage's instruction queue. */ 6261060SN/A TimeBuffer<FetchStruct> fetchQueue; 6271060SN/A 6281060SN/A /** The decode stage's instruction queue. */ 6291060SN/A TimeBuffer<DecodeStruct> decodeQueue; 6301060SN/A 6311060SN/A /** The rename stage's instruction queue. */ 6321060SN/A TimeBuffer<RenameStruct> renameQueue; 6331060SN/A 6341060SN/A /** The IEW stage's instruction queue. */ 6351060SN/A TimeBuffer<IEWStruct> iewQueue; 6361060SN/A 6372348SN/A private: 6382348SN/A /** The activity recorder; used to tell if the CPU has any 6392348SN/A * activity remaining or if it can go to idle and deschedule 6402348SN/A * itself. 6412348SN/A */ 6422325SN/A ActivityRecorder activityRec; 6431060SN/A 6442348SN/A public: 6452348SN/A /** Records that there was time buffer activity this cycle. */ 6462325SN/A void activityThisCycle() { activityRec.activity(); } 6472292SN/A 6482348SN/A /** Changes a stage's status to active within the activity recorder. */ 6492325SN/A void activateStage(const StageIdx idx) 6502325SN/A { activityRec.activateStage(idx); } 6512292SN/A 6522348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 6532325SN/A void deactivateStage(const StageIdx idx) 6542325SN/A { activityRec.deactivateStage(idx); } 6552292SN/A 6562292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 6572292SN/A void wakeCPU(); 6582260SN/A 6592292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 6602292SN/A int getFreeTid(); 6612292SN/A 6622292SN/A public: 6632680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 6642680Sktlim@umich.edu ThreadContext *tcBase(unsigned tid) 6651681SN/A { 6662680Sktlim@umich.edu return thread[tid]->getTC(); 6672190SN/A } 6682190SN/A 6692292SN/A /** The global sequence number counter. */ 6703093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 6711060SN/A 6724598Sbinkertn@umich.edu#if USE_CHECKER 6732348SN/A /** Pointer to the checker, which can dynamically verify 6742348SN/A * instruction results at run time. This can be set to NULL if it 6752348SN/A * is not being used. 6762348SN/A */ 6772316SN/A Checker<DynInstPtr> *checker; 6784598Sbinkertn@umich.edu#endif 6792316SN/A 6801858SN/A#if FULL_SYSTEM 6812292SN/A /** Pointer to the system. */ 6821060SN/A System *system; 6831060SN/A 6842292SN/A /** Pointer to physical memory. */ 6851060SN/A PhysicalMemory *physmem; 6862292SN/A#endif 6871060SN/A 6882843Sktlim@umich.edu /** Event to call process() on once draining has completed. */ 6892843Sktlim@umich.edu Event *drainEvent; 6902843Sktlim@umich.edu 6912843Sktlim@umich.edu /** Counter of how many stages have completed draining. */ 6922843Sktlim@umich.edu int drainCount; 6932316SN/A 6942348SN/A /** Pointers to all of the threads in the CPU. */ 6952292SN/A std::vector<Thread *> thread; 6962260SN/A 6972292SN/A /** Whether or not the CPU should defer its registration. */ 6981060SN/A bool deferRegistration; 6991060SN/A 7002292SN/A /** Is there a context switch pending? */ 7012292SN/A bool contextSwitch; 7021060SN/A 7032292SN/A /** Threads Scheduled to Enter CPU */ 7042292SN/A std::list<int> cpuWaitList; 7052292SN/A 7062292SN/A /** The cycle that the CPU was last running, used for statistics. */ 7072292SN/A Tick lastRunningCycle; 7082292SN/A 7092829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 7102829Sksewell@umich.edu Tick lastActivatedCycle; 7112829Sksewell@umich.edu 7122292SN/A /** Number of Threads CPU can process */ 7132292SN/A unsigned numThreads; 7142292SN/A 7152292SN/A /** Mapping for system thread id to cpu id */ 7162292SN/A std::map<unsigned,unsigned> threadMap; 7172292SN/A 7182292SN/A /** Available thread ids in the cpu*/ 7192292SN/A std::vector<unsigned> tids; 7202292SN/A 7212292SN/A /** Stat for total number of times the CPU is descheduled. */ 7222292SN/A Stats::Scalar<> timesIdled; 7232292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 7242292SN/A Stats::Scalar<> idleCycles; 7252292SN/A /** Stat for the number of committed instructions per thread. */ 7262292SN/A Stats::Vector<> committedInsts; 7272292SN/A /** Stat for the total number of committed instructions. */ 7282292SN/A Stats::Scalar<> totalCommittedInsts; 7292292SN/A /** Stat for the CPI per thread. */ 7302292SN/A Stats::Formula cpi; 7312292SN/A /** Stat for the total CPI. */ 7322292SN/A Stats::Formula totalCpi; 7332292SN/A /** Stat for the IPC per thread. */ 7342292SN/A Stats::Formula ipc; 7352292SN/A /** Stat for the total IPC. */ 7362292SN/A Stats::Formula totalIpc; 7371060SN/A}; 7381060SN/A 7392325SN/A#endif // __CPU_O3_CPU_HH__ 740