cpu.hh revision 4192
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322325SN/A#ifndef __CPU_O3_CPU_HH__ 332325SN/A#define __CPU_O3_CPU_HH__ 341060SN/A 351060SN/A#include <iostream> 361060SN/A#include <list> 372292SN/A#include <queue> 382292SN/A#include <set> 391681SN/A#include <vector> 401060SN/A 412980Sgblack@eecs.umich.edu#include "arch/types.hh" 421060SN/A#include "base/statistics.hh" 431060SN/A#include "base/timebuf.hh" 441858SN/A#include "config/full_system.hh" 452325SN/A#include "cpu/activity.hh" 461717SN/A#include "cpu/base.hh" 472683Sktlim@umich.edu#include "cpu/simple_thread.hh" 481717SN/A#include "cpu/o3/comm.hh" 491717SN/A#include "cpu/o3/cpu_policy.hh" 502292SN/A#include "cpu/o3/scoreboard.hh" 512292SN/A#include "cpu/o3/thread_state.hh" 522817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 531060SN/A#include "sim/process.hh" 541060SN/A 552316SN/Atemplate <class> 562316SN/Aclass Checker; 572680Sktlim@umich.educlass ThreadContext; 582817Sksewell@umich.edutemplate <class> 592817Sksewell@umich.educlass O3ThreadContext; 602843Sktlim@umich.edu 612843Sktlim@umich.educlass Checkpoint; 622669Sktlim@umich.educlass MemObject; 631060SN/Aclass Process; 641060SN/A 652733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 661060SN/A{ 671060SN/A //Stuff that's pretty ISA independent will go here. 681060SN/A public: 691464SN/A typedef BaseCPU::Params Params; 701061SN/A 712733Sktlim@umich.edu BaseO3CPU(Params *params); 722292SN/A 732292SN/A void regStats(); 742632Sstever@eecs.umich.edu 752817Sksewell@umich.edu /** Sets this CPU's ID. */ 762817Sksewell@umich.edu void setCpuId(int id) { cpu_id = id; } 772817Sksewell@umich.edu 782817Sksewell@umich.edu /** Reads this CPU's ID. */ 792669Sktlim@umich.edu int readCpuId() { return cpu_id; } 801681SN/A 811685SN/A protected: 821681SN/A int cpu_id; 831060SN/A}; 841060SN/A 852348SN/A/** 862348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 872348SN/A * within it, as well as all of the time buffers between stages. The 882348SN/A * tick() function for the CPU is defined here. 892348SN/A */ 901060SN/Atemplate <class Impl> 912733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 921060SN/A{ 931060SN/A public: 942325SN/A // Typedefs from the Impl here. 951060SN/A typedef typename Impl::CPUPol CPUPolicy; 961060SN/A typedef typename Impl::Params Params; 971061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 981060SN/A 992292SN/A typedef O3ThreadState<Impl> Thread; 1002292SN/A 1012292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1022292SN/A 1032817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1042829Sksewell@umich.edu 1051060SN/A public: 1061060SN/A enum Status { 1071060SN/A Running, 1081060SN/A Idle, 1091060SN/A Halted, 1102307SN/A Blocked, 1112307SN/A SwitchedOut 1121060SN/A }; 1131060SN/A 1143781Sgblack@eecs.umich.edu#if FULL_SYSTEM 1153781Sgblack@eecs.umich.edu TheISA::ITB * itb; 1163781Sgblack@eecs.umich.edu TheISA::DTB * dtb; 1173781Sgblack@eecs.umich.edu#endif 1183781Sgblack@eecs.umich.edu 1192292SN/A /** Overall CPU status. */ 1201060SN/A Status _status; 1211060SN/A 1222829Sksewell@umich.edu /** Per-thread status in CPU, used for SMT. */ 1232829Sksewell@umich.edu Status _threadStatus[Impl::MaxThreads]; 1242829Sksewell@umich.edu 1251060SN/A private: 1261060SN/A class TickEvent : public Event 1271060SN/A { 1281060SN/A private: 1292292SN/A /** Pointer to the CPU. */ 1301755SN/A FullO3CPU<Impl> *cpu; 1311060SN/A 1321060SN/A public: 1332292SN/A /** Constructs a tick event. */ 1341755SN/A TickEvent(FullO3CPU<Impl> *c); 1352292SN/A 1362292SN/A /** Processes a tick event, calling tick() on the CPU. */ 1371060SN/A void process(); 1382292SN/A /** Returns the description of the tick event. */ 1391060SN/A const char *description(); 1401060SN/A }; 1411060SN/A 1422292SN/A /** The tick event used for scheduling CPU ticks. */ 1431060SN/A TickEvent tickEvent; 1441060SN/A 1452292SN/A /** Schedule tick event, regardless of its current state. */ 1461060SN/A void scheduleTickEvent(int delay) 1471060SN/A { 1481060SN/A if (tickEvent.squashed()) 1492307SN/A tickEvent.reschedule(curTick + cycles(delay)); 1501060SN/A else if (!tickEvent.scheduled()) 1512307SN/A tickEvent.schedule(curTick + cycles(delay)); 1521060SN/A } 1531060SN/A 1542292SN/A /** Unschedule tick event, regardless of its current state. */ 1551060SN/A void unscheduleTickEvent() 1561060SN/A { 1571060SN/A if (tickEvent.scheduled()) 1581060SN/A tickEvent.squash(); 1591060SN/A } 1601060SN/A 1612829Sksewell@umich.edu class ActivateThreadEvent : public Event 1622829Sksewell@umich.edu { 1632829Sksewell@umich.edu private: 1642829Sksewell@umich.edu /** Number of Thread to Activate */ 1652829Sksewell@umich.edu int tid; 1662829Sksewell@umich.edu 1672829Sksewell@umich.edu /** Pointer to the CPU. */ 1682829Sksewell@umich.edu FullO3CPU<Impl> *cpu; 1692829Sksewell@umich.edu 1702829Sksewell@umich.edu public: 1712829Sksewell@umich.edu /** Constructs the event. */ 1722829Sksewell@umich.edu ActivateThreadEvent(); 1732829Sksewell@umich.edu 1742829Sksewell@umich.edu /** Initialize Event */ 1752829Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 1762829Sksewell@umich.edu 1772829Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 1782829Sksewell@umich.edu void process(); 1792829Sksewell@umich.edu 1802829Sksewell@umich.edu /** Returns the description of the event. */ 1812829Sksewell@umich.edu const char *description(); 1822829Sksewell@umich.edu }; 1832829Sksewell@umich.edu 1842829Sksewell@umich.edu /** Schedule thread to activate , regardless of its current state. */ 1852829Sksewell@umich.edu void scheduleActivateThreadEvent(int tid, int delay) 1862829Sksewell@umich.edu { 1872829Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 1882829Sksewell@umich.edu if (activateThreadEvent[tid].squashed()) 1892829Sksewell@umich.edu activateThreadEvent[tid].reschedule(curTick + cycles(delay)); 1902829Sksewell@umich.edu else if (!activateThreadEvent[tid].scheduled()) 1912829Sksewell@umich.edu activateThreadEvent[tid].schedule(curTick + cycles(delay)); 1922829Sksewell@umich.edu } 1932829Sksewell@umich.edu 1942829Sksewell@umich.edu /** Unschedule actiavte thread event, regardless of its current state. */ 1952829Sksewell@umich.edu void unscheduleActivateThreadEvent(int tid) 1962829Sksewell@umich.edu { 1972829Sksewell@umich.edu if (activateThreadEvent[tid].scheduled()) 1982829Sksewell@umich.edu activateThreadEvent[tid].squash(); 1992829Sksewell@umich.edu } 2002829Sksewell@umich.edu 2012829Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2022829Sksewell@umich.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 2032829Sksewell@umich.edu 2042875Sksewell@umich.edu class DeallocateContextEvent : public Event 2052875Sksewell@umich.edu { 2062875Sksewell@umich.edu private: 2073221Sktlim@umich.edu /** Number of Thread to deactivate */ 2082875Sksewell@umich.edu int tid; 2092875Sksewell@umich.edu 2103221Sktlim@umich.edu /** Should the thread be removed from the CPU? */ 2113221Sktlim@umich.edu bool remove; 2123221Sktlim@umich.edu 2132875Sksewell@umich.edu /** Pointer to the CPU. */ 2142875Sksewell@umich.edu FullO3CPU<Impl> *cpu; 2152875Sksewell@umich.edu 2162875Sksewell@umich.edu public: 2172875Sksewell@umich.edu /** Constructs the event. */ 2182875Sksewell@umich.edu DeallocateContextEvent(); 2192875Sksewell@umich.edu 2202875Sksewell@umich.edu /** Initialize Event */ 2212875Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 2222875Sksewell@umich.edu 2232875Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 2242875Sksewell@umich.edu void process(); 2252875Sksewell@umich.edu 2263221Sktlim@umich.edu /** Sets whether the thread should also be removed from the CPU. */ 2273221Sktlim@umich.edu void setRemove(bool _remove) { remove = _remove; } 2283221Sktlim@umich.edu 2292875Sksewell@umich.edu /** Returns the description of the event. */ 2302875Sksewell@umich.edu const char *description(); 2312875Sksewell@umich.edu }; 2322875Sksewell@umich.edu 2332875Sksewell@umich.edu /** Schedule cpu to deallocate thread context.*/ 2343221Sktlim@umich.edu void scheduleDeallocateContextEvent(int tid, bool remove, int delay) 2352875Sksewell@umich.edu { 2362875Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 2372875Sksewell@umich.edu if (deallocateContextEvent[tid].squashed()) 2382875Sksewell@umich.edu deallocateContextEvent[tid].reschedule(curTick + cycles(delay)); 2392875Sksewell@umich.edu else if (!deallocateContextEvent[tid].scheduled()) 2402875Sksewell@umich.edu deallocateContextEvent[tid].schedule(curTick + cycles(delay)); 2412875Sksewell@umich.edu } 2422875Sksewell@umich.edu 2432875Sksewell@umich.edu /** Unschedule thread deallocation in CPU */ 2442875Sksewell@umich.edu void unscheduleDeallocateContextEvent(int tid) 2452875Sksewell@umich.edu { 2462875Sksewell@umich.edu if (deallocateContextEvent[tid].scheduled()) 2472875Sksewell@umich.edu deallocateContextEvent[tid].squash(); 2482875Sksewell@umich.edu } 2492875Sksewell@umich.edu 2502875Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2512875Sksewell@umich.edu DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 2522875Sksewell@umich.edu 2531060SN/A public: 2542292SN/A /** Constructs a CPU with the given parameters. */ 2552292SN/A FullO3CPU(Params *params); 2562292SN/A /** Destructor. */ 2571755SN/A ~FullO3CPU(); 2581060SN/A 2592292SN/A /** Registers statistics. */ 2601684SN/A void fullCPURegStats(); 2611684SN/A 2622871Sktlim@umich.edu /** Returns a specific port. */ 2632871Sktlim@umich.edu Port *getPort(const std::string &if_name, int idx); 2642871Sktlim@umich.edu 2652292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 2662292SN/A * activity to see if the CPU should deschedule itself. 2672292SN/A */ 2681684SN/A void tick(); 2691684SN/A 2702292SN/A /** Initialize the CPU */ 2711060SN/A void init(); 2721060SN/A 2732834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 2742834Sksewell@umich.edu int numActiveThreads() 2752834Sksewell@umich.edu { return activeThreads.size(); } 2762834Sksewell@umich.edu 2772829Sksewell@umich.edu /** Add Thread to Active Threads List */ 2782875Sksewell@umich.edu void activateThread(unsigned tid); 2792875Sksewell@umich.edu 2802875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 2812875Sksewell@umich.edu void deactivateThread(unsigned tid); 2822829Sksewell@umich.edu 2832292SN/A /** Setup CPU to insert a thread's context */ 2842292SN/A void insertThread(unsigned tid); 2851060SN/A 2862292SN/A /** Remove all of a thread's context from CPU */ 2872292SN/A void removeThread(unsigned tid); 2882292SN/A 2892292SN/A /** Count the Total Instructions Committed in the CPU. */ 2902292SN/A virtual Counter totalInstructions() const 2912292SN/A { 2922292SN/A Counter total(0); 2932292SN/A 2942292SN/A for (int i=0; i < thread.size(); i++) 2952292SN/A total += thread[i]->numInst; 2962292SN/A 2972292SN/A return total; 2982292SN/A } 2992292SN/A 3002292SN/A /** Add Thread to Active Threads List. */ 3012292SN/A void activateContext(int tid, int delay); 3022292SN/A 3032292SN/A /** Remove Thread from Active Threads List */ 3042292SN/A void suspendContext(int tid); 3052292SN/A 3062292SN/A /** Remove Thread from Active Threads List && 3073221Sktlim@umich.edu * Possibly Remove Thread Context from CPU. 3082292SN/A */ 3093221Sktlim@umich.edu bool deallocateContext(int tid, bool remove, int delay = 1); 3102292SN/A 3112292SN/A /** Remove Thread from Active Threads List && 3122292SN/A * Remove Thread Context from CPU. 3132292SN/A */ 3142292SN/A void haltContext(int tid); 3152292SN/A 3162292SN/A /** Activate a Thread When CPU Resources are Available. */ 3172292SN/A void activateWhenReady(int tid); 3182292SN/A 3192292SN/A /** Add or Remove a Thread Context in the CPU. */ 3202292SN/A void doContextSwitch(); 3212292SN/A 3222292SN/A /** Update The Order In Which We Process Threads. */ 3232292SN/A void updateThreadPriority(); 3242292SN/A 3252864Sktlim@umich.edu /** Serialize state. */ 3262864Sktlim@umich.edu virtual void serialize(std::ostream &os); 3272864Sktlim@umich.edu 3282864Sktlim@umich.edu /** Unserialize from a checkpoint. */ 3292864Sktlim@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 3302864Sktlim@umich.edu 3312864Sktlim@umich.edu public: 3322292SN/A /** Executes a syscall on this cycle. 3332292SN/A * --------------------------------------- 3342292SN/A * Note: this is a virtual function. CPU-Specific 3352292SN/A * functionality defined in derived classes 3362292SN/A */ 3372325SN/A virtual void syscall(int tid) { panic("Unimplemented!"); } 3382292SN/A 3392843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 3402843Sktlim@umich.edu * order to stop all memory accesses. */ 3412905Sktlim@umich.edu virtual unsigned int drain(Event *drain_event); 3422843Sktlim@umich.edu 3432843Sktlim@umich.edu /** Resumes execution after a drain. */ 3442843Sktlim@umich.edu virtual void resume(); 3452292SN/A 3462348SN/A /** Signals to this CPU that a stage has completed switching out. */ 3472843Sktlim@umich.edu void signalDrained(); 3482843Sktlim@umich.edu 3492843Sktlim@umich.edu /** Switches out this CPU. */ 3502843Sktlim@umich.edu virtual void switchOut(); 3512316SN/A 3522348SN/A /** Takes over from another CPU. */ 3532843Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *oldCPU); 3541060SN/A 3551060SN/A /** Get the current instruction sequence number, and increment it. */ 3562316SN/A InstSeqNum getAndIncrementInstSeq() 3572316SN/A { return globalSeqNum++; } 3581060SN/A 3591858SN/A#if FULL_SYSTEM 3604192Sktlim@umich.edu /** Update the Virt and Phys ports of all ThreadContexts to 3614192Sktlim@umich.edu * reflect change in memory connections. */ 3624192Sktlim@umich.edu void updateMemPorts(); 3634192Sktlim@umich.edu 3641060SN/A /** Check if this address is a valid instruction address. */ 3651060SN/A bool validInstAddr(Addr addr) { return true; } 3661060SN/A 3671060SN/A /** Check if this address is a valid data address. */ 3681060SN/A bool validDataAddr(Addr addr) { return true; } 3691060SN/A 3701060SN/A /** Get instruction asid. */ 3712292SN/A int getInstAsid(unsigned tid) 3722292SN/A { return regFile.miscRegs[tid].getInstAsid(); } 3731060SN/A 3741060SN/A /** Get data asid. */ 3752292SN/A int getDataAsid(unsigned tid) 3762292SN/A { return regFile.miscRegs[tid].getDataAsid(); } 3771060SN/A#else 3782292SN/A /** Get instruction asid. */ 3792292SN/A int getInstAsid(unsigned tid) 3802683Sktlim@umich.edu { return thread[tid]->getInstAsid(); } 3811060SN/A 3822292SN/A /** Get data asid. */ 3832292SN/A int getDataAsid(unsigned tid) 3842683Sktlim@umich.edu { return thread[tid]->getDataAsid(); } 3851060SN/A 3861060SN/A#endif 3871060SN/A 3882348SN/A /** Register accessors. Index refers to the physical register index. */ 3891060SN/A uint64_t readIntReg(int reg_idx); 3901060SN/A 3913781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx); 3921060SN/A 3933781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx, int width); 3941060SN/A 3953781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx); 3962455SN/A 3973781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width); 3981060SN/A 3991060SN/A void setIntReg(int reg_idx, uint64_t val); 4001060SN/A 4013781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val); 4021060SN/A 4033781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val, int width); 4041060SN/A 4053781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 4062455SN/A 4073781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width); 4081060SN/A 4092292SN/A uint64_t readArchIntReg(int reg_idx, unsigned tid); 4101060SN/A 4112292SN/A float readArchFloatRegSingle(int reg_idx, unsigned tid); 4121060SN/A 4132292SN/A double readArchFloatRegDouble(int reg_idx, unsigned tid); 4142292SN/A 4152292SN/A uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 4162292SN/A 4172348SN/A /** Architectural register accessors. Looks up in the commit 4182348SN/A * rename table to obtain the true physical index of the 4192348SN/A * architected register first, then accesses that physical 4202348SN/A * register. 4212348SN/A */ 4222292SN/A void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 4232292SN/A 4242292SN/A void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 4252292SN/A 4262292SN/A void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 4272292SN/A 4282292SN/A void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 4292292SN/A 4302348SN/A /** Reads the commit PC of a specific thread. */ 4312292SN/A uint64_t readPC(unsigned tid); 4322292SN/A 4332348SN/A /** Sets the commit PC of a specific thread. */ 4342348SN/A void setPC(Addr new_PC, unsigned tid); 4352292SN/A 4362348SN/A /** Reads the next PC of a specific thread. */ 4372292SN/A uint64_t readNextPC(unsigned tid); 4382292SN/A 4392348SN/A /** Sets the next PC of a specific thread. */ 4402348SN/A void setNextPC(uint64_t val, unsigned tid); 4411060SN/A 4422756Sksewell@umich.edu /** Reads the next NPC of a specific thread. */ 4432756Sksewell@umich.edu uint64_t readNextNPC(unsigned tid); 4442756Sksewell@umich.edu 4452756Sksewell@umich.edu /** Sets the next NPC of a specific thread. */ 4462756Sksewell@umich.edu void setNextNPC(uint64_t val, unsigned tid); 4472756Sksewell@umich.edu 4481060SN/A /** Function to add instruction onto the head of the list of the 4491060SN/A * instructions. Used when new instructions are fetched. 4501060SN/A */ 4512292SN/A ListIt addInst(DynInstPtr &inst); 4521060SN/A 4531060SN/A /** Function to tell the CPU that an instruction has completed. */ 4542292SN/A void instDone(unsigned tid); 4551060SN/A 4562292SN/A /** Add Instructions to the CPU Remove List*/ 4572292SN/A void addToRemoveList(DynInstPtr &inst); 4581060SN/A 4592325SN/A /** Remove an instruction from the front end of the list. There's 4602325SN/A * no restriction on location of the instruction. 4611060SN/A */ 4621061SN/A void removeFrontInst(DynInstPtr &inst); 4631060SN/A 4642935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 4652935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 4662935Sksewell@umich.edu void removeInstsNotInROB(unsigned tid, bool squash_delay_slot, 4672935Sksewell@umich.edu const InstSeqNum &delay_slot_seq_num); 4681060SN/A 4691062SN/A /** Remove all instructions younger than the given sequence number. */ 4702292SN/A void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 4712292SN/A 4722348SN/A /** Removes the instruction pointed to by the iterator. */ 4732292SN/A inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 4742292SN/A 4752348SN/A /** Cleans up all instructions on the remove list. */ 4762292SN/A void cleanUpRemovedInsts(); 4771062SN/A 4782348SN/A /** Debug function to print all instructions on the list. */ 4791060SN/A void dumpInsts(); 4801060SN/A 4811060SN/A public: 4821060SN/A /** List of all the instructions in flight. */ 4832292SN/A std::list<DynInstPtr> instList; 4841060SN/A 4852292SN/A /** List of all the instructions that will be removed at the end of this 4862292SN/A * cycle. 4872292SN/A */ 4882292SN/A std::queue<ListIt> removeList; 4892292SN/A 4902325SN/A#ifdef DEBUG 4912348SN/A /** Debug structure to keep track of the sequence numbers still in 4922348SN/A * flight. 4932348SN/A */ 4942292SN/A std::set<InstSeqNum> snList; 4952325SN/A#endif 4962292SN/A 4972325SN/A /** Records if instructions need to be removed this cycle due to 4982325SN/A * being retired or squashed. 4992292SN/A */ 5002292SN/A bool removeInstsThisCycle; 5012292SN/A 5021060SN/A protected: 5031060SN/A /** The fetch stage. */ 5041060SN/A typename CPUPolicy::Fetch fetch; 5051060SN/A 5061060SN/A /** The decode stage. */ 5071060SN/A typename CPUPolicy::Decode decode; 5081060SN/A 5091060SN/A /** The dispatch stage. */ 5101060SN/A typename CPUPolicy::Rename rename; 5111060SN/A 5121060SN/A /** The issue/execute/writeback stages. */ 5131060SN/A typename CPUPolicy::IEW iew; 5141060SN/A 5151060SN/A /** The commit stage. */ 5161060SN/A typename CPUPolicy::Commit commit; 5171060SN/A 5181060SN/A /** The register file. */ 5191060SN/A typename CPUPolicy::RegFile regFile; 5201060SN/A 5211060SN/A /** The free list. */ 5221060SN/A typename CPUPolicy::FreeList freeList; 5231060SN/A 5241060SN/A /** The rename map. */ 5252292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 5262292SN/A 5272292SN/A /** The commit rename map. */ 5282292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 5291060SN/A 5301060SN/A /** The re-order buffer. */ 5311060SN/A typename CPUPolicy::ROB rob; 5321060SN/A 5332292SN/A /** Active Threads List */ 5342292SN/A std::list<unsigned> activeThreads; 5352292SN/A 5362292SN/A /** Integer Register Scoreboard */ 5372292SN/A Scoreboard scoreboard; 5382292SN/A 5391060SN/A public: 5402292SN/A /** Enum to give each stage a specific index, so when calling 5412292SN/A * activateStage() or deactivateStage(), they can specify which stage 5422292SN/A * is being activated/deactivated. 5432292SN/A */ 5442292SN/A enum StageIdx { 5452292SN/A FetchIdx, 5462292SN/A DecodeIdx, 5472292SN/A RenameIdx, 5482292SN/A IEWIdx, 5492292SN/A CommitIdx, 5502292SN/A NumStages }; 5512292SN/A 5521060SN/A /** Typedefs from the Impl to get the structs that each of the 5531060SN/A * time buffers should use. 5541060SN/A */ 5551061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 5561060SN/A 5571061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 5581060SN/A 5591061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 5601060SN/A 5611061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 5621060SN/A 5631061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 5641060SN/A 5651060SN/A /** The main time buffer to do backwards communication. */ 5661060SN/A TimeBuffer<TimeStruct> timeBuffer; 5671060SN/A 5681060SN/A /** The fetch stage's instruction queue. */ 5691060SN/A TimeBuffer<FetchStruct> fetchQueue; 5701060SN/A 5711060SN/A /** The decode stage's instruction queue. */ 5721060SN/A TimeBuffer<DecodeStruct> decodeQueue; 5731060SN/A 5741060SN/A /** The rename stage's instruction queue. */ 5751060SN/A TimeBuffer<RenameStruct> renameQueue; 5761060SN/A 5771060SN/A /** The IEW stage's instruction queue. */ 5781060SN/A TimeBuffer<IEWStruct> iewQueue; 5791060SN/A 5802348SN/A private: 5812348SN/A /** The activity recorder; used to tell if the CPU has any 5822348SN/A * activity remaining or if it can go to idle and deschedule 5832348SN/A * itself. 5842348SN/A */ 5852325SN/A ActivityRecorder activityRec; 5861060SN/A 5872348SN/A public: 5882348SN/A /** Records that there was time buffer activity this cycle. */ 5892325SN/A void activityThisCycle() { activityRec.activity(); } 5902292SN/A 5912348SN/A /** Changes a stage's status to active within the activity recorder. */ 5922325SN/A void activateStage(const StageIdx idx) 5932325SN/A { activityRec.activateStage(idx); } 5942292SN/A 5952348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 5962325SN/A void deactivateStage(const StageIdx idx) 5972325SN/A { activityRec.deactivateStage(idx); } 5982292SN/A 5992292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 6002292SN/A void wakeCPU(); 6012260SN/A 6022292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 6032292SN/A int getFreeTid(); 6042292SN/A 6052292SN/A public: 6062680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 6072680Sktlim@umich.edu ThreadContext *tcBase(unsigned tid) 6081681SN/A { 6092680Sktlim@umich.edu return thread[tid]->getTC(); 6102190SN/A } 6112190SN/A 6122292SN/A /** The global sequence number counter. */ 6133093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 6141060SN/A 6152348SN/A /** Pointer to the checker, which can dynamically verify 6162348SN/A * instruction results at run time. This can be set to NULL if it 6172348SN/A * is not being used. 6182348SN/A */ 6192316SN/A Checker<DynInstPtr> *checker; 6202316SN/A 6211858SN/A#if FULL_SYSTEM 6222292SN/A /** Pointer to the system. */ 6231060SN/A System *system; 6241060SN/A 6252292SN/A /** Pointer to physical memory. */ 6261060SN/A PhysicalMemory *physmem; 6272292SN/A#endif 6281060SN/A 6292843Sktlim@umich.edu /** Event to call process() on once draining has completed. */ 6302843Sktlim@umich.edu Event *drainEvent; 6312843Sktlim@umich.edu 6322843Sktlim@umich.edu /** Counter of how many stages have completed draining. */ 6332843Sktlim@umich.edu int drainCount; 6342316SN/A 6352348SN/A /** Pointers to all of the threads in the CPU. */ 6362292SN/A std::vector<Thread *> thread; 6372260SN/A 6382292SN/A /** Whether or not the CPU should defer its registration. */ 6391060SN/A bool deferRegistration; 6401060SN/A 6412292SN/A /** Is there a context switch pending? */ 6422292SN/A bool contextSwitch; 6431060SN/A 6442292SN/A /** Threads Scheduled to Enter CPU */ 6452292SN/A std::list<int> cpuWaitList; 6462292SN/A 6472292SN/A /** The cycle that the CPU was last running, used for statistics. */ 6482292SN/A Tick lastRunningCycle; 6492292SN/A 6502829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 6512829Sksewell@umich.edu Tick lastActivatedCycle; 6522829Sksewell@umich.edu 6532292SN/A /** Number of Threads CPU can process */ 6542292SN/A unsigned numThreads; 6552292SN/A 6562292SN/A /** Mapping for system thread id to cpu id */ 6572292SN/A std::map<unsigned,unsigned> threadMap; 6582292SN/A 6592292SN/A /** Available thread ids in the cpu*/ 6602292SN/A std::vector<unsigned> tids; 6612292SN/A 6622292SN/A /** Stat for total number of times the CPU is descheduled. */ 6632292SN/A Stats::Scalar<> timesIdled; 6642292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 6652292SN/A Stats::Scalar<> idleCycles; 6662292SN/A /** Stat for the number of committed instructions per thread. */ 6672292SN/A Stats::Vector<> committedInsts; 6682292SN/A /** Stat for the total number of committed instructions. */ 6692292SN/A Stats::Scalar<> totalCommittedInsts; 6702292SN/A /** Stat for the CPI per thread. */ 6712292SN/A Stats::Formula cpi; 6722292SN/A /** Stat for the total CPI. */ 6732292SN/A Stats::Formula totalCpi; 6742292SN/A /** Stat for the IPC per thread. */ 6752292SN/A Stats::Formula ipc; 6762292SN/A /** Stat for the total IPC. */ 6772292SN/A Stats::Formula totalIpc; 6781060SN/A}; 6791060SN/A 6802325SN/A#endif // __CPU_O3_CPU_HH__ 681