cpu.hh revision 3221
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322325SN/A#ifndef __CPU_O3_CPU_HH__ 332325SN/A#define __CPU_O3_CPU_HH__ 341060SN/A 351060SN/A#include <iostream> 361060SN/A#include <list> 372292SN/A#include <queue> 382292SN/A#include <set> 391681SN/A#include <vector> 401060SN/A 412980Sgblack@eecs.umich.edu#include "arch/types.hh" 421060SN/A#include "base/statistics.hh" 431060SN/A#include "base/timebuf.hh" 441858SN/A#include "config/full_system.hh" 452325SN/A#include "cpu/activity.hh" 461717SN/A#include "cpu/base.hh" 472683Sktlim@umich.edu#include "cpu/simple_thread.hh" 481717SN/A#include "cpu/o3/comm.hh" 491717SN/A#include "cpu/o3/cpu_policy.hh" 502292SN/A#include "cpu/o3/scoreboard.hh" 512292SN/A#include "cpu/o3/thread_state.hh" 522817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 531060SN/A#include "sim/process.hh" 541060SN/A 552316SN/Atemplate <class> 562316SN/Aclass Checker; 572680Sktlim@umich.educlass ThreadContext; 582817Sksewell@umich.edutemplate <class> 592817Sksewell@umich.educlass O3ThreadContext; 602843Sktlim@umich.edu 612843Sktlim@umich.educlass Checkpoint; 622669Sktlim@umich.educlass MemObject; 631060SN/Aclass Process; 641060SN/A 652733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 661060SN/A{ 671060SN/A //Stuff that's pretty ISA independent will go here. 681060SN/A public: 691464SN/A typedef BaseCPU::Params Params; 701061SN/A 712733Sktlim@umich.edu BaseO3CPU(Params *params); 722292SN/A 732292SN/A void regStats(); 742632Sstever@eecs.umich.edu 752817Sksewell@umich.edu /** Sets this CPU's ID. */ 762817Sksewell@umich.edu void setCpuId(int id) { cpu_id = id; } 772817Sksewell@umich.edu 782817Sksewell@umich.edu /** Reads this CPU's ID. */ 792669Sktlim@umich.edu int readCpuId() { return cpu_id; } 801681SN/A 811685SN/A protected: 821681SN/A int cpu_id; 831060SN/A}; 841060SN/A 852348SN/A/** 862348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 872348SN/A * within it, as well as all of the time buffers between stages. The 882348SN/A * tick() function for the CPU is defined here. 892348SN/A */ 901060SN/Atemplate <class Impl> 912733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 921060SN/A{ 931060SN/A public: 942669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 952669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 962669Sktlim@umich.edu 972325SN/A // Typedefs from the Impl here. 981060SN/A typedef typename Impl::CPUPol CPUPolicy; 991060SN/A typedef typename Impl::Params Params; 1001061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1011060SN/A 1022292SN/A typedef O3ThreadState<Impl> Thread; 1032292SN/A 1042292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1052292SN/A 1062817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1072829Sksewell@umich.edu 1081060SN/A public: 1091060SN/A enum Status { 1101060SN/A Running, 1111060SN/A Idle, 1121060SN/A Halted, 1132307SN/A Blocked, 1142307SN/A SwitchedOut 1151060SN/A }; 1161060SN/A 1172292SN/A /** Overall CPU status. */ 1181060SN/A Status _status; 1191060SN/A 1202829Sksewell@umich.edu /** Per-thread status in CPU, used for SMT. */ 1212829Sksewell@umich.edu Status _threadStatus[Impl::MaxThreads]; 1222829Sksewell@umich.edu 1231060SN/A private: 1241060SN/A class TickEvent : public Event 1251060SN/A { 1261060SN/A private: 1272292SN/A /** Pointer to the CPU. */ 1281755SN/A FullO3CPU<Impl> *cpu; 1291060SN/A 1301060SN/A public: 1312292SN/A /** Constructs a tick event. */ 1321755SN/A TickEvent(FullO3CPU<Impl> *c); 1332292SN/A 1342292SN/A /** Processes a tick event, calling tick() on the CPU. */ 1351060SN/A void process(); 1362292SN/A /** Returns the description of the tick event. */ 1371060SN/A const char *description(); 1381060SN/A }; 1391060SN/A 1402292SN/A /** The tick event used for scheduling CPU ticks. */ 1411060SN/A TickEvent tickEvent; 1421060SN/A 1432292SN/A /** Schedule tick event, regardless of its current state. */ 1441060SN/A void scheduleTickEvent(int delay) 1451060SN/A { 1461060SN/A if (tickEvent.squashed()) 1472307SN/A tickEvent.reschedule(curTick + cycles(delay)); 1481060SN/A else if (!tickEvent.scheduled()) 1492307SN/A tickEvent.schedule(curTick + cycles(delay)); 1501060SN/A } 1511060SN/A 1522292SN/A /** Unschedule tick event, regardless of its current state. */ 1531060SN/A void unscheduleTickEvent() 1541060SN/A { 1551060SN/A if (tickEvent.scheduled()) 1561060SN/A tickEvent.squash(); 1571060SN/A } 1581060SN/A 1592829Sksewell@umich.edu class ActivateThreadEvent : public Event 1602829Sksewell@umich.edu { 1612829Sksewell@umich.edu private: 1622829Sksewell@umich.edu /** Number of Thread to Activate */ 1632829Sksewell@umich.edu int tid; 1642829Sksewell@umich.edu 1652829Sksewell@umich.edu /** Pointer to the CPU. */ 1662829Sksewell@umich.edu FullO3CPU<Impl> *cpu; 1672829Sksewell@umich.edu 1682829Sksewell@umich.edu public: 1692829Sksewell@umich.edu /** Constructs the event. */ 1702829Sksewell@umich.edu ActivateThreadEvent(); 1712829Sksewell@umich.edu 1722829Sksewell@umich.edu /** Initialize Event */ 1732829Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 1742829Sksewell@umich.edu 1752829Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 1762829Sksewell@umich.edu void process(); 1772829Sksewell@umich.edu 1782829Sksewell@umich.edu /** Returns the description of the event. */ 1792829Sksewell@umich.edu const char *description(); 1802829Sksewell@umich.edu }; 1812829Sksewell@umich.edu 1822829Sksewell@umich.edu /** Schedule thread to activate , regardless of its current state. */ 1832829Sksewell@umich.edu void scheduleActivateThreadEvent(int tid, int delay) 1842829Sksewell@umich.edu { 1852829Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 1862829Sksewell@umich.edu if (activateThreadEvent[tid].squashed()) 1872829Sksewell@umich.edu activateThreadEvent[tid].reschedule(curTick + cycles(delay)); 1882829Sksewell@umich.edu else if (!activateThreadEvent[tid].scheduled()) 1892829Sksewell@umich.edu activateThreadEvent[tid].schedule(curTick + cycles(delay)); 1902829Sksewell@umich.edu } 1912829Sksewell@umich.edu 1922829Sksewell@umich.edu /** Unschedule actiavte thread event, regardless of its current state. */ 1932829Sksewell@umich.edu void unscheduleActivateThreadEvent(int tid) 1942829Sksewell@umich.edu { 1952829Sksewell@umich.edu if (activateThreadEvent[tid].scheduled()) 1962829Sksewell@umich.edu activateThreadEvent[tid].squash(); 1972829Sksewell@umich.edu } 1982829Sksewell@umich.edu 1992829Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2002829Sksewell@umich.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 2012829Sksewell@umich.edu 2022875Sksewell@umich.edu class DeallocateContextEvent : public Event 2032875Sksewell@umich.edu { 2042875Sksewell@umich.edu private: 2053221Sktlim@umich.edu /** Number of Thread to deactivate */ 2062875Sksewell@umich.edu int tid; 2072875Sksewell@umich.edu 2083221Sktlim@umich.edu /** Should the thread be removed from the CPU? */ 2093221Sktlim@umich.edu bool remove; 2103221Sktlim@umich.edu 2112875Sksewell@umich.edu /** Pointer to the CPU. */ 2122875Sksewell@umich.edu FullO3CPU<Impl> *cpu; 2132875Sksewell@umich.edu 2142875Sksewell@umich.edu public: 2152875Sksewell@umich.edu /** Constructs the event. */ 2162875Sksewell@umich.edu DeallocateContextEvent(); 2172875Sksewell@umich.edu 2182875Sksewell@umich.edu /** Initialize Event */ 2192875Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 2202875Sksewell@umich.edu 2212875Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 2222875Sksewell@umich.edu void process(); 2232875Sksewell@umich.edu 2243221Sktlim@umich.edu /** Sets whether the thread should also be removed from the CPU. */ 2253221Sktlim@umich.edu void setRemove(bool _remove) { remove = _remove; } 2263221Sktlim@umich.edu 2272875Sksewell@umich.edu /** Returns the description of the event. */ 2282875Sksewell@umich.edu const char *description(); 2292875Sksewell@umich.edu }; 2302875Sksewell@umich.edu 2312875Sksewell@umich.edu /** Schedule cpu to deallocate thread context.*/ 2323221Sktlim@umich.edu void scheduleDeallocateContextEvent(int tid, bool remove, int delay) 2332875Sksewell@umich.edu { 2342875Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 2352875Sksewell@umich.edu if (deallocateContextEvent[tid].squashed()) 2362875Sksewell@umich.edu deallocateContextEvent[tid].reschedule(curTick + cycles(delay)); 2372875Sksewell@umich.edu else if (!deallocateContextEvent[tid].scheduled()) 2382875Sksewell@umich.edu deallocateContextEvent[tid].schedule(curTick + cycles(delay)); 2392875Sksewell@umich.edu } 2402875Sksewell@umich.edu 2412875Sksewell@umich.edu /** Unschedule thread deallocation in CPU */ 2422875Sksewell@umich.edu void unscheduleDeallocateContextEvent(int tid) 2432875Sksewell@umich.edu { 2442875Sksewell@umich.edu if (deallocateContextEvent[tid].scheduled()) 2452875Sksewell@umich.edu deallocateContextEvent[tid].squash(); 2462875Sksewell@umich.edu } 2472875Sksewell@umich.edu 2482875Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2492875Sksewell@umich.edu DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 2502875Sksewell@umich.edu 2511060SN/A public: 2522292SN/A /** Constructs a CPU with the given parameters. */ 2532292SN/A FullO3CPU(Params *params); 2542292SN/A /** Destructor. */ 2551755SN/A ~FullO3CPU(); 2561060SN/A 2572292SN/A /** Registers statistics. */ 2581684SN/A void fullCPURegStats(); 2591684SN/A 2602871Sktlim@umich.edu /** Returns a specific port. */ 2612871Sktlim@umich.edu Port *getPort(const std::string &if_name, int idx); 2622871Sktlim@umich.edu 2632292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 2642292SN/A * activity to see if the CPU should deschedule itself. 2652292SN/A */ 2661684SN/A void tick(); 2671684SN/A 2682292SN/A /** Initialize the CPU */ 2691060SN/A void init(); 2701060SN/A 2712834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 2722834Sksewell@umich.edu int numActiveThreads() 2732834Sksewell@umich.edu { return activeThreads.size(); } 2742834Sksewell@umich.edu 2752829Sksewell@umich.edu /** Add Thread to Active Threads List */ 2762875Sksewell@umich.edu void activateThread(unsigned tid); 2772875Sksewell@umich.edu 2782875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 2792875Sksewell@umich.edu void deactivateThread(unsigned tid); 2802829Sksewell@umich.edu 2812292SN/A /** Setup CPU to insert a thread's context */ 2822292SN/A void insertThread(unsigned tid); 2831060SN/A 2842292SN/A /** Remove all of a thread's context from CPU */ 2852292SN/A void removeThread(unsigned tid); 2862292SN/A 2872292SN/A /** Count the Total Instructions Committed in the CPU. */ 2882292SN/A virtual Counter totalInstructions() const 2892292SN/A { 2902292SN/A Counter total(0); 2912292SN/A 2922292SN/A for (int i=0; i < thread.size(); i++) 2932292SN/A total += thread[i]->numInst; 2942292SN/A 2952292SN/A return total; 2962292SN/A } 2972292SN/A 2982292SN/A /** Add Thread to Active Threads List. */ 2992292SN/A void activateContext(int tid, int delay); 3002292SN/A 3012292SN/A /** Remove Thread from Active Threads List */ 3022292SN/A void suspendContext(int tid); 3032292SN/A 3042292SN/A /** Remove Thread from Active Threads List && 3053221Sktlim@umich.edu * Possibly Remove Thread Context from CPU. 3062292SN/A */ 3073221Sktlim@umich.edu bool deallocateContext(int tid, bool remove, int delay = 1); 3082292SN/A 3092292SN/A /** Remove Thread from Active Threads List && 3102292SN/A * Remove Thread Context from CPU. 3112292SN/A */ 3122292SN/A void haltContext(int tid); 3132292SN/A 3142292SN/A /** Activate a Thread When CPU Resources are Available. */ 3152292SN/A void activateWhenReady(int tid); 3162292SN/A 3172292SN/A /** Add or Remove a Thread Context in the CPU. */ 3182292SN/A void doContextSwitch(); 3192292SN/A 3202292SN/A /** Update The Order In Which We Process Threads. */ 3212292SN/A void updateThreadPriority(); 3222292SN/A 3232864Sktlim@umich.edu /** Serialize state. */ 3242864Sktlim@umich.edu virtual void serialize(std::ostream &os); 3252864Sktlim@umich.edu 3262864Sktlim@umich.edu /** Unserialize from a checkpoint. */ 3272864Sktlim@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 3282864Sktlim@umich.edu 3292864Sktlim@umich.edu public: 3302292SN/A /** Executes a syscall on this cycle. 3312292SN/A * --------------------------------------- 3322292SN/A * Note: this is a virtual function. CPU-Specific 3332292SN/A * functionality defined in derived classes 3342292SN/A */ 3352325SN/A virtual void syscall(int tid) { panic("Unimplemented!"); } 3362292SN/A 3372843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 3382843Sktlim@umich.edu * order to stop all memory accesses. */ 3392905Sktlim@umich.edu virtual unsigned int drain(Event *drain_event); 3402843Sktlim@umich.edu 3412843Sktlim@umich.edu /** Resumes execution after a drain. */ 3422843Sktlim@umich.edu virtual void resume(); 3432292SN/A 3442348SN/A /** Signals to this CPU that a stage has completed switching out. */ 3452843Sktlim@umich.edu void signalDrained(); 3462843Sktlim@umich.edu 3472843Sktlim@umich.edu /** Switches out this CPU. */ 3482843Sktlim@umich.edu virtual void switchOut(); 3492316SN/A 3502348SN/A /** Takes over from another CPU. */ 3512843Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *oldCPU); 3521060SN/A 3531060SN/A /** Get the current instruction sequence number, and increment it. */ 3542316SN/A InstSeqNum getAndIncrementInstSeq() 3552316SN/A { return globalSeqNum++; } 3561060SN/A 3571858SN/A#if FULL_SYSTEM 3581060SN/A /** Check if this address is a valid instruction address. */ 3591060SN/A bool validInstAddr(Addr addr) { return true; } 3601060SN/A 3611060SN/A /** Check if this address is a valid data address. */ 3621060SN/A bool validDataAddr(Addr addr) { return true; } 3631060SN/A 3641060SN/A /** Get instruction asid. */ 3652292SN/A int getInstAsid(unsigned tid) 3662292SN/A { return regFile.miscRegs[tid].getInstAsid(); } 3671060SN/A 3681060SN/A /** Get data asid. */ 3692292SN/A int getDataAsid(unsigned tid) 3702292SN/A { return regFile.miscRegs[tid].getDataAsid(); } 3711060SN/A#else 3722292SN/A /** Get instruction asid. */ 3732292SN/A int getInstAsid(unsigned tid) 3742683Sktlim@umich.edu { return thread[tid]->getInstAsid(); } 3751060SN/A 3762292SN/A /** Get data asid. */ 3772292SN/A int getDataAsid(unsigned tid) 3782683Sktlim@umich.edu { return thread[tid]->getDataAsid(); } 3791060SN/A 3801060SN/A#endif 3811060SN/A 3822348SN/A /** Register accessors. Index refers to the physical register index. */ 3831060SN/A uint64_t readIntReg(int reg_idx); 3841060SN/A 3852455SN/A FloatReg readFloatReg(int reg_idx); 3861060SN/A 3872455SN/A FloatReg readFloatReg(int reg_idx, int width); 3881060SN/A 3892455SN/A FloatRegBits readFloatRegBits(int reg_idx); 3902455SN/A 3912455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width); 3921060SN/A 3931060SN/A void setIntReg(int reg_idx, uint64_t val); 3941060SN/A 3952669Sktlim@umich.edu void setFloatReg(int reg_idx, FloatReg val); 3961060SN/A 3972455SN/A void setFloatReg(int reg_idx, FloatReg val, int width); 3981060SN/A 3992455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val); 4002455SN/A 4012669Sktlim@umich.edu void setFloatRegBits(int reg_idx, FloatRegBits val, int width); 4021060SN/A 4032292SN/A uint64_t readArchIntReg(int reg_idx, unsigned tid); 4041060SN/A 4052292SN/A float readArchFloatRegSingle(int reg_idx, unsigned tid); 4061060SN/A 4072292SN/A double readArchFloatRegDouble(int reg_idx, unsigned tid); 4082292SN/A 4092292SN/A uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 4102292SN/A 4112348SN/A /** Architectural register accessors. Looks up in the commit 4122348SN/A * rename table to obtain the true physical index of the 4132348SN/A * architected register first, then accesses that physical 4142348SN/A * register. 4152348SN/A */ 4162292SN/A void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 4172292SN/A 4182292SN/A void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 4192292SN/A 4202292SN/A void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 4212292SN/A 4222292SN/A void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 4232292SN/A 4242348SN/A /** Reads the commit PC of a specific thread. */ 4252292SN/A uint64_t readPC(unsigned tid); 4262292SN/A 4272348SN/A /** Sets the commit PC of a specific thread. */ 4282348SN/A void setPC(Addr new_PC, unsigned tid); 4292292SN/A 4302348SN/A /** Reads the next PC of a specific thread. */ 4312292SN/A uint64_t readNextPC(unsigned tid); 4322292SN/A 4332348SN/A /** Sets the next PC of a specific thread. */ 4342348SN/A void setNextPC(uint64_t val, unsigned tid); 4351060SN/A 4362756Sksewell@umich.edu /** Reads the next NPC of a specific thread. */ 4372756Sksewell@umich.edu uint64_t readNextNPC(unsigned tid); 4382756Sksewell@umich.edu 4392756Sksewell@umich.edu /** Sets the next NPC of a specific thread. */ 4402756Sksewell@umich.edu void setNextNPC(uint64_t val, unsigned tid); 4412756Sksewell@umich.edu 4421060SN/A /** Function to add instruction onto the head of the list of the 4431060SN/A * instructions. Used when new instructions are fetched. 4441060SN/A */ 4452292SN/A ListIt addInst(DynInstPtr &inst); 4461060SN/A 4471060SN/A /** Function to tell the CPU that an instruction has completed. */ 4482292SN/A void instDone(unsigned tid); 4491060SN/A 4502292SN/A /** Add Instructions to the CPU Remove List*/ 4512292SN/A void addToRemoveList(DynInstPtr &inst); 4521060SN/A 4532325SN/A /** Remove an instruction from the front end of the list. There's 4542325SN/A * no restriction on location of the instruction. 4551060SN/A */ 4561061SN/A void removeFrontInst(DynInstPtr &inst); 4571060SN/A 4582935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 4592935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 4602935Sksewell@umich.edu void removeInstsNotInROB(unsigned tid, bool squash_delay_slot, 4612935Sksewell@umich.edu const InstSeqNum &delay_slot_seq_num); 4621060SN/A 4631062SN/A /** Remove all instructions younger than the given sequence number. */ 4642292SN/A void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 4652292SN/A 4662348SN/A /** Removes the instruction pointed to by the iterator. */ 4672292SN/A inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 4682292SN/A 4692348SN/A /** Cleans up all instructions on the remove list. */ 4702292SN/A void cleanUpRemovedInsts(); 4711062SN/A 4722348SN/A /** Debug function to print all instructions on the list. */ 4731060SN/A void dumpInsts(); 4741060SN/A 4751060SN/A public: 4761060SN/A /** List of all the instructions in flight. */ 4772292SN/A std::list<DynInstPtr> instList; 4781060SN/A 4792292SN/A /** List of all the instructions that will be removed at the end of this 4802292SN/A * cycle. 4812292SN/A */ 4822292SN/A std::queue<ListIt> removeList; 4832292SN/A 4842325SN/A#ifdef DEBUG 4852348SN/A /** Debug structure to keep track of the sequence numbers still in 4862348SN/A * flight. 4872348SN/A */ 4882292SN/A std::set<InstSeqNum> snList; 4892325SN/A#endif 4902292SN/A 4912325SN/A /** Records if instructions need to be removed this cycle due to 4922325SN/A * being retired or squashed. 4932292SN/A */ 4942292SN/A bool removeInstsThisCycle; 4952292SN/A 4961060SN/A protected: 4971060SN/A /** The fetch stage. */ 4981060SN/A typename CPUPolicy::Fetch fetch; 4991060SN/A 5001060SN/A /** The decode stage. */ 5011060SN/A typename CPUPolicy::Decode decode; 5021060SN/A 5031060SN/A /** The dispatch stage. */ 5041060SN/A typename CPUPolicy::Rename rename; 5051060SN/A 5061060SN/A /** The issue/execute/writeback stages. */ 5071060SN/A typename CPUPolicy::IEW iew; 5081060SN/A 5091060SN/A /** The commit stage. */ 5101060SN/A typename CPUPolicy::Commit commit; 5111060SN/A 5121060SN/A /** The register file. */ 5131060SN/A typename CPUPolicy::RegFile regFile; 5141060SN/A 5151060SN/A /** The free list. */ 5161060SN/A typename CPUPolicy::FreeList freeList; 5171060SN/A 5181060SN/A /** The rename map. */ 5192292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 5202292SN/A 5212292SN/A /** The commit rename map. */ 5222292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 5231060SN/A 5241060SN/A /** The re-order buffer. */ 5251060SN/A typename CPUPolicy::ROB rob; 5261060SN/A 5272292SN/A /** Active Threads List */ 5282292SN/A std::list<unsigned> activeThreads; 5292292SN/A 5302292SN/A /** Integer Register Scoreboard */ 5312292SN/A Scoreboard scoreboard; 5322292SN/A 5331060SN/A public: 5342292SN/A /** Enum to give each stage a specific index, so when calling 5352292SN/A * activateStage() or deactivateStage(), they can specify which stage 5362292SN/A * is being activated/deactivated. 5372292SN/A */ 5382292SN/A enum StageIdx { 5392292SN/A FetchIdx, 5402292SN/A DecodeIdx, 5412292SN/A RenameIdx, 5422292SN/A IEWIdx, 5432292SN/A CommitIdx, 5442292SN/A NumStages }; 5452292SN/A 5461060SN/A /** Typedefs from the Impl to get the structs that each of the 5471060SN/A * time buffers should use. 5481060SN/A */ 5491061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 5501060SN/A 5511061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 5521060SN/A 5531061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 5541060SN/A 5551061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 5561060SN/A 5571061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 5581060SN/A 5591060SN/A /** The main time buffer to do backwards communication. */ 5601060SN/A TimeBuffer<TimeStruct> timeBuffer; 5611060SN/A 5621060SN/A /** The fetch stage's instruction queue. */ 5631060SN/A TimeBuffer<FetchStruct> fetchQueue; 5641060SN/A 5651060SN/A /** The decode stage's instruction queue. */ 5661060SN/A TimeBuffer<DecodeStruct> decodeQueue; 5671060SN/A 5681060SN/A /** The rename stage's instruction queue. */ 5691060SN/A TimeBuffer<RenameStruct> renameQueue; 5701060SN/A 5711060SN/A /** The IEW stage's instruction queue. */ 5721060SN/A TimeBuffer<IEWStruct> iewQueue; 5731060SN/A 5742348SN/A private: 5752348SN/A /** The activity recorder; used to tell if the CPU has any 5762348SN/A * activity remaining or if it can go to idle and deschedule 5772348SN/A * itself. 5782348SN/A */ 5792325SN/A ActivityRecorder activityRec; 5801060SN/A 5812348SN/A public: 5822348SN/A /** Records that there was time buffer activity this cycle. */ 5832325SN/A void activityThisCycle() { activityRec.activity(); } 5842292SN/A 5852348SN/A /** Changes a stage's status to active within the activity recorder. */ 5862325SN/A void activateStage(const StageIdx idx) 5872325SN/A { activityRec.activateStage(idx); } 5882292SN/A 5892348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 5902325SN/A void deactivateStage(const StageIdx idx) 5912325SN/A { activityRec.deactivateStage(idx); } 5922292SN/A 5932292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 5942292SN/A void wakeCPU(); 5952260SN/A 5962292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 5972292SN/A int getFreeTid(); 5982292SN/A 5992292SN/A public: 6002680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 6012680Sktlim@umich.edu ThreadContext *tcBase(unsigned tid) 6021681SN/A { 6032680Sktlim@umich.edu return thread[tid]->getTC(); 6042190SN/A } 6052190SN/A 6062292SN/A /** The global sequence number counter. */ 6073093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 6081060SN/A 6092348SN/A /** Pointer to the checker, which can dynamically verify 6102348SN/A * instruction results at run time. This can be set to NULL if it 6112348SN/A * is not being used. 6122348SN/A */ 6132316SN/A Checker<DynInstPtr> *checker; 6142316SN/A 6151858SN/A#if FULL_SYSTEM 6162292SN/A /** Pointer to the system. */ 6171060SN/A System *system; 6181060SN/A 6192292SN/A /** Pointer to physical memory. */ 6201060SN/A PhysicalMemory *physmem; 6212292SN/A#endif 6221060SN/A 6232316SN/A /** Pointer to memory. */ 6242669Sktlim@umich.edu MemObject *mem; 6251060SN/A 6262843Sktlim@umich.edu /** Event to call process() on once draining has completed. */ 6272843Sktlim@umich.edu Event *drainEvent; 6282843Sktlim@umich.edu 6292843Sktlim@umich.edu /** Counter of how many stages have completed draining. */ 6302843Sktlim@umich.edu int drainCount; 6312316SN/A 6322348SN/A /** Pointers to all of the threads in the CPU. */ 6332292SN/A std::vector<Thread *> thread; 6342260SN/A 6352292SN/A /** Whether or not the CPU should defer its registration. */ 6361060SN/A bool deferRegistration; 6371060SN/A 6382292SN/A /** Is there a context switch pending? */ 6392292SN/A bool contextSwitch; 6401060SN/A 6412292SN/A /** Threads Scheduled to Enter CPU */ 6422292SN/A std::list<int> cpuWaitList; 6432292SN/A 6442292SN/A /** The cycle that the CPU was last running, used for statistics. */ 6452292SN/A Tick lastRunningCycle; 6462292SN/A 6472829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 6482829Sksewell@umich.edu Tick lastActivatedCycle; 6492829Sksewell@umich.edu 6502292SN/A /** Number of Threads CPU can process */ 6512292SN/A unsigned numThreads; 6522292SN/A 6532292SN/A /** Mapping for system thread id to cpu id */ 6542292SN/A std::map<unsigned,unsigned> threadMap; 6552292SN/A 6562292SN/A /** Available thread ids in the cpu*/ 6572292SN/A std::vector<unsigned> tids; 6582292SN/A 6592292SN/A /** Stat for total number of times the CPU is descheduled. */ 6602292SN/A Stats::Scalar<> timesIdled; 6612292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 6622292SN/A Stats::Scalar<> idleCycles; 6632292SN/A /** Stat for the number of committed instructions per thread. */ 6642292SN/A Stats::Vector<> committedInsts; 6652292SN/A /** Stat for the total number of committed instructions. */ 6662292SN/A Stats::Scalar<> totalCommittedInsts; 6672292SN/A /** Stat for the CPI per thread. */ 6682292SN/A Stats::Formula cpi; 6692292SN/A /** Stat for the total CPI. */ 6702292SN/A Stats::Formula totalCpi; 6712292SN/A /** Stat for the IPC per thread. */ 6722292SN/A Stats::Formula ipc; 6732292SN/A /** Stat for the total IPC. */ 6742292SN/A Stats::Formula totalIpc; 6751060SN/A}; 6761060SN/A 6772325SN/A#endif // __CPU_O3_CPU_HH__ 678