cpu.hh revision 2817
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322325SN/A#ifndef __CPU_O3_CPU_HH__ 332325SN/A#define __CPU_O3_CPU_HH__ 341060SN/A 351060SN/A#include <iostream> 361060SN/A#include <list> 372292SN/A#include <queue> 382292SN/A#include <set> 391681SN/A#include <vector> 401060SN/A 412669Sktlim@umich.edu#include "arch/isa_traits.hh" 421060SN/A#include "base/statistics.hh" 431060SN/A#include "base/timebuf.hh" 441858SN/A#include "config/full_system.hh" 452325SN/A#include "cpu/activity.hh" 461717SN/A#include "cpu/base.hh" 472683Sktlim@umich.edu#include "cpu/simple_thread.hh" 481717SN/A#include "cpu/o3/comm.hh" 491717SN/A#include "cpu/o3/cpu_policy.hh" 502292SN/A#include "cpu/o3/scoreboard.hh" 512292SN/A#include "cpu/o3/thread_state.hh" 522817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 531060SN/A#include "sim/process.hh" 541060SN/A 552316SN/Atemplate <class> 562316SN/Aclass Checker; 572680Sktlim@umich.educlass ThreadContext; 582817Sksewell@umich.edutemplate <class> 592817Sksewell@umich.educlass O3ThreadContext; 602669Sktlim@umich.educlass MemObject; 611060SN/Aclass Process; 621060SN/A 632733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 641060SN/A{ 651060SN/A //Stuff that's pretty ISA independent will go here. 661060SN/A public: 671464SN/A typedef BaseCPU::Params Params; 681061SN/A 692733Sktlim@umich.edu BaseO3CPU(Params *params); 702292SN/A 712292SN/A void regStats(); 722632Sstever@eecs.umich.edu 732817Sksewell@umich.edu /** Sets this CPU's ID. */ 742817Sksewell@umich.edu void setCpuId(int id) { cpu_id = id; } 752817Sksewell@umich.edu 762817Sksewell@umich.edu /** Reads this CPU's ID. */ 772669Sktlim@umich.edu int readCpuId() { return cpu_id; } 781681SN/A 791685SN/A protected: 801681SN/A int cpu_id; 811060SN/A}; 821060SN/A 832348SN/A/** 842348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 852348SN/A * within it, as well as all of the time buffers between stages. The 862348SN/A * tick() function for the CPU is defined here. 872348SN/A */ 881060SN/Atemplate <class Impl> 892733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 901060SN/A{ 911060SN/A public: 922669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 932669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 942669Sktlim@umich.edu 952325SN/A // Typedefs from the Impl here. 961060SN/A typedef typename Impl::CPUPol CPUPolicy; 971060SN/A typedef typename Impl::Params Params; 981061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 991060SN/A 1002292SN/A typedef O3ThreadState<Impl> Thread; 1012292SN/A 1022292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1032292SN/A 1042817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1051060SN/A public: 1061060SN/A enum Status { 1071060SN/A Running, 1081060SN/A Idle, 1091060SN/A Halted, 1102307SN/A Blocked, 1112307SN/A SwitchedOut 1121060SN/A }; 1131060SN/A 1142292SN/A /** Overall CPU status. */ 1151060SN/A Status _status; 1161060SN/A 1171060SN/A private: 1181060SN/A class TickEvent : public Event 1191060SN/A { 1201060SN/A private: 1212292SN/A /** Pointer to the CPU. */ 1221755SN/A FullO3CPU<Impl> *cpu; 1231060SN/A 1241060SN/A public: 1252292SN/A /** Constructs a tick event. */ 1261755SN/A TickEvent(FullO3CPU<Impl> *c); 1272292SN/A 1282292SN/A /** Processes a tick event, calling tick() on the CPU. */ 1291060SN/A void process(); 1302292SN/A /** Returns the description of the tick event. */ 1311060SN/A const char *description(); 1321060SN/A }; 1331060SN/A 1342292SN/A /** The tick event used for scheduling CPU ticks. */ 1351060SN/A TickEvent tickEvent; 1361060SN/A 1372292SN/A /** Schedule tick event, regardless of its current state. */ 1381060SN/A void scheduleTickEvent(int delay) 1391060SN/A { 1401060SN/A if (tickEvent.squashed()) 1412307SN/A tickEvent.reschedule(curTick + cycles(delay)); 1421060SN/A else if (!tickEvent.scheduled()) 1432307SN/A tickEvent.schedule(curTick + cycles(delay)); 1441060SN/A } 1451060SN/A 1462292SN/A /** Unschedule tick event, regardless of its current state. */ 1471060SN/A void unscheduleTickEvent() 1481060SN/A { 1491060SN/A if (tickEvent.scheduled()) 1501060SN/A tickEvent.squash(); 1511060SN/A } 1521060SN/A 1531060SN/A public: 1542292SN/A /** Constructs a CPU with the given parameters. */ 1552292SN/A FullO3CPU(Params *params); 1562292SN/A /** Destructor. */ 1571755SN/A ~FullO3CPU(); 1581060SN/A 1592292SN/A /** Registers statistics. */ 1601684SN/A void fullCPURegStats(); 1611684SN/A 1622292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 1632292SN/A * activity to see if the CPU should deschedule itself. 1642292SN/A */ 1651684SN/A void tick(); 1661684SN/A 1672292SN/A /** Initialize the CPU */ 1681060SN/A void init(); 1691060SN/A 1702292SN/A /** Setup CPU to insert a thread's context */ 1712292SN/A void insertThread(unsigned tid); 1721060SN/A 1732292SN/A /** Remove all of a thread's context from CPU */ 1742292SN/A void removeThread(unsigned tid); 1752292SN/A 1762292SN/A /** Count the Total Instructions Committed in the CPU. */ 1772292SN/A virtual Counter totalInstructions() const 1782292SN/A { 1792292SN/A Counter total(0); 1802292SN/A 1812292SN/A for (int i=0; i < thread.size(); i++) 1822292SN/A total += thread[i]->numInst; 1832292SN/A 1842292SN/A return total; 1852292SN/A } 1862292SN/A 1872292SN/A /** Add Thread to Active Threads List. */ 1882292SN/A void activateContext(int tid, int delay); 1892292SN/A 1902292SN/A /** Remove Thread from Active Threads List */ 1912292SN/A void suspendContext(int tid); 1922292SN/A 1932292SN/A /** Remove Thread from Active Threads List && 1942292SN/A * Remove Thread Context from CPU. 1952292SN/A */ 1962292SN/A void deallocateContext(int tid); 1972292SN/A 1982292SN/A /** Remove Thread from Active Threads List && 1992292SN/A * Remove Thread Context from CPU. 2002292SN/A */ 2012292SN/A void haltContext(int tid); 2022292SN/A 2032292SN/A /** Activate a Thread When CPU Resources are Available. */ 2042292SN/A void activateWhenReady(int tid); 2052292SN/A 2062292SN/A /** Add or Remove a Thread Context in the CPU. */ 2072292SN/A void doContextSwitch(); 2082292SN/A 2092292SN/A /** Update The Order In Which We Process Threads. */ 2102292SN/A void updateThreadPriority(); 2112292SN/A 2122292SN/A /** Executes a syscall on this cycle. 2132292SN/A * --------------------------------------- 2142292SN/A * Note: this is a virtual function. CPU-Specific 2152292SN/A * functionality defined in derived classes 2162292SN/A */ 2172325SN/A virtual void syscall(int tid) { panic("Unimplemented!"); } 2182292SN/A 2192348SN/A /** Switches out this CPU. */ 2202307SN/A void switchOut(Sampler *sampler); 2212292SN/A 2222348SN/A /** Signals to this CPU that a stage has completed switching out. */ 2232316SN/A void signalSwitched(); 2242316SN/A 2252348SN/A /** Takes over from another CPU. */ 2261060SN/A void takeOverFrom(BaseCPU *oldCPU); 2271060SN/A 2281060SN/A /** Get the current instruction sequence number, and increment it. */ 2292316SN/A InstSeqNum getAndIncrementInstSeq() 2302316SN/A { return globalSeqNum++; } 2311060SN/A 2321858SN/A#if FULL_SYSTEM 2331060SN/A /** Check if this address is a valid instruction address. */ 2341060SN/A bool validInstAddr(Addr addr) { return true; } 2351060SN/A 2361060SN/A /** Check if this address is a valid data address. */ 2371060SN/A bool validDataAddr(Addr addr) { return true; } 2381060SN/A 2391060SN/A /** Get instruction asid. */ 2402292SN/A int getInstAsid(unsigned tid) 2412292SN/A { return regFile.miscRegs[tid].getInstAsid(); } 2421060SN/A 2431060SN/A /** Get data asid. */ 2442292SN/A int getDataAsid(unsigned tid) 2452292SN/A { return regFile.miscRegs[tid].getDataAsid(); } 2461060SN/A#else 2472292SN/A /** Get instruction asid. */ 2482292SN/A int getInstAsid(unsigned tid) 2492683Sktlim@umich.edu { return thread[tid]->getInstAsid(); } 2501060SN/A 2512292SN/A /** Get data asid. */ 2522292SN/A int getDataAsid(unsigned tid) 2532683Sktlim@umich.edu { return thread[tid]->getDataAsid(); } 2541060SN/A 2551060SN/A#endif 2561060SN/A 2572348SN/A /** Register accessors. Index refers to the physical register index. */ 2581060SN/A uint64_t readIntReg(int reg_idx); 2591060SN/A 2602455SN/A FloatReg readFloatReg(int reg_idx); 2611060SN/A 2622455SN/A FloatReg readFloatReg(int reg_idx, int width); 2631060SN/A 2642455SN/A FloatRegBits readFloatRegBits(int reg_idx); 2652455SN/A 2662455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width); 2671060SN/A 2681060SN/A void setIntReg(int reg_idx, uint64_t val); 2691060SN/A 2702669Sktlim@umich.edu void setFloatReg(int reg_idx, FloatReg val); 2711060SN/A 2722455SN/A void setFloatReg(int reg_idx, FloatReg val, int width); 2731060SN/A 2742455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val); 2752455SN/A 2762669Sktlim@umich.edu void setFloatRegBits(int reg_idx, FloatRegBits val, int width); 2771060SN/A 2782292SN/A uint64_t readArchIntReg(int reg_idx, unsigned tid); 2791060SN/A 2802292SN/A float readArchFloatRegSingle(int reg_idx, unsigned tid); 2811060SN/A 2822292SN/A double readArchFloatRegDouble(int reg_idx, unsigned tid); 2832292SN/A 2842292SN/A uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 2852292SN/A 2862348SN/A /** Architectural register accessors. Looks up in the commit 2872348SN/A * rename table to obtain the true physical index of the 2882348SN/A * architected register first, then accesses that physical 2892348SN/A * register. 2902348SN/A */ 2912292SN/A void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 2922292SN/A 2932292SN/A void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 2942292SN/A 2952292SN/A void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 2962292SN/A 2972292SN/A void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 2982292SN/A 2992348SN/A /** Reads the commit PC of a specific thread. */ 3002292SN/A uint64_t readPC(unsigned tid); 3012292SN/A 3022348SN/A /** Sets the commit PC of a specific thread. */ 3032348SN/A void setPC(Addr new_PC, unsigned tid); 3042292SN/A 3052348SN/A /** Reads the next PC of a specific thread. */ 3062292SN/A uint64_t readNextPC(unsigned tid); 3072292SN/A 3082348SN/A /** Sets the next PC of a specific thread. */ 3092348SN/A void setNextPC(uint64_t val, unsigned tid); 3101060SN/A 3112756Sksewell@umich.edu /** Reads the next NPC of a specific thread. */ 3122756Sksewell@umich.edu uint64_t readNextNPC(unsigned tid); 3132756Sksewell@umich.edu 3142756Sksewell@umich.edu /** Sets the next NPC of a specific thread. */ 3152756Sksewell@umich.edu void setNextNPC(uint64_t val, unsigned tid); 3162756Sksewell@umich.edu 3171060SN/A /** Function to add instruction onto the head of the list of the 3181060SN/A * instructions. Used when new instructions are fetched. 3191060SN/A */ 3202292SN/A ListIt addInst(DynInstPtr &inst); 3211060SN/A 3221060SN/A /** Function to tell the CPU that an instruction has completed. */ 3232292SN/A void instDone(unsigned tid); 3241060SN/A 3252292SN/A /** Add Instructions to the CPU Remove List*/ 3262292SN/A void addToRemoveList(DynInstPtr &inst); 3271060SN/A 3282325SN/A /** Remove an instruction from the front end of the list. There's 3292325SN/A * no restriction on location of the instruction. 3301060SN/A */ 3311061SN/A void removeFrontInst(DynInstPtr &inst); 3321060SN/A 3331060SN/A /** Remove all instructions that are not currently in the ROB. */ 3342292SN/A void removeInstsNotInROB(unsigned tid); 3351060SN/A 3361062SN/A /** Remove all instructions younger than the given sequence number. */ 3372292SN/A void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 3382292SN/A 3392348SN/A /** Removes the instruction pointed to by the iterator. */ 3402292SN/A inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 3412292SN/A 3422348SN/A /** Cleans up all instructions on the remove list. */ 3432292SN/A void cleanUpRemovedInsts(); 3441062SN/A 3452348SN/A /** Debug function to print all instructions on the list. */ 3461060SN/A void dumpInsts(); 3471060SN/A 3481060SN/A public: 3491060SN/A /** List of all the instructions in flight. */ 3502292SN/A std::list<DynInstPtr> instList; 3511060SN/A 3522292SN/A /** List of all the instructions that will be removed at the end of this 3532292SN/A * cycle. 3542292SN/A */ 3552292SN/A std::queue<ListIt> removeList; 3562292SN/A 3572325SN/A#ifdef DEBUG 3582348SN/A /** Debug structure to keep track of the sequence numbers still in 3592348SN/A * flight. 3602348SN/A */ 3612292SN/A std::set<InstSeqNum> snList; 3622325SN/A#endif 3632292SN/A 3642325SN/A /** Records if instructions need to be removed this cycle due to 3652325SN/A * being retired or squashed. 3662292SN/A */ 3672292SN/A bool removeInstsThisCycle; 3682292SN/A 3691060SN/A protected: 3701060SN/A /** The fetch stage. */ 3711060SN/A typename CPUPolicy::Fetch fetch; 3721060SN/A 3731060SN/A /** The decode stage. */ 3741060SN/A typename CPUPolicy::Decode decode; 3751060SN/A 3761060SN/A /** The dispatch stage. */ 3771060SN/A typename CPUPolicy::Rename rename; 3781060SN/A 3791060SN/A /** The issue/execute/writeback stages. */ 3801060SN/A typename CPUPolicy::IEW iew; 3811060SN/A 3821060SN/A /** The commit stage. */ 3831060SN/A typename CPUPolicy::Commit commit; 3841060SN/A 3851060SN/A /** The register file. */ 3861060SN/A typename CPUPolicy::RegFile regFile; 3871060SN/A 3881060SN/A /** The free list. */ 3891060SN/A typename CPUPolicy::FreeList freeList; 3901060SN/A 3911060SN/A /** The rename map. */ 3922292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 3932292SN/A 3942292SN/A /** The commit rename map. */ 3952292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 3961060SN/A 3971060SN/A /** The re-order buffer. */ 3981060SN/A typename CPUPolicy::ROB rob; 3991060SN/A 4002292SN/A /** Active Threads List */ 4012292SN/A std::list<unsigned> activeThreads; 4022292SN/A 4032292SN/A /** Integer Register Scoreboard */ 4042292SN/A Scoreboard scoreboard; 4052292SN/A 4061060SN/A public: 4072292SN/A /** Enum to give each stage a specific index, so when calling 4082292SN/A * activateStage() or deactivateStage(), they can specify which stage 4092292SN/A * is being activated/deactivated. 4102292SN/A */ 4112292SN/A enum StageIdx { 4122292SN/A FetchIdx, 4132292SN/A DecodeIdx, 4142292SN/A RenameIdx, 4152292SN/A IEWIdx, 4162292SN/A CommitIdx, 4172292SN/A NumStages }; 4182292SN/A 4191060SN/A /** Typedefs from the Impl to get the structs that each of the 4201060SN/A * time buffers should use. 4211060SN/A */ 4221061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 4231060SN/A 4241061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 4251060SN/A 4261061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 4271060SN/A 4281061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 4291060SN/A 4301061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 4311060SN/A 4321060SN/A /** The main time buffer to do backwards communication. */ 4331060SN/A TimeBuffer<TimeStruct> timeBuffer; 4341060SN/A 4351060SN/A /** The fetch stage's instruction queue. */ 4361060SN/A TimeBuffer<FetchStruct> fetchQueue; 4371060SN/A 4381060SN/A /** The decode stage's instruction queue. */ 4391060SN/A TimeBuffer<DecodeStruct> decodeQueue; 4401060SN/A 4411060SN/A /** The rename stage's instruction queue. */ 4421060SN/A TimeBuffer<RenameStruct> renameQueue; 4431060SN/A 4441060SN/A /** The IEW stage's instruction queue. */ 4451060SN/A TimeBuffer<IEWStruct> iewQueue; 4461060SN/A 4472348SN/A private: 4482348SN/A /** The activity recorder; used to tell if the CPU has any 4492348SN/A * activity remaining or if it can go to idle and deschedule 4502348SN/A * itself. 4512348SN/A */ 4522325SN/A ActivityRecorder activityRec; 4531060SN/A 4542348SN/A public: 4552348SN/A /** Records that there was time buffer activity this cycle. */ 4562325SN/A void activityThisCycle() { activityRec.activity(); } 4572292SN/A 4582348SN/A /** Changes a stage's status to active within the activity recorder. */ 4592325SN/A void activateStage(const StageIdx idx) 4602325SN/A { activityRec.activateStage(idx); } 4612292SN/A 4622348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 4632325SN/A void deactivateStage(const StageIdx idx) 4642325SN/A { activityRec.deactivateStage(idx); } 4652292SN/A 4662292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 4672292SN/A void wakeCPU(); 4682260SN/A 4692292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 4702292SN/A int getFreeTid(); 4712292SN/A 4722292SN/A public: 4732680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 4742680Sktlim@umich.edu ThreadContext *tcBase(unsigned tid) 4751681SN/A { 4762680Sktlim@umich.edu return thread[tid]->getTC(); 4772190SN/A } 4782190SN/A 4792292SN/A /** The global sequence number counter. */ 4801060SN/A InstSeqNum globalSeqNum; 4811060SN/A 4822348SN/A /** Pointer to the checker, which can dynamically verify 4832348SN/A * instruction results at run time. This can be set to NULL if it 4842348SN/A * is not being used. 4852348SN/A */ 4862316SN/A Checker<DynInstPtr> *checker; 4872316SN/A 4881858SN/A#if FULL_SYSTEM 4892292SN/A /** Pointer to the system. */ 4901060SN/A System *system; 4911060SN/A 4922292SN/A /** Pointer to physical memory. */ 4931060SN/A PhysicalMemory *physmem; 4942292SN/A#endif 4951060SN/A 4962316SN/A /** Pointer to memory. */ 4972669Sktlim@umich.edu MemObject *mem; 4981060SN/A 4992348SN/A /** Pointer to the sampler */ 5002316SN/A Sampler *sampler; 5012316SN/A 5022348SN/A /** Counter of how many stages have completed switching out. */ 5032316SN/A int switchCount; 5042316SN/A 5052348SN/A /** Pointers to all of the threads in the CPU. */ 5062292SN/A std::vector<Thread *> thread; 5072260SN/A 5082292SN/A /** Pointer to the icache interface. */ 5091060SN/A MemInterface *icacheInterface; 5102292SN/A /** Pointer to the dcache interface. */ 5111060SN/A MemInterface *dcacheInterface; 5121060SN/A 5132292SN/A /** Whether or not the CPU should defer its registration. */ 5141060SN/A bool deferRegistration; 5151060SN/A 5162292SN/A /** Is there a context switch pending? */ 5172292SN/A bool contextSwitch; 5181060SN/A 5192292SN/A /** Threads Scheduled to Enter CPU */ 5202292SN/A std::list<int> cpuWaitList; 5212292SN/A 5222292SN/A /** The cycle that the CPU was last running, used for statistics. */ 5232292SN/A Tick lastRunningCycle; 5242292SN/A 5252292SN/A /** Number of Threads CPU can process */ 5262292SN/A unsigned numThreads; 5272292SN/A 5282292SN/A /** Mapping for system thread id to cpu id */ 5292292SN/A std::map<unsigned,unsigned> threadMap; 5302292SN/A 5312292SN/A /** Available thread ids in the cpu*/ 5322292SN/A std::vector<unsigned> tids; 5332292SN/A 5342292SN/A /** Stat for total number of times the CPU is descheduled. */ 5352292SN/A Stats::Scalar<> timesIdled; 5362292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 5372292SN/A Stats::Scalar<> idleCycles; 5382292SN/A /** Stat for the number of committed instructions per thread. */ 5392292SN/A Stats::Vector<> committedInsts; 5402292SN/A /** Stat for the total number of committed instructions. */ 5412292SN/A Stats::Scalar<> totalCommittedInsts; 5422292SN/A /** Stat for the CPI per thread. */ 5432292SN/A Stats::Formula cpi; 5442292SN/A /** Stat for the total CPI. */ 5452292SN/A Stats::Formula totalCpi; 5462292SN/A /** Stat for the IPC per thread. */ 5472292SN/A Stats::Formula ipc; 5482292SN/A /** Stat for the total IPC. */ 5492292SN/A Stats::Formula totalIpc; 5501060SN/A}; 5511060SN/A 5522325SN/A#endif // __CPU_O3_CPU_HH__ 553