cpu.hh revision 2669
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271689SN/A */ 281689SN/A 292325SN/A#ifndef __CPU_O3_CPU_HH__ 302325SN/A#define __CPU_O3_CPU_HH__ 311060SN/A 321060SN/A#include <iostream> 331060SN/A#include <list> 342292SN/A#include <queue> 352292SN/A#include <set> 361681SN/A#include <vector> 371060SN/A 382669Sktlim@umich.edu#include "arch/isa_traits.hh" 391060SN/A#include "base/statistics.hh" 401060SN/A#include "base/timebuf.hh" 411858SN/A#include "config/full_system.hh" 422325SN/A#include "cpu/activity.hh" 431717SN/A#include "cpu/base.hh" 442190SN/A#include "cpu/cpu_exec_context.hh" 451717SN/A#include "cpu/o3/comm.hh" 461717SN/A#include "cpu/o3/cpu_policy.hh" 472292SN/A#include "cpu/o3/scoreboard.hh" 482292SN/A#include "cpu/o3/thread_state.hh" 491060SN/A#include "sim/process.hh" 501060SN/A 512316SN/Atemplate <class> 522316SN/Aclass Checker; 532190SN/Aclass ExecContext; 542669Sktlim@umich.educlass MemObject; 551060SN/Aclass Process; 561060SN/A 571060SN/Aclass BaseFullCPU : public BaseCPU 581060SN/A{ 591060SN/A //Stuff that's pretty ISA independent will go here. 601060SN/A public: 611464SN/A typedef BaseCPU::Params Params; 621061SN/A 632292SN/A BaseFullCPU(Params *params); 642292SN/A 652292SN/A void regStats(); 661681SN/A 672669Sktlim@umich.edu int readCpuId() { return cpu_id; } 682669Sktlim@umich.edu 691685SN/A protected: 701681SN/A int cpu_id; 711060SN/A}; 721060SN/A 731060SN/Atemplate <class Impl> 741755SN/Aclass FullO3CPU : public BaseFullCPU 751060SN/A{ 761060SN/A public: 772669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 782669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 792669Sktlim@umich.edu 802325SN/A // Typedefs from the Impl here. 811060SN/A typedef typename Impl::CPUPol CPUPolicy; 821060SN/A typedef typename Impl::Params Params; 831061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 841060SN/A 852292SN/A typedef O3ThreadState<Impl> Thread; 862292SN/A 872292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 882292SN/A 891060SN/A public: 901060SN/A enum Status { 911060SN/A Running, 921060SN/A Idle, 931060SN/A Halted, 942307SN/A Blocked, 952307SN/A SwitchedOut 961060SN/A }; 971060SN/A 982292SN/A /** Overall CPU status. */ 991060SN/A Status _status; 1001060SN/A 1011060SN/A private: 1021060SN/A class TickEvent : public Event 1031060SN/A { 1041060SN/A private: 1052292SN/A /** Pointer to the CPU. */ 1061755SN/A FullO3CPU<Impl> *cpu; 1071060SN/A 1081060SN/A public: 1092292SN/A /** Constructs a tick event. */ 1101755SN/A TickEvent(FullO3CPU<Impl> *c); 1112292SN/A 1122292SN/A /** Processes a tick event, calling tick() on the CPU. */ 1131060SN/A void process(); 1142292SN/A /** Returns the description of the tick event. */ 1151060SN/A const char *description(); 1161060SN/A }; 1171060SN/A 1182292SN/A /** The tick event used for scheduling CPU ticks. */ 1191060SN/A TickEvent tickEvent; 1201060SN/A 1212292SN/A /** Schedule tick event, regardless of its current state. */ 1221060SN/A void scheduleTickEvent(int delay) 1231060SN/A { 1241060SN/A if (tickEvent.squashed()) 1252307SN/A tickEvent.reschedule(curTick + cycles(delay)); 1261060SN/A else if (!tickEvent.scheduled()) 1272307SN/A tickEvent.schedule(curTick + cycles(delay)); 1281060SN/A } 1291060SN/A 1302292SN/A /** Unschedule tick event, regardless of its current state. */ 1311060SN/A void unscheduleTickEvent() 1321060SN/A { 1331060SN/A if (tickEvent.scheduled()) 1341060SN/A tickEvent.squash(); 1351060SN/A } 1361060SN/A 1371060SN/A public: 1382292SN/A /** Constructs a CPU with the given parameters. */ 1392292SN/A FullO3CPU(Params *params); 1402292SN/A /** Destructor. */ 1411755SN/A ~FullO3CPU(); 1421060SN/A 1432292SN/A /** Registers statistics. */ 1441684SN/A void fullCPURegStats(); 1451684SN/A 1462292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 1472292SN/A * activity to see if the CPU should deschedule itself. 1482292SN/A */ 1491684SN/A void tick(); 1501684SN/A 1512292SN/A /** Initialize the CPU */ 1521060SN/A void init(); 1531060SN/A 1542292SN/A /** Setup CPU to insert a thread's context */ 1552292SN/A void insertThread(unsigned tid); 1561060SN/A 1572292SN/A /** Remove all of a thread's context from CPU */ 1582292SN/A void removeThread(unsigned tid); 1592292SN/A 1602292SN/A /** Count the Total Instructions Committed in the CPU. */ 1612292SN/A virtual Counter totalInstructions() const 1622292SN/A { 1632292SN/A Counter total(0); 1642292SN/A 1652292SN/A for (int i=0; i < thread.size(); i++) 1662292SN/A total += thread[i]->numInst; 1672292SN/A 1682292SN/A return total; 1692292SN/A } 1702292SN/A 1712292SN/A /** Add Thread to Active Threads List. */ 1722292SN/A void activateContext(int tid, int delay); 1732292SN/A 1742292SN/A /** Remove Thread from Active Threads List */ 1752292SN/A void suspendContext(int tid); 1762292SN/A 1772292SN/A /** Remove Thread from Active Threads List && 1782292SN/A * Remove Thread Context from CPU. 1792292SN/A */ 1802292SN/A void deallocateContext(int tid); 1812292SN/A 1822292SN/A /** Remove Thread from Active Threads List && 1832292SN/A * Remove Thread Context from CPU. 1842292SN/A */ 1852292SN/A void haltContext(int tid); 1862292SN/A 1872292SN/A /** Activate a Thread When CPU Resources are Available. */ 1882292SN/A void activateWhenReady(int tid); 1892292SN/A 1902292SN/A /** Add or Remove a Thread Context in the CPU. */ 1912292SN/A void doContextSwitch(); 1922292SN/A 1932292SN/A /** Update The Order In Which We Process Threads. */ 1942292SN/A void updateThreadPriority(); 1952292SN/A 1962292SN/A /** Executes a syscall on this cycle. 1972292SN/A * --------------------------------------- 1982292SN/A * Note: this is a virtual function. CPU-Specific 1992292SN/A * functionality defined in derived classes 2002292SN/A */ 2012325SN/A virtual void syscall(int tid) { panic("Unimplemented!"); } 2022292SN/A 2032292SN/A /** Check if there are any system calls pending. */ 2042292SN/A void checkSyscalls(); 2052292SN/A 2062292SN/A /** Switches out this CPU. 2072292SN/A */ 2082307SN/A void switchOut(Sampler *sampler); 2092292SN/A 2102316SN/A void signalSwitched(); 2112316SN/A 2122292SN/A /** Takes over from another CPU. 2132292SN/A */ 2141060SN/A void takeOverFrom(BaseCPU *oldCPU); 2151060SN/A 2161060SN/A /** Get the current instruction sequence number, and increment it. */ 2172316SN/A InstSeqNum getAndIncrementInstSeq() 2182316SN/A { return globalSeqNum++; } 2191060SN/A 2201858SN/A#if FULL_SYSTEM 2211060SN/A /** Check if this address is a valid instruction address. */ 2221060SN/A bool validInstAddr(Addr addr) { return true; } 2231060SN/A 2241060SN/A /** Check if this address is a valid data address. */ 2251060SN/A bool validDataAddr(Addr addr) { return true; } 2261060SN/A 2271060SN/A /** Get instruction asid. */ 2282292SN/A int getInstAsid(unsigned tid) 2292292SN/A { return regFile.miscRegs[tid].getInstAsid(); } 2301060SN/A 2311060SN/A /** Get data asid. */ 2322292SN/A int getDataAsid(unsigned tid) 2332292SN/A { return regFile.miscRegs[tid].getDataAsid(); } 2341060SN/A#else 2352292SN/A /** Get instruction asid. */ 2362292SN/A int getInstAsid(unsigned tid) 2372292SN/A { return thread[tid]->asid; } 2382292SN/A 2392292SN/A /** Get data asid. */ 2402292SN/A int getDataAsid(unsigned tid) 2412292SN/A { return thread[tid]->asid; } 2421060SN/A 2431060SN/A#endif 2441060SN/A 2451060SN/A // 2461060SN/A // New accessors for new decoder. 2471060SN/A // 2481060SN/A uint64_t readIntReg(int reg_idx); 2491060SN/A 2502455SN/A FloatReg readFloatReg(int reg_idx); 2511060SN/A 2522455SN/A FloatReg readFloatReg(int reg_idx, int width); 2531060SN/A 2542455SN/A FloatRegBits readFloatRegBits(int reg_idx); 2552455SN/A 2562455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width); 2571060SN/A 2581060SN/A void setIntReg(int reg_idx, uint64_t val); 2591060SN/A 2602669Sktlim@umich.edu void setFloatReg(int reg_idx, FloatReg val); 2611060SN/A 2622455SN/A void setFloatReg(int reg_idx, FloatReg val, int width); 2631060SN/A 2642455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val); 2652455SN/A 2662669Sktlim@umich.edu void setFloatRegBits(int reg_idx, FloatRegBits val, int width); 2671060SN/A 2682292SN/A uint64_t readArchIntReg(int reg_idx, unsigned tid); 2691060SN/A 2702292SN/A float readArchFloatRegSingle(int reg_idx, unsigned tid); 2711060SN/A 2722292SN/A double readArchFloatRegDouble(int reg_idx, unsigned tid); 2732292SN/A 2742292SN/A uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 2752292SN/A 2762292SN/A void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 2772292SN/A 2782292SN/A void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 2792292SN/A 2802292SN/A void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 2812292SN/A 2822292SN/A void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 2832292SN/A 2842292SN/A uint64_t readPC(unsigned tid); 2852292SN/A 2862292SN/A void setPC(Addr new_PC,unsigned tid); 2872292SN/A 2882292SN/A uint64_t readNextPC(unsigned tid); 2892292SN/A 2902292SN/A void setNextPC(uint64_t val,unsigned tid); 2911060SN/A 2921060SN/A /** Function to add instruction onto the head of the list of the 2931060SN/A * instructions. Used when new instructions are fetched. 2941060SN/A */ 2952292SN/A ListIt addInst(DynInstPtr &inst); 2961060SN/A 2971060SN/A /** Function to tell the CPU that an instruction has completed. */ 2982292SN/A void instDone(unsigned tid); 2991060SN/A 3002292SN/A /** Add Instructions to the CPU Remove List*/ 3012292SN/A void addToRemoveList(DynInstPtr &inst); 3021060SN/A 3032325SN/A /** Remove an instruction from the front end of the list. There's 3042325SN/A * no restriction on location of the instruction. 3051060SN/A */ 3061061SN/A void removeFrontInst(DynInstPtr &inst); 3071060SN/A 3081060SN/A /** Remove all instructions that are not currently in the ROB. */ 3092292SN/A void removeInstsNotInROB(unsigned tid); 3101060SN/A 3111062SN/A /** Remove all instructions younger than the given sequence number. */ 3122292SN/A void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 3132292SN/A 3142292SN/A inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 3152292SN/A 3162292SN/A void cleanUpRemovedInsts(); 3171062SN/A 3181060SN/A /** Remove all instructions from the list. */ 3192325SN/A// void removeAllInsts(); 3201060SN/A 3211060SN/A void dumpInsts(); 3221060SN/A 3231060SN/A /** Basically a wrapper function so that instructions executed at 3242325SN/A * commit can tell the instruction queue that they have 3252325SN/A * completed. Eventually this hack should be removed. 3261060SN/A */ 3272325SN/A// void wakeDependents(DynInstPtr &inst); 3281060SN/A 3291060SN/A public: 3301060SN/A /** List of all the instructions in flight. */ 3312292SN/A std::list<DynInstPtr> instList; 3321060SN/A 3332292SN/A /** List of all the instructions that will be removed at the end of this 3342292SN/A * cycle. 3352292SN/A */ 3362292SN/A std::queue<ListIt> removeList; 3372292SN/A 3382325SN/A#ifdef DEBUG 3392292SN/A std::set<InstSeqNum> snList; 3402325SN/A#endif 3412292SN/A 3422325SN/A /** Records if instructions need to be removed this cycle due to 3432325SN/A * being retired or squashed. 3442292SN/A */ 3452292SN/A bool removeInstsThisCycle; 3462292SN/A 3471060SN/A protected: 3481060SN/A /** The fetch stage. */ 3491060SN/A typename CPUPolicy::Fetch fetch; 3501060SN/A 3511060SN/A /** The decode stage. */ 3521060SN/A typename CPUPolicy::Decode decode; 3531060SN/A 3541060SN/A /** The dispatch stage. */ 3551060SN/A typename CPUPolicy::Rename rename; 3561060SN/A 3571060SN/A /** The issue/execute/writeback stages. */ 3581060SN/A typename CPUPolicy::IEW iew; 3591060SN/A 3601060SN/A /** The commit stage. */ 3611060SN/A typename CPUPolicy::Commit commit; 3621060SN/A 3631060SN/A /** The register file. */ 3641060SN/A typename CPUPolicy::RegFile regFile; 3651060SN/A 3661060SN/A /** The free list. */ 3671060SN/A typename CPUPolicy::FreeList freeList; 3681060SN/A 3691060SN/A /** The rename map. */ 3702292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 3712292SN/A 3722292SN/A /** The commit rename map. */ 3732292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 3741060SN/A 3751060SN/A /** The re-order buffer. */ 3761060SN/A typename CPUPolicy::ROB rob; 3771060SN/A 3782292SN/A /** Active Threads List */ 3792292SN/A std::list<unsigned> activeThreads; 3802292SN/A 3812292SN/A /** Integer Register Scoreboard */ 3822292SN/A Scoreboard scoreboard; 3832292SN/A 3841060SN/A public: 3852292SN/A /** Enum to give each stage a specific index, so when calling 3862292SN/A * activateStage() or deactivateStage(), they can specify which stage 3872292SN/A * is being activated/deactivated. 3882292SN/A */ 3892292SN/A enum StageIdx { 3902292SN/A FetchIdx, 3912292SN/A DecodeIdx, 3922292SN/A RenameIdx, 3932292SN/A IEWIdx, 3942292SN/A CommitIdx, 3952292SN/A NumStages }; 3962292SN/A 3971060SN/A /** Typedefs from the Impl to get the structs that each of the 3981060SN/A * time buffers should use. 3991060SN/A */ 4001061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 4011060SN/A 4021061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 4031060SN/A 4041061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 4051060SN/A 4061061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 4071060SN/A 4081061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 4091060SN/A 4101060SN/A /** The main time buffer to do backwards communication. */ 4111060SN/A TimeBuffer<TimeStruct> timeBuffer; 4121060SN/A 4131060SN/A /** The fetch stage's instruction queue. */ 4141060SN/A TimeBuffer<FetchStruct> fetchQueue; 4151060SN/A 4161060SN/A /** The decode stage's instruction queue. */ 4171060SN/A TimeBuffer<DecodeStruct> decodeQueue; 4181060SN/A 4191060SN/A /** The rename stage's instruction queue. */ 4201060SN/A TimeBuffer<RenameStruct> renameQueue; 4211060SN/A 4221060SN/A /** The IEW stage's instruction queue. */ 4231060SN/A TimeBuffer<IEWStruct> iewQueue; 4241060SN/A 4251060SN/A public: 4262325SN/A ActivityRecorder activityRec; 4271060SN/A 4282325SN/A void activityThisCycle() { activityRec.activity(); } 4292292SN/A 4302325SN/A void activateStage(const StageIdx idx) 4312325SN/A { activityRec.activateStage(idx); } 4322292SN/A 4332325SN/A void deactivateStage(const StageIdx idx) 4342325SN/A { activityRec.deactivateStage(idx); } 4352292SN/A 4362292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 4372292SN/A void wakeCPU(); 4382260SN/A 4392292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 4402292SN/A int getFreeTid(); 4412292SN/A 4422292SN/A public: 4431060SN/A /** Temporary function to get pointer to exec context. */ 4442292SN/A ExecContext *xcBase(unsigned tid) 4451681SN/A { 4462292SN/A return thread[tid]->getXCProxy(); 4472190SN/A } 4482190SN/A 4492292SN/A /** The global sequence number counter. */ 4501060SN/A InstSeqNum globalSeqNum; 4511060SN/A 4522316SN/A Checker<DynInstPtr> *checker; 4532316SN/A 4541858SN/A#if FULL_SYSTEM 4552292SN/A /** Pointer to the system. */ 4561060SN/A System *system; 4571060SN/A 4582292SN/A /** Pointer to the memory controller. */ 4591060SN/A MemoryController *memCtrl; 4602292SN/A /** Pointer to physical memory. */ 4611060SN/A PhysicalMemory *physmem; 4622292SN/A#endif 4631060SN/A 4642316SN/A /** Pointer to memory. */ 4652669Sktlim@umich.edu MemObject *mem; 4661060SN/A 4672316SN/A Sampler *sampler; 4682316SN/A 4692316SN/A int switchCount; 4702316SN/A 4712292SN/A // List of all ExecContexts. 4722292SN/A std::vector<Thread *> thread; 4732260SN/A 4742292SN/A#if 0 4752292SN/A /** Page table pointer. */ 4762292SN/A PageTable *pTable; 4772292SN/A#endif 4782292SN/A 4792292SN/A /** Pointer to the icache interface. */ 4801060SN/A MemInterface *icacheInterface; 4812292SN/A /** Pointer to the dcache interface. */ 4821060SN/A MemInterface *dcacheInterface; 4831060SN/A 4842292SN/A /** Whether or not the CPU should defer its registration. */ 4851060SN/A bool deferRegistration; 4861060SN/A 4872292SN/A /** Is there a context switch pending? */ 4882292SN/A bool contextSwitch; 4891060SN/A 4902292SN/A /** Threads Scheduled to Enter CPU */ 4912292SN/A std::list<int> cpuWaitList; 4922292SN/A 4932292SN/A /** The cycle that the CPU was last running, used for statistics. */ 4942292SN/A Tick lastRunningCycle; 4952292SN/A 4962292SN/A /** Number of Threads CPU can process */ 4972292SN/A unsigned numThreads; 4982292SN/A 4992292SN/A /** Mapping for system thread id to cpu id */ 5002292SN/A std::map<unsigned,unsigned> threadMap; 5012292SN/A 5022292SN/A /** Available thread ids in the cpu*/ 5032292SN/A std::vector<unsigned> tids; 5042292SN/A 5052292SN/A /** Stat for total number of times the CPU is descheduled. */ 5062292SN/A Stats::Scalar<> timesIdled; 5072292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 5082292SN/A Stats::Scalar<> idleCycles; 5092292SN/A /** Stat for the number of committed instructions per thread. */ 5102292SN/A Stats::Vector<> committedInsts; 5112292SN/A /** Stat for the total number of committed instructions. */ 5122292SN/A Stats::Scalar<> totalCommittedInsts; 5132292SN/A /** Stat for the CPI per thread. */ 5142292SN/A Stats::Formula cpi; 5152292SN/A /** Stat for the total CPI. */ 5162292SN/A Stats::Formula totalCpi; 5172292SN/A /** Stat for the IPC per thread. */ 5182292SN/A Stats::Formula ipc; 5192292SN/A /** Stat for the total IPC. */ 5202292SN/A Stats::Formula totalIpc; 5211060SN/A}; 5221060SN/A 5232325SN/A#endif // __CPU_O3_CPU_HH__ 524