cpu.hh revision 1685
12SN/A//Todo: Add in a lot of the functions that are ISA specific. Also define 21762SN/A//the functions that currently exist within the base cpu class. Define 32SN/A//everything for the simobject stuff so it can be serialized and 42SN/A//instantiated, add in debugging statements everywhere. Have CPU schedule 52SN/A//itself properly. Constructor. Derived alpha class. Threads! 62SN/A// Avoid running stages and advancing queues if idle/stalled. 72SN/A 82SN/A#ifndef __CPU_BETA_CPU_FULL_CPU_HH__ 92SN/A#define __CPU_BETA_CPU_FULL_CPU_HH__ 102SN/A 112SN/A#include <iostream> 122SN/A#include <list> 132SN/A#include <vector> 142SN/A 152SN/A#include "base/statistics.hh" 162SN/A#include "base/timebuf.hh" 172SN/A#include "cpu/base_cpu.hh" 182SN/A#include "cpu/beta_cpu/comm.hh" 192SN/A#include "cpu/beta_cpu/cpu_policy.hh" 202SN/A#include "cpu/exec_context.hh" 212SN/A#include "sim/process.hh" 222SN/A 232SN/A#ifdef FULL_SYSTEM 242SN/A#include "arch/alpha/ev5.hh" 252SN/Ausing namespace EV5; 262SN/A#endif 272665Ssaidi@eecs.umich.edu 282665Ssaidi@eecs.umich.educlass FunctionalMemory; 292665Ssaidi@eecs.umich.educlass Process; 302SN/A 312SN/Aclass BaseFullCPU : public BaseCPU 321388SN/A{ 332SN/A //Stuff that's pretty ISA independent will go here. 342SN/A public: 352SN/A typedef BaseCPU::Params Params; 361191SN/A 371191SN/A#ifdef FULL_SYSTEM 381191SN/A BaseFullCPU(Params ¶ms); 391388SN/A#else 401717SN/A BaseFullCPU(Params ¶ms); 412651Ssaidi@eecs.umich.edu#endif // FULL_SYSTEM 422680Sktlim@umich.edu 431977SN/A protected: 443144Shsul@eecs.umich.edu int cpu_id; 452190SN/A}; 4656SN/A 472190SN/Atemplate <class Impl> 482SN/Aclass FullBetaCPU : public BaseFullCPU 491062SN/A{ 501062SN/A public: 512359SN/A //Put typedefs from the Impl here. 522359SN/A typedef typename Impl::ISA ISA; 532359SN/A typedef typename Impl::CPUPol CPUPolicy; 542SN/A typedef typename Impl::Params Params; 552SN/A typedef typename Impl::DynInstPtr DynInstPtr; 562SN/A 572SN/A public: 582SN/A enum Status { 592SN/A Running, 602SN/A Idle, 612SN/A Halted, 622SN/A Blocked // ? 633126Sktlim@umich.edu }; 643126Sktlim@umich.edu 654075Sbinkertn@umich.edu Status _status; 663126Sktlim@umich.edu 673126Sktlim@umich.edu private: 683126Sktlim@umich.edu class TickEvent : public Event 693126Sktlim@umich.edu { 703126Sktlim@umich.edu private: 713126Sktlim@umich.edu FullBetaCPU<Impl> *cpu; 722356SN/A 732356SN/A public: 742356SN/A TickEvent(FullBetaCPU<Impl> *c); 752367SN/A void process(); 762356SN/A const char *description(); 775100Ssaidi@eecs.umich.edu }; 782367SN/A 792356SN/A TickEvent tickEvent; 802356SN/A 812356SN/A /// Schedule tick event, regardless of its current state. 822367SN/A void scheduleTickEvent(int delay) 832367SN/A { 842367SN/A if (tickEvent.squashed()) 852367SN/A tickEvent.reschedule(curTick + delay); 862356SN/A else if (!tickEvent.scheduled()) 872356SN/A tickEvent.schedule(curTick + delay); 882356SN/A } 892356SN/A 902356SN/A /// Unschedule tick event, regardless of its current state. 915336Shines@cs.fsu.edu void unscheduleTickEvent() 922356SN/A { 934873Sstever@eecs.umich.edu if (tickEvent.scheduled()) 942356SN/A tickEvent.squash(); 952356SN/A } 961858SN/A 971400SN/A public: 985034Smilesck@eecs.umich.edu FullBetaCPU(Params ¶ms); 993661Srdreslin@umich.edu ~FullBetaCPU(); 1003661Srdreslin@umich.edu 1012SN/A void fullCPURegStats(); 1021400SN/A 1035034Smilesck@eecs.umich.edu void tick(); 1043661Srdreslin@umich.edu 1053661Srdreslin@umich.edu void init(); 1062SN/A 1072SN/A void activateContext(int thread_num, int delay); 1082359SN/A void suspendContext(int thread_num); 1091062SN/A void deallocateContext(int thread_num); 1102SN/A void haltContext(int thread_num); 1112SN/A 1122SN/A void switchOut(); 1132SN/A void takeOverFrom(BaseCPU *oldCPU); 1142SN/A 1152SN/A /** Get the current instruction sequence number, and increment it. */ 1162SN/A InstSeqNum getAndIncrementInstSeq(); 1171354SN/A 1182SN/A#ifdef FULL_SYSTEM 119503SN/A /** Check if this address is a valid instruction address. */ 1202SN/A bool validInstAddr(Addr addr) { return true; } 1212SN/A 1222SN/A /** Check if this address is a valid data address. */ 1232SN/A bool validDataAddr(Addr addr) { return true; } 1241400SN/A 1252SN/A /** Get instruction asid. */ 1263144Shsul@eecs.umich.edu int getInstAsid() 1273144Shsul@eecs.umich.edu { return ITB_ASN_ASN(regFile.getIpr()[ISA::IPR_ITB_ASN]); } 1283144Shsul@eecs.umich.edu 1292SN/A /** Get data asid. */ 1301400SN/A int getDataAsid() 1312SN/A { return DTB_ASN_ASN(regFile.getIpr()[ISA::IPR_DTB_ASN]); } 1322SN/A#else 1332SN/A bool validInstAddr(Addr addr) 1342SN/A { return thread[0]->validInstAddr(addr); } 1352SN/A 1362SN/A bool validDataAddr(Addr addr) 137503SN/A { return thread[0]->validDataAddr(addr); } 1382SN/A 1391400SN/A int getInstAsid() { return thread[0]->asid; } 1402SN/A int getDataAsid() { return thread[0]->asid; } 1412SN/A 142124SN/A#endif 1431354SN/A 144124SN/A // 145124SN/A // New accessors for new decoder. 146124SN/A // 147124SN/A uint64_t readIntReg(int reg_idx); 148124SN/A 149124SN/A float readFloatRegSingle(int reg_idx); 1501400SN/A 151124SN/A double readFloatRegDouble(int reg_idx); 1523144Shsul@eecs.umich.edu 1533144Shsul@eecs.umich.edu uint64_t readFloatRegInt(int reg_idx); 1543144Shsul@eecs.umich.edu 155124SN/A void setIntReg(int reg_idx, uint64_t val); 1561400SN/A 157124SN/A void setFloatRegSingle(int reg_idx, float val); 158124SN/A 159124SN/A void setFloatRegDouble(int reg_idx, double val); 160124SN/A 161124SN/A void setFloatRegInt(int reg_idx, uint64_t val); 162124SN/A 163124SN/A uint64_t readPC(); 164124SN/A 1651400SN/A void setNextPC(uint64_t val); 166124SN/A 167124SN/A void setPC(Addr new_PC); 1681191SN/A 1691400SN/A /** Function to add instruction onto the head of the list of the 1701388SN/A * instructions. Used when new instructions are fetched. 1711191SN/A */ 1721400SN/A void addInst(DynInstPtr &inst); 1731191SN/A 1741400SN/A /** Function to tell the CPU that an instruction has completed. */ 1751191SN/A void instDone(); 1761191SN/A 1774471Sstever@eecs.umich.edu /** Remove all instructions in back of the given instruction, but leave 1784471Sstever@eecs.umich.edu * that instruction in the list. This is useful in a squash, when there 1794471Sstever@eecs.umich.edu * are instructions in this list that don't exist in structures such as 1801191SN/A * the ROB. The instruction doesn't have to be the last instruction in 1811191SN/A * the list, but will be once this function completes. 1821917SN/A * @todo: Remove only up until that inst? Squashed inst is most likely 1831917SN/A * valid. 1841917SN/A */ 1851917SN/A void removeBackInst(DynInstPtr &inst); 1861917SN/A 1874776Sgblack@eecs.umich.edu /** Remove an instruction from the front of the list. It is expected 1882SN/A * that there are no instructions in front of it (that is, none are older 1892SN/A * than the instruction being removed). Used when retiring instructions. 1901917SN/A * @todo: Remove the argument to this function, and just have it remove 1911917SN/A * last instruction once it's verified that commit has the same ordering 1921917SN/A * as the instruction list. 1931917SN/A */ 1941917SN/A void removeFrontInst(DynInstPtr &inst); 1952315SN/A 1964776Sgblack@eecs.umich.edu /** Remove all instructions that are not currently in the ROB. */ 1971917SN/A void removeInstsNotInROB(); 1981191SN/A 1991191SN/A /** Remove all instructions younger than the given sequence number. */ 2001191SN/A void removeInstsUntil(const InstSeqNum &seq_num); 2011191SN/A 2021191SN/A /** Remove all instructions from the list. */ 2031191SN/A void removeAllInsts(); 2041191SN/A 2051191SN/A void dumpInsts(); 2061191SN/A 2071191SN/A /** Basically a wrapper function so that instructions executed at 2081191SN/A * commit can tell the instruction queue that they have completed. 2091129SN/A * Eventually this hack should be removed. 2101129SN/A */ 2111129SN/A void wakeDependents(DynInstPtr &inst); 2121400SN/A 2132680Sktlim@umich.edu public: 2141129SN/A /** List of all the instructions in flight. */ 215180SN/A list<DynInstPtr> instList; 2162SN/A 2171917SN/A //not sure these should be private. 2181917SN/A protected: 2191917SN/A /** The fetch stage. */ 2201917SN/A typename CPUPolicy::Fetch fetch; 2211917SN/A 2221917SN/A /** The fetch stage's status. */ 2232356SN/A typename CPUPolicy::Fetch::Status fetchStatus; 2242356SN/A 2254031Sktlim@umich.edu /** The decode stage. */ 2265100Ssaidi@eecs.umich.edu typename CPUPolicy::Decode decode; 2272356SN/A 2282356SN/A /** The decode stage's status. */ 2291917SN/A typename CPUPolicy::Decode::Status decodeStatus; 2301917SN/A 2311917SN/A /** The dispatch stage. */ 2321917SN/A typename CPUPolicy::Rename rename; 2332SN/A 2342SN/A /** The dispatch stage's status. */ 235729SN/A typename CPUPolicy::Rename::Status renameStatus; 236707SN/A 237707SN/A /** The issue/execute/writeback stages. */ 238707SN/A typename CPUPolicy::IEW iew; 239707SN/A 240707SN/A /** The issue/execute/writeback stage's status. */ 241707SN/A typename CPUPolicy::IEW::Status iewStatus; 2422680Sktlim@umich.edu 2432SN/A /** The commit stage. */ 2442SN/A typename CPUPolicy::Commit commit; 2452SN/A 2462SN/A /** The fetch stage's status. */ 2472680Sktlim@umich.edu typename CPUPolicy::Commit::Status commitStatus; 2482SN/A 2492SN/A //Might want to just pass these objects in to the constructors of the 2502680Sktlim@umich.edu //appropriate stage. regFile is in iew, freeList in dispatch, renameMap 2512190SN/A //in dispatch, and the rob in commit. 2522190SN/A /** The register file. */ 2532190SN/A typename CPUPolicy::RegFile regFile; 2542SN/A 2552SN/A /** The free list. */ 2563495Sktlim@umich.edu typename CPUPolicy::FreeList freeList; 2573495Sktlim@umich.edu 2583495Sktlim@umich.edu /** The rename map. */ 2593661Srdreslin@umich.edu typename CPUPolicy::RenameMap renameMap; 2603495Sktlim@umich.edu 2613661Srdreslin@umich.edu /** The re-order buffer. */ 2623495Sktlim@umich.edu typename CPUPolicy::ROB rob; 2633495Sktlim@umich.edu 2643495Sktlim@umich.edu public: 2653495Sktlim@umich.edu /** Typedefs from the Impl to get the structs that each of the 2663495Sktlim@umich.edu * time buffers should use. 2673495Sktlim@umich.edu */ 2683495Sktlim@umich.edu typedef typename CPUPolicy::TimeStruct TimeStruct; 2694599Sacolyte@umich.edu 2704599Sacolyte@umich.edu typedef typename CPUPolicy::FetchStruct FetchStruct; 2713661Srdreslin@umich.edu 2723495Sktlim@umich.edu typedef typename CPUPolicy::DecodeStruct DecodeStruct; 2733495Sktlim@umich.edu 2743495Sktlim@umich.edu typedef typename CPUPolicy::RenameStruct RenameStruct; 2753495Sktlim@umich.edu 276180SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 277180SN/A 2782680Sktlim@umich.edu /** The main time buffer to do backwards communication. */ 279180SN/A TimeBuffer<TimeStruct> timeBuffer; 2802680Sktlim@umich.edu 2812680Sktlim@umich.edu /** The fetch stage's instruction queue. */ 2822378SN/A TimeBuffer<FetchStruct> fetchQueue; 2831858SN/A 2841806SN/A /** The decode stage's instruction queue. */ 2851806SN/A TimeBuffer<DecodeStruct> decodeQueue; 2861806SN/A 287180SN/A /** The rename stage's instruction queue. */ 2882680Sktlim@umich.edu TimeBuffer<RenameStruct> renameQueue; 289180SN/A 2902680Sktlim@umich.edu /** The IEW stage's instruction queue. */ 291180SN/A TimeBuffer<IEWStruct> iewQueue; 292180SN/A 293180SN/A public: 294180SN/A /** The temporary exec context to support older accessors. */ 295180SN/A ExecContext *xc; 2964000Ssaidi@eecs.umich.edu 2974000Ssaidi@eecs.umich.edu /** Temporary function to get pointer to exec context. */ 2984000Ssaidi@eecs.umich.edu ExecContext *xcBase() 2994000Ssaidi@eecs.umich.edu { 3004000Ssaidi@eecs.umich.edu#ifdef FULL_SYSTEM 3014000Ssaidi@eecs.umich.edu return system->execContexts[0]; 3024000Ssaidi@eecs.umich.edu#else 3034000Ssaidi@eecs.umich.edu return thread[0]; 3044000Ssaidi@eecs.umich.edu#endif 3054000Ssaidi@eecs.umich.edu } 306180SN/A 3072798Sktlim@umich.edu InstSeqNum globalSeqNum; 308180SN/A 3092359SN/A#ifdef FULL_SYSTEM 3102359SN/A System *system; 3112359SN/A 3122359SN/A MemoryController *memCtrl; 3132359SN/A PhysicalMemory *physmem; 314180SN/A 315180SN/A AlphaITB *itb; 316180SN/A AlphaDTB *dtb; 3174192Sktlim@umich.edu 318180SN/A// SWContext *swCtx; 3192680Sktlim@umich.edu#else 320180SN/A std::vector<ExecContext *> thread; 3212680Sktlim@umich.edu#endif 3222680Sktlim@umich.edu 3232680Sktlim@umich.edu FunctionalMemory *mem; 324180SN/A 3252680Sktlim@umich.edu MemInterface *icacheInterface; 3262651Ssaidi@eecs.umich.edu MemInterface *dcacheInterface; 3272680Sktlim@umich.edu 3282651Ssaidi@eecs.umich.edu bool deferRegistration; 3292680Sktlim@umich.edu 3301858SN/A Counter numInsts; 3312680Sktlim@umich.edu 332180SN/A Counter funcExeInst; 3332680Sktlim@umich.edu}; 3342680Sktlim@umich.edu 335180SN/A#endif 3362359SN/A