cpu.hh revision 13641
11689SN/A/* 213601Sgiacomo.travaglini@arm.com * Copyright (c) 2011-2013, 2016-2019 ARM Limited 39919Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 151689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 167897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432756Sksewell@umich.edu * Korey Sewell 447897Shestness@cs.utexas.edu * Rick Strong 451689SN/A */ 461689SN/A 472325SN/A#ifndef __CPU_O3_CPU_HH__ 482325SN/A#define __CPU_O3_CPU_HH__ 491060SN/A 501060SN/A#include <iostream> 511060SN/A#include <list> 522292SN/A#include <queue> 532292SN/A#include <set> 541681SN/A#include <vector> 551060SN/A 5612109SRekai.GonzalezAlberquilla@arm.com#include "arch/generic/types.hh" 572980Sgblack@eecs.umich.edu#include "arch/types.hh" 581060SN/A#include "base/statistics.hh" 596658Snate@binkert.org#include "config/the_isa.hh" 601717SN/A#include "cpu/o3/comm.hh" 611717SN/A#include "cpu/o3/cpu_policy.hh" 622292SN/A#include "cpu/o3/scoreboard.hh" 632292SN/A#include "cpu/o3/thread_state.hh" 648229Snate@binkert.org#include "cpu/activity.hh" 658229Snate@binkert.org#include "cpu/base.hh" 668229Snate@binkert.org#include "cpu/simple_thread.hh" 678229Snate@binkert.org#include "cpu/timebuf.hh" 682817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 698229Snate@binkert.org#include "params/DerivO3CPU.hh" 701060SN/A#include "sim/process.hh" 711060SN/A 722316SN/Atemplate <class> 732316SN/Aclass Checker; 742680Sktlim@umich.educlass ThreadContext; 752817Sksewell@umich.edutemplate <class> 762817Sksewell@umich.educlass O3ThreadContext; 772843Sktlim@umich.edu 782843Sktlim@umich.educlass Checkpoint; 792669Sktlim@umich.educlass MemObject; 801060SN/Aclass Process; 811060SN/A 828737Skoansin.tan@gmail.comstruct BaseCPUParams; 835529Snate@binkert.org 842733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 851060SN/A{ 861060SN/A //Stuff that's pretty ISA independent will go here. 871060SN/A public: 885529Snate@binkert.org BaseO3CPU(BaseCPUParams *params); 892292SN/A 902292SN/A void regStats(); 911060SN/A}; 921060SN/A 932348SN/A/** 942348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 952348SN/A * within it, as well as all of the time buffers between stages. The 962348SN/A * tick() function for the CPU is defined here. 972348SN/A */ 981060SN/Atemplate <class Impl> 992733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 1001060SN/A{ 1011060SN/A public: 1022325SN/A // Typedefs from the Impl here. 1031060SN/A typedef typename Impl::CPUPol CPUPolicy; 1041061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1054329Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 1061060SN/A 10712109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 10812109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 10912109SRekai.GonzalezAlberquilla@arm.com 11013610Sgiacomo.gabrielli@arm.com using VecPredRegContainer = TheISA::VecPredRegContainer; 11113610Sgiacomo.gabrielli@arm.com 1125595Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> ImplState; 1132292SN/A typedef O3ThreadState<Impl> Thread; 1142292SN/A 1152292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1162292SN/A 1172817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1182829Sksewell@umich.edu 1191060SN/A public: 1201060SN/A enum Status { 1211060SN/A Running, 1221060SN/A Idle, 1231060SN/A Halted, 1242307SN/A Blocked, 1252307SN/A SwitchedOut 1261060SN/A }; 1271060SN/A 12812406Sgabeblack@google.com BaseTLB *itb; 12912406Sgabeblack@google.com BaseTLB *dtb; 13013590Srekai.gonzalezalberquilla@arm.com using LSQRequest = typename LSQ<Impl>::LSQRequest; 1313781Sgblack@eecs.umich.edu 1322292SN/A /** Overall CPU status. */ 1331060SN/A Status _status; 1341060SN/A 1351060SN/A private: 1368707Sandreas.hansson@arm.com 1378707Sandreas.hansson@arm.com /** 1388707Sandreas.hansson@arm.com * IcachePort class for instruction fetch. 1398707Sandreas.hansson@arm.com */ 1409608Sandreas.hansson@arm.com class IcachePort : public MasterPort 1418707Sandreas.hansson@arm.com { 1428707Sandreas.hansson@arm.com protected: 1438707Sandreas.hansson@arm.com /** Pointer to fetch. */ 1448707Sandreas.hansson@arm.com DefaultFetch<Impl> *fetch; 1458707Sandreas.hansson@arm.com 1468707Sandreas.hansson@arm.com public: 1478707Sandreas.hansson@arm.com /** Default constructor. */ 1488707Sandreas.hansson@arm.com IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 1499608Sandreas.hansson@arm.com : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 1508707Sandreas.hansson@arm.com { } 1518707Sandreas.hansson@arm.com 1528707Sandreas.hansson@arm.com protected: 1538707Sandreas.hansson@arm.com 1548707Sandreas.hansson@arm.com /** Timing version of receive. Handles setting fetch to the 1558707Sandreas.hansson@arm.com * proper status to start fetching. */ 1568975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1578707Sandreas.hansson@arm.com 1588707Sandreas.hansson@arm.com /** Handles doing a retry of a failed fetch. */ 15910713Sandreas.hansson@arm.com virtual void recvReqRetry(); 1608707Sandreas.hansson@arm.com }; 1618707Sandreas.hansson@arm.com 1628707Sandreas.hansson@arm.com /** 1638707Sandreas.hansson@arm.com * DcachePort class for the load/store queue. 1648707Sandreas.hansson@arm.com */ 1659608Sandreas.hansson@arm.com class DcachePort : public MasterPort 1668707Sandreas.hansson@arm.com { 1678707Sandreas.hansson@arm.com protected: 1688707Sandreas.hansson@arm.com 1698707Sandreas.hansson@arm.com /** Pointer to LSQ. */ 1708707Sandreas.hansson@arm.com LSQ<Impl> *lsq; 17110529Smorr@cs.wisc.edu FullO3CPU<Impl> *cpu; 1728707Sandreas.hansson@arm.com 1738707Sandreas.hansson@arm.com public: 1748707Sandreas.hansson@arm.com /** Default constructor. */ 1758707Sandreas.hansson@arm.com DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 17610529Smorr@cs.wisc.edu : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), 17710529Smorr@cs.wisc.edu cpu(_cpu) 1788707Sandreas.hansson@arm.com { } 1798707Sandreas.hansson@arm.com 1808707Sandreas.hansson@arm.com protected: 1818707Sandreas.hansson@arm.com 1828707Sandreas.hansson@arm.com /** Timing version of receive. Handles writing back and 1838707Sandreas.hansson@arm.com * completing the load or store that has returned from 1848707Sandreas.hansson@arm.com * memory. */ 1858975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1868975Sandreas.hansson@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt); 1878707Sandreas.hansson@arm.com 1889608Sandreas.hansson@arm.com virtual void recvFunctionalSnoop(PacketPtr pkt) 1899608Sandreas.hansson@arm.com { 1909608Sandreas.hansson@arm.com // @todo: Is there a need for potential invalidation here? 1919608Sandreas.hansson@arm.com } 1929608Sandreas.hansson@arm.com 1938707Sandreas.hansson@arm.com /** Handles doing a retry of the previous send. */ 19410713Sandreas.hansson@arm.com virtual void recvReqRetry(); 1958707Sandreas.hansson@arm.com 1968707Sandreas.hansson@arm.com /** 1978707Sandreas.hansson@arm.com * As this CPU requires snooping to maintain the load store queue 1988707Sandreas.hansson@arm.com * change the behaviour from the base CPU port. 1998707Sandreas.hansson@arm.com * 2008711Sandreas.hansson@arm.com * @return true since we have to snoop 2018707Sandreas.hansson@arm.com */ 2028922Swilliam.wang@arm.com virtual bool isSnooping() const { return true; } 2038707Sandreas.hansson@arm.com }; 2048707Sandreas.hansson@arm.com 2052292SN/A /** The tick event used for scheduling CPU ticks. */ 20612127Sspwilson2@wisc.edu EventFunctionWrapper tickEvent; 2071060SN/A 20813641Sqtt2@cornell.edu /** The exit event used for terminating all ready-to-exit threads */ 20913641Sqtt2@cornell.edu EventFunctionWrapper threadExitEvent; 21013641Sqtt2@cornell.edu 2112292SN/A /** Schedule tick event, regardless of its current state. */ 2129180Sandreas.hansson@arm.com void scheduleTickEvent(Cycles delay) 2131060SN/A { 2141060SN/A if (tickEvent.squashed()) 2159179Sandreas.hansson@arm.com reschedule(tickEvent, clockEdge(delay)); 2161060SN/A else if (!tickEvent.scheduled()) 2179179Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(delay)); 2181060SN/A } 2191060SN/A 2202292SN/A /** Unschedule tick event, regardless of its current state. */ 2211060SN/A void unscheduleTickEvent() 2221060SN/A { 2231060SN/A if (tickEvent.scheduled()) 2241060SN/A tickEvent.squash(); 2251060SN/A } 2261060SN/A 2279444SAndreas.Sandberg@ARM.com /** 22810913Sandreas.sandberg@arm.com * Check if the pipeline has drained and signal drain done. 2299444SAndreas.Sandberg@ARM.com * 2309444SAndreas.Sandberg@ARM.com * This method checks if a drain has been requested and if the CPU 2319444SAndreas.Sandberg@ARM.com * has drained successfully (i.e., there are no instructions in 2329444SAndreas.Sandberg@ARM.com * the pipeline). If the CPU has drained, it deschedules the tick 2339444SAndreas.Sandberg@ARM.com * event and signals the drain manager. 2349444SAndreas.Sandberg@ARM.com * 2359444SAndreas.Sandberg@ARM.com * @return False if a drain hasn't been requested or the CPU 2369444SAndreas.Sandberg@ARM.com * hasn't drained, true otherwise. 2379444SAndreas.Sandberg@ARM.com */ 2389444SAndreas.Sandberg@ARM.com bool tryDrain(); 2399444SAndreas.Sandberg@ARM.com 2409444SAndreas.Sandberg@ARM.com /** 2419444SAndreas.Sandberg@ARM.com * Perform sanity checks after a drain. 2429444SAndreas.Sandberg@ARM.com * 2439444SAndreas.Sandberg@ARM.com * This method is called from drain() when it has determined that 2449444SAndreas.Sandberg@ARM.com * the CPU is fully drained when gem5 is compiled with the NDEBUG 2459444SAndreas.Sandberg@ARM.com * macro undefined. The intention of this method is to do more 2469444SAndreas.Sandberg@ARM.com * extensive tests than the isDrained() method to weed out any 2479444SAndreas.Sandberg@ARM.com * draining bugs. 2489444SAndreas.Sandberg@ARM.com */ 2499444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 2509444SAndreas.Sandberg@ARM.com 2519444SAndreas.Sandberg@ARM.com /** Check if a system is in a drained state. */ 2529444SAndreas.Sandberg@ARM.com bool isDrained() const; 2539444SAndreas.Sandberg@ARM.com 2541060SN/A public: 2552292SN/A /** Constructs a CPU with the given parameters. */ 2565595Sgblack@eecs.umich.edu FullO3CPU(DerivO3CPUParams *params); 2572292SN/A /** Destructor. */ 2581755SN/A ~FullO3CPU(); 2591060SN/A 2602292SN/A /** Registers statistics. */ 26111169Sandreas.hansson@arm.com void regStats() override; 2621684SN/A 26310023Smatt.horsnell@ARM.com ProbePointArg<PacketPtr> *ppInstAccessComplete; 26410023Smatt.horsnell@ARM.com ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete; 26510023Smatt.horsnell@ARM.com 26610023Smatt.horsnell@ARM.com /** Register probe points. */ 26711169Sandreas.hansson@arm.com void regProbePoints() override; 26810023Smatt.horsnell@ARM.com 2695358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 2705358Sgblack@eecs.umich.edu { 2715358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2725358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2735358Sgblack@eecs.umich.edu } 2745358Sgblack@eecs.umich.edu 2755358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 2765358Sgblack@eecs.umich.edu { 2775358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2785358Sgblack@eecs.umich.edu } 2795358Sgblack@eecs.umich.edu 2805358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 2815358Sgblack@eecs.umich.edu { 2825358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2835358Sgblack@eecs.umich.edu } 2845358Sgblack@eecs.umich.edu 2852292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 2862292SN/A * activity to see if the CPU should deschedule itself. 2872292SN/A */ 2881684SN/A void tick(); 2891684SN/A 2902292SN/A /** Initialize the CPU */ 29111169Sandreas.hansson@arm.com void init() override; 2921060SN/A 29311169Sandreas.hansson@arm.com void startup() override; 2949427SAndreas.Sandberg@ARM.com 2952834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 2962834Sksewell@umich.edu int numActiveThreads() 2972834Sksewell@umich.edu { return activeThreads.size(); } 2982834Sksewell@umich.edu 2992829Sksewell@umich.edu /** Add Thread to Active Threads List */ 3006221Snate@binkert.org void activateThread(ThreadID tid); 3012875Sksewell@umich.edu 3022875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 3036221Snate@binkert.org void deactivateThread(ThreadID tid); 3042829Sksewell@umich.edu 3052292SN/A /** Setup CPU to insert a thread's context */ 3066221Snate@binkert.org void insertThread(ThreadID tid); 3071060SN/A 3082292SN/A /** Remove all of a thread's context from CPU */ 3096221Snate@binkert.org void removeThread(ThreadID tid); 3102292SN/A 3112292SN/A /** Count the Total Instructions Committed in the CPU. */ 31211169Sandreas.hansson@arm.com Counter totalInsts() const override; 3138834Satgutier@umich.edu 3148834Satgutier@umich.edu /** Count the Total Ops (including micro ops) committed in the CPU. */ 31511169Sandreas.hansson@arm.com Counter totalOps() const override; 3162292SN/A 3172292SN/A /** Add Thread to Active Threads List. */ 31811169Sandreas.hansson@arm.com void activateContext(ThreadID tid) override; 3192292SN/A 3202292SN/A /** Remove Thread from Active Threads List */ 32111169Sandreas.hansson@arm.com void suspendContext(ThreadID tid) override; 3222292SN/A 3232292SN/A /** Remove Thread from Active Threads List && 3242292SN/A * Remove Thread Context from CPU. 3252292SN/A */ 32611169Sandreas.hansson@arm.com void haltContext(ThreadID tid) override; 3272292SN/A 3282292SN/A /** Update The Order In Which We Process Threads. */ 3292292SN/A void updateThreadPriority(); 3302292SN/A 3319444SAndreas.Sandberg@ARM.com /** Is the CPU draining? */ 33210913Sandreas.sandberg@arm.com bool isDraining() const { return drainState() == DrainState::Draining; } 3339444SAndreas.Sandberg@ARM.com 33411168Sandreas.hansson@arm.com void serializeThread(CheckpointOut &cp, ThreadID tid) const override; 33511168Sandreas.hansson@arm.com void unserializeThread(CheckpointIn &cp, ThreadID tid) override; 3362864Sktlim@umich.edu 33713641Sqtt2@cornell.edu /** Insert tid to the list of threads trying to exit */ 33813641Sqtt2@cornell.edu void addThreadToExitingList(ThreadID tid); 33913641Sqtt2@cornell.edu 34013641Sqtt2@cornell.edu /** Is the thread trying to exit? */ 34113641Sqtt2@cornell.edu bool isThreadExiting(ThreadID tid) const; 34213641Sqtt2@cornell.edu 34313641Sqtt2@cornell.edu /** 34413641Sqtt2@cornell.edu * If a thread is trying to exit and its corresponding trap event 34513641Sqtt2@cornell.edu * has been completed, schedule an event to terminate the thread. 34613641Sqtt2@cornell.edu */ 34713641Sqtt2@cornell.edu void scheduleThreadExitEvent(ThreadID tid); 34813641Sqtt2@cornell.edu 34913641Sqtt2@cornell.edu /** Terminate all threads that are ready to exit */ 35013641Sqtt2@cornell.edu void exitThreads(); 35113641Sqtt2@cornell.edu 3522864Sktlim@umich.edu public: 3535595Sgblack@eecs.umich.edu /** Executes a syscall. 3545595Sgblack@eecs.umich.edu * @todo: Determine if this needs to be virtual. 3552292SN/A */ 35611877Sbrandon.potter@amd.com void syscall(int64_t callnum, ThreadID tid, Fault *fault); 3572292SN/A 3582843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 3592843Sktlim@umich.edu * order to stop all memory accesses. */ 36011168Sandreas.hansson@arm.com DrainState drain() override; 3612843Sktlim@umich.edu 3622843Sktlim@umich.edu /** Resumes execution after a drain. */ 36311168Sandreas.hansson@arm.com void drainResume() override; 3642292SN/A 3659444SAndreas.Sandberg@ARM.com /** 3669444SAndreas.Sandberg@ARM.com * Commit has reached a safe point to drain a thread. 3679444SAndreas.Sandberg@ARM.com * 3689444SAndreas.Sandberg@ARM.com * Commit calls this method to inform the pipeline that it has 3699444SAndreas.Sandberg@ARM.com * reached a point where it is not executed microcode and is about 3709444SAndreas.Sandberg@ARM.com * to squash uncommitted instructions to fully drain the pipeline. 3719444SAndreas.Sandberg@ARM.com */ 3729444SAndreas.Sandberg@ARM.com void commitDrained(ThreadID tid); 3732843Sktlim@umich.edu 3742843Sktlim@umich.edu /** Switches out this CPU. */ 37511169Sandreas.hansson@arm.com void switchOut() override; 3762316SN/A 3772348SN/A /** Takes over from another CPU. */ 37811169Sandreas.hansson@arm.com void takeOverFrom(BaseCPU *oldCPU) override; 3791060SN/A 38011169Sandreas.hansson@arm.com void verifyMemoryMode() const override; 3819523SAndreas.Sandberg@ARM.com 3821060SN/A /** Get the current instruction sequence number, and increment it. */ 3832316SN/A InstSeqNum getAndIncrementInstSeq() 3842316SN/A { return globalSeqNum++; } 3851060SN/A 3865595Sgblack@eecs.umich.edu /** Traps to handle given fault. */ 38710417Sandreas.hansson@arm.com void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst); 3885595Sgblack@eecs.umich.edu 3895702Ssaidi@eecs.umich.edu /** HW return from error interrupt. */ 3906221Snate@binkert.org Fault hwrei(ThreadID tid); 3915702Ssaidi@eecs.umich.edu 3926221Snate@binkert.org bool simPalCheck(int palFunc, ThreadID tid); 3935702Ssaidi@eecs.umich.edu 39413601Sgiacomo.travaglini@arm.com /** Check if a change in renaming is needed for vector registers. 39513601Sgiacomo.travaglini@arm.com * The vecMode variable is updated and propagated to rename maps. 39613601Sgiacomo.travaglini@arm.com * 39713601Sgiacomo.travaglini@arm.com * @param tid ThreadID 39813601Sgiacomo.travaglini@arm.com * @param freelist list of free registers 39913601Sgiacomo.travaglini@arm.com */ 40013601Sgiacomo.travaglini@arm.com void switchRenameMode(ThreadID tid, UnifiedFreeList* freelist); 40113601Sgiacomo.travaglini@arm.com 4025595Sgblack@eecs.umich.edu /** Returns the Fault for any valid interrupt. */ 4035595Sgblack@eecs.umich.edu Fault getInterrupts(); 4045595Sgblack@eecs.umich.edu 4055595Sgblack@eecs.umich.edu /** Processes any an interrupt fault. */ 40610379Sandreas.hansson@arm.com void processInterrupts(const Fault &interrupt); 4075595Sgblack@eecs.umich.edu 4085595Sgblack@eecs.umich.edu /** Halts the CPU. */ 4095595Sgblack@eecs.umich.edu void halt() { panic("Halt not implemented!\n"); } 4105595Sgblack@eecs.umich.edu 4112348SN/A /** Register accessors. Index refers to the physical register index. */ 4125595Sgblack@eecs.umich.edu 4135595Sgblack@eecs.umich.edu /** Reads a miscellaneous register. */ 41413557Sgabeblack@google.com RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const; 4155595Sgblack@eecs.umich.edu 4165595Sgblack@eecs.umich.edu /** Reads a misc. register, including any side effects the read 4175595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4185595Sgblack@eecs.umich.edu */ 41913557Sgabeblack@google.com RegVal readMiscReg(int misc_reg, ThreadID tid); 4205595Sgblack@eecs.umich.edu 4215595Sgblack@eecs.umich.edu /** Sets a miscellaneous register. */ 42213582Sgabeblack@google.com void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid); 4235595Sgblack@eecs.umich.edu 4245595Sgblack@eecs.umich.edu /** Sets a misc. register, including any side effects the write 4255595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4265595Sgblack@eecs.umich.edu */ 42713582Sgabeblack@google.com void setMiscReg(int misc_reg, RegVal val, ThreadID tid); 4285595Sgblack@eecs.umich.edu 42913557Sgabeblack@google.com RegVal readIntReg(PhysRegIdPtr phys_reg); 4301060SN/A 43113611Sgabeblack@google.com RegVal readFloatReg(PhysRegIdPtr phys_reg); 4322455SN/A 43312109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const; 43412109SRekai.GonzalezAlberquilla@arm.com 43512109SRekai.GonzalezAlberquilla@arm.com /** 43612109SRekai.GonzalezAlberquilla@arm.com * Read physical vector register for modification. 43712109SRekai.GonzalezAlberquilla@arm.com */ 43812109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx); 43912109SRekai.GonzalezAlberquilla@arm.com 44013601Sgiacomo.travaglini@arm.com /** Returns current vector renaming mode */ 44113601Sgiacomo.travaglini@arm.com Enums::VecRegRenameMode vecRenameMode() const { return vecMode; } 44213601Sgiacomo.travaglini@arm.com 44313601Sgiacomo.travaglini@arm.com /** Sets the current vector renaming mode */ 44413601Sgiacomo.travaglini@arm.com void vecRenameMode(Enums::VecRegRenameMode vec_mode) 44513601Sgiacomo.travaglini@arm.com { vecMode = vec_mode; } 44613601Sgiacomo.travaglini@arm.com 44712109SRekai.GonzalezAlberquilla@arm.com /** 44812109SRekai.GonzalezAlberquilla@arm.com * Read physical vector register lane 44912109SRekai.GonzalezAlberquilla@arm.com */ 45012109SRekai.GonzalezAlberquilla@arm.com template<typename VecElem, int LaneIdx> 45112109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 45212109SRekai.GonzalezAlberquilla@arm.com readVecLane(PhysRegIdPtr phys_reg) const 45312109SRekai.GonzalezAlberquilla@arm.com { 45412109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads++; 45512109SRekai.GonzalezAlberquilla@arm.com return regFile.readVecLane<VecElem, LaneIdx>(phys_reg); 45612109SRekai.GonzalezAlberquilla@arm.com } 45712109SRekai.GonzalezAlberquilla@arm.com 45812109SRekai.GonzalezAlberquilla@arm.com /** 45912109SRekai.GonzalezAlberquilla@arm.com * Read physical vector register lane 46012109SRekai.GonzalezAlberquilla@arm.com */ 46112109SRekai.GonzalezAlberquilla@arm.com template<typename VecElem> 46212109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 46312109SRekai.GonzalezAlberquilla@arm.com readVecLane(PhysRegIdPtr phys_reg) const 46412109SRekai.GonzalezAlberquilla@arm.com { 46512109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads++; 46612109SRekai.GonzalezAlberquilla@arm.com return regFile.readVecLane<VecElem>(phys_reg); 46712109SRekai.GonzalezAlberquilla@arm.com } 46812109SRekai.GonzalezAlberquilla@arm.com 46912109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 47012109SRekai.GonzalezAlberquilla@arm.com template<typename LD> 47112109SRekai.GonzalezAlberquilla@arm.com void 47212109SRekai.GonzalezAlberquilla@arm.com setVecLane(PhysRegIdPtr phys_reg, const LD& val) 47312109SRekai.GonzalezAlberquilla@arm.com { 47412109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 47512109SRekai.GonzalezAlberquilla@arm.com return regFile.setVecLane(phys_reg, val); 47612109SRekai.GonzalezAlberquilla@arm.com } 47712109SRekai.GonzalezAlberquilla@arm.com 47812109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElem(PhysRegIdPtr reg_idx) const; 47912109SRekai.GonzalezAlberquilla@arm.com 48013610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const; 48113610Sgiacomo.gabrielli@arm.com 48213610Sgiacomo.gabrielli@arm.com VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx); 48313610Sgiacomo.gabrielli@arm.com 48413622Sgabeblack@google.com RegVal readCCReg(PhysRegIdPtr phys_reg); 4859920Syasuko.eckert@amd.com 48613557Sgabeblack@google.com void setIntReg(PhysRegIdPtr phys_reg, RegVal val); 4871060SN/A 48813611Sgabeblack@google.com void setFloatReg(PhysRegIdPtr phys_reg, RegVal val); 4892455SN/A 49012109SRekai.GonzalezAlberquilla@arm.com void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); 49112109SRekai.GonzalezAlberquilla@arm.com 49212109SRekai.GonzalezAlberquilla@arm.com void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val); 49312109SRekai.GonzalezAlberquilla@arm.com 49413610Sgiacomo.gabrielli@arm.com void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val); 49513610Sgiacomo.gabrielli@arm.com 49613622Sgabeblack@google.com void setCCReg(PhysRegIdPtr phys_reg, RegVal val); 4979920Syasuko.eckert@amd.com 49813557Sgabeblack@google.com RegVal readArchIntReg(int reg_idx, ThreadID tid); 4991060SN/A 50013611Sgabeblack@google.com RegVal readArchFloatReg(int reg_idx, ThreadID tid); 5012292SN/A 50212109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; 50312109SRekai.GonzalezAlberquilla@arm.com /** Read architectural vector register for modification. */ 50412109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid); 50512109SRekai.GonzalezAlberquilla@arm.com 50612109SRekai.GonzalezAlberquilla@arm.com /** Read architectural vector register lane. */ 50712109SRekai.GonzalezAlberquilla@arm.com template<typename VecElem> 50812109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 50912109SRekai.GonzalezAlberquilla@arm.com readArchVecLane(int reg_idx, int lId, ThreadID tid) const 51012109SRekai.GonzalezAlberquilla@arm.com { 51112109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 51212109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 51312109SRekai.GonzalezAlberquilla@arm.com return readVecLane<VecElem>(phys_reg); 51412109SRekai.GonzalezAlberquilla@arm.com } 51512109SRekai.GonzalezAlberquilla@arm.com 51612109SRekai.GonzalezAlberquilla@arm.com 51712109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 51812109SRekai.GonzalezAlberquilla@arm.com template<typename LD> 51912109SRekai.GonzalezAlberquilla@arm.com void 52012109SRekai.GonzalezAlberquilla@arm.com setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val) 52112109SRekai.GonzalezAlberquilla@arm.com { 52212109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 52312109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 52412109SRekai.GonzalezAlberquilla@arm.com setVecLane(phys_reg, val); 52512109SRekai.GonzalezAlberquilla@arm.com } 52612109SRekai.GonzalezAlberquilla@arm.com 52712109SRekai.GonzalezAlberquilla@arm.com const VecElem& readArchVecElem(const RegIndex& reg_idx, 52812109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& ldx, ThreadID tid) const; 52912109SRekai.GonzalezAlberquilla@arm.com 53013610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& readArchVecPredReg(int reg_idx, 53113610Sgiacomo.gabrielli@arm.com ThreadID tid) const; 53213610Sgiacomo.gabrielli@arm.com 53313610Sgiacomo.gabrielli@arm.com VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid); 53413610Sgiacomo.gabrielli@arm.com 53513622Sgabeblack@google.com RegVal readArchCCReg(int reg_idx, ThreadID tid); 5369920Syasuko.eckert@amd.com 5372348SN/A /** Architectural register accessors. Looks up in the commit 5382348SN/A * rename table to obtain the true physical index of the 5392348SN/A * architected register first, then accesses that physical 5402348SN/A * register. 5412348SN/A */ 54213557Sgabeblack@google.com void setArchIntReg(int reg_idx, RegVal val, ThreadID tid); 5432292SN/A 54413611Sgabeblack@google.com void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid); 5452292SN/A 54613610Sgiacomo.gabrielli@arm.com void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, 54713610Sgiacomo.gabrielli@arm.com ThreadID tid); 54813610Sgiacomo.gabrielli@arm.com 54912109SRekai.GonzalezAlberquilla@arm.com void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid); 55012109SRekai.GonzalezAlberquilla@arm.com 55112109SRekai.GonzalezAlberquilla@arm.com void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 55212109SRekai.GonzalezAlberquilla@arm.com const VecElem& val, ThreadID tid); 55312109SRekai.GonzalezAlberquilla@arm.com 55413622Sgabeblack@google.com void setArchCCReg(int reg_idx, RegVal val, ThreadID tid); 5559920Syasuko.eckert@amd.com 5567720Sgblack@eecs.umich.edu /** Sets the commit PC state of a specific thread. */ 5577720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &newPCState, ThreadID tid); 5587720Sgblack@eecs.umich.edu 5597720Sgblack@eecs.umich.edu /** Reads the commit PC state of a specific thread. */ 5607720Sgblack@eecs.umich.edu TheISA::PCState pcState(ThreadID tid); 5617720Sgblack@eecs.umich.edu 5622348SN/A /** Reads the commit PC of a specific thread. */ 5637720Sgblack@eecs.umich.edu Addr instAddr(ThreadID tid); 5642292SN/A 5654636Sgblack@eecs.umich.edu /** Reads the commit micro PC of a specific thread. */ 5667720Sgblack@eecs.umich.edu MicroPC microPC(ThreadID tid); 5674636Sgblack@eecs.umich.edu 5682348SN/A /** Reads the next PC of a specific thread. */ 5697720Sgblack@eecs.umich.edu Addr nextInstAddr(ThreadID tid); 5702756Sksewell@umich.edu 5715595Sgblack@eecs.umich.edu /** Initiates a squash of all in-flight instructions for a given 5725595Sgblack@eecs.umich.edu * thread. The source of the squash is an external update of 5735595Sgblack@eecs.umich.edu * state through the TC. 5745595Sgblack@eecs.umich.edu */ 5756221Snate@binkert.org void squashFromTC(ThreadID tid); 5765595Sgblack@eecs.umich.edu 5771060SN/A /** Function to add instruction onto the head of the list of the 5781060SN/A * instructions. Used when new instructions are fetched. 5791060SN/A */ 58013429Srekai.gonzalezalberquilla@arm.com ListIt addInst(const DynInstPtr &inst); 5811060SN/A 5821060SN/A /** Function to tell the CPU that an instruction has completed. */ 58313429Srekai.gonzalezalberquilla@arm.com void instDone(ThreadID tid, const DynInstPtr &inst); 5841060SN/A 5852325SN/A /** Remove an instruction from the front end of the list. There's 5862325SN/A * no restriction on location of the instruction. 5871060SN/A */ 58813429Srekai.gonzalezalberquilla@arm.com void removeFrontInst(const DynInstPtr &inst); 5891060SN/A 5902935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 5912935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 5926221Snate@binkert.org void removeInstsNotInROB(ThreadID tid); 5931060SN/A 5941062SN/A /** Remove all instructions younger than the given sequence number. */ 5956221Snate@binkert.org void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 5962292SN/A 5972348SN/A /** Removes the instruction pointed to by the iterator. */ 5986221Snate@binkert.org inline void squashInstIt(const ListIt &instIt, ThreadID tid); 5992292SN/A 6002348SN/A /** Cleans up all instructions on the remove list. */ 6012292SN/A void cleanUpRemovedInsts(); 6021062SN/A 6032348SN/A /** Debug function to print all instructions on the list. */ 6041060SN/A void dumpInsts(); 6051060SN/A 6061060SN/A public: 6075737Scws3k@cs.virginia.edu#ifndef NDEBUG 6085737Scws3k@cs.virginia.edu /** Count of total number of dynamic instructions in flight. */ 6095737Scws3k@cs.virginia.edu int instcount; 6105737Scws3k@cs.virginia.edu#endif 6115737Scws3k@cs.virginia.edu 6121060SN/A /** List of all the instructions in flight. */ 6132292SN/A std::list<DynInstPtr> instList; 6141060SN/A 6152292SN/A /** List of all the instructions that will be removed at the end of this 6162292SN/A * cycle. 6172292SN/A */ 6182292SN/A std::queue<ListIt> removeList; 6192292SN/A 6202325SN/A#ifdef DEBUG 6212348SN/A /** Debug structure to keep track of the sequence numbers still in 6222348SN/A * flight. 6232348SN/A */ 6242292SN/A std::set<InstSeqNum> snList; 6252325SN/A#endif 6262292SN/A 6272325SN/A /** Records if instructions need to be removed this cycle due to 6282325SN/A * being retired or squashed. 6292292SN/A */ 6302292SN/A bool removeInstsThisCycle; 6312292SN/A 6321060SN/A protected: 6331060SN/A /** The fetch stage. */ 6341060SN/A typename CPUPolicy::Fetch fetch; 6351060SN/A 6361060SN/A /** The decode stage. */ 6371060SN/A typename CPUPolicy::Decode decode; 6381060SN/A 6391060SN/A /** The dispatch stage. */ 6401060SN/A typename CPUPolicy::Rename rename; 6411060SN/A 6421060SN/A /** The issue/execute/writeback stages. */ 6431060SN/A typename CPUPolicy::IEW iew; 6441060SN/A 6451060SN/A /** The commit stage. */ 6461060SN/A typename CPUPolicy::Commit commit; 6471060SN/A 64812109SRekai.GonzalezAlberquilla@arm.com /** The rename mode of the vector registers */ 64912109SRekai.GonzalezAlberquilla@arm.com Enums::VecRegRenameMode vecMode; 65012109SRekai.GonzalezAlberquilla@arm.com 6511060SN/A /** The register file. */ 6529919Ssteve.reinhardt@amd.com PhysRegFile regFile; 6531060SN/A 6541060SN/A /** The free list. */ 6551060SN/A typename CPUPolicy::FreeList freeList; 6561060SN/A 6571060SN/A /** The rename map. */ 6582292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 6592292SN/A 6602292SN/A /** The commit rename map. */ 6612292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 6621060SN/A 6631060SN/A /** The re-order buffer. */ 6641060SN/A typename CPUPolicy::ROB rob; 6651060SN/A 6662292SN/A /** Active Threads List */ 6676221Snate@binkert.org std::list<ThreadID> activeThreads; 6682292SN/A 66913641Sqtt2@cornell.edu /** 67013641Sqtt2@cornell.edu * This is a list of threads that are trying to exit. Each thread id 67113641Sqtt2@cornell.edu * is mapped to a boolean value denoting whether the thread is ready 67213641Sqtt2@cornell.edu * to exit. 67313641Sqtt2@cornell.edu */ 67413641Sqtt2@cornell.edu std::unordered_map<ThreadID, bool> exitingThreads; 67513641Sqtt2@cornell.edu 6762292SN/A /** Integer Register Scoreboard */ 6772292SN/A Scoreboard scoreboard; 6782292SN/A 6799384SAndreas.Sandberg@arm.com std::vector<TheISA::ISA *> isa; 6806313Sgblack@eecs.umich.edu 6818707Sandreas.hansson@arm.com /** Instruction port. Note that it has to appear after the fetch stage. */ 6828707Sandreas.hansson@arm.com IcachePort icachePort; 6838707Sandreas.hansson@arm.com 6848707Sandreas.hansson@arm.com /** Data port. Note that it has to appear after the iew stages */ 6858707Sandreas.hansson@arm.com DcachePort dcachePort; 6868707Sandreas.hansson@arm.com 6871060SN/A public: 6882292SN/A /** Enum to give each stage a specific index, so when calling 6892292SN/A * activateStage() or deactivateStage(), they can specify which stage 6902292SN/A * is being activated/deactivated. 6912292SN/A */ 6922292SN/A enum StageIdx { 6932292SN/A FetchIdx, 6942292SN/A DecodeIdx, 6952292SN/A RenameIdx, 6962292SN/A IEWIdx, 6972292SN/A CommitIdx, 6982292SN/A NumStages }; 6992292SN/A 7001060SN/A /** Typedefs from the Impl to get the structs that each of the 7011060SN/A * time buffers should use. 7021060SN/A */ 7031061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 7041060SN/A 7051061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 7061060SN/A 7071061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 7081060SN/A 7091061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 7101060SN/A 7111061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 7121060SN/A 7131060SN/A /** The main time buffer to do backwards communication. */ 7141060SN/A TimeBuffer<TimeStruct> timeBuffer; 7151060SN/A 7161060SN/A /** The fetch stage's instruction queue. */ 7171060SN/A TimeBuffer<FetchStruct> fetchQueue; 7181060SN/A 7191060SN/A /** The decode stage's instruction queue. */ 7201060SN/A TimeBuffer<DecodeStruct> decodeQueue; 7211060SN/A 7221060SN/A /** The rename stage's instruction queue. */ 7231060SN/A TimeBuffer<RenameStruct> renameQueue; 7241060SN/A 7251060SN/A /** The IEW stage's instruction queue. */ 7261060SN/A TimeBuffer<IEWStruct> iewQueue; 7271060SN/A 7282348SN/A private: 7292348SN/A /** The activity recorder; used to tell if the CPU has any 7302348SN/A * activity remaining or if it can go to idle and deschedule 7312348SN/A * itself. 7322348SN/A */ 7332325SN/A ActivityRecorder activityRec; 7341060SN/A 7352348SN/A public: 7362348SN/A /** Records that there was time buffer activity this cycle. */ 7372325SN/A void activityThisCycle() { activityRec.activity(); } 7382292SN/A 7392348SN/A /** Changes a stage's status to active within the activity recorder. */ 7402325SN/A void activateStage(const StageIdx idx) 7412325SN/A { activityRec.activateStage(idx); } 7422292SN/A 7432348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 7442325SN/A void deactivateStage(const StageIdx idx) 7452325SN/A { activityRec.deactivateStage(idx); } 7462292SN/A 7472292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 7482292SN/A void wakeCPU(); 7492260SN/A 75011168Sandreas.hansson@arm.com virtual void wakeup(ThreadID tid) override; 7515807Snate@binkert.org 7522292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 7536221Snate@binkert.org ThreadID getFreeTid(); 7542292SN/A 7552292SN/A public: 7562680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 7576221Snate@binkert.org ThreadContext * 7586221Snate@binkert.org tcBase(ThreadID tid) 7591681SN/A { 7602680Sktlim@umich.edu return thread[tid]->getTC(); 7612190SN/A } 7622190SN/A 7632292SN/A /** The global sequence number counter. */ 7643093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 7651060SN/A 7662348SN/A /** Pointer to the checker, which can dynamically verify 7672348SN/A * instruction results at run time. This can be set to NULL if it 7682348SN/A * is not being used. 7692348SN/A */ 7708733Sgeoffrey.blake@arm.com Checker<Impl> *checker; 7712316SN/A 7722292SN/A /** Pointer to the system. */ 7731060SN/A System *system; 7741060SN/A 7752348SN/A /** Pointers to all of the threads in the CPU. */ 7762292SN/A std::vector<Thread *> thread; 7772260SN/A 7782292SN/A /** Threads Scheduled to Enter CPU */ 7792292SN/A std::list<int> cpuWaitList; 7802292SN/A 7812292SN/A /** The cycle that the CPU was last running, used for statistics. */ 7829180Sandreas.hansson@arm.com Cycles lastRunningCycle; 7832292SN/A 7842829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 7852829Sksewell@umich.edu Tick lastActivatedCycle; 7862829Sksewell@umich.edu 7872292SN/A /** Mapping for system thread id to cpu id */ 7886221Snate@binkert.org std::map<ThreadID, unsigned> threadMap; 7892292SN/A 7902292SN/A /** Available thread ids in the cpu*/ 7916221Snate@binkert.org std::vector<ThreadID> tids; 7922292SN/A 79313590Srekai.gonzalezalberquilla@arm.com /** CPU pushRequest function, forwards request to LSQ. */ 79413590Srekai.gonzalezalberquilla@arm.com Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data, 79513590Srekai.gonzalezalberquilla@arm.com unsigned int size, Addr addr, Request::Flags flags, 79613590Srekai.gonzalezalberquilla@arm.com uint64_t *res) 79713590Srekai.gonzalezalberquilla@arm.com { 79813590Srekai.gonzalezalberquilla@arm.com return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr, 79913590Srekai.gonzalezalberquilla@arm.com flags, res); 80013590Srekai.gonzalezalberquilla@arm.com } 80113590Srekai.gonzalezalberquilla@arm.com 8025595Sgblack@eecs.umich.edu /** CPU read function, forwards read to LSQ. */ 80313590Srekai.gonzalezalberquilla@arm.com Fault read(LSQRequest* req, int load_idx) 8045595Sgblack@eecs.umich.edu { 80513590Srekai.gonzalezalberquilla@arm.com return this->iew.ldstQueue.read(req, load_idx); 8065595Sgblack@eecs.umich.edu } 8075595Sgblack@eecs.umich.edu 8085595Sgblack@eecs.umich.edu /** CPU write function, forwards write to LSQ. */ 80913590Srekai.gonzalezalberquilla@arm.com Fault write(LSQRequest* req, uint8_t *data, int store_idx) 8105595Sgblack@eecs.umich.edu { 81113590Srekai.gonzalezalberquilla@arm.com return this->iew.ldstQueue.write(req, data, store_idx); 8125595Sgblack@eecs.umich.edu } 8135595Sgblack@eecs.umich.edu 8148707Sandreas.hansson@arm.com /** Used by the fetch unit to get a hold of the instruction port. */ 81511169Sandreas.hansson@arm.com MasterPort &getInstPort() override { return icachePort; } 8168707Sandreas.hansson@arm.com 8176974Stjones1@inf.ed.ac.uk /** Get the dcache port (used to find block size for translations). */ 81811169Sandreas.hansson@arm.com MasterPort &getDataPort() override { return dcachePort; } 8196974Stjones1@inf.ed.ac.uk 8202292SN/A /** Stat for total number of times the CPU is descheduled. */ 8215999Snate@binkert.org Stats::Scalar timesIdled; 8222292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 8235999Snate@binkert.org Stats::Scalar idleCycles; 8248627SAli.Saidi@ARM.com /** Stat for total number of cycles the CPU spends descheduled due to a 8258627SAli.Saidi@ARM.com * quiesce operation or waiting for an interrupt. */ 8268627SAli.Saidi@ARM.com Stats::Scalar quiesceCycles; 8272292SN/A /** Stat for the number of committed instructions per thread. */ 8285999Snate@binkert.org Stats::Vector committedInsts; 8298834Satgutier@umich.edu /** Stat for the number of committed ops (including micro ops) per thread. */ 8308834Satgutier@umich.edu Stats::Vector committedOps; 8312292SN/A /** Stat for the CPI per thread. */ 8322292SN/A Stats::Formula cpi; 8332292SN/A /** Stat for the total CPI. */ 8342292SN/A Stats::Formula totalCpi; 8352292SN/A /** Stat for the IPC per thread. */ 8362292SN/A Stats::Formula ipc; 8372292SN/A /** Stat for the total IPC. */ 8382292SN/A Stats::Formula totalIpc; 8397897Shestness@cs.utexas.edu 8407897Shestness@cs.utexas.edu //number of integer register file accesses 8417897Shestness@cs.utexas.edu Stats::Scalar intRegfileReads; 8427897Shestness@cs.utexas.edu Stats::Scalar intRegfileWrites; 8437897Shestness@cs.utexas.edu //number of float register file accesses 8447897Shestness@cs.utexas.edu Stats::Scalar fpRegfileReads; 8457897Shestness@cs.utexas.edu Stats::Scalar fpRegfileWrites; 84612109SRekai.GonzalezAlberquilla@arm.com //number of vector register file accesses 84712109SRekai.GonzalezAlberquilla@arm.com mutable Stats::Scalar vecRegfileReads; 84812109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar vecRegfileWrites; 84913610Sgiacomo.gabrielli@arm.com //number of predicate register file accesses 85013610Sgiacomo.gabrielli@arm.com mutable Stats::Scalar vecPredRegfileReads; 85113610Sgiacomo.gabrielli@arm.com Stats::Scalar vecPredRegfileWrites; 8529920Syasuko.eckert@amd.com //number of CC register file accesses 8539920Syasuko.eckert@amd.com Stats::Scalar ccRegfileReads; 8549920Syasuko.eckert@amd.com Stats::Scalar ccRegfileWrites; 8557897Shestness@cs.utexas.edu //number of misc 8567897Shestness@cs.utexas.edu Stats::Scalar miscRegfileReads; 8577897Shestness@cs.utexas.edu Stats::Scalar miscRegfileWrites; 8581060SN/A}; 8591060SN/A 8602325SN/A#endif // __CPU_O3_CPU_HH__ 861