cpu.cc revision 9954:72a72649a156 
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 *          Korey Sewell
44 *          Rick Strong
45 */
46
47#include "arch/kernel_stats.hh"
48#include "config/the_isa.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/checker/thread_context.hh"
51#include "cpu/o3/cpu.hh"
52#include "cpu/o3/isa_specific.hh"
53#include "cpu/o3/thread_context.hh"
54#include "cpu/activity.hh"
55#include "cpu/quiesce_event.hh"
56#include "cpu/simple_thread.hh"
57#include "cpu/thread_context.hh"
58#include "debug/Activity.hh"
59#include "debug/Drain.hh"
60#include "debug/O3CPU.hh"
61#include "debug/Quiesce.hh"
62#include "enums/MemoryMode.hh"
63#include "sim/core.hh"
64#include "sim/full_system.hh"
65#include "sim/process.hh"
66#include "sim/stat_control.hh"
67#include "sim/system.hh"
68
69#if THE_ISA == ALPHA_ISA
70#include "arch/alpha/osfpal.hh"
71#include "debug/Activity.hh"
72#endif
73
74struct BaseCPUParams;
75
76using namespace TheISA;
77using namespace std;
78
79BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
80    : BaseCPU(params)
81{
82}
83
84void
85BaseO3CPU::regStats()
86{
87    BaseCPU::regStats();
88}
89
90template<class Impl>
91bool
92FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
93{
94    DPRINTF(O3CPU, "Fetch unit received timing\n");
95    // We shouldn't ever get a block in ownership state
96    assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
97    fetch->processCacheCompletion(pkt);
98
99    return true;
100}
101
102template<class Impl>
103void
104FullO3CPU<Impl>::IcachePort::recvRetry()
105{
106    fetch->recvRetry();
107}
108
109template <class Impl>
110bool
111FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
112{
113    return lsq->recvTimingResp(pkt);
114}
115
116template <class Impl>
117void
118FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
119{
120    lsq->recvTimingSnoopReq(pkt);
121}
122
123template <class Impl>
124void
125FullO3CPU<Impl>::DcachePort::recvRetry()
126{
127    lsq->recvRetry();
128}
129
130template <class Impl>
131FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
132    : Event(CPU_Tick_Pri), cpu(c)
133{
134}
135
136template <class Impl>
137void
138FullO3CPU<Impl>::TickEvent::process()
139{
140    cpu->tick();
141}
142
143template <class Impl>
144const char *
145FullO3CPU<Impl>::TickEvent::description() const
146{
147    return "FullO3CPU tick";
148}
149
150template <class Impl>
151FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
152    : Event(CPU_Switch_Pri)
153{
154}
155
156template <class Impl>
157void
158FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
159                                           FullO3CPU<Impl> *thread_cpu)
160{
161    tid = thread_num;
162    cpu = thread_cpu;
163}
164
165template <class Impl>
166void
167FullO3CPU<Impl>::ActivateThreadEvent::process()
168{
169    cpu->activateThread(tid);
170}
171
172template <class Impl>
173const char *
174FullO3CPU<Impl>::ActivateThreadEvent::description() const
175{
176    return "FullO3CPU \"Activate Thread\"";
177}
178
179template <class Impl>
180FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
181    : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
182{
183}
184
185template <class Impl>
186void
187FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
188                                              FullO3CPU<Impl> *thread_cpu)
189{
190    tid = thread_num;
191    cpu = thread_cpu;
192    remove = false;
193}
194
195template <class Impl>
196void
197FullO3CPU<Impl>::DeallocateContextEvent::process()
198{
199    cpu->deactivateThread(tid);
200    if (remove)
201        cpu->removeThread(tid);
202}
203
204template <class Impl>
205const char *
206FullO3CPU<Impl>::DeallocateContextEvent::description() const
207{
208    return "FullO3CPU \"Deallocate Context\"";
209}
210
211template <class Impl>
212FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
213    : BaseO3CPU(params),
214      itb(params->itb),
215      dtb(params->dtb),
216      tickEvent(this),
217#ifndef NDEBUG
218      instcount(0),
219#endif
220      removeInstsThisCycle(false),
221      fetch(this, params),
222      decode(this, params),
223      rename(this, params),
224      iew(this, params),
225      commit(this, params),
226
227      regFile(params->numPhysIntRegs,
228              params->numPhysFloatRegs,
229              params->numPhysCCRegs),
230
231      freeList(name() + ".freelist", &regFile),
232
233      rob(this, params),
234
235      scoreboard(name() + ".scoreboard",
236                 regFile.totalNumPhysRegs(), TheISA::NumMiscRegs,
237                 TheISA::ZeroReg, TheISA::ZeroReg),
238
239      isa(numThreads, NULL),
240
241      icachePort(&fetch, this),
242      dcachePort(&iew.ldstQueue, this),
243
244      timeBuffer(params->backComSize, params->forwardComSize),
245      fetchQueue(params->backComSize, params->forwardComSize),
246      decodeQueue(params->backComSize, params->forwardComSize),
247      renameQueue(params->backComSize, params->forwardComSize),
248      iewQueue(params->backComSize, params->forwardComSize),
249      activityRec(name(), NumStages,
250                  params->backComSize + params->forwardComSize,
251                  params->activity),
252
253      globalSeqNum(1),
254      system(params->system),
255      drainManager(NULL),
256      lastRunningCycle(curCycle())
257{
258    if (!params->switched_out) {
259        _status = Running;
260    } else {
261        _status = SwitchedOut;
262    }
263
264    if (params->checker) {
265        BaseCPU *temp_checker = params->checker;
266        checker = dynamic_cast<Checker<Impl> *>(temp_checker);
267        checker->setIcachePort(&icachePort);
268        checker->setSystem(params->system);
269    } else {
270        checker = NULL;
271    }
272
273    if (!FullSystem) {
274        thread.resize(numThreads);
275        tids.resize(numThreads);
276    }
277
278    // The stages also need their CPU pointer setup.  However this
279    // must be done at the upper level CPU because they have pointers
280    // to the upper level CPU, and not this FullO3CPU.
281
282    // Set up Pointers to the activeThreads list for each stage
283    fetch.setActiveThreads(&activeThreads);
284    decode.setActiveThreads(&activeThreads);
285    rename.setActiveThreads(&activeThreads);
286    iew.setActiveThreads(&activeThreads);
287    commit.setActiveThreads(&activeThreads);
288
289    // Give each of the stages the time buffer they will use.
290    fetch.setTimeBuffer(&timeBuffer);
291    decode.setTimeBuffer(&timeBuffer);
292    rename.setTimeBuffer(&timeBuffer);
293    iew.setTimeBuffer(&timeBuffer);
294    commit.setTimeBuffer(&timeBuffer);
295
296    // Also setup each of the stages' queues.
297    fetch.setFetchQueue(&fetchQueue);
298    decode.setFetchQueue(&fetchQueue);
299    commit.setFetchQueue(&fetchQueue);
300    decode.setDecodeQueue(&decodeQueue);
301    rename.setDecodeQueue(&decodeQueue);
302    rename.setRenameQueue(&renameQueue);
303    iew.setRenameQueue(&renameQueue);
304    iew.setIEWQueue(&iewQueue);
305    commit.setIEWQueue(&iewQueue);
306    commit.setRenameQueue(&renameQueue);
307
308    commit.setIEWStage(&iew);
309    rename.setIEWStage(&iew);
310    rename.setCommitStage(&commit);
311
312    ThreadID active_threads;
313    if (FullSystem) {
314        active_threads = 1;
315    } else {
316        active_threads = params->workload.size();
317
318        if (active_threads > Impl::MaxThreads) {
319            panic("Workload Size too large. Increase the 'MaxThreads' "
320                  "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
321                  "or edit your workload size.");
322        }
323    }
324
325    //Make Sure That this a Valid Architeture
326    assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
327    assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
328    assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
329
330    rename.setScoreboard(&scoreboard);
331    iew.setScoreboard(&scoreboard);
332
333    // Setup the rename map for whichever stages need it.
334    for (ThreadID tid = 0; tid < numThreads; tid++) {
335        isa[tid] = params->isa[tid];
336
337        // Only Alpha has an FP zero register, so for other ISAs we
338        // use an invalid FP register index to avoid special treatment
339        // of any valid FP reg.
340        RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
341        RegIndex fpZeroReg =
342            (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
343
344        commitRenameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
345                                  &freeList);
346
347        renameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
348                            &freeList);
349
350        activateThreadEvent[tid].init(tid, this);
351        deallocateContextEvent[tid].init(tid, this);
352    }
353
354    // Initialize rename map to assign physical registers to the
355    // architectural registers for active threads only.
356    for (ThreadID tid = 0; tid < active_threads; tid++) {
357        for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
358            // Note that we can't use the rename() method because we don't
359            // want special treatment for the zero register at this point
360            PhysRegIndex phys_reg = freeList.getIntReg();
361            renameMap[tid].setIntEntry(ridx, phys_reg);
362            commitRenameMap[tid].setIntEntry(ridx, phys_reg);
363        }
364
365        for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
366            PhysRegIndex phys_reg = freeList.getFloatReg();
367            renameMap[tid].setFloatEntry(ridx, phys_reg);
368            commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
369        }
370
371        for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
372            PhysRegIndex phys_reg = freeList.getCCReg();
373            renameMap[tid].setCCEntry(ridx, phys_reg);
374            commitRenameMap[tid].setCCEntry(ridx, phys_reg);
375        }
376    }
377
378    rename.setRenameMap(renameMap);
379    commit.setRenameMap(commitRenameMap);
380    rename.setFreeList(&freeList);
381
382    // Setup the ROB for whichever stages need it.
383    commit.setROB(&rob);
384
385    lastActivatedCycle = 0;
386#if 0
387    // Give renameMap & rename stage access to the freeList;
388    for (ThreadID tid = 0; tid < numThreads; tid++)
389        globalSeqNum[tid] = 1;
390#endif
391
392    contextSwitch = false;
393    DPRINTF(O3CPU, "Creating O3CPU object.\n");
394
395    // Setup any thread state.
396    this->thread.resize(this->numThreads);
397
398    for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
399        if (FullSystem) {
400            // SMT is not supported in FS mode yet.
401            assert(this->numThreads == 1);
402            this->thread[tid] = new Thread(this, 0, NULL);
403        } else {
404            if (tid < params->workload.size()) {
405                DPRINTF(O3CPU, "Workload[%i] process is %#x",
406                        tid, this->thread[tid]);
407                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
408                        (typename Impl::O3CPU *)(this),
409                        tid, params->workload[tid]);
410
411                //usedTids[tid] = true;
412                //threadMap[tid] = tid;
413            } else {
414                //Allocate Empty thread so M5 can use later
415                //when scheduling threads to CPU
416                Process* dummy_proc = NULL;
417
418                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
419                        (typename Impl::O3CPU *)(this),
420                        tid, dummy_proc);
421                //usedTids[tid] = false;
422            }
423        }
424
425        ThreadContext *tc;
426
427        // Setup the TC that will serve as the interface to the threads/CPU.
428        O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
429
430        tc = o3_tc;
431
432        // If we're using a checker, then the TC should be the
433        // CheckerThreadContext.
434        if (params->checker) {
435            tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
436                o3_tc, this->checker);
437        }
438
439        o3_tc->cpu = (typename Impl::O3CPU *)(this);
440        assert(o3_tc->cpu);
441        o3_tc->thread = this->thread[tid];
442
443        if (FullSystem) {
444            // Setup quiesce event.
445            this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
446        }
447        // Give the thread the TC.
448        this->thread[tid]->tc = tc;
449
450        // Add the TC to the CPU's list of TC's.
451        this->threadContexts.push_back(tc);
452    }
453
454    // FullO3CPU always requires an interrupt controller.
455    if (!params->switched_out && !interrupts) {
456        fatal("FullO3CPU %s has no interrupt controller.\n"
457              "Ensure createInterruptController() is called.\n", name());
458    }
459
460    for (ThreadID tid = 0; tid < this->numThreads; tid++)
461        this->thread[tid]->setFuncExeInst(0);
462}
463
464template <class Impl>
465FullO3CPU<Impl>::~FullO3CPU()
466{
467}
468
469template <class Impl>
470void
471FullO3CPU<Impl>::regStats()
472{
473    BaseO3CPU::regStats();
474
475    // Register any of the O3CPU's stats here.
476    timesIdled
477        .name(name() + ".timesIdled")
478        .desc("Number of times that the entire CPU went into an idle state and"
479              " unscheduled itself")
480        .prereq(timesIdled);
481
482    idleCycles
483        .name(name() + ".idleCycles")
484        .desc("Total number of cycles that the CPU has spent unscheduled due "
485              "to idling")
486        .prereq(idleCycles);
487
488    quiesceCycles
489        .name(name() + ".quiesceCycles")
490        .desc("Total number of cycles that CPU has spent quiesced or waiting "
491              "for an interrupt")
492        .prereq(quiesceCycles);
493
494    // Number of Instructions simulated
495    // --------------------------------
496    // Should probably be in Base CPU but need templated
497    // MaxThreads so put in here instead
498    committedInsts
499        .init(numThreads)
500        .name(name() + ".committedInsts")
501        .desc("Number of Instructions Simulated");
502
503    committedOps
504        .init(numThreads)
505        .name(name() + ".committedOps")
506        .desc("Number of Ops (including micro ops) Simulated");
507
508    totalCommittedInsts
509        .name(name() + ".committedInsts_total")
510        .desc("Number of Instructions Simulated");
511
512    cpi
513        .name(name() + ".cpi")
514        .desc("CPI: Cycles Per Instruction")
515        .precision(6);
516    cpi = numCycles / committedInsts;
517
518    totalCpi
519        .name(name() + ".cpi_total")
520        .desc("CPI: Total CPI of All Threads")
521        .precision(6);
522    totalCpi = numCycles / totalCommittedInsts;
523
524    ipc
525        .name(name() + ".ipc")
526        .desc("IPC: Instructions Per Cycle")
527        .precision(6);
528    ipc =  committedInsts / numCycles;
529
530    totalIpc
531        .name(name() + ".ipc_total")
532        .desc("IPC: Total IPC of All Threads")
533        .precision(6);
534    totalIpc =  totalCommittedInsts / numCycles;
535
536    this->fetch.regStats();
537    this->decode.regStats();
538    this->rename.regStats();
539    this->iew.regStats();
540    this->commit.regStats();
541    this->rob.regStats();
542
543    intRegfileReads
544        .name(name() + ".int_regfile_reads")
545        .desc("number of integer regfile reads")
546        .prereq(intRegfileReads);
547
548    intRegfileWrites
549        .name(name() + ".int_regfile_writes")
550        .desc("number of integer regfile writes")
551        .prereq(intRegfileWrites);
552
553    fpRegfileReads
554        .name(name() + ".fp_regfile_reads")
555        .desc("number of floating regfile reads")
556        .prereq(fpRegfileReads);
557
558    fpRegfileWrites
559        .name(name() + ".fp_regfile_writes")
560        .desc("number of floating regfile writes")
561        .prereq(fpRegfileWrites);
562
563    ccRegfileReads
564        .name(name() + ".cc_regfile_reads")
565        .desc("number of cc regfile reads")
566        .prereq(ccRegfileReads);
567
568    ccRegfileWrites
569        .name(name() + ".cc_regfile_writes")
570        .desc("number of cc regfile writes")
571        .prereq(ccRegfileWrites);
572
573    miscRegfileReads
574        .name(name() + ".misc_regfile_reads")
575        .desc("number of misc regfile reads")
576        .prereq(miscRegfileReads);
577
578    miscRegfileWrites
579        .name(name() + ".misc_regfile_writes")
580        .desc("number of misc regfile writes")
581        .prereq(miscRegfileWrites);
582}
583
584template <class Impl>
585void
586FullO3CPU<Impl>::tick()
587{
588    DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
589    assert(!switchedOut());
590    assert(getDrainState() != Drainable::Drained);
591
592    ++numCycles;
593
594//    activity = false;
595
596    //Tick each of the stages
597    fetch.tick();
598
599    decode.tick();
600
601    rename.tick();
602
603    iew.tick();
604
605    commit.tick();
606
607    if (!FullSystem)
608        doContextSwitch();
609
610    // Now advance the time buffers
611    timeBuffer.advance();
612
613    fetchQueue.advance();
614    decodeQueue.advance();
615    renameQueue.advance();
616    iewQueue.advance();
617
618    activityRec.advance();
619
620    if (removeInstsThisCycle) {
621        cleanUpRemovedInsts();
622    }
623
624    if (!tickEvent.scheduled()) {
625        if (_status == SwitchedOut) {
626            DPRINTF(O3CPU, "Switched out!\n");
627            // increment stat
628            lastRunningCycle = curCycle();
629        } else if (!activityRec.active() || _status == Idle) {
630            DPRINTF(O3CPU, "Idle!\n");
631            lastRunningCycle = curCycle();
632            timesIdled++;
633        } else {
634            schedule(tickEvent, clockEdge(Cycles(1)));
635            DPRINTF(O3CPU, "Scheduling next tick!\n");
636        }
637    }
638
639    if (!FullSystem)
640        updateThreadPriority();
641
642    tryDrain();
643}
644
645template <class Impl>
646void
647FullO3CPU<Impl>::init()
648{
649    BaseCPU::init();
650
651    for (ThreadID tid = 0; tid < numThreads; ++tid) {
652        // Set noSquashFromTC so that the CPU doesn't squash when initially
653        // setting up registers.
654        thread[tid]->noSquashFromTC = true;
655        // Initialise the ThreadContext's memory proxies
656        thread[tid]->initMemProxies(thread[tid]->getTC());
657    }
658
659    if (FullSystem && !params()->switched_out) {
660        for (ThreadID tid = 0; tid < numThreads; tid++) {
661            ThreadContext *src_tc = threadContexts[tid];
662            TheISA::initCPU(src_tc, src_tc->contextId());
663        }
664    }
665
666    // Clear noSquashFromTC.
667    for (int tid = 0; tid < numThreads; ++tid)
668        thread[tid]->noSquashFromTC = false;
669
670    commit.setThreads(thread);
671}
672
673template <class Impl>
674void
675FullO3CPU<Impl>::startup()
676{
677    for (int tid = 0; tid < numThreads; ++tid)
678        isa[tid]->startup(threadContexts[tid]);
679
680    fetch.startupStage();
681    decode.startupStage();
682    iew.startupStage();
683    rename.startupStage();
684    commit.startupStage();
685}
686
687template <class Impl>
688void
689FullO3CPU<Impl>::activateThread(ThreadID tid)
690{
691    list<ThreadID>::iterator isActive =
692        std::find(activeThreads.begin(), activeThreads.end(), tid);
693
694    DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
695    assert(!switchedOut());
696
697    if (isActive == activeThreads.end()) {
698        DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
699                tid);
700
701        activeThreads.push_back(tid);
702    }
703}
704
705template <class Impl>
706void
707FullO3CPU<Impl>::deactivateThread(ThreadID tid)
708{
709    //Remove From Active List, if Active
710    list<ThreadID>::iterator thread_it =
711        std::find(activeThreads.begin(), activeThreads.end(), tid);
712
713    DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
714    assert(!switchedOut());
715
716    if (thread_it != activeThreads.end()) {
717        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
718                tid);
719        activeThreads.erase(thread_it);
720    }
721}
722
723template <class Impl>
724Counter
725FullO3CPU<Impl>::totalInsts() const
726{
727    Counter total(0);
728
729    ThreadID size = thread.size();
730    for (ThreadID i = 0; i < size; i++)
731        total += thread[i]->numInst;
732
733    return total;
734}
735
736template <class Impl>
737Counter
738FullO3CPU<Impl>::totalOps() const
739{
740    Counter total(0);
741
742    ThreadID size = thread.size();
743    for (ThreadID i = 0; i < size; i++)
744        total += thread[i]->numOp;
745
746    return total;
747}
748
749template <class Impl>
750void
751FullO3CPU<Impl>::activateContext(ThreadID tid, Cycles delay)
752{
753    assert(!switchedOut());
754
755    // Needs to set each stage to running as well.
756    if (delay){
757        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
758                "on cycle %d\n", tid, clockEdge(delay));
759        scheduleActivateThreadEvent(tid, delay);
760    } else {
761        activateThread(tid);
762    }
763
764    // We don't want to wake the CPU if it is drained. In that case,
765    // we just want to flag the thread as active and schedule the tick
766    // event from drainResume() instead.
767    if (getDrainState() == Drainable::Drained)
768        return;
769
770    // If we are time 0 or if the last activation time is in the past,
771    // schedule the next tick and wake up the fetch unit
772    if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
773        scheduleTickEvent(delay);
774
775        // Be sure to signal that there's some activity so the CPU doesn't
776        // deschedule itself.
777        activityRec.activity();
778        fetch.wakeFromQuiesce();
779
780        Cycles cycles(curCycle() - lastRunningCycle);
781        // @todo: This is an oddity that is only here to match the stats
782        if (cycles != 0)
783            --cycles;
784        quiesceCycles += cycles;
785
786        lastActivatedCycle = curTick();
787
788        _status = Running;
789    }
790}
791
792template <class Impl>
793bool
794FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove,
795                                           Cycles delay)
796{
797    // Schedule removal of thread data from CPU
798    if (delay){
799        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
800                "on tick %d\n", tid, clockEdge(delay));
801        scheduleDeallocateContextEvent(tid, remove, delay);
802        return false;
803    } else {
804        deactivateThread(tid);
805        if (remove)
806            removeThread(tid);
807        return true;
808    }
809}
810
811template <class Impl>
812void
813FullO3CPU<Impl>::suspendContext(ThreadID tid)
814{
815    DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
816    assert(!switchedOut());
817    bool deallocated = scheduleDeallocateContext(tid, false, Cycles(1));
818    // If this was the last thread then unschedule the tick event.
819    if ((activeThreads.size() == 1 && !deallocated) ||
820        activeThreads.size() == 0)
821        unscheduleTickEvent();
822
823    DPRINTF(Quiesce, "Suspending Context\n");
824    lastRunningCycle = curCycle();
825    _status = Idle;
826}
827
828template <class Impl>
829void
830FullO3CPU<Impl>::haltContext(ThreadID tid)
831{
832    //For now, this is the same as deallocate
833    DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
834    assert(!switchedOut());
835    scheduleDeallocateContext(tid, true, Cycles(1));
836}
837
838template <class Impl>
839void
840FullO3CPU<Impl>::insertThread(ThreadID tid)
841{
842    DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
843    // Will change now that the PC and thread state is internal to the CPU
844    // and not in the ThreadContext.
845    ThreadContext *src_tc;
846    if (FullSystem)
847        src_tc = system->threadContexts[tid];
848    else
849        src_tc = tcBase(tid);
850
851    //Bind Int Regs to Rename Map
852    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
853        PhysRegIndex phys_reg = freeList.getIntReg();
854
855        renameMap[tid].setEntry(ireg,phys_reg);
856        scoreboard.setReg(phys_reg);
857    }
858
859    //Bind Float Regs to Rename Map
860    int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
861    for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
862        PhysRegIndex phys_reg = freeList.getFloatReg();
863
864        renameMap[tid].setEntry(freg,phys_reg);
865        scoreboard.setReg(phys_reg);
866    }
867
868    //Bind condition-code Regs to Rename Map
869    max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
870    for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
871         creg < max_reg; creg++) {
872        PhysRegIndex phys_reg = freeList.getCCReg();
873
874        renameMap[tid].setEntry(creg,phys_reg);
875        scoreboard.setReg(phys_reg);
876    }
877
878    //Copy Thread Data Into RegFile
879    //this->copyFromTC(tid);
880
881    //Set PC/NPC/NNPC
882    pcState(src_tc->pcState(), tid);
883
884    src_tc->setStatus(ThreadContext::Active);
885
886    activateContext(tid, Cycles(1));
887
888    //Reset ROB/IQ/LSQ Entries
889    commit.rob->resetEntries();
890    iew.resetEntries();
891}
892
893template <class Impl>
894void
895FullO3CPU<Impl>::removeThread(ThreadID tid)
896{
897    DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
898
899    // Copy Thread Data From RegFile
900    // If thread is suspended, it might be re-allocated
901    // this->copyToTC(tid);
902
903
904    // @todo: 2-27-2008: Fix how we free up rename mappings
905    // here to alleviate the case for double-freeing registers
906    // in SMT workloads.
907
908    // Unbind Int Regs from Rename Map
909    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
910        PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
911
912        scoreboard.unsetReg(phys_reg);
913        freeList.addReg(phys_reg);
914    }
915
916    // Unbind Float Regs from Rename Map
917    int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
918    for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
919        PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
920
921        scoreboard.unsetReg(phys_reg);
922        freeList.addReg(phys_reg);
923    }
924
925    // Unbind condition-code Regs from Rename Map
926    max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
927    for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
928         creg < max_reg; creg++) {
929        PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
930
931        scoreboard.unsetReg(phys_reg);
932        freeList.addReg(phys_reg);
933    }
934
935    // Squash Throughout Pipeline
936    DynInstPtr inst = commit.rob->readHeadInst(tid);
937    InstSeqNum squash_seq_num = inst->seqNum;
938    fetch.squash(0, squash_seq_num, inst, tid);
939    decode.squash(tid);
940    rename.squash(squash_seq_num, tid);
941    iew.squash(tid);
942    iew.ldstQueue.squash(squash_seq_num, tid);
943    commit.rob->squash(squash_seq_num, tid);
944
945
946    assert(iew.instQueue.getCount(tid) == 0);
947    assert(iew.ldstQueue.getCount(tid) == 0);
948
949    // Reset ROB/IQ/LSQ Entries
950
951    // Commented out for now.  This should be possible to do by
952    // telling all the pipeline stages to drain first, and then
953    // checking until the drain completes.  Once the pipeline is
954    // drained, call resetEntries(). - 10-09-06 ktlim
955/*
956    if (activeThreads.size() >= 1) {
957        commit.rob->resetEntries();
958        iew.resetEntries();
959    }
960*/
961}
962
963
964template <class Impl>
965void
966FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
967{
968    DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
969            "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
970            tid);
971
972    bool ready = true;
973
974    // Should these all be '<' not '>='?  This seems backwards...
975    if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
976        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
977                "Phys. Int. Regs.\n",
978                tid);
979        ready = false;
980    } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
981        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
982                "Phys. Float. Regs.\n",
983                tid);
984        ready = false;
985    } else if (freeList.numFreeCCRegs() >= TheISA::NumCCRegs) {
986        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
987                "Phys. CC. Regs.\n",
988                tid);
989        ready = false;
990    } else if (commit.rob->numFreeEntries() >=
991               commit.rob->entryAmount(activeThreads.size() + 1)) {
992        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
993                "ROB entries.\n",
994                tid);
995        ready = false;
996    } else if (iew.instQueue.numFreeEntries() >=
997               iew.instQueue.entryAmount(activeThreads.size() + 1)) {
998        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
999                "IQ entries.\n",
1000                tid);
1001        ready = false;
1002    } else if (iew.ldstQueue.numFreeEntries() >=
1003               iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
1004        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
1005                "LSQ entries.\n",
1006                tid);
1007        ready = false;
1008    }
1009
1010    if (ready) {
1011        insertThread(tid);
1012
1013        contextSwitch = false;
1014
1015        cpuWaitList.remove(tid);
1016    } else {
1017        suspendContext(tid);
1018
1019        //blocks fetch
1020        contextSwitch = true;
1021
1022        //@todo: dont always add to waitlist
1023        //do waitlist
1024        cpuWaitList.push_back(tid);
1025    }
1026}
1027
1028template <class Impl>
1029Fault
1030FullO3CPU<Impl>::hwrei(ThreadID tid)
1031{
1032#if THE_ISA == ALPHA_ISA
1033    // Need to clear the lock flag upon returning from an interrupt.
1034    this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
1035
1036    this->thread[tid]->kernelStats->hwrei();
1037
1038    // FIXME: XXX check for interrupts? XXX
1039#endif
1040    return NoFault;
1041}
1042
1043template <class Impl>
1044bool
1045FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
1046{
1047#if THE_ISA == ALPHA_ISA
1048    if (this->thread[tid]->kernelStats)
1049        this->thread[tid]->kernelStats->callpal(palFunc,
1050                                                this->threadContexts[tid]);
1051
1052    switch (palFunc) {
1053      case PAL::halt:
1054        halt();
1055        if (--System::numSystemsRunning == 0)
1056            exitSimLoop("all cpus halted");
1057        break;
1058
1059      case PAL::bpt:
1060      case PAL::bugchk:
1061        if (this->system->breakpoint())
1062            return false;
1063        break;
1064    }
1065#endif
1066    return true;
1067}
1068
1069template <class Impl>
1070Fault
1071FullO3CPU<Impl>::getInterrupts()
1072{
1073    // Check if there are any outstanding interrupts
1074    return this->interrupts->getInterrupt(this->threadContexts[0]);
1075}
1076
1077template <class Impl>
1078void
1079FullO3CPU<Impl>::processInterrupts(Fault interrupt)
1080{
1081    // Check for interrupts here.  For now can copy the code that
1082    // exists within isa_fullsys_traits.hh.  Also assume that thread 0
1083    // is the one that handles the interrupts.
1084    // @todo: Possibly consolidate the interrupt checking code.
1085    // @todo: Allow other threads to handle interrupts.
1086
1087    assert(interrupt != NoFault);
1088    this->interrupts->updateIntrInfo(this->threadContexts[0]);
1089
1090    DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
1091    this->trap(interrupt, 0, NULL);
1092}
1093
1094template <class Impl>
1095void
1096FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
1097{
1098    // Pass the thread's TC into the invoke method.
1099    fault->invoke(this->threadContexts[tid], inst);
1100}
1101
1102template <class Impl>
1103void
1104FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
1105{
1106    DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1107
1108    DPRINTF(Activity,"Activity: syscall() called.\n");
1109
1110    // Temporarily increase this by one to account for the syscall
1111    // instruction.
1112    ++(this->thread[tid]->funcExeInst);
1113
1114    // Execute the actual syscall.
1115    this->thread[tid]->syscall(callnum);
1116
1117    // Decrease funcExeInst by one as the normal commit will handle
1118    // incrementing it.
1119    --(this->thread[tid]->funcExeInst);
1120}
1121
1122template <class Impl>
1123void
1124FullO3CPU<Impl>::serializeThread(std::ostream &os, ThreadID tid)
1125{
1126    thread[tid]->serialize(os);
1127}
1128
1129template <class Impl>
1130void
1131FullO3CPU<Impl>::unserializeThread(Checkpoint *cp, const std::string &section,
1132                                   ThreadID tid)
1133{
1134    thread[tid]->unserialize(cp, section);
1135}
1136
1137template <class Impl>
1138unsigned int
1139FullO3CPU<Impl>::drain(DrainManager *drain_manager)
1140{
1141    // If the CPU isn't doing anything, then return immediately.
1142    if (switchedOut()) {
1143        setDrainState(Drainable::Drained);
1144        return 0;
1145    }
1146
1147    DPRINTF(Drain, "Draining...\n");
1148    setDrainState(Drainable::Draining);
1149
1150    // We only need to signal a drain to the commit stage as this
1151    // initiates squashing controls the draining. Once the commit
1152    // stage commits an instruction where it is safe to stop, it'll
1153    // squash the rest of the instructions in the pipeline and force
1154    // the fetch stage to stall. The pipeline will be drained once all
1155    // in-flight instructions have retired.
1156    commit.drain();
1157
1158    // Wake the CPU and record activity so everything can drain out if
1159    // the CPU was not able to immediately drain.
1160    if (!isDrained())  {
1161        drainManager = drain_manager;
1162
1163        wakeCPU();
1164        activityRec.activity();
1165
1166        DPRINTF(Drain, "CPU not drained\n");
1167
1168        return 1;
1169    } else {
1170        setDrainState(Drainable::Drained);
1171        DPRINTF(Drain, "CPU is already drained\n");
1172        if (tickEvent.scheduled())
1173            deschedule(tickEvent);
1174
1175        // Flush out any old data from the time buffers.  In
1176        // particular, there might be some data in flight from the
1177        // fetch stage that isn't visible in any of the CPU buffers we
1178        // test in isDrained().
1179        for (int i = 0; i < timeBuffer.getSize(); ++i) {
1180            timeBuffer.advance();
1181            fetchQueue.advance();
1182            decodeQueue.advance();
1183            renameQueue.advance();
1184            iewQueue.advance();
1185        }
1186
1187        drainSanityCheck();
1188        return 0;
1189    }
1190}
1191
1192template <class Impl>
1193bool
1194FullO3CPU<Impl>::tryDrain()
1195{
1196    if (!drainManager || !isDrained())
1197        return false;
1198
1199    if (tickEvent.scheduled())
1200        deschedule(tickEvent);
1201
1202    DPRINTF(Drain, "CPU done draining, processing drain event\n");
1203    drainManager->signalDrainDone();
1204    drainManager = NULL;
1205
1206    return true;
1207}
1208
1209template <class Impl>
1210void
1211FullO3CPU<Impl>::drainSanityCheck() const
1212{
1213    assert(isDrained());
1214    fetch.drainSanityCheck();
1215    decode.drainSanityCheck();
1216    rename.drainSanityCheck();
1217    iew.drainSanityCheck();
1218    commit.drainSanityCheck();
1219}
1220
1221template <class Impl>
1222bool
1223FullO3CPU<Impl>::isDrained() const
1224{
1225    bool drained(true);
1226
1227    for (ThreadID i = 0; i < thread.size(); ++i) {
1228        if (activateThreadEvent[i].scheduled()) {
1229            DPRINTF(Drain, "CPU not drained, tread %i has a "
1230                    "pending activate event\n", i);
1231            drained = false;
1232        }
1233        if (deallocateContextEvent[i].scheduled()) {
1234            DPRINTF(Drain, "CPU not drained, tread %i has a "
1235                    "pending deallocate context event\n", i);
1236            drained = false;
1237        }
1238    }
1239
1240    if (!instList.empty() || !removeList.empty()) {
1241        DPRINTF(Drain, "Main CPU structures not drained.\n");
1242        drained = false;
1243    }
1244
1245    if (!fetch.isDrained()) {
1246        DPRINTF(Drain, "Fetch not drained.\n");
1247        drained = false;
1248    }
1249
1250    if (!decode.isDrained()) {
1251        DPRINTF(Drain, "Decode not drained.\n");
1252        drained = false;
1253    }
1254
1255    if (!rename.isDrained()) {
1256        DPRINTF(Drain, "Rename not drained.\n");
1257        drained = false;
1258    }
1259
1260    if (!iew.isDrained()) {
1261        DPRINTF(Drain, "IEW not drained.\n");
1262        drained = false;
1263    }
1264
1265    if (!commit.isDrained()) {
1266        DPRINTF(Drain, "Commit not drained.\n");
1267        drained = false;
1268    }
1269
1270    return drained;
1271}
1272
1273template <class Impl>
1274void
1275FullO3CPU<Impl>::commitDrained(ThreadID tid)
1276{
1277    fetch.drainStall(tid);
1278}
1279
1280template <class Impl>
1281void
1282FullO3CPU<Impl>::drainResume()
1283{
1284    setDrainState(Drainable::Running);
1285    if (switchedOut())
1286        return;
1287
1288    DPRINTF(Drain, "Resuming...\n");
1289    verifyMemoryMode();
1290
1291    fetch.drainResume();
1292    commit.drainResume();
1293
1294    _status = Idle;
1295    for (ThreadID i = 0; i < thread.size(); i++) {
1296        if (thread[i]->status() == ThreadContext::Active) {
1297            DPRINTF(Drain, "Activating thread: %i\n", i);
1298            activateThread(i);
1299            _status = Running;
1300        }
1301    }
1302
1303    assert(!tickEvent.scheduled());
1304    if (_status == Running)
1305        schedule(tickEvent, nextCycle());
1306}
1307
1308template <class Impl>
1309void
1310FullO3CPU<Impl>::switchOut()
1311{
1312    DPRINTF(O3CPU, "Switching out\n");
1313    BaseCPU::switchOut();
1314
1315    activityRec.reset();
1316
1317    _status = SwitchedOut;
1318
1319    if (checker)
1320        checker->switchOut();
1321}
1322
1323template <class Impl>
1324void
1325FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1326{
1327    BaseCPU::takeOverFrom(oldCPU);
1328
1329    fetch.takeOverFrom();
1330    decode.takeOverFrom();
1331    rename.takeOverFrom();
1332    iew.takeOverFrom();
1333    commit.takeOverFrom();
1334
1335    assert(!tickEvent.scheduled());
1336
1337    FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1338    if (oldO3CPU)
1339        globalSeqNum = oldO3CPU->globalSeqNum;
1340
1341    lastRunningCycle = curCycle();
1342    _status = Idle;
1343}
1344
1345template <class Impl>
1346void
1347FullO3CPU<Impl>::verifyMemoryMode() const
1348{
1349    if (!system->isTimingMode()) {
1350        fatal("The O3 CPU requires the memory system to be in "
1351              "'timing' mode.\n");
1352    }
1353}
1354
1355template <class Impl>
1356TheISA::MiscReg
1357FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1358{
1359    return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1360}
1361
1362template <class Impl>
1363TheISA::MiscReg
1364FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1365{
1366    miscRegfileReads++;
1367    return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1368}
1369
1370template <class Impl>
1371void
1372FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1373        const TheISA::MiscReg &val, ThreadID tid)
1374{
1375    this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1376}
1377
1378template <class Impl>
1379void
1380FullO3CPU<Impl>::setMiscReg(int misc_reg,
1381        const TheISA::MiscReg &val, ThreadID tid)
1382{
1383    miscRegfileWrites++;
1384    this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1385}
1386
1387template <class Impl>
1388uint64_t
1389FullO3CPU<Impl>::readIntReg(int reg_idx)
1390{
1391    intRegfileReads++;
1392    return regFile.readIntReg(reg_idx);
1393}
1394
1395template <class Impl>
1396FloatReg
1397FullO3CPU<Impl>::readFloatReg(int reg_idx)
1398{
1399    fpRegfileReads++;
1400    return regFile.readFloatReg(reg_idx);
1401}
1402
1403template <class Impl>
1404FloatRegBits
1405FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1406{
1407    fpRegfileReads++;
1408    return regFile.readFloatRegBits(reg_idx);
1409}
1410
1411template <class Impl>
1412CCReg
1413FullO3CPU<Impl>::readCCReg(int reg_idx)
1414{
1415    ccRegfileReads++;
1416    return regFile.readCCReg(reg_idx);
1417}
1418
1419template <class Impl>
1420void
1421FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1422{
1423    intRegfileWrites++;
1424    regFile.setIntReg(reg_idx, val);
1425}
1426
1427template <class Impl>
1428void
1429FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1430{
1431    fpRegfileWrites++;
1432    regFile.setFloatReg(reg_idx, val);
1433}
1434
1435template <class Impl>
1436void
1437FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1438{
1439    fpRegfileWrites++;
1440    regFile.setFloatRegBits(reg_idx, val);
1441}
1442
1443template <class Impl>
1444void
1445FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val)
1446{
1447    ccRegfileWrites++;
1448    regFile.setCCReg(reg_idx, val);
1449}
1450
1451template <class Impl>
1452uint64_t
1453FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1454{
1455    intRegfileReads++;
1456    PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1457
1458    return regFile.readIntReg(phys_reg);
1459}
1460
1461template <class Impl>
1462float
1463FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1464{
1465    fpRegfileReads++;
1466    PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1467
1468    return regFile.readFloatReg(phys_reg);
1469}
1470
1471template <class Impl>
1472uint64_t
1473FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1474{
1475    fpRegfileReads++;
1476    PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1477
1478    return regFile.readFloatRegBits(phys_reg);
1479}
1480
1481template <class Impl>
1482CCReg
1483FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1484{
1485    ccRegfileReads++;
1486    PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1487
1488    return regFile.readCCReg(phys_reg);
1489}
1490
1491template <class Impl>
1492void
1493FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1494{
1495    intRegfileWrites++;
1496    PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1497
1498    regFile.setIntReg(phys_reg, val);
1499}
1500
1501template <class Impl>
1502void
1503FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1504{
1505    fpRegfileWrites++;
1506    PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1507
1508    regFile.setFloatReg(phys_reg, val);
1509}
1510
1511template <class Impl>
1512void
1513FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1514{
1515    fpRegfileWrites++;
1516    PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1517
1518    regFile.setFloatRegBits(phys_reg, val);
1519}
1520
1521template <class Impl>
1522void
1523FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1524{
1525    ccRegfileWrites++;
1526    PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1527
1528    regFile.setCCReg(phys_reg, val);
1529}
1530
1531template <class Impl>
1532TheISA::PCState
1533FullO3CPU<Impl>::pcState(ThreadID tid)
1534{
1535    return commit.pcState(tid);
1536}
1537
1538template <class Impl>
1539void
1540FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1541{
1542    commit.pcState(val, tid);
1543}
1544
1545template <class Impl>
1546Addr
1547FullO3CPU<Impl>::instAddr(ThreadID tid)
1548{
1549    return commit.instAddr(tid);
1550}
1551
1552template <class Impl>
1553Addr
1554FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1555{
1556    return commit.nextInstAddr(tid);
1557}
1558
1559template <class Impl>
1560MicroPC
1561FullO3CPU<Impl>::microPC(ThreadID tid)
1562{
1563    return commit.microPC(tid);
1564}
1565
1566template <class Impl>
1567void
1568FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1569{
1570    this->thread[tid]->noSquashFromTC = true;
1571    this->commit.generateTCEvent(tid);
1572}
1573
1574template <class Impl>
1575typename FullO3CPU<Impl>::ListIt
1576FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1577{
1578    instList.push_back(inst);
1579
1580    return --(instList.end());
1581}
1582
1583template <class Impl>
1584void
1585FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1586{
1587    // Keep an instruction count.
1588    if (!inst->isMicroop() || inst->isLastMicroop()) {
1589        thread[tid]->numInst++;
1590        thread[tid]->numInsts++;
1591        committedInsts[tid]++;
1592        totalCommittedInsts++;
1593    }
1594    thread[tid]->numOp++;
1595    thread[tid]->numOps++;
1596    committedOps[tid]++;
1597
1598    system->totalNumInsts++;
1599    // Check for instruction-count-based events.
1600    comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1601    system->instEventQueue.serviceEvents(system->totalNumInsts);
1602}
1603
1604template <class Impl>
1605void
1606FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1607{
1608    DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1609            "[sn:%lli]\n",
1610            inst->threadNumber, inst->pcState(), inst->seqNum);
1611
1612    removeInstsThisCycle = true;
1613
1614    // Remove the front instruction.
1615    removeList.push(inst->getInstListIt());
1616}
1617
1618template <class Impl>
1619void
1620FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1621{
1622    DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1623            " list.\n", tid);
1624
1625    ListIt end_it;
1626
1627    bool rob_empty = false;
1628
1629    if (instList.empty()) {
1630        return;
1631    } else if (rob.isEmpty(/*tid*/)) {
1632        DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1633        end_it = instList.begin();
1634        rob_empty = true;
1635    } else {
1636        end_it = (rob.readTailInst(tid))->getInstListIt();
1637        DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1638    }
1639
1640    removeInstsThisCycle = true;
1641
1642    ListIt inst_it = instList.end();
1643
1644    inst_it--;
1645
1646    // Walk through the instruction list, removing any instructions
1647    // that were inserted after the given instruction iterator, end_it.
1648    while (inst_it != end_it) {
1649        assert(!instList.empty());
1650
1651        squashInstIt(inst_it, tid);
1652
1653        inst_it--;
1654    }
1655
1656    // If the ROB was empty, then we actually need to remove the first
1657    // instruction as well.
1658    if (rob_empty) {
1659        squashInstIt(inst_it, tid);
1660    }
1661}
1662
1663template <class Impl>
1664void
1665FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1666{
1667    assert(!instList.empty());
1668
1669    removeInstsThisCycle = true;
1670
1671    ListIt inst_iter = instList.end();
1672
1673    inst_iter--;
1674
1675    DPRINTF(O3CPU, "Deleting instructions from instruction "
1676            "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1677            tid, seq_num, (*inst_iter)->seqNum);
1678
1679    while ((*inst_iter)->seqNum > seq_num) {
1680
1681        bool break_loop = (inst_iter == instList.begin());
1682
1683        squashInstIt(inst_iter, tid);
1684
1685        inst_iter--;
1686
1687        if (break_loop)
1688            break;
1689    }
1690}
1691
1692template <class Impl>
1693inline void
1694FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1695{
1696    if ((*instIt)->threadNumber == tid) {
1697        DPRINTF(O3CPU, "Squashing instruction, "
1698                "[tid:%i] [sn:%lli] PC %s\n",
1699                (*instIt)->threadNumber,
1700                (*instIt)->seqNum,
1701                (*instIt)->pcState());
1702
1703        // Mark it as squashed.
1704        (*instIt)->setSquashed();
1705
1706        // @todo: Formulate a consistent method for deleting
1707        // instructions from the instruction list
1708        // Remove the instruction from the list.
1709        removeList.push(instIt);
1710    }
1711}
1712
1713template <class Impl>
1714void
1715FullO3CPU<Impl>::cleanUpRemovedInsts()
1716{
1717    while (!removeList.empty()) {
1718        DPRINTF(O3CPU, "Removing instruction, "
1719                "[tid:%i] [sn:%lli] PC %s\n",
1720                (*removeList.front())->threadNumber,
1721                (*removeList.front())->seqNum,
1722                (*removeList.front())->pcState());
1723
1724        instList.erase(removeList.front());
1725
1726        removeList.pop();
1727    }
1728
1729    removeInstsThisCycle = false;
1730}
1731/*
1732template <class Impl>
1733void
1734FullO3CPU<Impl>::removeAllInsts()
1735{
1736    instList.clear();
1737}
1738*/
1739template <class Impl>
1740void
1741FullO3CPU<Impl>::dumpInsts()
1742{
1743    int num = 0;
1744
1745    ListIt inst_list_it = instList.begin();
1746
1747    cprintf("Dumping Instruction List\n");
1748
1749    while (inst_list_it != instList.end()) {
1750        cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1751                "Squashed:%i\n\n",
1752                num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1753                (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1754                (*inst_list_it)->isSquashed());
1755        inst_list_it++;
1756        ++num;
1757    }
1758}
1759/*
1760template <class Impl>
1761void
1762FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1763{
1764    iew.wakeDependents(inst);
1765}
1766*/
1767template <class Impl>
1768void
1769FullO3CPU<Impl>::wakeCPU()
1770{
1771    if (activityRec.active() || tickEvent.scheduled()) {
1772        DPRINTF(Activity, "CPU already running.\n");
1773        return;
1774    }
1775
1776    DPRINTF(Activity, "Waking up CPU\n");
1777
1778    Cycles cycles(curCycle() - lastRunningCycle);
1779    // @todo: This is an oddity that is only here to match the stats
1780    if (cycles != 0)
1781        --cycles;
1782    idleCycles += cycles;
1783    numCycles += cycles;
1784
1785    schedule(tickEvent, clockEdge());
1786}
1787
1788template <class Impl>
1789void
1790FullO3CPU<Impl>::wakeup()
1791{
1792    if (this->thread[0]->status() != ThreadContext::Suspended)
1793        return;
1794
1795    this->wakeCPU();
1796
1797    DPRINTF(Quiesce, "Suspended Processor woken\n");
1798    this->threadContexts[0]->activate();
1799}
1800
1801template <class Impl>
1802ThreadID
1803FullO3CPU<Impl>::getFreeTid()
1804{
1805    for (ThreadID tid = 0; tid < numThreads; tid++) {
1806        if (!tids[tid]) {
1807            tids[tid] = true;
1808            return tid;
1809        }
1810    }
1811
1812    return InvalidThreadID;
1813}
1814
1815template <class Impl>
1816void
1817FullO3CPU<Impl>::doContextSwitch()
1818{
1819    if (contextSwitch) {
1820
1821        //ADD CODE TO DEACTIVE THREAD HERE (???)
1822
1823        ThreadID size = cpuWaitList.size();
1824        for (ThreadID tid = 0; tid < size; tid++) {
1825            activateWhenReady(tid);
1826        }
1827
1828        if (cpuWaitList.size() == 0)
1829            contextSwitch = true;
1830    }
1831}
1832
1833template <class Impl>
1834void
1835FullO3CPU<Impl>::updateThreadPriority()
1836{
1837    if (activeThreads.size() > 1) {
1838        //DEFAULT TO ROUND ROBIN SCHEME
1839        //e.g. Move highest priority to end of thread list
1840        list<ThreadID>::iterator list_begin = activeThreads.begin();
1841
1842        unsigned high_thread = *list_begin;
1843
1844        activeThreads.erase(list_begin);
1845
1846        activeThreads.push_back(high_thread);
1847    }
1848}
1849
1850// Forward declaration of FullO3CPU.
1851template class FullO3CPU<O3CPUImpl>;
1852