cpu.cc revision 9448
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 * Rick Strong 44 */ 45 46#include "arch/kernel_stats.hh" 47#include "config/the_isa.hh" 48#include "cpu/checker/cpu.hh" 49#include "cpu/checker/thread_context.hh" 50#include "cpu/o3/cpu.hh" 51#include "cpu/o3/isa_specific.hh" 52#include "cpu/o3/thread_context.hh" 53#include "cpu/activity.hh" 54#include "cpu/quiesce_event.hh" 55#include "cpu/simple_thread.hh" 56#include "cpu/thread_context.hh" 57#include "debug/Activity.hh" 58#include "debug/Drain.hh" 59#include "debug/O3CPU.hh" 60#include "debug/Quiesce.hh" 61#include "enums/MemoryMode.hh" 62#include "sim/core.hh" 63#include "sim/full_system.hh" 64#include "sim/process.hh" 65#include "sim/stat_control.hh" 66#include "sim/system.hh" 67 68#if THE_ISA == ALPHA_ISA 69#include "arch/alpha/osfpal.hh" 70#include "debug/Activity.hh" 71#endif 72 73struct BaseCPUParams; 74 75using namespace TheISA; 76using namespace std; 77 78BaseO3CPU::BaseO3CPU(BaseCPUParams *params) 79 : BaseCPU(params) 80{ 81} 82 83void 84BaseO3CPU::regStats() 85{ 86 BaseCPU::regStats(); 87} 88 89template<class Impl> 90bool 91FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 92{ 93 DPRINTF(O3CPU, "Fetch unit received timing\n"); 94 // We shouldn't ever get a block in ownership state 95 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 96 fetch->processCacheCompletion(pkt); 97 98 return true; 99} 100 101template<class Impl> 102void 103FullO3CPU<Impl>::IcachePort::recvRetry() 104{ 105 fetch->recvRetry(); 106} 107 108template <class Impl> 109bool 110FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 111{ 112 return lsq->recvTimingResp(pkt); 113} 114 115template <class Impl> 116void 117FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 118{ 119 lsq->recvTimingSnoopReq(pkt); 120} 121 122template <class Impl> 123void 124FullO3CPU<Impl>::DcachePort::recvRetry() 125{ 126 lsq->recvRetry(); 127} 128 129template <class Impl> 130FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 131 : Event(CPU_Tick_Pri), cpu(c) 132{ 133} 134 135template <class Impl> 136void 137FullO3CPU<Impl>::TickEvent::process() 138{ 139 cpu->tick(); 140} 141 142template <class Impl> 143const char * 144FullO3CPU<Impl>::TickEvent::description() const 145{ 146 return "FullO3CPU tick"; 147} 148 149template <class Impl> 150FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 151 : Event(CPU_Switch_Pri) 152{ 153} 154 155template <class Impl> 156void 157FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 158 FullO3CPU<Impl> *thread_cpu) 159{ 160 tid = thread_num; 161 cpu = thread_cpu; 162} 163 164template <class Impl> 165void 166FullO3CPU<Impl>::ActivateThreadEvent::process() 167{ 168 cpu->activateThread(tid); 169} 170 171template <class Impl> 172const char * 173FullO3CPU<Impl>::ActivateThreadEvent::description() const 174{ 175 return "FullO3CPU \"Activate Thread\""; 176} 177 178template <class Impl> 179FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 180 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 181{ 182} 183 184template <class Impl> 185void 186FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 187 FullO3CPU<Impl> *thread_cpu) 188{ 189 tid = thread_num; 190 cpu = thread_cpu; 191 remove = false; 192} 193 194template <class Impl> 195void 196FullO3CPU<Impl>::DeallocateContextEvent::process() 197{ 198 cpu->deactivateThread(tid); 199 if (remove) 200 cpu->removeThread(tid); 201} 202 203template <class Impl> 204const char * 205FullO3CPU<Impl>::DeallocateContextEvent::description() const 206{ 207 return "FullO3CPU \"Deallocate Context\""; 208} 209 210template <class Impl> 211FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 212 : BaseO3CPU(params), 213 itb(params->itb), 214 dtb(params->dtb), 215 tickEvent(this), 216#ifndef NDEBUG 217 instcount(0), 218#endif 219 removeInstsThisCycle(false), 220 fetch(this, params), 221 decode(this, params), 222 rename(this, params), 223 iew(this, params), 224 commit(this, params), 225 226 regFile(this, params->numPhysIntRegs, 227 params->numPhysFloatRegs), 228 229 freeList(params->numThreads, 230 TheISA::NumIntRegs, params->numPhysIntRegs, 231 TheISA::NumFloatRegs, params->numPhysFloatRegs), 232 233 rob(this, 234 params->numROBEntries, params->squashWidth, 235 params->smtROBPolicy, params->smtROBThreshold, 236 params->numThreads), 237 238 scoreboard(params->numThreads, 239 TheISA::NumIntRegs, params->numPhysIntRegs, 240 TheISA::NumFloatRegs, params->numPhysFloatRegs, 241 TheISA::NumMiscRegs * numThreads, 242 TheISA::ZeroReg), 243 244 isa(numThreads, NULL), 245 246 icachePort(&fetch, this), 247 dcachePort(&iew.ldstQueue, this), 248 249 timeBuffer(params->backComSize, params->forwardComSize), 250 fetchQueue(params->backComSize, params->forwardComSize), 251 decodeQueue(params->backComSize, params->forwardComSize), 252 renameQueue(params->backComSize, params->forwardComSize), 253 iewQueue(params->backComSize, params->forwardComSize), 254 activityRec(name(), NumStages, 255 params->backComSize + params->forwardComSize, 256 params->activity), 257 258 globalSeqNum(1), 259 system(params->system), 260 drainManager(NULL), 261 lastRunningCycle(curCycle()) 262{ 263 if (!params->switched_out) { 264 _status = Running; 265 } else { 266 _status = SwitchedOut; 267 } 268 269 if (params->checker) { 270 BaseCPU *temp_checker = params->checker; 271 checker = dynamic_cast<Checker<Impl> *>(temp_checker); 272 checker->setIcachePort(&icachePort); 273 checker->setSystem(params->system); 274 } else { 275 checker = NULL; 276 } 277 278 if (!FullSystem) { 279 thread.resize(numThreads); 280 tids.resize(numThreads); 281 } 282 283 // The stages also need their CPU pointer setup. However this 284 // must be done at the upper level CPU because they have pointers 285 // to the upper level CPU, and not this FullO3CPU. 286 287 // Set up Pointers to the activeThreads list for each stage 288 fetch.setActiveThreads(&activeThreads); 289 decode.setActiveThreads(&activeThreads); 290 rename.setActiveThreads(&activeThreads); 291 iew.setActiveThreads(&activeThreads); 292 commit.setActiveThreads(&activeThreads); 293 294 // Give each of the stages the time buffer they will use. 295 fetch.setTimeBuffer(&timeBuffer); 296 decode.setTimeBuffer(&timeBuffer); 297 rename.setTimeBuffer(&timeBuffer); 298 iew.setTimeBuffer(&timeBuffer); 299 commit.setTimeBuffer(&timeBuffer); 300 301 // Also setup each of the stages' queues. 302 fetch.setFetchQueue(&fetchQueue); 303 decode.setFetchQueue(&fetchQueue); 304 commit.setFetchQueue(&fetchQueue); 305 decode.setDecodeQueue(&decodeQueue); 306 rename.setDecodeQueue(&decodeQueue); 307 rename.setRenameQueue(&renameQueue); 308 iew.setRenameQueue(&renameQueue); 309 iew.setIEWQueue(&iewQueue); 310 commit.setIEWQueue(&iewQueue); 311 commit.setRenameQueue(&renameQueue); 312 313 commit.setIEWStage(&iew); 314 rename.setIEWStage(&iew); 315 rename.setCommitStage(&commit); 316 317 ThreadID active_threads; 318 if (FullSystem) { 319 active_threads = 1; 320 } else { 321 active_threads = params->workload.size(); 322 323 if (active_threads > Impl::MaxThreads) { 324 panic("Workload Size too large. Increase the 'MaxThreads' " 325 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 326 "or edit your workload size."); 327 } 328 } 329 330 //Make Sure That this a Valid Architeture 331 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 332 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 333 334 rename.setScoreboard(&scoreboard); 335 iew.setScoreboard(&scoreboard); 336 337 // Setup the rename map for whichever stages need it. 338 PhysRegIndex lreg_idx = 0; 339 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 340 341 for (ThreadID tid = 0; tid < numThreads; tid++) { 342 bool bindRegs = (tid <= active_threads - 1); 343 344 isa[tid] = params->isa[tid]; 345 346 commitRenameMap[tid].init(TheISA::NumIntRegs, 347 params->numPhysIntRegs, 348 lreg_idx, //Index for Logical. Regs 349 350 TheISA::NumFloatRegs, 351 params->numPhysFloatRegs, 352 freg_idx, //Index for Float Regs 353 354 TheISA::NumMiscRegs, 355 356 TheISA::ZeroReg, 357 TheISA::ZeroReg, 358 359 tid, 360 false); 361 362 renameMap[tid].init(TheISA::NumIntRegs, 363 params->numPhysIntRegs, 364 lreg_idx, //Index for Logical. Regs 365 366 TheISA::NumFloatRegs, 367 params->numPhysFloatRegs, 368 freg_idx, //Index for Float Regs 369 370 TheISA::NumMiscRegs, 371 372 TheISA::ZeroReg, 373 TheISA::ZeroReg, 374 375 tid, 376 bindRegs); 377 378 activateThreadEvent[tid].init(tid, this); 379 deallocateContextEvent[tid].init(tid, this); 380 } 381 382 rename.setRenameMap(renameMap); 383 commit.setRenameMap(commitRenameMap); 384 385 // Give renameMap & rename stage access to the freeList; 386 for (ThreadID tid = 0; tid < numThreads; tid++) 387 renameMap[tid].setFreeList(&freeList); 388 rename.setFreeList(&freeList); 389 390 // Setup the ROB for whichever stages need it. 391 commit.setROB(&rob); 392 393 lastActivatedCycle = 0; 394#if 0 395 // Give renameMap & rename stage access to the freeList; 396 for (ThreadID tid = 0; tid < numThreads; tid++) 397 globalSeqNum[tid] = 1; 398#endif 399 400 contextSwitch = false; 401 DPRINTF(O3CPU, "Creating O3CPU object.\n"); 402 403 // Setup any thread state. 404 this->thread.resize(this->numThreads); 405 406 for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 407 if (FullSystem) { 408 // SMT is not supported in FS mode yet. 409 assert(this->numThreads == 1); 410 this->thread[tid] = new Thread(this, 0, NULL); 411 } else { 412 if (tid < params->workload.size()) { 413 DPRINTF(O3CPU, "Workload[%i] process is %#x", 414 tid, this->thread[tid]); 415 this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 416 (typename Impl::O3CPU *)(this), 417 tid, params->workload[tid]); 418 419 //usedTids[tid] = true; 420 //threadMap[tid] = tid; 421 } else { 422 //Allocate Empty thread so M5 can use later 423 //when scheduling threads to CPU 424 Process* dummy_proc = NULL; 425 426 this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 427 (typename Impl::O3CPU *)(this), 428 tid, dummy_proc); 429 //usedTids[tid] = false; 430 } 431 } 432 433 ThreadContext *tc; 434 435 // Setup the TC that will serve as the interface to the threads/CPU. 436 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 437 438 tc = o3_tc; 439 440 // If we're using a checker, then the TC should be the 441 // CheckerThreadContext. 442 if (params->checker) { 443 tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 444 o3_tc, this->checker); 445 } 446 447 o3_tc->cpu = (typename Impl::O3CPU *)(this); 448 assert(o3_tc->cpu); 449 o3_tc->thread = this->thread[tid]; 450 451 if (FullSystem) { 452 // Setup quiesce event. 453 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 454 } 455 // Give the thread the TC. 456 this->thread[tid]->tc = tc; 457 458 // Add the TC to the CPU's list of TC's. 459 this->threadContexts.push_back(tc); 460 } 461 462 // FullO3CPU always requires an interrupt controller. 463 if (!params->switched_out && !interrupts) { 464 fatal("FullO3CPU %s has no interrupt controller.\n" 465 "Ensure createInterruptController() is called.\n", name()); 466 } 467 468 for (ThreadID tid = 0; tid < this->numThreads; tid++) 469 this->thread[tid]->setFuncExeInst(0); 470} 471 472template <class Impl> 473FullO3CPU<Impl>::~FullO3CPU() 474{ 475} 476 477template <class Impl> 478void 479FullO3CPU<Impl>::regStats() 480{ 481 BaseO3CPU::regStats(); 482 483 // Register any of the O3CPU's stats here. 484 timesIdled 485 .name(name() + ".timesIdled") 486 .desc("Number of times that the entire CPU went into an idle state and" 487 " unscheduled itself") 488 .prereq(timesIdled); 489 490 idleCycles 491 .name(name() + ".idleCycles") 492 .desc("Total number of cycles that the CPU has spent unscheduled due " 493 "to idling") 494 .prereq(idleCycles); 495 496 quiesceCycles 497 .name(name() + ".quiesceCycles") 498 .desc("Total number of cycles that CPU has spent quiesced or waiting " 499 "for an interrupt") 500 .prereq(quiesceCycles); 501 502 // Number of Instructions simulated 503 // -------------------------------- 504 // Should probably be in Base CPU but need templated 505 // MaxThreads so put in here instead 506 committedInsts 507 .init(numThreads) 508 .name(name() + ".committedInsts") 509 .desc("Number of Instructions Simulated"); 510 511 committedOps 512 .init(numThreads) 513 .name(name() + ".committedOps") 514 .desc("Number of Ops (including micro ops) Simulated"); 515 516 totalCommittedInsts 517 .name(name() + ".committedInsts_total") 518 .desc("Number of Instructions Simulated"); 519 520 cpi 521 .name(name() + ".cpi") 522 .desc("CPI: Cycles Per Instruction") 523 .precision(6); 524 cpi = numCycles / committedInsts; 525 526 totalCpi 527 .name(name() + ".cpi_total") 528 .desc("CPI: Total CPI of All Threads") 529 .precision(6); 530 totalCpi = numCycles / totalCommittedInsts; 531 532 ipc 533 .name(name() + ".ipc") 534 .desc("IPC: Instructions Per Cycle") 535 .precision(6); 536 ipc = committedInsts / numCycles; 537 538 totalIpc 539 .name(name() + ".ipc_total") 540 .desc("IPC: Total IPC of All Threads") 541 .precision(6); 542 totalIpc = totalCommittedInsts / numCycles; 543 544 this->fetch.regStats(); 545 this->decode.regStats(); 546 this->rename.regStats(); 547 this->iew.regStats(); 548 this->commit.regStats(); 549 this->rob.regStats(); 550 551 intRegfileReads 552 .name(name() + ".int_regfile_reads") 553 .desc("number of integer regfile reads") 554 .prereq(intRegfileReads); 555 556 intRegfileWrites 557 .name(name() + ".int_regfile_writes") 558 .desc("number of integer regfile writes") 559 .prereq(intRegfileWrites); 560 561 fpRegfileReads 562 .name(name() + ".fp_regfile_reads") 563 .desc("number of floating regfile reads") 564 .prereq(fpRegfileReads); 565 566 fpRegfileWrites 567 .name(name() + ".fp_regfile_writes") 568 .desc("number of floating regfile writes") 569 .prereq(fpRegfileWrites); 570 571 miscRegfileReads 572 .name(name() + ".misc_regfile_reads") 573 .desc("number of misc regfile reads") 574 .prereq(miscRegfileReads); 575 576 miscRegfileWrites 577 .name(name() + ".misc_regfile_writes") 578 .desc("number of misc regfile writes") 579 .prereq(miscRegfileWrites); 580} 581 582template <class Impl> 583void 584FullO3CPU<Impl>::tick() 585{ 586 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 587 assert(!switchedOut()); 588 assert(getDrainState() != Drainable::Drained); 589 590 ++numCycles; 591 592// activity = false; 593 594 //Tick each of the stages 595 fetch.tick(); 596 597 decode.tick(); 598 599 rename.tick(); 600 601 iew.tick(); 602 603 commit.tick(); 604 605 if (!FullSystem) 606 doContextSwitch(); 607 608 // Now advance the time buffers 609 timeBuffer.advance(); 610 611 fetchQueue.advance(); 612 decodeQueue.advance(); 613 renameQueue.advance(); 614 iewQueue.advance(); 615 616 activityRec.advance(); 617 618 if (removeInstsThisCycle) { 619 cleanUpRemovedInsts(); 620 } 621 622 if (!tickEvent.scheduled()) { 623 if (_status == SwitchedOut) { 624 DPRINTF(O3CPU, "Switched out!\n"); 625 // increment stat 626 lastRunningCycle = curCycle(); 627 } else if (!activityRec.active() || _status == Idle) { 628 DPRINTF(O3CPU, "Idle!\n"); 629 lastRunningCycle = curCycle(); 630 timesIdled++; 631 } else { 632 schedule(tickEvent, clockEdge(Cycles(1))); 633 DPRINTF(O3CPU, "Scheduling next tick!\n"); 634 } 635 } 636 637 if (!FullSystem) 638 updateThreadPriority(); 639 640 tryDrain(); 641} 642 643template <class Impl> 644void 645FullO3CPU<Impl>::init() 646{ 647 BaseCPU::init(); 648 649 if (!params()->switched_out && 650 system->getMemoryMode() != Enums::timing) { 651 fatal("The O3 CPU requires the memory system to be in " 652 "'timing' mode.\n"); 653 } 654 655 for (ThreadID tid = 0; tid < numThreads; ++tid) { 656 // Set noSquashFromTC so that the CPU doesn't squash when initially 657 // setting up registers. 658 thread[tid]->noSquashFromTC = true; 659 // Initialise the ThreadContext's memory proxies 660 thread[tid]->initMemProxies(thread[tid]->getTC()); 661 } 662 663 if (FullSystem && !params()->switched_out) { 664 for (ThreadID tid = 0; tid < numThreads; tid++) { 665 ThreadContext *src_tc = threadContexts[tid]; 666 TheISA::initCPU(src_tc, src_tc->contextId()); 667 } 668 } 669 670 // Clear noSquashFromTC. 671 for (int tid = 0; tid < numThreads; ++tid) 672 thread[tid]->noSquashFromTC = false; 673 674 commit.setThreads(thread); 675} 676 677template <class Impl> 678void 679FullO3CPU<Impl>::startup() 680{ 681 fetch.startupStage(); 682 decode.startupStage(); 683 iew.startupStage(); 684 rename.startupStage(); 685 commit.startupStage(); 686} 687 688template <class Impl> 689void 690FullO3CPU<Impl>::activateThread(ThreadID tid) 691{ 692 list<ThreadID>::iterator isActive = 693 std::find(activeThreads.begin(), activeThreads.end(), tid); 694 695 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 696 assert(!switchedOut()); 697 698 if (isActive == activeThreads.end()) { 699 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 700 tid); 701 702 activeThreads.push_back(tid); 703 } 704} 705 706template <class Impl> 707void 708FullO3CPU<Impl>::deactivateThread(ThreadID tid) 709{ 710 //Remove From Active List, if Active 711 list<ThreadID>::iterator thread_it = 712 std::find(activeThreads.begin(), activeThreads.end(), tid); 713 714 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 715 assert(!switchedOut()); 716 717 if (thread_it != activeThreads.end()) { 718 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 719 tid); 720 activeThreads.erase(thread_it); 721 } 722} 723 724template <class Impl> 725Counter 726FullO3CPU<Impl>::totalInsts() const 727{ 728 Counter total(0); 729 730 ThreadID size = thread.size(); 731 for (ThreadID i = 0; i < size; i++) 732 total += thread[i]->numInst; 733 734 return total; 735} 736 737template <class Impl> 738Counter 739FullO3CPU<Impl>::totalOps() const 740{ 741 Counter total(0); 742 743 ThreadID size = thread.size(); 744 for (ThreadID i = 0; i < size; i++) 745 total += thread[i]->numOp; 746 747 return total; 748} 749 750template <class Impl> 751void 752FullO3CPU<Impl>::activateContext(ThreadID tid, Cycles delay) 753{ 754 assert(!switchedOut()); 755 756 // Needs to set each stage to running as well. 757 if (delay){ 758 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 759 "on cycle %d\n", tid, clockEdge(delay)); 760 scheduleActivateThreadEvent(tid, delay); 761 } else { 762 activateThread(tid); 763 } 764 765 // We don't want to wake the CPU if it is drained. In that case, 766 // we just want to flag the thread as active and schedule the tick 767 // event from drainResume() instead. 768 if (getDrainState() == Drainable::Drained) 769 return; 770 771 // If we are time 0 or if the last activation time is in the past, 772 // schedule the next tick and wake up the fetch unit 773 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 774 scheduleTickEvent(delay); 775 776 // Be sure to signal that there's some activity so the CPU doesn't 777 // deschedule itself. 778 activityRec.activity(); 779 fetch.wakeFromQuiesce(); 780 781 Cycles cycles(curCycle() - lastRunningCycle); 782 // @todo: This is an oddity that is only here to match the stats 783 if (cycles != 0) 784 --cycles; 785 quiesceCycles += cycles; 786 787 lastActivatedCycle = curTick(); 788 789 _status = Running; 790 } 791} 792 793template <class Impl> 794bool 795FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove, 796 Cycles delay) 797{ 798 // Schedule removal of thread data from CPU 799 if (delay){ 800 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 801 "on tick %d\n", tid, clockEdge(delay)); 802 scheduleDeallocateContextEvent(tid, remove, delay); 803 return false; 804 } else { 805 deactivateThread(tid); 806 if (remove) 807 removeThread(tid); 808 return true; 809 } 810} 811 812template <class Impl> 813void 814FullO3CPU<Impl>::suspendContext(ThreadID tid) 815{ 816 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 817 assert(!switchedOut()); 818 bool deallocated = scheduleDeallocateContext(tid, false, Cycles(1)); 819 // If this was the last thread then unschedule the tick event. 820 if ((activeThreads.size() == 1 && !deallocated) || 821 activeThreads.size() == 0) 822 unscheduleTickEvent(); 823 824 DPRINTF(Quiesce, "Suspending Context\n"); 825 lastRunningCycle = curCycle(); 826 _status = Idle; 827} 828 829template <class Impl> 830void 831FullO3CPU<Impl>::haltContext(ThreadID tid) 832{ 833 //For now, this is the same as deallocate 834 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 835 assert(!switchedOut()); 836 scheduleDeallocateContext(tid, true, Cycles(1)); 837} 838 839template <class Impl> 840void 841FullO3CPU<Impl>::insertThread(ThreadID tid) 842{ 843 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 844 // Will change now that the PC and thread state is internal to the CPU 845 // and not in the ThreadContext. 846 ThreadContext *src_tc; 847 if (FullSystem) 848 src_tc = system->threadContexts[tid]; 849 else 850 src_tc = tcBase(tid); 851 852 //Bind Int Regs to Rename Map 853 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 854 PhysRegIndex phys_reg = freeList.getIntReg(); 855 856 renameMap[tid].setEntry(ireg,phys_reg); 857 scoreboard.setReg(phys_reg); 858 } 859 860 //Bind Float Regs to Rename Map 861 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 862 PhysRegIndex phys_reg = freeList.getFloatReg(); 863 864 renameMap[tid].setEntry(freg,phys_reg); 865 scoreboard.setReg(phys_reg); 866 } 867 868 //Copy Thread Data Into RegFile 869 //this->copyFromTC(tid); 870 871 //Set PC/NPC/NNPC 872 pcState(src_tc->pcState(), tid); 873 874 src_tc->setStatus(ThreadContext::Active); 875 876 activateContext(tid, Cycles(1)); 877 878 //Reset ROB/IQ/LSQ Entries 879 commit.rob->resetEntries(); 880 iew.resetEntries(); 881} 882 883template <class Impl> 884void 885FullO3CPU<Impl>::removeThread(ThreadID tid) 886{ 887 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 888 889 // Copy Thread Data From RegFile 890 // If thread is suspended, it might be re-allocated 891 // this->copyToTC(tid); 892 893 894 // @todo: 2-27-2008: Fix how we free up rename mappings 895 // here to alleviate the case for double-freeing registers 896 // in SMT workloads. 897 898 // Unbind Int Regs from Rename Map 899 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 900 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 901 902 scoreboard.unsetReg(phys_reg); 903 freeList.addReg(phys_reg); 904 } 905 906 // Unbind Float Regs from Rename Map 907 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 908 PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 909 910 scoreboard.unsetReg(phys_reg); 911 freeList.addReg(phys_reg); 912 } 913 914 // Squash Throughout Pipeline 915 DynInstPtr inst = commit.rob->readHeadInst(tid); 916 InstSeqNum squash_seq_num = inst->seqNum; 917 fetch.squash(0, squash_seq_num, inst, tid); 918 decode.squash(tid); 919 rename.squash(squash_seq_num, tid); 920 iew.squash(tid); 921 iew.ldstQueue.squash(squash_seq_num, tid); 922 commit.rob->squash(squash_seq_num, tid); 923 924 925 assert(iew.instQueue.getCount(tid) == 0); 926 assert(iew.ldstQueue.getCount(tid) == 0); 927 928 // Reset ROB/IQ/LSQ Entries 929 930 // Commented out for now. This should be possible to do by 931 // telling all the pipeline stages to drain first, and then 932 // checking until the drain completes. Once the pipeline is 933 // drained, call resetEntries(). - 10-09-06 ktlim 934/* 935 if (activeThreads.size() >= 1) { 936 commit.rob->resetEntries(); 937 iew.resetEntries(); 938 } 939*/ 940} 941 942 943template <class Impl> 944void 945FullO3CPU<Impl>::activateWhenReady(ThreadID tid) 946{ 947 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 948 "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 949 tid); 950 951 bool ready = true; 952 953 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 954 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 955 "Phys. Int. Regs.\n", 956 tid); 957 ready = false; 958 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 959 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 960 "Phys. Float. Regs.\n", 961 tid); 962 ready = false; 963 } else if (commit.rob->numFreeEntries() >= 964 commit.rob->entryAmount(activeThreads.size() + 1)) { 965 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 966 "ROB entries.\n", 967 tid); 968 ready = false; 969 } else if (iew.instQueue.numFreeEntries() >= 970 iew.instQueue.entryAmount(activeThreads.size() + 1)) { 971 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 972 "IQ entries.\n", 973 tid); 974 ready = false; 975 } else if (iew.ldstQueue.numFreeEntries() >= 976 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 977 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 978 "LSQ entries.\n", 979 tid); 980 ready = false; 981 } 982 983 if (ready) { 984 insertThread(tid); 985 986 contextSwitch = false; 987 988 cpuWaitList.remove(tid); 989 } else { 990 suspendContext(tid); 991 992 //blocks fetch 993 contextSwitch = true; 994 995 //@todo: dont always add to waitlist 996 //do waitlist 997 cpuWaitList.push_back(tid); 998 } 999} 1000 1001template <class Impl> 1002Fault 1003FullO3CPU<Impl>::hwrei(ThreadID tid) 1004{ 1005#if THE_ISA == ALPHA_ISA 1006 // Need to clear the lock flag upon returning from an interrupt. 1007 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 1008 1009 this->thread[tid]->kernelStats->hwrei(); 1010 1011 // FIXME: XXX check for interrupts? XXX 1012#endif 1013 return NoFault; 1014} 1015 1016template <class Impl> 1017bool 1018FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 1019{ 1020#if THE_ISA == ALPHA_ISA 1021 if (this->thread[tid]->kernelStats) 1022 this->thread[tid]->kernelStats->callpal(palFunc, 1023 this->threadContexts[tid]); 1024 1025 switch (palFunc) { 1026 case PAL::halt: 1027 halt(); 1028 if (--System::numSystemsRunning == 0) 1029 exitSimLoop("all cpus halted"); 1030 break; 1031 1032 case PAL::bpt: 1033 case PAL::bugchk: 1034 if (this->system->breakpoint()) 1035 return false; 1036 break; 1037 } 1038#endif 1039 return true; 1040} 1041 1042template <class Impl> 1043Fault 1044FullO3CPU<Impl>::getInterrupts() 1045{ 1046 // Check if there are any outstanding interrupts 1047 return this->interrupts->getInterrupt(this->threadContexts[0]); 1048} 1049 1050template <class Impl> 1051void 1052FullO3CPU<Impl>::processInterrupts(Fault interrupt) 1053{ 1054 // Check for interrupts here. For now can copy the code that 1055 // exists within isa_fullsys_traits.hh. Also assume that thread 0 1056 // is the one that handles the interrupts. 1057 // @todo: Possibly consolidate the interrupt checking code. 1058 // @todo: Allow other threads to handle interrupts. 1059 1060 assert(interrupt != NoFault); 1061 this->interrupts->updateIntrInfo(this->threadContexts[0]); 1062 1063 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 1064 this->trap(interrupt, 0, NULL); 1065} 1066 1067template <class Impl> 1068void 1069FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) 1070{ 1071 // Pass the thread's TC into the invoke method. 1072 fault->invoke(this->threadContexts[tid], inst); 1073} 1074 1075template <class Impl> 1076void 1077FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 1078{ 1079 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 1080 1081 DPRINTF(Activity,"Activity: syscall() called.\n"); 1082 1083 // Temporarily increase this by one to account for the syscall 1084 // instruction. 1085 ++(this->thread[tid]->funcExeInst); 1086 1087 // Execute the actual syscall. 1088 this->thread[tid]->syscall(callnum); 1089 1090 // Decrease funcExeInst by one as the normal commit will handle 1091 // incrementing it. 1092 --(this->thread[tid]->funcExeInst); 1093} 1094 1095template <class Impl> 1096void 1097FullO3CPU<Impl>::serializeThread(std::ostream &os, ThreadID tid) 1098{ 1099 thread[tid]->serialize(os); 1100} 1101 1102template <class Impl> 1103void 1104FullO3CPU<Impl>::unserializeThread(Checkpoint *cp, const std::string §ion, 1105 ThreadID tid) 1106{ 1107 thread[tid]->unserialize(cp, section); 1108} 1109 1110template <class Impl> 1111unsigned int 1112FullO3CPU<Impl>::drain(DrainManager *drain_manager) 1113{ 1114 // If the CPU isn't doing anything, then return immediately. 1115 if (switchedOut()) { 1116 setDrainState(Drainable::Drained); 1117 return 0; 1118 } 1119 1120 DPRINTF(Drain, "Draining...\n"); 1121 setDrainState(Drainable::Draining); 1122 1123 // We only need to signal a drain to the commit stage as this 1124 // initiates squashing controls the draining. Once the commit 1125 // stage commits an instruction where it is safe to stop, it'll 1126 // squash the rest of the instructions in the pipeline and force 1127 // the fetch stage to stall. The pipeline will be drained once all 1128 // in-flight instructions have retired. 1129 commit.drain(); 1130 1131 // Wake the CPU and record activity so everything can drain out if 1132 // the CPU was not able to immediately drain. 1133 if (!isDrained()) { 1134 drainManager = drain_manager; 1135 1136 wakeCPU(); 1137 activityRec.activity(); 1138 1139 DPRINTF(Drain, "CPU not drained\n"); 1140 1141 return 1; 1142 } else { 1143 setDrainState(Drainable::Drained); 1144 DPRINTF(Drain, "CPU is already drained\n"); 1145 if (tickEvent.scheduled()) 1146 deschedule(tickEvent); 1147 1148 // Flush out any old data from the time buffers. In 1149 // particular, there might be some data in flight from the 1150 // fetch stage that isn't visible in any of the CPU buffers we 1151 // test in isDrained(). 1152 for (int i = 0; i < timeBuffer.getSize(); ++i) { 1153 timeBuffer.advance(); 1154 fetchQueue.advance(); 1155 decodeQueue.advance(); 1156 renameQueue.advance(); 1157 iewQueue.advance(); 1158 } 1159 1160 drainSanityCheck(); 1161 return 0; 1162 } 1163} 1164 1165template <class Impl> 1166bool 1167FullO3CPU<Impl>::tryDrain() 1168{ 1169 if (!drainManager || !isDrained()) 1170 return false; 1171 1172 if (tickEvent.scheduled()) 1173 deschedule(tickEvent); 1174 1175 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 1176 drainManager->signalDrainDone(); 1177 drainManager = NULL; 1178 1179 return true; 1180} 1181 1182template <class Impl> 1183void 1184FullO3CPU<Impl>::drainSanityCheck() const 1185{ 1186 assert(isDrained()); 1187 fetch.drainSanityCheck(); 1188 decode.drainSanityCheck(); 1189 rename.drainSanityCheck(); 1190 iew.drainSanityCheck(); 1191 commit.drainSanityCheck(); 1192} 1193 1194template <class Impl> 1195bool 1196FullO3CPU<Impl>::isDrained() const 1197{ 1198 bool drained(true); 1199 1200 for (ThreadID i = 0; i < thread.size(); ++i) { 1201 if (activateThreadEvent[i].scheduled()) { 1202 DPRINTF(Drain, "CPU not drained, tread %i has a " 1203 "pending activate event\n", i); 1204 drained = false; 1205 } 1206 if (deallocateContextEvent[i].scheduled()) { 1207 DPRINTF(Drain, "CPU not drained, tread %i has a " 1208 "pending deallocate context event\n", i); 1209 drained = false; 1210 } 1211 } 1212 1213 if (!instList.empty() || !removeList.empty()) { 1214 DPRINTF(Drain, "Main CPU structures not drained.\n"); 1215 drained = false; 1216 } 1217 1218 if (!fetch.isDrained()) { 1219 DPRINTF(Drain, "Fetch not drained.\n"); 1220 drained = false; 1221 } 1222 1223 if (!decode.isDrained()) { 1224 DPRINTF(Drain, "Decode not drained.\n"); 1225 drained = false; 1226 } 1227 1228 if (!rename.isDrained()) { 1229 DPRINTF(Drain, "Rename not drained.\n"); 1230 drained = false; 1231 } 1232 1233 if (!iew.isDrained()) { 1234 DPRINTF(Drain, "IEW not drained.\n"); 1235 drained = false; 1236 } 1237 1238 if (!commit.isDrained()) { 1239 DPRINTF(Drain, "Commit not drained.\n"); 1240 drained = false; 1241 } 1242 1243 return drained; 1244} 1245 1246template <class Impl> 1247void 1248FullO3CPU<Impl>::commitDrained(ThreadID tid) 1249{ 1250 fetch.drainStall(tid); 1251} 1252 1253template <class Impl> 1254void 1255FullO3CPU<Impl>::drainResume() 1256{ 1257 setDrainState(Drainable::Running); 1258 if (switchedOut()) 1259 return; 1260 1261 DPRINTF(Drain, "Resuming...\n"); 1262 1263 if (system->getMemoryMode() != Enums::timing) { 1264 fatal("The O3 CPU requires the memory system to be in " 1265 "'timing' mode.\n"); 1266 } 1267 1268 fetch.drainResume(); 1269 commit.drainResume(); 1270 1271 _status = Idle; 1272 for (ThreadID i = 0; i < thread.size(); i++) { 1273 if (thread[i]->status() == ThreadContext::Active) { 1274 DPRINTF(Drain, "Activating thread: %i\n", i); 1275 activateThread(i); 1276 _status = Running; 1277 } 1278 } 1279 1280 assert(!tickEvent.scheduled()); 1281 if (_status == Running) 1282 schedule(tickEvent, nextCycle()); 1283} 1284 1285template <class Impl> 1286void 1287FullO3CPU<Impl>::switchOut() 1288{ 1289 DPRINTF(O3CPU, "Switching out\n"); 1290 BaseCPU::switchOut(); 1291 1292 activityRec.reset(); 1293 1294 _status = SwitchedOut; 1295 1296 if (checker) 1297 checker->switchOut(); 1298} 1299 1300template <class Impl> 1301void 1302FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 1303{ 1304 BaseCPU::takeOverFrom(oldCPU); 1305 1306 fetch.takeOverFrom(); 1307 decode.takeOverFrom(); 1308 rename.takeOverFrom(); 1309 iew.takeOverFrom(); 1310 commit.takeOverFrom(); 1311 1312 assert(!tickEvent.scheduled()); 1313 1314 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 1315 if (oldO3CPU) 1316 globalSeqNum = oldO3CPU->globalSeqNum; 1317 1318 lastRunningCycle = curCycle(); 1319 _status = Idle; 1320} 1321 1322template <class Impl> 1323TheISA::MiscReg 1324FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 1325{ 1326 return this->isa[tid]->readMiscRegNoEffect(misc_reg); 1327} 1328 1329template <class Impl> 1330TheISA::MiscReg 1331FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 1332{ 1333 miscRegfileReads++; 1334 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 1335} 1336 1337template <class Impl> 1338void 1339FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 1340 const TheISA::MiscReg &val, ThreadID tid) 1341{ 1342 this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 1343} 1344 1345template <class Impl> 1346void 1347FullO3CPU<Impl>::setMiscReg(int misc_reg, 1348 const TheISA::MiscReg &val, ThreadID tid) 1349{ 1350 miscRegfileWrites++; 1351 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 1352} 1353 1354template <class Impl> 1355uint64_t 1356FullO3CPU<Impl>::readIntReg(int reg_idx) 1357{ 1358 intRegfileReads++; 1359 return regFile.readIntReg(reg_idx); 1360} 1361 1362template <class Impl> 1363FloatReg 1364FullO3CPU<Impl>::readFloatReg(int reg_idx) 1365{ 1366 fpRegfileReads++; 1367 return regFile.readFloatReg(reg_idx); 1368} 1369 1370template <class Impl> 1371FloatRegBits 1372FullO3CPU<Impl>::readFloatRegBits(int reg_idx) 1373{ 1374 fpRegfileReads++; 1375 return regFile.readFloatRegBits(reg_idx); 1376} 1377 1378template <class Impl> 1379void 1380FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 1381{ 1382 intRegfileWrites++; 1383 regFile.setIntReg(reg_idx, val); 1384} 1385 1386template <class Impl> 1387void 1388FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 1389{ 1390 fpRegfileWrites++; 1391 regFile.setFloatReg(reg_idx, val); 1392} 1393 1394template <class Impl> 1395void 1396FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 1397{ 1398 fpRegfileWrites++; 1399 regFile.setFloatRegBits(reg_idx, val); 1400} 1401 1402template <class Impl> 1403uint64_t 1404FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 1405{ 1406 intRegfileReads++; 1407 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 1408 1409 return regFile.readIntReg(phys_reg); 1410} 1411 1412template <class Impl> 1413float 1414FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 1415{ 1416 fpRegfileReads++; 1417 int idx = reg_idx + TheISA::NumIntRegs; 1418 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1419 1420 return regFile.readFloatReg(phys_reg); 1421} 1422 1423template <class Impl> 1424uint64_t 1425FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 1426{ 1427 fpRegfileReads++; 1428 int idx = reg_idx + TheISA::NumIntRegs; 1429 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1430 1431 return regFile.readFloatRegBits(phys_reg); 1432} 1433 1434template <class Impl> 1435void 1436FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 1437{ 1438 intRegfileWrites++; 1439 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 1440 1441 regFile.setIntReg(phys_reg, val); 1442} 1443 1444template <class Impl> 1445void 1446FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 1447{ 1448 fpRegfileWrites++; 1449 int idx = reg_idx + TheISA::NumIntRegs; 1450 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1451 1452 regFile.setFloatReg(phys_reg, val); 1453} 1454 1455template <class Impl> 1456void 1457FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 1458{ 1459 fpRegfileWrites++; 1460 int idx = reg_idx + TheISA::NumIntRegs; 1461 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1462 1463 regFile.setFloatRegBits(phys_reg, val); 1464} 1465 1466template <class Impl> 1467TheISA::PCState 1468FullO3CPU<Impl>::pcState(ThreadID tid) 1469{ 1470 return commit.pcState(tid); 1471} 1472 1473template <class Impl> 1474void 1475FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 1476{ 1477 commit.pcState(val, tid); 1478} 1479 1480template <class Impl> 1481Addr 1482FullO3CPU<Impl>::instAddr(ThreadID tid) 1483{ 1484 return commit.instAddr(tid); 1485} 1486 1487template <class Impl> 1488Addr 1489FullO3CPU<Impl>::nextInstAddr(ThreadID tid) 1490{ 1491 return commit.nextInstAddr(tid); 1492} 1493 1494template <class Impl> 1495MicroPC 1496FullO3CPU<Impl>::microPC(ThreadID tid) 1497{ 1498 return commit.microPC(tid); 1499} 1500 1501template <class Impl> 1502void 1503FullO3CPU<Impl>::squashFromTC(ThreadID tid) 1504{ 1505 this->thread[tid]->noSquashFromTC = true; 1506 this->commit.generateTCEvent(tid); 1507} 1508 1509template <class Impl> 1510typename FullO3CPU<Impl>::ListIt 1511FullO3CPU<Impl>::addInst(DynInstPtr &inst) 1512{ 1513 instList.push_back(inst); 1514 1515 return --(instList.end()); 1516} 1517 1518template <class Impl> 1519void 1520FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 1521{ 1522 // Keep an instruction count. 1523 if (!inst->isMicroop() || inst->isLastMicroop()) { 1524 thread[tid]->numInst++; 1525 thread[tid]->numInsts++; 1526 committedInsts[tid]++; 1527 totalCommittedInsts++; 1528 } 1529 thread[tid]->numOp++; 1530 thread[tid]->numOps++; 1531 committedOps[tid]++; 1532 1533 system->totalNumInsts++; 1534 // Check for instruction-count-based events. 1535 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 1536 system->instEventQueue.serviceEvents(system->totalNumInsts); 1537} 1538 1539template <class Impl> 1540void 1541FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 1542{ 1543 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 1544 "[sn:%lli]\n", 1545 inst->threadNumber, inst->pcState(), inst->seqNum); 1546 1547 removeInstsThisCycle = true; 1548 1549 // Remove the front instruction. 1550 removeList.push(inst->getInstListIt()); 1551} 1552 1553template <class Impl> 1554void 1555FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 1556{ 1557 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 1558 " list.\n", tid); 1559 1560 ListIt end_it; 1561 1562 bool rob_empty = false; 1563 1564 if (instList.empty()) { 1565 return; 1566 } else if (rob.isEmpty(/*tid*/)) { 1567 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 1568 end_it = instList.begin(); 1569 rob_empty = true; 1570 } else { 1571 end_it = (rob.readTailInst(tid))->getInstListIt(); 1572 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 1573 } 1574 1575 removeInstsThisCycle = true; 1576 1577 ListIt inst_it = instList.end(); 1578 1579 inst_it--; 1580 1581 // Walk through the instruction list, removing any instructions 1582 // that were inserted after the given instruction iterator, end_it. 1583 while (inst_it != end_it) { 1584 assert(!instList.empty()); 1585 1586 squashInstIt(inst_it, tid); 1587 1588 inst_it--; 1589 } 1590 1591 // If the ROB was empty, then we actually need to remove the first 1592 // instruction as well. 1593 if (rob_empty) { 1594 squashInstIt(inst_it, tid); 1595 } 1596} 1597 1598template <class Impl> 1599void 1600FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 1601{ 1602 assert(!instList.empty()); 1603 1604 removeInstsThisCycle = true; 1605 1606 ListIt inst_iter = instList.end(); 1607 1608 inst_iter--; 1609 1610 DPRINTF(O3CPU, "Deleting instructions from instruction " 1611 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 1612 tid, seq_num, (*inst_iter)->seqNum); 1613 1614 while ((*inst_iter)->seqNum > seq_num) { 1615 1616 bool break_loop = (inst_iter == instList.begin()); 1617 1618 squashInstIt(inst_iter, tid); 1619 1620 inst_iter--; 1621 1622 if (break_loop) 1623 break; 1624 } 1625} 1626 1627template <class Impl> 1628inline void 1629FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 1630{ 1631 if ((*instIt)->threadNumber == tid) { 1632 DPRINTF(O3CPU, "Squashing instruction, " 1633 "[tid:%i] [sn:%lli] PC %s\n", 1634 (*instIt)->threadNumber, 1635 (*instIt)->seqNum, 1636 (*instIt)->pcState()); 1637 1638 // Mark it as squashed. 1639 (*instIt)->setSquashed(); 1640 1641 // @todo: Formulate a consistent method for deleting 1642 // instructions from the instruction list 1643 // Remove the instruction from the list. 1644 removeList.push(instIt); 1645 } 1646} 1647 1648template <class Impl> 1649void 1650FullO3CPU<Impl>::cleanUpRemovedInsts() 1651{ 1652 while (!removeList.empty()) { 1653 DPRINTF(O3CPU, "Removing instruction, " 1654 "[tid:%i] [sn:%lli] PC %s\n", 1655 (*removeList.front())->threadNumber, 1656 (*removeList.front())->seqNum, 1657 (*removeList.front())->pcState()); 1658 1659 instList.erase(removeList.front()); 1660 1661 removeList.pop(); 1662 } 1663 1664 removeInstsThisCycle = false; 1665} 1666/* 1667template <class Impl> 1668void 1669FullO3CPU<Impl>::removeAllInsts() 1670{ 1671 instList.clear(); 1672} 1673*/ 1674template <class Impl> 1675void 1676FullO3CPU<Impl>::dumpInsts() 1677{ 1678 int num = 0; 1679 1680 ListIt inst_list_it = instList.begin(); 1681 1682 cprintf("Dumping Instruction List\n"); 1683 1684 while (inst_list_it != instList.end()) { 1685 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 1686 "Squashed:%i\n\n", 1687 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 1688 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 1689 (*inst_list_it)->isSquashed()); 1690 inst_list_it++; 1691 ++num; 1692 } 1693} 1694/* 1695template <class Impl> 1696void 1697FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 1698{ 1699 iew.wakeDependents(inst); 1700} 1701*/ 1702template <class Impl> 1703void 1704FullO3CPU<Impl>::wakeCPU() 1705{ 1706 if (activityRec.active() || tickEvent.scheduled()) { 1707 DPRINTF(Activity, "CPU already running.\n"); 1708 return; 1709 } 1710 1711 DPRINTF(Activity, "Waking up CPU\n"); 1712 1713 Cycles cycles(curCycle() - lastRunningCycle); 1714 // @todo: This is an oddity that is only here to match the stats 1715 if (cycles != 0) 1716 --cycles; 1717 idleCycles += cycles; 1718 numCycles += cycles; 1719 1720 schedule(tickEvent, nextCycle()); 1721} 1722 1723template <class Impl> 1724void 1725FullO3CPU<Impl>::wakeup() 1726{ 1727 if (this->thread[0]->status() != ThreadContext::Suspended) 1728 return; 1729 1730 this->wakeCPU(); 1731 1732 DPRINTF(Quiesce, "Suspended Processor woken\n"); 1733 this->threadContexts[0]->activate(); 1734} 1735 1736template <class Impl> 1737ThreadID 1738FullO3CPU<Impl>::getFreeTid() 1739{ 1740 for (ThreadID tid = 0; tid < numThreads; tid++) { 1741 if (!tids[tid]) { 1742 tids[tid] = true; 1743 return tid; 1744 } 1745 } 1746 1747 return InvalidThreadID; 1748} 1749 1750template <class Impl> 1751void 1752FullO3CPU<Impl>::doContextSwitch() 1753{ 1754 if (contextSwitch) { 1755 1756 //ADD CODE TO DEACTIVE THREAD HERE (???) 1757 1758 ThreadID size = cpuWaitList.size(); 1759 for (ThreadID tid = 0; tid < size; tid++) { 1760 activateWhenReady(tid); 1761 } 1762 1763 if (cpuWaitList.size() == 0) 1764 contextSwitch = true; 1765 } 1766} 1767 1768template <class Impl> 1769void 1770FullO3CPU<Impl>::updateThreadPriority() 1771{ 1772 if (activeThreads.size() > 1) { 1773 //DEFAULT TO ROUND ROBIN SCHEME 1774 //e.g. Move highest priority to end of thread list 1775 list<ThreadID>::iterator list_begin = activeThreads.begin(); 1776 1777 unsigned high_thread = *list_begin; 1778 1779 activeThreads.erase(list_begin); 1780 1781 activeThreads.push_back(high_thread); 1782 } 1783} 1784 1785// Forward declaration of FullO3CPU. 1786template class FullO3CPU<O3CPUImpl>; 1787