cpu.cc revision 9436:4a0223da4924 
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Korey Sewell
43 *          Rick Strong
44 */
45
46#include "arch/kernel_stats.hh"
47#include "config/the_isa.hh"
48#include "cpu/checker/cpu.hh"
49#include "cpu/checker/thread_context.hh"
50#include "cpu/o3/cpu.hh"
51#include "cpu/o3/isa_specific.hh"
52#include "cpu/o3/thread_context.hh"
53#include "cpu/activity.hh"
54#include "cpu/quiesce_event.hh"
55#include "cpu/simple_thread.hh"
56#include "cpu/thread_context.hh"
57#include "debug/Activity.hh"
58#include "debug/Drain.hh"
59#include "debug/O3CPU.hh"
60#include "debug/Quiesce.hh"
61#include "enums/MemoryMode.hh"
62#include "sim/core.hh"
63#include "sim/full_system.hh"
64#include "sim/process.hh"
65#include "sim/stat_control.hh"
66#include "sim/system.hh"
67
68#if THE_ISA == ALPHA_ISA
69#include "arch/alpha/osfpal.hh"
70#include "debug/Activity.hh"
71#endif
72
73struct BaseCPUParams;
74
75using namespace TheISA;
76using namespace std;
77
78BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
79    : BaseCPU(params)
80{
81}
82
83void
84BaseO3CPU::regStats()
85{
86    BaseCPU::regStats();
87}
88
89template<class Impl>
90bool
91FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
92{
93    DPRINTF(O3CPU, "Fetch unit received timing\n");
94    // We shouldn't ever get a block in ownership state
95    assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
96    fetch->processCacheCompletion(pkt);
97
98    return true;
99}
100
101template<class Impl>
102void
103FullO3CPU<Impl>::IcachePort::recvRetry()
104{
105    fetch->recvRetry();
106}
107
108template <class Impl>
109bool
110FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
111{
112    return lsq->recvTimingResp(pkt);
113}
114
115template <class Impl>
116void
117FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
118{
119    lsq->recvTimingSnoopReq(pkt);
120}
121
122template <class Impl>
123void
124FullO3CPU<Impl>::DcachePort::recvRetry()
125{
126    lsq->recvRetry();
127}
128
129template <class Impl>
130FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
131    : Event(CPU_Tick_Pri), cpu(c)
132{
133}
134
135template <class Impl>
136void
137FullO3CPU<Impl>::TickEvent::process()
138{
139    cpu->tick();
140}
141
142template <class Impl>
143const char *
144FullO3CPU<Impl>::TickEvent::description() const
145{
146    return "FullO3CPU tick";
147}
148
149template <class Impl>
150FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
151    : Event(CPU_Switch_Pri)
152{
153}
154
155template <class Impl>
156void
157FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
158                                           FullO3CPU<Impl> *thread_cpu)
159{
160    tid = thread_num;
161    cpu = thread_cpu;
162}
163
164template <class Impl>
165void
166FullO3CPU<Impl>::ActivateThreadEvent::process()
167{
168    cpu->activateThread(tid);
169}
170
171template <class Impl>
172const char *
173FullO3CPU<Impl>::ActivateThreadEvent::description() const
174{
175    return "FullO3CPU \"Activate Thread\"";
176}
177
178template <class Impl>
179FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
180    : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
181{
182}
183
184template <class Impl>
185void
186FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
187                                              FullO3CPU<Impl> *thread_cpu)
188{
189    tid = thread_num;
190    cpu = thread_cpu;
191    remove = false;
192}
193
194template <class Impl>
195void
196FullO3CPU<Impl>::DeallocateContextEvent::process()
197{
198    cpu->deactivateThread(tid);
199    if (remove)
200        cpu->removeThread(tid);
201}
202
203template <class Impl>
204const char *
205FullO3CPU<Impl>::DeallocateContextEvent::description() const
206{
207    return "FullO3CPU \"Deallocate Context\"";
208}
209
210template <class Impl>
211FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
212    : BaseO3CPU(params),
213      itb(params->itb),
214      dtb(params->dtb),
215      tickEvent(this),
216#ifndef NDEBUG
217      instcount(0),
218#endif
219      removeInstsThisCycle(false),
220      fetch(this, params),
221      decode(this, params),
222      rename(this, params),
223      iew(this, params),
224      commit(this, params),
225
226      regFile(this, params->numPhysIntRegs,
227              params->numPhysFloatRegs),
228
229      freeList(params->numThreads,
230               TheISA::NumIntRegs, params->numPhysIntRegs,
231               TheISA::NumFloatRegs, params->numPhysFloatRegs),
232
233      rob(this,
234          params->numROBEntries, params->squashWidth,
235          params->smtROBPolicy, params->smtROBThreshold,
236          params->numThreads),
237
238      scoreboard(params->numThreads,
239                 TheISA::NumIntRegs, params->numPhysIntRegs,
240                 TheISA::NumFloatRegs, params->numPhysFloatRegs,
241                 TheISA::NumMiscRegs * numThreads,
242                 TheISA::ZeroReg),
243
244      isa(numThreads, NULL),
245
246      icachePort(&fetch, this),
247      dcachePort(&iew.ldstQueue, this),
248
249      timeBuffer(params->backComSize, params->forwardComSize),
250      fetchQueue(params->backComSize, params->forwardComSize),
251      decodeQueue(params->backComSize, params->forwardComSize),
252      renameQueue(params->backComSize, params->forwardComSize),
253      iewQueue(params->backComSize, params->forwardComSize),
254      activityRec(name(), NumStages,
255                  params->backComSize + params->forwardComSize,
256                  params->activity),
257
258      globalSeqNum(1),
259      system(params->system),
260      drainCount(0),
261      lastRunningCycle(curCycle())
262{
263    if (!params->switched_out) {
264        _status = Running;
265    } else {
266        _status = SwitchedOut;
267    }
268
269    if (params->checker) {
270        BaseCPU *temp_checker = params->checker;
271        checker = dynamic_cast<Checker<Impl> *>(temp_checker);
272        checker->setIcachePort(&icachePort);
273        checker->setSystem(params->system);
274    } else {
275        checker = NULL;
276    }
277
278    if (!FullSystem) {
279        thread.resize(numThreads);
280        tids.resize(numThreads);
281    }
282
283    // The stages also need their CPU pointer setup.  However this
284    // must be done at the upper level CPU because they have pointers
285    // to the upper level CPU, and not this FullO3CPU.
286
287    // Set up Pointers to the activeThreads list for each stage
288    fetch.setActiveThreads(&activeThreads);
289    decode.setActiveThreads(&activeThreads);
290    rename.setActiveThreads(&activeThreads);
291    iew.setActiveThreads(&activeThreads);
292    commit.setActiveThreads(&activeThreads);
293
294    // Give each of the stages the time buffer they will use.
295    fetch.setTimeBuffer(&timeBuffer);
296    decode.setTimeBuffer(&timeBuffer);
297    rename.setTimeBuffer(&timeBuffer);
298    iew.setTimeBuffer(&timeBuffer);
299    commit.setTimeBuffer(&timeBuffer);
300
301    // Also setup each of the stages' queues.
302    fetch.setFetchQueue(&fetchQueue);
303    decode.setFetchQueue(&fetchQueue);
304    commit.setFetchQueue(&fetchQueue);
305    decode.setDecodeQueue(&decodeQueue);
306    rename.setDecodeQueue(&decodeQueue);
307    rename.setRenameQueue(&renameQueue);
308    iew.setRenameQueue(&renameQueue);
309    iew.setIEWQueue(&iewQueue);
310    commit.setIEWQueue(&iewQueue);
311    commit.setRenameQueue(&renameQueue);
312
313    commit.setIEWStage(&iew);
314    rename.setIEWStage(&iew);
315    rename.setCommitStage(&commit);
316
317    ThreadID active_threads;
318    if (FullSystem) {
319        active_threads = 1;
320    } else {
321        active_threads = params->workload.size();
322
323        if (active_threads > Impl::MaxThreads) {
324            panic("Workload Size too large. Increase the 'MaxThreads' "
325                  "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
326                  "or edit your workload size.");
327        }
328    }
329
330    //Make Sure That this a Valid Architeture
331    assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
332    assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
333
334    rename.setScoreboard(&scoreboard);
335    iew.setScoreboard(&scoreboard);
336
337    // Setup the rename map for whichever stages need it.
338    PhysRegIndex lreg_idx = 0;
339    PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
340
341    for (ThreadID tid = 0; tid < numThreads; tid++) {
342        bool bindRegs = (tid <= active_threads - 1);
343
344        isa[tid] = params->isa[tid];
345
346        commitRenameMap[tid].init(TheISA::NumIntRegs,
347                                  params->numPhysIntRegs,
348                                  lreg_idx,            //Index for Logical. Regs
349
350                                  TheISA::NumFloatRegs,
351                                  params->numPhysFloatRegs,
352                                  freg_idx,            //Index for Float Regs
353
354                                  TheISA::NumMiscRegs,
355
356                                  TheISA::ZeroReg,
357                                  TheISA::ZeroReg,
358
359                                  tid,
360                                  false);
361
362        renameMap[tid].init(TheISA::NumIntRegs,
363                            params->numPhysIntRegs,
364                            lreg_idx,                  //Index for Logical. Regs
365
366                            TheISA::NumFloatRegs,
367                            params->numPhysFloatRegs,
368                            freg_idx,                  //Index for Float Regs
369
370                            TheISA::NumMiscRegs,
371
372                            TheISA::ZeroReg,
373                            TheISA::ZeroReg,
374
375                            tid,
376                            bindRegs);
377
378        activateThreadEvent[tid].init(tid, this);
379        deallocateContextEvent[tid].init(tid, this);
380    }
381
382    rename.setRenameMap(renameMap);
383    commit.setRenameMap(commitRenameMap);
384
385    // Give renameMap & rename stage access to the freeList;
386    for (ThreadID tid = 0; tid < numThreads; tid++)
387        renameMap[tid].setFreeList(&freeList);
388    rename.setFreeList(&freeList);
389
390    // Setup the ROB for whichever stages need it.
391    commit.setROB(&rob);
392
393    lastActivatedCycle = 0;
394#if 0
395    // Give renameMap & rename stage access to the freeList;
396    for (ThreadID tid = 0; tid < numThreads; tid++)
397        globalSeqNum[tid] = 1;
398#endif
399
400    contextSwitch = false;
401    DPRINTF(O3CPU, "Creating O3CPU object.\n");
402
403    // Setup any thread state.
404    this->thread.resize(this->numThreads);
405
406    for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
407        if (FullSystem) {
408            // SMT is not supported in FS mode yet.
409            assert(this->numThreads == 1);
410            this->thread[tid] = new Thread(this, 0, NULL);
411        } else {
412            if (tid < params->workload.size()) {
413                DPRINTF(O3CPU, "Workload[%i] process is %#x",
414                        tid, this->thread[tid]);
415                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
416                        (typename Impl::O3CPU *)(this),
417                        tid, params->workload[tid]);
418
419                //usedTids[tid] = true;
420                //threadMap[tid] = tid;
421            } else {
422                //Allocate Empty thread so M5 can use later
423                //when scheduling threads to CPU
424                Process* dummy_proc = NULL;
425
426                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
427                        (typename Impl::O3CPU *)(this),
428                        tid, dummy_proc);
429                //usedTids[tid] = false;
430            }
431        }
432
433        ThreadContext *tc;
434
435        // Setup the TC that will serve as the interface to the threads/CPU.
436        O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
437
438        tc = o3_tc;
439
440        // If we're using a checker, then the TC should be the
441        // CheckerThreadContext.
442        if (params->checker) {
443            tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
444                o3_tc, this->checker);
445        }
446
447        o3_tc->cpu = (typename Impl::O3CPU *)(this);
448        assert(o3_tc->cpu);
449        o3_tc->thread = this->thread[tid];
450
451        if (FullSystem) {
452            // Setup quiesce event.
453            this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
454        }
455        // Give the thread the TC.
456        this->thread[tid]->tc = tc;
457
458        // Add the TC to the CPU's list of TC's.
459        this->threadContexts.push_back(tc);
460    }
461
462    // FullO3CPU always requires an interrupt controller.
463    if (!params->switched_out && !interrupts) {
464        fatal("FullO3CPU %s has no interrupt controller.\n"
465              "Ensure createInterruptController() is called.\n", name());
466    }
467
468    for (ThreadID tid = 0; tid < this->numThreads; tid++)
469        this->thread[tid]->setFuncExeInst(0);
470}
471
472template <class Impl>
473FullO3CPU<Impl>::~FullO3CPU()
474{
475}
476
477template <class Impl>
478void
479FullO3CPU<Impl>::regStats()
480{
481    BaseO3CPU::regStats();
482
483    // Register any of the O3CPU's stats here.
484    timesIdled
485        .name(name() + ".timesIdled")
486        .desc("Number of times that the entire CPU went into an idle state and"
487              " unscheduled itself")
488        .prereq(timesIdled);
489
490    idleCycles
491        .name(name() + ".idleCycles")
492        .desc("Total number of cycles that the CPU has spent unscheduled due "
493              "to idling")
494        .prereq(idleCycles);
495
496    quiesceCycles
497        .name(name() + ".quiesceCycles")
498        .desc("Total number of cycles that CPU has spent quiesced or waiting "
499              "for an interrupt")
500        .prereq(quiesceCycles);
501
502    // Number of Instructions simulated
503    // --------------------------------
504    // Should probably be in Base CPU but need templated
505    // MaxThreads so put in here instead
506    committedInsts
507        .init(numThreads)
508        .name(name() + ".committedInsts")
509        .desc("Number of Instructions Simulated");
510
511    committedOps
512        .init(numThreads)
513        .name(name() + ".committedOps")
514        .desc("Number of Ops (including micro ops) Simulated");
515
516    totalCommittedInsts
517        .name(name() + ".committedInsts_total")
518        .desc("Number of Instructions Simulated");
519
520    cpi
521        .name(name() + ".cpi")
522        .desc("CPI: Cycles Per Instruction")
523        .precision(6);
524    cpi = numCycles / committedInsts;
525
526    totalCpi
527        .name(name() + ".cpi_total")
528        .desc("CPI: Total CPI of All Threads")
529        .precision(6);
530    totalCpi = numCycles / totalCommittedInsts;
531
532    ipc
533        .name(name() + ".ipc")
534        .desc("IPC: Instructions Per Cycle")
535        .precision(6);
536    ipc =  committedInsts / numCycles;
537
538    totalIpc
539        .name(name() + ".ipc_total")
540        .desc("IPC: Total IPC of All Threads")
541        .precision(6);
542    totalIpc =  totalCommittedInsts / numCycles;
543
544    this->fetch.regStats();
545    this->decode.regStats();
546    this->rename.regStats();
547    this->iew.regStats();
548    this->commit.regStats();
549    this->rob.regStats();
550
551    intRegfileReads
552        .name(name() + ".int_regfile_reads")
553        .desc("number of integer regfile reads")
554        .prereq(intRegfileReads);
555
556    intRegfileWrites
557        .name(name() + ".int_regfile_writes")
558        .desc("number of integer regfile writes")
559        .prereq(intRegfileWrites);
560
561    fpRegfileReads
562        .name(name() + ".fp_regfile_reads")
563        .desc("number of floating regfile reads")
564        .prereq(fpRegfileReads);
565
566    fpRegfileWrites
567        .name(name() + ".fp_regfile_writes")
568        .desc("number of floating regfile writes")
569        .prereq(fpRegfileWrites);
570
571    miscRegfileReads
572        .name(name() + ".misc_regfile_reads")
573        .desc("number of misc regfile reads")
574        .prereq(miscRegfileReads);
575
576    miscRegfileWrites
577        .name(name() + ".misc_regfile_writes")
578        .desc("number of misc regfile writes")
579        .prereq(miscRegfileWrites);
580}
581
582template <class Impl>
583void
584FullO3CPU<Impl>::tick()
585{
586    DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
587
588    ++numCycles;
589
590//    activity = false;
591
592    //Tick each of the stages
593    fetch.tick();
594
595    decode.tick();
596
597    rename.tick();
598
599    iew.tick();
600
601    commit.tick();
602
603    if (!FullSystem)
604        doContextSwitch();
605
606    // Now advance the time buffers
607    timeBuffer.advance();
608
609    fetchQueue.advance();
610    decodeQueue.advance();
611    renameQueue.advance();
612    iewQueue.advance();
613
614    activityRec.advance();
615
616    if (removeInstsThisCycle) {
617        cleanUpRemovedInsts();
618    }
619
620    if (!tickEvent.scheduled()) {
621        if (_status == SwitchedOut ||
622            getDrainState() == Drainable::Drained) {
623            DPRINTF(O3CPU, "Switched out!\n");
624            // increment stat
625            lastRunningCycle = curCycle();
626        } else if (!activityRec.active() || _status == Idle) {
627            DPRINTF(O3CPU, "Idle!\n");
628            lastRunningCycle = curCycle();
629            timesIdled++;
630        } else {
631            schedule(tickEvent, clockEdge(Cycles(1)));
632            DPRINTF(O3CPU, "Scheduling next tick!\n");
633        }
634    }
635
636    if (!FullSystem)
637        updateThreadPriority();
638}
639
640template <class Impl>
641void
642FullO3CPU<Impl>::init()
643{
644    BaseCPU::init();
645
646    if (!params()->switched_out &&
647        system->getMemoryMode() != Enums::timing) {
648        fatal("The O3 CPU requires the memory system to be in "
649              "'timing' mode.\n");
650    }
651
652    for (ThreadID tid = 0; tid < numThreads; ++tid) {
653        // Set noSquashFromTC so that the CPU doesn't squash when initially
654        // setting up registers.
655        thread[tid]->noSquashFromTC = true;
656        // Initialise the ThreadContext's memory proxies
657        thread[tid]->initMemProxies(thread[tid]->getTC());
658    }
659
660    // this CPU could still be unconnected if we are restoring from a
661    // checkpoint and this CPU is to be switched in, thus we can only
662    // do this here if the instruction port is actually connected, if
663    // not we have to do it as part of takeOverFrom
664    if (icachePort.isConnected())
665        fetch.setIcache();
666
667    if (FullSystem && !params()->switched_out) {
668        for (ThreadID tid = 0; tid < numThreads; tid++) {
669            ThreadContext *src_tc = threadContexts[tid];
670            TheISA::initCPU(src_tc, src_tc->contextId());
671        }
672    }
673
674    // Clear noSquashFromTC.
675    for (int tid = 0; tid < numThreads; ++tid)
676        thread[tid]->noSquashFromTC = false;
677
678    commit.setThreads(thread);
679}
680
681template <class Impl>
682void
683FullO3CPU<Impl>::startup()
684{
685    fetch.startupStage();
686    iew.startupStage();
687    rename.startupStage();
688    commit.startupStage();
689}
690
691template <class Impl>
692void
693FullO3CPU<Impl>::activateThread(ThreadID tid)
694{
695    list<ThreadID>::iterator isActive =
696        std::find(activeThreads.begin(), activeThreads.end(), tid);
697
698    DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
699
700    if (isActive == activeThreads.end()) {
701        DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
702                tid);
703
704        activeThreads.push_back(tid);
705    }
706}
707
708template <class Impl>
709void
710FullO3CPU<Impl>::deactivateThread(ThreadID tid)
711{
712    //Remove From Active List, if Active
713    list<ThreadID>::iterator thread_it =
714        std::find(activeThreads.begin(), activeThreads.end(), tid);
715
716    DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
717
718    if (thread_it != activeThreads.end()) {
719        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
720                tid);
721        activeThreads.erase(thread_it);
722    }
723}
724
725template <class Impl>
726Counter
727FullO3CPU<Impl>::totalInsts() const
728{
729    Counter total(0);
730
731    ThreadID size = thread.size();
732    for (ThreadID i = 0; i < size; i++)
733        total += thread[i]->numInst;
734
735    return total;
736}
737
738template <class Impl>
739Counter
740FullO3CPU<Impl>::totalOps() const
741{
742    Counter total(0);
743
744    ThreadID size = thread.size();
745    for (ThreadID i = 0; i < size; i++)
746        total += thread[i]->numOp;
747
748    return total;
749}
750
751template <class Impl>
752void
753FullO3CPU<Impl>::activateContext(ThreadID tid, Cycles delay)
754{
755    // Needs to set each stage to running as well.
756    if (delay){
757        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
758                "on cycle %d\n", tid, clockEdge(delay));
759        scheduleActivateThreadEvent(tid, delay);
760    } else {
761        activateThread(tid);
762    }
763
764    // If we are time 0 or if the last activation time is in the past,
765    // schedule the next tick and wake up the fetch unit
766    if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
767        scheduleTickEvent(delay);
768
769        // Be sure to signal that there's some activity so the CPU doesn't
770        // deschedule itself.
771        activityRec.activity();
772        fetch.wakeFromQuiesce();
773
774        Cycles cycles(curCycle() - lastRunningCycle);
775        // @todo: This is an oddity that is only here to match the stats
776        if (cycles != 0)
777            --cycles;
778        quiesceCycles += cycles;
779
780        lastActivatedCycle = curTick();
781
782        _status = Running;
783    }
784}
785
786template <class Impl>
787bool
788FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove,
789                                           Cycles delay)
790{
791    // Schedule removal of thread data from CPU
792    if (delay){
793        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
794                "on tick %d\n", tid, clockEdge(delay));
795        scheduleDeallocateContextEvent(tid, remove, delay);
796        return false;
797    } else {
798        deactivateThread(tid);
799        if (remove)
800            removeThread(tid);
801        return true;
802    }
803}
804
805template <class Impl>
806void
807FullO3CPU<Impl>::suspendContext(ThreadID tid)
808{
809    DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
810    bool deallocated = scheduleDeallocateContext(tid, false, Cycles(1));
811    // If this was the last thread then unschedule the tick event.
812    if ((activeThreads.size() == 1 && !deallocated) ||
813        activeThreads.size() == 0)
814        unscheduleTickEvent();
815
816    DPRINTF(Quiesce, "Suspending Context\n");
817    lastRunningCycle = curCycle();
818    _status = Idle;
819}
820
821template <class Impl>
822void
823FullO3CPU<Impl>::haltContext(ThreadID tid)
824{
825    //For now, this is the same as deallocate
826    DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
827    scheduleDeallocateContext(tid, true, Cycles(1));
828}
829
830template <class Impl>
831void
832FullO3CPU<Impl>::insertThread(ThreadID tid)
833{
834    DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
835    // Will change now that the PC and thread state is internal to the CPU
836    // and not in the ThreadContext.
837    ThreadContext *src_tc;
838    if (FullSystem)
839        src_tc = system->threadContexts[tid];
840    else
841        src_tc = tcBase(tid);
842
843    //Bind Int Regs to Rename Map
844    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
845        PhysRegIndex phys_reg = freeList.getIntReg();
846
847        renameMap[tid].setEntry(ireg,phys_reg);
848        scoreboard.setReg(phys_reg);
849    }
850
851    //Bind Float Regs to Rename Map
852    for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
853        PhysRegIndex phys_reg = freeList.getFloatReg();
854
855        renameMap[tid].setEntry(freg,phys_reg);
856        scoreboard.setReg(phys_reg);
857    }
858
859    //Copy Thread Data Into RegFile
860    //this->copyFromTC(tid);
861
862    //Set PC/NPC/NNPC
863    pcState(src_tc->pcState(), tid);
864
865    src_tc->setStatus(ThreadContext::Active);
866
867    activateContext(tid, Cycles(1));
868
869    //Reset ROB/IQ/LSQ Entries
870    commit.rob->resetEntries();
871    iew.resetEntries();
872}
873
874template <class Impl>
875void
876FullO3CPU<Impl>::removeThread(ThreadID tid)
877{
878    DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
879
880    // Copy Thread Data From RegFile
881    // If thread is suspended, it might be re-allocated
882    // this->copyToTC(tid);
883
884
885    // @todo: 2-27-2008: Fix how we free up rename mappings
886    // here to alleviate the case for double-freeing registers
887    // in SMT workloads.
888
889    // Unbind Int Regs from Rename Map
890    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
891        PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
892
893        scoreboard.unsetReg(phys_reg);
894        freeList.addReg(phys_reg);
895    }
896
897    // Unbind Float Regs from Rename Map
898    for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
899        PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
900
901        scoreboard.unsetReg(phys_reg);
902        freeList.addReg(phys_reg);
903    }
904
905    // Squash Throughout Pipeline
906    DynInstPtr inst = commit.rob->readHeadInst(tid);
907    InstSeqNum squash_seq_num = inst->seqNum;
908    fetch.squash(0, squash_seq_num, inst, tid);
909    decode.squash(tid);
910    rename.squash(squash_seq_num, tid);
911    iew.squash(tid);
912    iew.ldstQueue.squash(squash_seq_num, tid);
913    commit.rob->squash(squash_seq_num, tid);
914
915
916    assert(iew.instQueue.getCount(tid) == 0);
917    assert(iew.ldstQueue.getCount(tid) == 0);
918
919    // Reset ROB/IQ/LSQ Entries
920
921    // Commented out for now.  This should be possible to do by
922    // telling all the pipeline stages to drain first, and then
923    // checking until the drain completes.  Once the pipeline is
924    // drained, call resetEntries(). - 10-09-06 ktlim
925/*
926    if (activeThreads.size() >= 1) {
927        commit.rob->resetEntries();
928        iew.resetEntries();
929    }
930*/
931}
932
933
934template <class Impl>
935void
936FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
937{
938    DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
939            "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
940            tid);
941
942    bool ready = true;
943
944    if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
945        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
946                "Phys. Int. Regs.\n",
947                tid);
948        ready = false;
949    } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
950        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
951                "Phys. Float. Regs.\n",
952                tid);
953        ready = false;
954    } else if (commit.rob->numFreeEntries() >=
955               commit.rob->entryAmount(activeThreads.size() + 1)) {
956        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
957                "ROB entries.\n",
958                tid);
959        ready = false;
960    } else if (iew.instQueue.numFreeEntries() >=
961               iew.instQueue.entryAmount(activeThreads.size() + 1)) {
962        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
963                "IQ entries.\n",
964                tid);
965        ready = false;
966    } else if (iew.ldstQueue.numFreeEntries() >=
967               iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
968        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
969                "LSQ entries.\n",
970                tid);
971        ready = false;
972    }
973
974    if (ready) {
975        insertThread(tid);
976
977        contextSwitch = false;
978
979        cpuWaitList.remove(tid);
980    } else {
981        suspendContext(tid);
982
983        //blocks fetch
984        contextSwitch = true;
985
986        //@todo: dont always add to waitlist
987        //do waitlist
988        cpuWaitList.push_back(tid);
989    }
990}
991
992template <class Impl>
993Fault
994FullO3CPU<Impl>::hwrei(ThreadID tid)
995{
996#if THE_ISA == ALPHA_ISA
997    // Need to clear the lock flag upon returning from an interrupt.
998    this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
999
1000    this->thread[tid]->kernelStats->hwrei();
1001
1002    // FIXME: XXX check for interrupts? XXX
1003#endif
1004    return NoFault;
1005}
1006
1007template <class Impl>
1008bool
1009FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
1010{
1011#if THE_ISA == ALPHA_ISA
1012    if (this->thread[tid]->kernelStats)
1013        this->thread[tid]->kernelStats->callpal(palFunc,
1014                                                this->threadContexts[tid]);
1015
1016    switch (palFunc) {
1017      case PAL::halt:
1018        halt();
1019        if (--System::numSystemsRunning == 0)
1020            exitSimLoop("all cpus halted");
1021        break;
1022
1023      case PAL::bpt:
1024      case PAL::bugchk:
1025        if (this->system->breakpoint())
1026            return false;
1027        break;
1028    }
1029#endif
1030    return true;
1031}
1032
1033template <class Impl>
1034Fault
1035FullO3CPU<Impl>::getInterrupts()
1036{
1037    // Check if there are any outstanding interrupts
1038    return this->interrupts->getInterrupt(this->threadContexts[0]);
1039}
1040
1041template <class Impl>
1042void
1043FullO3CPU<Impl>::processInterrupts(Fault interrupt)
1044{
1045    // Check for interrupts here.  For now can copy the code that
1046    // exists within isa_fullsys_traits.hh.  Also assume that thread 0
1047    // is the one that handles the interrupts.
1048    // @todo: Possibly consolidate the interrupt checking code.
1049    // @todo: Allow other threads to handle interrupts.
1050
1051    assert(interrupt != NoFault);
1052    this->interrupts->updateIntrInfo(this->threadContexts[0]);
1053
1054    DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
1055    this->trap(interrupt, 0, NULL);
1056}
1057
1058template <class Impl>
1059void
1060FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
1061{
1062    // Pass the thread's TC into the invoke method.
1063    fault->invoke(this->threadContexts[tid], inst);
1064}
1065
1066template <class Impl>
1067void
1068FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
1069{
1070    DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1071
1072    DPRINTF(Activity,"Activity: syscall() called.\n");
1073
1074    // Temporarily increase this by one to account for the syscall
1075    // instruction.
1076    ++(this->thread[tid]->funcExeInst);
1077
1078    // Execute the actual syscall.
1079    this->thread[tid]->syscall(callnum);
1080
1081    // Decrease funcExeInst by one as the normal commit will handle
1082    // incrementing it.
1083    --(this->thread[tid]->funcExeInst);
1084}
1085
1086template <class Impl>
1087void
1088FullO3CPU<Impl>::serialize(std::ostream &os)
1089{
1090    Drainable::State so_state(getDrainState());
1091    SERIALIZE_ENUM(so_state);
1092    BaseCPU::serialize(os);
1093    nameOut(os, csprintf("%s.tickEvent", name()));
1094    tickEvent.serialize(os);
1095
1096    for (ThreadID i = 0; i < thread.size(); i++) {
1097        nameOut(os, csprintf("%s.xc.%i", name(), i));
1098        thread[i]->serialize(os);
1099    }
1100}
1101
1102template <class Impl>
1103void
1104FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
1105{
1106    Drainable::State so_state;
1107    UNSERIALIZE_ENUM(so_state);
1108    BaseCPU::unserialize(cp, section);
1109    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1110
1111    for (ThreadID i = 0; i < thread.size(); i++) {
1112        thread[i]->unserialize(cp,
1113                               csprintf("%s.xc.%i", section, i));
1114        if (thread[i]->status() == ThreadContext::Active)
1115            activateThread(i);
1116    }
1117}
1118
1119template <class Impl>
1120unsigned int
1121FullO3CPU<Impl>::drain(DrainManager *drain_manager)
1122{
1123    DPRINTF(O3CPU, "Switching out\n");
1124
1125    // If the CPU isn't doing anything, then return immediately.
1126    if (_status == SwitchedOut)
1127        return 0;
1128
1129    drainCount = 0;
1130    fetch.drain();
1131    decode.drain();
1132    rename.drain();
1133    iew.drain();
1134    commit.drain();
1135
1136    // Wake the CPU and record activity so everything can drain out if
1137    // the CPU was not able to immediately drain.
1138    if (getDrainState() != Drainable::Drained) {
1139        // A bit of a hack...set the drainManager after all the drain()
1140        // calls have been made, that way if all of the stages drain
1141        // immediately, the signalDrained() function knows not to call
1142        // process on the drain event.
1143        drainManager = drain_manager;
1144
1145        wakeCPU();
1146        activityRec.activity();
1147
1148        DPRINTF(Drain, "CPU not drained\n");
1149
1150        return 1;
1151    } else {
1152        return 0;
1153    }
1154}
1155
1156template <class Impl>
1157void
1158FullO3CPU<Impl>::drainResume()
1159{
1160    fetch.resume();
1161    decode.resume();
1162    rename.resume();
1163    iew.resume();
1164    commit.resume();
1165
1166    setDrainState(Drainable::Running);
1167
1168    if (_status == SwitchedOut)
1169        return;
1170
1171    if (system->getMemoryMode() != Enums::timing) {
1172        fatal("The O3 CPU requires the memory system to be in "
1173              "'timing' mode.\n");
1174    }
1175
1176    if (!tickEvent.scheduled())
1177        schedule(tickEvent, nextCycle());
1178    _status = Running;
1179}
1180
1181template <class Impl>
1182void
1183FullO3CPU<Impl>::signalDrained()
1184{
1185    if (++drainCount == NumStages) {
1186        if (tickEvent.scheduled())
1187            tickEvent.squash();
1188
1189        setDrainState(Drainable::Drained);
1190
1191        if (drainManager) {
1192            DPRINTF(Drain, "CPU done draining, processing drain event\n");
1193            drainManager->signalDrainDone();
1194            drainManager = NULL;
1195        }
1196    }
1197    assert(drainCount <= 5);
1198}
1199
1200template <class Impl>
1201void
1202FullO3CPU<Impl>::switchOut()
1203{
1204    BaseCPU::switchOut();
1205
1206    fetch.switchOut();
1207    rename.switchOut();
1208    iew.switchOut();
1209    commit.switchOut();
1210    instList.clear();
1211    while (!removeList.empty()) {
1212        removeList.pop();
1213    }
1214
1215    _status = SwitchedOut;
1216
1217    if (checker)
1218        checker->switchOut();
1219
1220    if (tickEvent.scheduled())
1221        tickEvent.squash();
1222}
1223
1224template <class Impl>
1225void
1226FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1227{
1228    // Flush out any old data from the time buffers.
1229    for (int i = 0; i < timeBuffer.getSize(); ++i) {
1230        timeBuffer.advance();
1231        fetchQueue.advance();
1232        decodeQueue.advance();
1233        renameQueue.advance();
1234        iewQueue.advance();
1235    }
1236
1237    activityRec.reset();
1238
1239    BaseCPU::takeOverFrom(oldCPU);
1240
1241    fetch.takeOverFrom();
1242    decode.takeOverFrom();
1243    rename.takeOverFrom();
1244    iew.takeOverFrom();
1245    commit.takeOverFrom();
1246
1247    assert(!tickEvent.scheduled() || tickEvent.squashed());
1248
1249    FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1250    if (oldO3CPU)
1251        globalSeqNum = oldO3CPU->globalSeqNum;
1252
1253    // @todo: Figure out how to properly select the tid to put onto
1254    // the active threads list.
1255    ThreadID tid = 0;
1256
1257    list<ThreadID>::iterator isActive =
1258        std::find(activeThreads.begin(), activeThreads.end(), tid);
1259
1260    if (isActive == activeThreads.end()) {
1261        //May Need to Re-code this if the delay variable is the delay
1262        //needed for thread to activate
1263        DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1264                tid);
1265
1266        activeThreads.push_back(tid);
1267    }
1268
1269    // Set all statuses to active, schedule the CPU's tick event.
1270    // @todo: Fix up statuses so this is handled properly
1271    ThreadID size = threadContexts.size();
1272    for (ThreadID i = 0; i < size; ++i) {
1273        ThreadContext *tc = threadContexts[i];
1274        if (tc->status() == ThreadContext::Active && _status != Running) {
1275            _status = Running;
1276            reschedule(tickEvent, nextCycle(), true);
1277        }
1278    }
1279    if (!tickEvent.scheduled())
1280        schedule(tickEvent, nextCycle());
1281
1282    lastRunningCycle = curCycle();
1283}
1284
1285template <class Impl>
1286TheISA::MiscReg
1287FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1288{
1289    return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1290}
1291
1292template <class Impl>
1293TheISA::MiscReg
1294FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1295{
1296    miscRegfileReads++;
1297    return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1298}
1299
1300template <class Impl>
1301void
1302FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1303        const TheISA::MiscReg &val, ThreadID tid)
1304{
1305    this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1306}
1307
1308template <class Impl>
1309void
1310FullO3CPU<Impl>::setMiscReg(int misc_reg,
1311        const TheISA::MiscReg &val, ThreadID tid)
1312{
1313    miscRegfileWrites++;
1314    this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1315}
1316
1317template <class Impl>
1318uint64_t
1319FullO3CPU<Impl>::readIntReg(int reg_idx)
1320{
1321    intRegfileReads++;
1322    return regFile.readIntReg(reg_idx);
1323}
1324
1325template <class Impl>
1326FloatReg
1327FullO3CPU<Impl>::readFloatReg(int reg_idx)
1328{
1329    fpRegfileReads++;
1330    return regFile.readFloatReg(reg_idx);
1331}
1332
1333template <class Impl>
1334FloatRegBits
1335FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1336{
1337    fpRegfileReads++;
1338    return regFile.readFloatRegBits(reg_idx);
1339}
1340
1341template <class Impl>
1342void
1343FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1344{
1345    intRegfileWrites++;
1346    regFile.setIntReg(reg_idx, val);
1347}
1348
1349template <class Impl>
1350void
1351FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1352{
1353    fpRegfileWrites++;
1354    regFile.setFloatReg(reg_idx, val);
1355}
1356
1357template <class Impl>
1358void
1359FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1360{
1361    fpRegfileWrites++;
1362    regFile.setFloatRegBits(reg_idx, val);
1363}
1364
1365template <class Impl>
1366uint64_t
1367FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1368{
1369    intRegfileReads++;
1370    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1371
1372    return regFile.readIntReg(phys_reg);
1373}
1374
1375template <class Impl>
1376float
1377FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1378{
1379    fpRegfileReads++;
1380    int idx = reg_idx + TheISA::NumIntRegs;
1381    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1382
1383    return regFile.readFloatReg(phys_reg);
1384}
1385
1386template <class Impl>
1387uint64_t
1388FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1389{
1390    fpRegfileReads++;
1391    int idx = reg_idx + TheISA::NumIntRegs;
1392    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1393
1394    return regFile.readFloatRegBits(phys_reg);
1395}
1396
1397template <class Impl>
1398void
1399FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1400{
1401    intRegfileWrites++;
1402    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1403
1404    regFile.setIntReg(phys_reg, val);
1405}
1406
1407template <class Impl>
1408void
1409FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1410{
1411    fpRegfileWrites++;
1412    int idx = reg_idx + TheISA::NumIntRegs;
1413    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1414
1415    regFile.setFloatReg(phys_reg, val);
1416}
1417
1418template <class Impl>
1419void
1420FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1421{
1422    fpRegfileWrites++;
1423    int idx = reg_idx + TheISA::NumIntRegs;
1424    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1425
1426    regFile.setFloatRegBits(phys_reg, val);
1427}
1428
1429template <class Impl>
1430TheISA::PCState
1431FullO3CPU<Impl>::pcState(ThreadID tid)
1432{
1433    return commit.pcState(tid);
1434}
1435
1436template <class Impl>
1437void
1438FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1439{
1440    commit.pcState(val, tid);
1441}
1442
1443template <class Impl>
1444Addr
1445FullO3CPU<Impl>::instAddr(ThreadID tid)
1446{
1447    return commit.instAddr(tid);
1448}
1449
1450template <class Impl>
1451Addr
1452FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1453{
1454    return commit.nextInstAddr(tid);
1455}
1456
1457template <class Impl>
1458MicroPC
1459FullO3CPU<Impl>::microPC(ThreadID tid)
1460{
1461    return commit.microPC(tid);
1462}
1463
1464template <class Impl>
1465void
1466FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1467{
1468    this->thread[tid]->noSquashFromTC = true;
1469    this->commit.generateTCEvent(tid);
1470}
1471
1472template <class Impl>
1473typename FullO3CPU<Impl>::ListIt
1474FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1475{
1476    instList.push_back(inst);
1477
1478    return --(instList.end());
1479}
1480
1481template <class Impl>
1482void
1483FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1484{
1485    // Keep an instruction count.
1486    if (!inst->isMicroop() || inst->isLastMicroop()) {
1487        thread[tid]->numInst++;
1488        thread[tid]->numInsts++;
1489        committedInsts[tid]++;
1490        totalCommittedInsts++;
1491    }
1492    thread[tid]->numOp++;
1493    thread[tid]->numOps++;
1494    committedOps[tid]++;
1495
1496    system->totalNumInsts++;
1497    // Check for instruction-count-based events.
1498    comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1499    system->instEventQueue.serviceEvents(system->totalNumInsts);
1500}
1501
1502template <class Impl>
1503void
1504FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1505{
1506    DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1507            "[sn:%lli]\n",
1508            inst->threadNumber, inst->pcState(), inst->seqNum);
1509
1510    removeInstsThisCycle = true;
1511
1512    // Remove the front instruction.
1513    removeList.push(inst->getInstListIt());
1514}
1515
1516template <class Impl>
1517void
1518FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1519{
1520    DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1521            " list.\n", tid);
1522
1523    ListIt end_it;
1524
1525    bool rob_empty = false;
1526
1527    if (instList.empty()) {
1528        return;
1529    } else if (rob.isEmpty(/*tid*/)) {
1530        DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1531        end_it = instList.begin();
1532        rob_empty = true;
1533    } else {
1534        end_it = (rob.readTailInst(tid))->getInstListIt();
1535        DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1536    }
1537
1538    removeInstsThisCycle = true;
1539
1540    ListIt inst_it = instList.end();
1541
1542    inst_it--;
1543
1544    // Walk through the instruction list, removing any instructions
1545    // that were inserted after the given instruction iterator, end_it.
1546    while (inst_it != end_it) {
1547        assert(!instList.empty());
1548
1549        squashInstIt(inst_it, tid);
1550
1551        inst_it--;
1552    }
1553
1554    // If the ROB was empty, then we actually need to remove the first
1555    // instruction as well.
1556    if (rob_empty) {
1557        squashInstIt(inst_it, tid);
1558    }
1559}
1560
1561template <class Impl>
1562void
1563FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1564{
1565    assert(!instList.empty());
1566
1567    removeInstsThisCycle = true;
1568
1569    ListIt inst_iter = instList.end();
1570
1571    inst_iter--;
1572
1573    DPRINTF(O3CPU, "Deleting instructions from instruction "
1574            "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1575            tid, seq_num, (*inst_iter)->seqNum);
1576
1577    while ((*inst_iter)->seqNum > seq_num) {
1578
1579        bool break_loop = (inst_iter == instList.begin());
1580
1581        squashInstIt(inst_iter, tid);
1582
1583        inst_iter--;
1584
1585        if (break_loop)
1586            break;
1587    }
1588}
1589
1590template <class Impl>
1591inline void
1592FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1593{
1594    if ((*instIt)->threadNumber == tid) {
1595        DPRINTF(O3CPU, "Squashing instruction, "
1596                "[tid:%i] [sn:%lli] PC %s\n",
1597                (*instIt)->threadNumber,
1598                (*instIt)->seqNum,
1599                (*instIt)->pcState());
1600
1601        // Mark it as squashed.
1602        (*instIt)->setSquashed();
1603
1604        // @todo: Formulate a consistent method for deleting
1605        // instructions from the instruction list
1606        // Remove the instruction from the list.
1607        removeList.push(instIt);
1608    }
1609}
1610
1611template <class Impl>
1612void
1613FullO3CPU<Impl>::cleanUpRemovedInsts()
1614{
1615    while (!removeList.empty()) {
1616        DPRINTF(O3CPU, "Removing instruction, "
1617                "[tid:%i] [sn:%lli] PC %s\n",
1618                (*removeList.front())->threadNumber,
1619                (*removeList.front())->seqNum,
1620                (*removeList.front())->pcState());
1621
1622        instList.erase(removeList.front());
1623
1624        removeList.pop();
1625    }
1626
1627    removeInstsThisCycle = false;
1628}
1629/*
1630template <class Impl>
1631void
1632FullO3CPU<Impl>::removeAllInsts()
1633{
1634    instList.clear();
1635}
1636*/
1637template <class Impl>
1638void
1639FullO3CPU<Impl>::dumpInsts()
1640{
1641    int num = 0;
1642
1643    ListIt inst_list_it = instList.begin();
1644
1645    cprintf("Dumping Instruction List\n");
1646
1647    while (inst_list_it != instList.end()) {
1648        cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1649                "Squashed:%i\n\n",
1650                num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1651                (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1652                (*inst_list_it)->isSquashed());
1653        inst_list_it++;
1654        ++num;
1655    }
1656}
1657/*
1658template <class Impl>
1659void
1660FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1661{
1662    iew.wakeDependents(inst);
1663}
1664*/
1665template <class Impl>
1666void
1667FullO3CPU<Impl>::wakeCPU()
1668{
1669    if (activityRec.active() || tickEvent.scheduled()) {
1670        DPRINTF(Activity, "CPU already running.\n");
1671        return;
1672    }
1673
1674    DPRINTF(Activity, "Waking up CPU\n");
1675
1676    Cycles cycles(curCycle() - lastRunningCycle);
1677    // @todo: This is an oddity that is only here to match the stats
1678    if (cycles != 0)
1679        --cycles;
1680    idleCycles += cycles;
1681    numCycles += cycles;
1682
1683    schedule(tickEvent, nextCycle());
1684}
1685
1686template <class Impl>
1687void
1688FullO3CPU<Impl>::wakeup()
1689{
1690    if (this->thread[0]->status() != ThreadContext::Suspended)
1691        return;
1692
1693    this->wakeCPU();
1694
1695    DPRINTF(Quiesce, "Suspended Processor woken\n");
1696    this->threadContexts[0]->activate();
1697}
1698
1699template <class Impl>
1700ThreadID
1701FullO3CPU<Impl>::getFreeTid()
1702{
1703    for (ThreadID tid = 0; tid < numThreads; tid++) {
1704        if (!tids[tid]) {
1705            tids[tid] = true;
1706            return tid;
1707        }
1708    }
1709
1710    return InvalidThreadID;
1711}
1712
1713template <class Impl>
1714void
1715FullO3CPU<Impl>::doContextSwitch()
1716{
1717    if (contextSwitch) {
1718
1719        //ADD CODE TO DEACTIVE THREAD HERE (???)
1720
1721        ThreadID size = cpuWaitList.size();
1722        for (ThreadID tid = 0; tid < size; tid++) {
1723            activateWhenReady(tid);
1724        }
1725
1726        if (cpuWaitList.size() == 0)
1727            contextSwitch = true;
1728    }
1729}
1730
1731template <class Impl>
1732void
1733FullO3CPU<Impl>::updateThreadPriority()
1734{
1735    if (activeThreads.size() > 1) {
1736        //DEFAULT TO ROUND ROBIN SCHEME
1737        //e.g. Move highest priority to end of thread list
1738        list<ThreadID>::iterator list_begin = activeThreads.begin();
1739
1740        unsigned high_thread = *list_begin;
1741
1742        activeThreads.erase(list_begin);
1743
1744        activeThreads.push_back(high_thread);
1745    }
1746}
1747
1748// Forward declaration of FullO3CPU.
1749template class FullO3CPU<O3CPUImpl>;
1750