cpu.cc revision 8809:bb10807da889 
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Korey Sewell
43 *          Rick Strong
44 */
45
46#include "arch/kernel_stats.hh"
47#include "config/the_isa.hh"
48#include "config/use_checker.hh"
49#include "cpu/o3/cpu.hh"
50#include "cpu/o3/isa_specific.hh"
51#include "cpu/o3/thread_context.hh"
52#include "cpu/activity.hh"
53#include "cpu/quiesce_event.hh"
54#include "cpu/simple_thread.hh"
55#include "cpu/thread_context.hh"
56#include "debug/Activity.hh"
57#include "debug/O3CPU.hh"
58#include "debug/Quiesce.hh"
59#include "enums/MemoryMode.hh"
60#include "sim/core.hh"
61#include "sim/full_system.hh"
62#include "sim/process.hh"
63#include "sim/stat_control.hh"
64#include "sim/system.hh"
65
66#if USE_CHECKER
67#include "cpu/checker/cpu.hh"
68#include "cpu/checker/thread_context.hh"
69#endif
70
71#if THE_ISA == ALPHA_ISA
72#include "arch/alpha/osfpal.hh"
73#include "debug/Activity.hh"
74#endif
75
76struct BaseCPUParams;
77
78using namespace TheISA;
79using namespace std;
80
81BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
82    : BaseCPU(params)
83{
84}
85
86void
87BaseO3CPU::regStats()
88{
89    BaseCPU::regStats();
90}
91
92template<class Impl>
93bool
94FullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt)
95{
96    DPRINTF(O3CPU, "Fetch unit received timing\n");
97    if (pkt->isResponse()) {
98        // We shouldn't ever get a block in ownership state
99        assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
100
101        fetch->processCacheCompletion(pkt);
102    }
103    //else Snooped a coherence request, just return
104    return true;
105}
106
107template<class Impl>
108void
109FullO3CPU<Impl>::IcachePort::recvRetry()
110{
111    fetch->recvRetry();
112}
113
114template <class Impl>
115bool
116FullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt)
117{
118    return lsq->recvTiming(pkt);
119}
120
121template <class Impl>
122void
123FullO3CPU<Impl>::DcachePort::recvRetry()
124{
125    lsq->recvRetry();
126}
127
128template <class Impl>
129FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
130    : Event(CPU_Tick_Pri), cpu(c)
131{
132}
133
134template <class Impl>
135void
136FullO3CPU<Impl>::TickEvent::process()
137{
138    cpu->tick();
139}
140
141template <class Impl>
142const char *
143FullO3CPU<Impl>::TickEvent::description() const
144{
145    return "FullO3CPU tick";
146}
147
148template <class Impl>
149FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
150    : Event(CPU_Switch_Pri)
151{
152}
153
154template <class Impl>
155void
156FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
157                                           FullO3CPU<Impl> *thread_cpu)
158{
159    tid = thread_num;
160    cpu = thread_cpu;
161}
162
163template <class Impl>
164void
165FullO3CPU<Impl>::ActivateThreadEvent::process()
166{
167    cpu->activateThread(tid);
168}
169
170template <class Impl>
171const char *
172FullO3CPU<Impl>::ActivateThreadEvent::description() const
173{
174    return "FullO3CPU \"Activate Thread\"";
175}
176
177template <class Impl>
178FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
179    : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
180{
181}
182
183template <class Impl>
184void
185FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
186                                              FullO3CPU<Impl> *thread_cpu)
187{
188    tid = thread_num;
189    cpu = thread_cpu;
190    remove = false;
191}
192
193template <class Impl>
194void
195FullO3CPU<Impl>::DeallocateContextEvent::process()
196{
197    cpu->deactivateThread(tid);
198    if (remove)
199        cpu->removeThread(tid);
200}
201
202template <class Impl>
203const char *
204FullO3CPU<Impl>::DeallocateContextEvent::description() const
205{
206    return "FullO3CPU \"Deallocate Context\"";
207}
208
209template <class Impl>
210FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
211    : BaseO3CPU(params),
212      itb(params->itb),
213      dtb(params->dtb),
214      tickEvent(this),
215#ifndef NDEBUG
216      instcount(0),
217#endif
218      removeInstsThisCycle(false),
219      fetch(this, params),
220      decode(this, params),
221      rename(this, params),
222      iew(this, params),
223      commit(this, params),
224
225      regFile(this, params->numPhysIntRegs,
226              params->numPhysFloatRegs),
227
228      freeList(params->numThreads,
229               TheISA::NumIntRegs, params->numPhysIntRegs,
230               TheISA::NumFloatRegs, params->numPhysFloatRegs),
231
232      rob(this,
233          params->numROBEntries, params->squashWidth,
234          params->smtROBPolicy, params->smtROBThreshold,
235          params->numThreads),
236
237      scoreboard(params->numThreads,
238                 TheISA::NumIntRegs, params->numPhysIntRegs,
239                 TheISA::NumFloatRegs, params->numPhysFloatRegs,
240                 TheISA::NumMiscRegs * numThreads,
241                 TheISA::ZeroReg),
242
243      icachePort(&fetch, this),
244      dcachePort(&iew.ldstQueue, this),
245
246      timeBuffer(params->backComSize, params->forwardComSize),
247      fetchQueue(params->backComSize, params->forwardComSize),
248      decodeQueue(params->backComSize, params->forwardComSize),
249      renameQueue(params->backComSize, params->forwardComSize),
250      iewQueue(params->backComSize, params->forwardComSize),
251      activityRec(name(), NumStages,
252                  params->backComSize + params->forwardComSize,
253                  params->activity),
254
255      globalSeqNum(1),
256      system(params->system),
257      drainCount(0),
258      deferRegistration(params->defer_registration)
259{
260    if (!deferRegistration) {
261        _status = Running;
262    } else {
263        _status = Idle;
264    }
265
266#if USE_CHECKER
267    if (params->checker) {
268        BaseCPU *temp_checker = params->checker;
269        checker = dynamic_cast<Checker<Impl> *>(temp_checker);
270        checker->setIcachePort(&icachePort);
271        checker->setSystem(params->system);
272    } else {
273        checker = NULL;
274    }
275#endif // USE_CHECKER
276
277    if (!FullSystem) {
278        thread.resize(numThreads);
279        tids.resize(numThreads);
280    }
281
282    // The stages also need their CPU pointer setup.  However this
283    // must be done at the upper level CPU because they have pointers
284    // to the upper level CPU, and not this FullO3CPU.
285
286    // Set up Pointers to the activeThreads list for each stage
287    fetch.setActiveThreads(&activeThreads);
288    decode.setActiveThreads(&activeThreads);
289    rename.setActiveThreads(&activeThreads);
290    iew.setActiveThreads(&activeThreads);
291    commit.setActiveThreads(&activeThreads);
292
293    // Give each of the stages the time buffer they will use.
294    fetch.setTimeBuffer(&timeBuffer);
295    decode.setTimeBuffer(&timeBuffer);
296    rename.setTimeBuffer(&timeBuffer);
297    iew.setTimeBuffer(&timeBuffer);
298    commit.setTimeBuffer(&timeBuffer);
299
300    // Also setup each of the stages' queues.
301    fetch.setFetchQueue(&fetchQueue);
302    decode.setFetchQueue(&fetchQueue);
303    commit.setFetchQueue(&fetchQueue);
304    decode.setDecodeQueue(&decodeQueue);
305    rename.setDecodeQueue(&decodeQueue);
306    rename.setRenameQueue(&renameQueue);
307    iew.setRenameQueue(&renameQueue);
308    iew.setIEWQueue(&iewQueue);
309    commit.setIEWQueue(&iewQueue);
310    commit.setRenameQueue(&renameQueue);
311
312    commit.setIEWStage(&iew);
313    rename.setIEWStage(&iew);
314    rename.setCommitStage(&commit);
315
316    ThreadID active_threads;
317    if (FullSystem) {
318        active_threads = 1;
319    } else {
320        active_threads = params->workload.size();
321
322        if (active_threads > Impl::MaxThreads) {
323            panic("Workload Size too large. Increase the 'MaxThreads' "
324                  "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
325                  "or edit your workload size.");
326        }
327    }
328
329    //Make Sure That this a Valid Architeture
330    assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
331    assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
332
333    rename.setScoreboard(&scoreboard);
334    iew.setScoreboard(&scoreboard);
335
336    // Setup the rename map for whichever stages need it.
337    PhysRegIndex lreg_idx = 0;
338    PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
339
340    for (ThreadID tid = 0; tid < numThreads; tid++) {
341        bool bindRegs = (tid <= active_threads - 1);
342
343        commitRenameMap[tid].init(TheISA::NumIntRegs,
344                                  params->numPhysIntRegs,
345                                  lreg_idx,            //Index for Logical. Regs
346
347                                  TheISA::NumFloatRegs,
348                                  params->numPhysFloatRegs,
349                                  freg_idx,            //Index for Float Regs
350
351                                  TheISA::NumMiscRegs,
352
353                                  TheISA::ZeroReg,
354                                  TheISA::ZeroReg,
355
356                                  tid,
357                                  false);
358
359        renameMap[tid].init(TheISA::NumIntRegs,
360                            params->numPhysIntRegs,
361                            lreg_idx,                  //Index for Logical. Regs
362
363                            TheISA::NumFloatRegs,
364                            params->numPhysFloatRegs,
365                            freg_idx,                  //Index for Float Regs
366
367                            TheISA::NumMiscRegs,
368
369                            TheISA::ZeroReg,
370                            TheISA::ZeroReg,
371
372                            tid,
373                            bindRegs);
374
375        activateThreadEvent[tid].init(tid, this);
376        deallocateContextEvent[tid].init(tid, this);
377    }
378
379    rename.setRenameMap(renameMap);
380    commit.setRenameMap(commitRenameMap);
381
382    // Give renameMap & rename stage access to the freeList;
383    for (ThreadID tid = 0; tid < numThreads; tid++)
384        renameMap[tid].setFreeList(&freeList);
385    rename.setFreeList(&freeList);
386
387    // Setup the ROB for whichever stages need it.
388    commit.setROB(&rob);
389
390    lastRunningCycle = curTick();
391
392    lastActivatedCycle = -1;
393#if 0
394    // Give renameMap & rename stage access to the freeList;
395    for (ThreadID tid = 0; tid < numThreads; tid++)
396        globalSeqNum[tid] = 1;
397#endif
398
399    contextSwitch = false;
400    DPRINTF(O3CPU, "Creating O3CPU object.\n");
401
402    // Setup any thread state.
403    this->thread.resize(this->numThreads);
404
405    for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
406        if (FullSystem) {
407            // SMT is not supported in FS mode yet.
408            assert(this->numThreads == 1);
409            this->thread[tid] = new Thread(this, 0, NULL);
410        } else {
411            if (tid < params->workload.size()) {
412                DPRINTF(O3CPU, "Workload[%i] process is %#x",
413                        tid, this->thread[tid]);
414                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
415                        (typename Impl::O3CPU *)(this),
416                        tid, params->workload[tid]);
417
418                //usedTids[tid] = true;
419                //threadMap[tid] = tid;
420            } else {
421                //Allocate Empty thread so M5 can use later
422                //when scheduling threads to CPU
423                Process* dummy_proc = NULL;
424
425                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
426                        (typename Impl::O3CPU *)(this),
427                        tid, dummy_proc);
428                //usedTids[tid] = false;
429            }
430        }
431
432        ThreadContext *tc;
433
434        // Setup the TC that will serve as the interface to the threads/CPU.
435        O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
436
437        tc = o3_tc;
438
439        // If we're using a checker, then the TC should be the
440        // CheckerThreadContext.
441#if USE_CHECKER
442        if (params->checker) {
443            tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
444                o3_tc, this->checker);
445        }
446#endif
447
448        o3_tc->cpu = (typename Impl::O3CPU *)(this);
449        assert(o3_tc->cpu);
450        o3_tc->thread = this->thread[tid];
451
452        if (FullSystem) {
453            // Setup quiesce event.
454            this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
455        }
456        // Give the thread the TC.
457        this->thread[tid]->tc = tc;
458
459        // Add the TC to the CPU's list of TC's.
460        this->threadContexts.push_back(tc);
461    }
462
463    for (ThreadID tid = 0; tid < this->numThreads; tid++)
464        this->thread[tid]->setFuncExeInst(0);
465
466    lockAddr = 0;
467    lockFlag = false;
468}
469
470template <class Impl>
471FullO3CPU<Impl>::~FullO3CPU()
472{
473}
474
475template <class Impl>
476void
477FullO3CPU<Impl>::regStats()
478{
479    BaseO3CPU::regStats();
480
481    // Register any of the O3CPU's stats here.
482    timesIdled
483        .name(name() + ".timesIdled")
484        .desc("Number of times that the entire CPU went into an idle state and"
485              " unscheduled itself")
486        .prereq(timesIdled);
487
488    idleCycles
489        .name(name() + ".idleCycles")
490        .desc("Total number of cycles that the CPU has spent unscheduled due "
491              "to idling")
492        .prereq(idleCycles);
493
494    quiesceCycles
495        .name(name() + ".quiesceCycles")
496        .desc("Total number of cycles that CPU has spent quiesced or waiting "
497              "for an interrupt")
498        .prereq(quiesceCycles);
499
500    // Number of Instructions simulated
501    // --------------------------------
502    // Should probably be in Base CPU but need templated
503    // MaxThreads so put in here instead
504    committedInsts
505        .init(numThreads)
506        .name(name() + ".committedInsts")
507        .desc("Number of Instructions Simulated");
508
509    totalCommittedInsts
510        .name(name() + ".committedInsts_total")
511        .desc("Number of Instructions Simulated");
512
513    cpi
514        .name(name() + ".cpi")
515        .desc("CPI: Cycles Per Instruction")
516        .precision(6);
517    cpi = numCycles / committedInsts;
518
519    totalCpi
520        .name(name() + ".cpi_total")
521        .desc("CPI: Total CPI of All Threads")
522        .precision(6);
523    totalCpi = numCycles / totalCommittedInsts;
524
525    ipc
526        .name(name() + ".ipc")
527        .desc("IPC: Instructions Per Cycle")
528        .precision(6);
529    ipc =  committedInsts / numCycles;
530
531    totalIpc
532        .name(name() + ".ipc_total")
533        .desc("IPC: Total IPC of All Threads")
534        .precision(6);
535    totalIpc =  totalCommittedInsts / numCycles;
536
537    this->fetch.regStats();
538    this->decode.regStats();
539    this->rename.regStats();
540    this->iew.regStats();
541    this->commit.regStats();
542    this->rob.regStats();
543
544    intRegfileReads
545        .name(name() + ".int_regfile_reads")
546        .desc("number of integer regfile reads")
547        .prereq(intRegfileReads);
548
549    intRegfileWrites
550        .name(name() + ".int_regfile_writes")
551        .desc("number of integer regfile writes")
552        .prereq(intRegfileWrites);
553
554    fpRegfileReads
555        .name(name() + ".fp_regfile_reads")
556        .desc("number of floating regfile reads")
557        .prereq(fpRegfileReads);
558
559    fpRegfileWrites
560        .name(name() + ".fp_regfile_writes")
561        .desc("number of floating regfile writes")
562        .prereq(fpRegfileWrites);
563
564    miscRegfileReads
565        .name(name() + ".misc_regfile_reads")
566        .desc("number of misc regfile reads")
567        .prereq(miscRegfileReads);
568
569    miscRegfileWrites
570        .name(name() + ".misc_regfile_writes")
571        .desc("number of misc regfile writes")
572        .prereq(miscRegfileWrites);
573}
574
575template <class Impl>
576Port *
577FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
578{
579    if (if_name == "dcache_port")
580        return &dcachePort;
581    else if (if_name == "icache_port")
582        return &icachePort;
583    else
584        panic("No Such Port\n");
585}
586
587template <class Impl>
588void
589FullO3CPU<Impl>::tick()
590{
591    DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
592
593    ++numCycles;
594
595//    activity = false;
596
597    //Tick each of the stages
598    fetch.tick();
599
600    decode.tick();
601
602    rename.tick();
603
604    iew.tick();
605
606    commit.tick();
607
608    if (!FullSystem)
609        doContextSwitch();
610
611    // Now advance the time buffers
612    timeBuffer.advance();
613
614    fetchQueue.advance();
615    decodeQueue.advance();
616    renameQueue.advance();
617    iewQueue.advance();
618
619    activityRec.advance();
620
621    if (removeInstsThisCycle) {
622        cleanUpRemovedInsts();
623    }
624
625    if (!tickEvent.scheduled()) {
626        if (_status == SwitchedOut ||
627            getState() == SimObject::Drained) {
628            DPRINTF(O3CPU, "Switched out!\n");
629            // increment stat
630            lastRunningCycle = curTick();
631        } else if (!activityRec.active() || _status == Idle) {
632            DPRINTF(O3CPU, "Idle!\n");
633            lastRunningCycle = curTick();
634            timesIdled++;
635        } else {
636            schedule(tickEvent, nextCycle(curTick() + ticks(1)));
637            DPRINTF(O3CPU, "Scheduling next tick!\n");
638        }
639    }
640
641    if (!FullSystem)
642        updateThreadPriority();
643}
644
645template <class Impl>
646void
647FullO3CPU<Impl>::init()
648{
649    BaseCPU::init();
650
651    // Set inSyscall so that the CPU doesn't squash when initially
652    // setting up registers.
653    for (ThreadID tid = 0; tid < numThreads; ++tid)
654        thread[tid]->inSyscall = true;
655
656    // this CPU could still be unconnected if we are restoring from a
657    // checkpoint and this CPU is to be switched in, thus we can only
658    // do this here if the instruction port is actually connected, if
659    // not we have to do it as part of takeOverFrom
660    if (icachePort.isConnected())
661        fetch.setIcache();
662
663    if (FullSystem) {
664        for (ThreadID tid = 0; tid < numThreads; tid++) {
665            ThreadContext *src_tc = threadContexts[tid];
666            TheISA::initCPU(src_tc, src_tc->contextId());
667            // Initialise the ThreadContext's memory proxies
668            thread[tid]->initMemProxies(thread[tid]->getTC());
669        }
670    }
671
672    // Clear inSyscall.
673    for (int tid = 0; tid < numThreads; ++tid)
674        thread[tid]->inSyscall = false;
675
676    // Initialize stages.
677    fetch.initStage();
678    iew.initStage();
679    rename.initStage();
680    commit.initStage();
681
682    commit.setThreads(thread);
683}
684
685template <class Impl>
686void
687FullO3CPU<Impl>::activateThread(ThreadID tid)
688{
689    list<ThreadID>::iterator isActive =
690        std::find(activeThreads.begin(), activeThreads.end(), tid);
691
692    DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
693
694    if (isActive == activeThreads.end()) {
695        DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
696                tid);
697
698        activeThreads.push_back(tid);
699    }
700}
701
702template <class Impl>
703void
704FullO3CPU<Impl>::deactivateThread(ThreadID tid)
705{
706    //Remove From Active List, if Active
707    list<ThreadID>::iterator thread_it =
708        std::find(activeThreads.begin(), activeThreads.end(), tid);
709
710    DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
711
712    if (thread_it != activeThreads.end()) {
713        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
714                tid);
715        activeThreads.erase(thread_it);
716    }
717}
718
719template <class Impl>
720Counter
721FullO3CPU<Impl>::totalInstructions() const
722{
723    Counter total(0);
724
725    ThreadID size = thread.size();
726    for (ThreadID i = 0; i < size; i++)
727        total += thread[i]->numInst;
728
729    return total;
730}
731
732template <class Impl>
733void
734FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
735{
736    // Needs to set each stage to running as well.
737    if (delay){
738        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
739                "on cycle %d\n", tid, curTick() + ticks(delay));
740        scheduleActivateThreadEvent(tid, delay);
741    } else {
742        activateThread(tid);
743    }
744
745    if (lastActivatedCycle < curTick()) {
746        scheduleTickEvent(delay);
747
748        // Be sure to signal that there's some activity so the CPU doesn't
749        // deschedule itself.
750        activityRec.activity();
751        fetch.wakeFromQuiesce();
752
753        quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
754
755        lastActivatedCycle = curTick();
756
757        _status = Running;
758    }
759}
760
761template <class Impl>
762bool
763FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove,
764                                           int delay)
765{
766    // Schedule removal of thread data from CPU
767    if (delay){
768        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
769                "on cycle %d\n", tid, curTick() + ticks(delay));
770        scheduleDeallocateContextEvent(tid, remove, delay);
771        return false;
772    } else {
773        deactivateThread(tid);
774        if (remove)
775            removeThread(tid);
776        return true;
777    }
778}
779
780template <class Impl>
781void
782FullO3CPU<Impl>::suspendContext(ThreadID tid)
783{
784    DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
785    bool deallocated = scheduleDeallocateContext(tid, false, 1);
786    // If this was the last thread then unschedule the tick event.
787    if ((activeThreads.size() == 1 && !deallocated) ||
788        activeThreads.size() == 0)
789        unscheduleTickEvent();
790
791    DPRINTF(Quiesce, "Suspending Context\n");
792    lastRunningCycle = curTick();
793    _status = Idle;
794}
795
796template <class Impl>
797void
798FullO3CPU<Impl>::haltContext(ThreadID tid)
799{
800    //For now, this is the same as deallocate
801    DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
802    scheduleDeallocateContext(tid, true, 1);
803}
804
805template <class Impl>
806void
807FullO3CPU<Impl>::insertThread(ThreadID tid)
808{
809    DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
810    // Will change now that the PC and thread state is internal to the CPU
811    // and not in the ThreadContext.
812    ThreadContext *src_tc;
813    if (FullSystem)
814        src_tc = system->threadContexts[tid];
815    else
816        src_tc = tcBase(tid);
817
818    //Bind Int Regs to Rename Map
819    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
820        PhysRegIndex phys_reg = freeList.getIntReg();
821
822        renameMap[tid].setEntry(ireg,phys_reg);
823        scoreboard.setReg(phys_reg);
824    }
825
826    //Bind Float Regs to Rename Map
827    for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
828        PhysRegIndex phys_reg = freeList.getFloatReg();
829
830        renameMap[tid].setEntry(freg,phys_reg);
831        scoreboard.setReg(phys_reg);
832    }
833
834    //Copy Thread Data Into RegFile
835    //this->copyFromTC(tid);
836
837    //Set PC/NPC/NNPC
838    pcState(src_tc->pcState(), tid);
839
840    src_tc->setStatus(ThreadContext::Active);
841
842    activateContext(tid,1);
843
844    //Reset ROB/IQ/LSQ Entries
845    commit.rob->resetEntries();
846    iew.resetEntries();
847}
848
849template <class Impl>
850void
851FullO3CPU<Impl>::removeThread(ThreadID tid)
852{
853    DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
854
855    // Copy Thread Data From RegFile
856    // If thread is suspended, it might be re-allocated
857    // this->copyToTC(tid);
858
859
860    // @todo: 2-27-2008: Fix how we free up rename mappings
861    // here to alleviate the case for double-freeing registers
862    // in SMT workloads.
863
864    // Unbind Int Regs from Rename Map
865    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
866        PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
867
868        scoreboard.unsetReg(phys_reg);
869        freeList.addReg(phys_reg);
870    }
871
872    // Unbind Float Regs from Rename Map
873    for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
874        PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
875
876        scoreboard.unsetReg(phys_reg);
877        freeList.addReg(phys_reg);
878    }
879
880    // Squash Throughout Pipeline
881    DynInstPtr inst = commit.rob->readHeadInst(tid);
882    InstSeqNum squash_seq_num = inst->seqNum;
883    fetch.squash(0, squash_seq_num, inst, tid);
884    decode.squash(tid);
885    rename.squash(squash_seq_num, tid);
886    iew.squash(tid);
887    iew.ldstQueue.squash(squash_seq_num, tid);
888    commit.rob->squash(squash_seq_num, tid);
889
890
891    assert(iew.instQueue.getCount(tid) == 0);
892    assert(iew.ldstQueue.getCount(tid) == 0);
893
894    // Reset ROB/IQ/LSQ Entries
895
896    // Commented out for now.  This should be possible to do by
897    // telling all the pipeline stages to drain first, and then
898    // checking until the drain completes.  Once the pipeline is
899    // drained, call resetEntries(). - 10-09-06 ktlim
900/*
901    if (activeThreads.size() >= 1) {
902        commit.rob->resetEntries();
903        iew.resetEntries();
904    }
905*/
906}
907
908
909template <class Impl>
910void
911FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
912{
913    DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
914            "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
915            tid);
916
917    bool ready = true;
918
919    if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
920        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
921                "Phys. Int. Regs.\n",
922                tid);
923        ready = false;
924    } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
925        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
926                "Phys. Float. Regs.\n",
927                tid);
928        ready = false;
929    } else if (commit.rob->numFreeEntries() >=
930               commit.rob->entryAmount(activeThreads.size() + 1)) {
931        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
932                "ROB entries.\n",
933                tid);
934        ready = false;
935    } else if (iew.instQueue.numFreeEntries() >=
936               iew.instQueue.entryAmount(activeThreads.size() + 1)) {
937        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
938                "IQ entries.\n",
939                tid);
940        ready = false;
941    } else if (iew.ldstQueue.numFreeEntries() >=
942               iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
943        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
944                "LSQ entries.\n",
945                tid);
946        ready = false;
947    }
948
949    if (ready) {
950        insertThread(tid);
951
952        contextSwitch = false;
953
954        cpuWaitList.remove(tid);
955    } else {
956        suspendContext(tid);
957
958        //blocks fetch
959        contextSwitch = true;
960
961        //@todo: dont always add to waitlist
962        //do waitlist
963        cpuWaitList.push_back(tid);
964    }
965}
966
967template <class Impl>
968Fault
969FullO3CPU<Impl>::hwrei(ThreadID tid)
970{
971#if THE_ISA == ALPHA_ISA
972    // Need to clear the lock flag upon returning from an interrupt.
973    this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
974
975    this->thread[tid]->kernelStats->hwrei();
976
977    // FIXME: XXX check for interrupts? XXX
978#endif
979    return NoFault;
980}
981
982template <class Impl>
983bool
984FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
985{
986#if THE_ISA == ALPHA_ISA
987    if (this->thread[tid]->kernelStats)
988        this->thread[tid]->kernelStats->callpal(palFunc,
989                                                this->threadContexts[tid]);
990
991    switch (palFunc) {
992      case PAL::halt:
993        halt();
994        if (--System::numSystemsRunning == 0)
995            exitSimLoop("all cpus halted");
996        break;
997
998      case PAL::bpt:
999      case PAL::bugchk:
1000        if (this->system->breakpoint())
1001            return false;
1002        break;
1003    }
1004#endif
1005    return true;
1006}
1007
1008template <class Impl>
1009Fault
1010FullO3CPU<Impl>::getInterrupts()
1011{
1012    // Check if there are any outstanding interrupts
1013    return this->interrupts->getInterrupt(this->threadContexts[0]);
1014}
1015
1016template <class Impl>
1017void
1018FullO3CPU<Impl>::processInterrupts(Fault interrupt)
1019{
1020    // Check for interrupts here.  For now can copy the code that
1021    // exists within isa_fullsys_traits.hh.  Also assume that thread 0
1022    // is the one that handles the interrupts.
1023    // @todo: Possibly consolidate the interrupt checking code.
1024    // @todo: Allow other threads to handle interrupts.
1025
1026    assert(interrupt != NoFault);
1027    this->interrupts->updateIntrInfo(this->threadContexts[0]);
1028
1029    DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
1030    this->trap(interrupt, 0, NULL);
1031}
1032
1033template <class Impl>
1034void
1035FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
1036{
1037    // Pass the thread's TC into the invoke method.
1038    fault->invoke(this->threadContexts[tid], inst);
1039}
1040
1041template <class Impl>
1042void
1043FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
1044{
1045    DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1046
1047    DPRINTF(Activity,"Activity: syscall() called.\n");
1048
1049    // Temporarily increase this by one to account for the syscall
1050    // instruction.
1051    ++(this->thread[tid]->funcExeInst);
1052
1053    // Execute the actual syscall.
1054    this->thread[tid]->syscall(callnum);
1055
1056    // Decrease funcExeInst by one as the normal commit will handle
1057    // incrementing it.
1058    --(this->thread[tid]->funcExeInst);
1059}
1060
1061template <class Impl>
1062void
1063FullO3CPU<Impl>::serialize(std::ostream &os)
1064{
1065    SimObject::State so_state = SimObject::getState();
1066    SERIALIZE_ENUM(so_state);
1067    BaseCPU::serialize(os);
1068    nameOut(os, csprintf("%s.tickEvent", name()));
1069    tickEvent.serialize(os);
1070
1071    // Use SimpleThread's ability to checkpoint to make it easier to
1072    // write out the registers.  Also make this static so it doesn't
1073    // get instantiated multiple times (causes a panic in statistics).
1074    static SimpleThread temp;
1075
1076    ThreadID size = thread.size();
1077    for (ThreadID i = 0; i < size; i++) {
1078        nameOut(os, csprintf("%s.xc.%i", name(), i));
1079        temp.copyTC(thread[i]->getTC());
1080        temp.serialize(os);
1081    }
1082}
1083
1084template <class Impl>
1085void
1086FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
1087{
1088    SimObject::State so_state;
1089    UNSERIALIZE_ENUM(so_state);
1090    BaseCPU::unserialize(cp, section);
1091    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1092
1093    // Use SimpleThread's ability to checkpoint to make it easier to
1094    // read in the registers.  Also make this static so it doesn't
1095    // get instantiated multiple times (causes a panic in statistics).
1096    static SimpleThread temp;
1097
1098    ThreadID size = thread.size();
1099    for (ThreadID i = 0; i < size; i++) {
1100        temp.copyTC(thread[i]->getTC());
1101        temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1102        thread[i]->getTC()->copyArchRegs(temp.getTC());
1103    }
1104}
1105
1106template <class Impl>
1107unsigned int
1108FullO3CPU<Impl>::drain(Event *drain_event)
1109{
1110    DPRINTF(O3CPU, "Switching out\n");
1111
1112    // If the CPU isn't doing anything, then return immediately.
1113    if (_status == Idle || _status == SwitchedOut) {
1114        return 0;
1115    }
1116
1117    drainCount = 0;
1118    fetch.drain();
1119    decode.drain();
1120    rename.drain();
1121    iew.drain();
1122    commit.drain();
1123
1124    // Wake the CPU and record activity so everything can drain out if
1125    // the CPU was not able to immediately drain.
1126    if (getState() != SimObject::Drained) {
1127        // A bit of a hack...set the drainEvent after all the drain()
1128        // calls have been made, that way if all of the stages drain
1129        // immediately, the signalDrained() function knows not to call
1130        // process on the drain event.
1131        drainEvent = drain_event;
1132
1133        wakeCPU();
1134        activityRec.activity();
1135
1136        return 1;
1137    } else {
1138        return 0;
1139    }
1140}
1141
1142template <class Impl>
1143void
1144FullO3CPU<Impl>::resume()
1145{
1146    fetch.resume();
1147    decode.resume();
1148    rename.resume();
1149    iew.resume();
1150    commit.resume();
1151
1152    changeState(SimObject::Running);
1153
1154    if (_status == SwitchedOut || _status == Idle)
1155        return;
1156
1157    assert(system->getMemoryMode() == Enums::timing);
1158
1159    if (!tickEvent.scheduled())
1160        schedule(tickEvent, nextCycle());
1161    _status = Running;
1162}
1163
1164template <class Impl>
1165void
1166FullO3CPU<Impl>::signalDrained()
1167{
1168    if (++drainCount == NumStages) {
1169        if (tickEvent.scheduled())
1170            tickEvent.squash();
1171
1172        changeState(SimObject::Drained);
1173
1174        BaseCPU::switchOut();
1175
1176        if (drainEvent) {
1177            drainEvent->process();
1178            drainEvent = NULL;
1179        }
1180    }
1181    assert(drainCount <= 5);
1182}
1183
1184template <class Impl>
1185void
1186FullO3CPU<Impl>::switchOut()
1187{
1188    fetch.switchOut();
1189    rename.switchOut();
1190    iew.switchOut();
1191    commit.switchOut();
1192    instList.clear();
1193    while (!removeList.empty()) {
1194        removeList.pop();
1195    }
1196
1197    _status = SwitchedOut;
1198#if USE_CHECKER
1199    if (checker)
1200        checker->switchOut();
1201#endif
1202    if (tickEvent.scheduled())
1203        tickEvent.squash();
1204}
1205
1206template <class Impl>
1207void
1208FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1209{
1210    // Flush out any old data from the time buffers.
1211    for (int i = 0; i < timeBuffer.getSize(); ++i) {
1212        timeBuffer.advance();
1213        fetchQueue.advance();
1214        decodeQueue.advance();
1215        renameQueue.advance();
1216        iewQueue.advance();
1217    }
1218
1219    activityRec.reset();
1220
1221    BaseCPU::takeOverFrom(oldCPU);
1222
1223    fetch.takeOverFrom();
1224    decode.takeOverFrom();
1225    rename.takeOverFrom();
1226    iew.takeOverFrom();
1227    commit.takeOverFrom();
1228
1229    assert(!tickEvent.scheduled() || tickEvent.squashed());
1230
1231    // @todo: Figure out how to properly select the tid to put onto
1232    // the active threads list.
1233    ThreadID tid = 0;
1234
1235    list<ThreadID>::iterator isActive =
1236        std::find(activeThreads.begin(), activeThreads.end(), tid);
1237
1238    if (isActive == activeThreads.end()) {
1239        //May Need to Re-code this if the delay variable is the delay
1240        //needed for thread to activate
1241        DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1242                tid);
1243
1244        activeThreads.push_back(tid);
1245    }
1246
1247    // Set all statuses to active, schedule the CPU's tick event.
1248    // @todo: Fix up statuses so this is handled properly
1249    ThreadID size = threadContexts.size();
1250    for (ThreadID i = 0; i < size; ++i) {
1251        ThreadContext *tc = threadContexts[i];
1252        if (tc->status() == ThreadContext::Active && _status != Running) {
1253            _status = Running;
1254            reschedule(tickEvent, nextCycle(), true);
1255        }
1256    }
1257    if (!tickEvent.scheduled())
1258        schedule(tickEvent, nextCycle());
1259
1260    lastRunningCycle = curTick();
1261}
1262
1263template <class Impl>
1264TheISA::MiscReg
1265FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1266{
1267    return this->isa[tid].readMiscRegNoEffect(misc_reg);
1268}
1269
1270template <class Impl>
1271TheISA::MiscReg
1272FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1273{
1274    miscRegfileReads++;
1275    return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1276}
1277
1278template <class Impl>
1279void
1280FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1281        const TheISA::MiscReg &val, ThreadID tid)
1282{
1283    this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1284}
1285
1286template <class Impl>
1287void
1288FullO3CPU<Impl>::setMiscReg(int misc_reg,
1289        const TheISA::MiscReg &val, ThreadID tid)
1290{
1291    miscRegfileWrites++;
1292    this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1293}
1294
1295template <class Impl>
1296uint64_t
1297FullO3CPU<Impl>::readIntReg(int reg_idx)
1298{
1299    intRegfileReads++;
1300    return regFile.readIntReg(reg_idx);
1301}
1302
1303template <class Impl>
1304FloatReg
1305FullO3CPU<Impl>::readFloatReg(int reg_idx)
1306{
1307    fpRegfileReads++;
1308    return regFile.readFloatReg(reg_idx);
1309}
1310
1311template <class Impl>
1312FloatRegBits
1313FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1314{
1315    fpRegfileReads++;
1316    return regFile.readFloatRegBits(reg_idx);
1317}
1318
1319template <class Impl>
1320void
1321FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1322{
1323    intRegfileWrites++;
1324    regFile.setIntReg(reg_idx, val);
1325}
1326
1327template <class Impl>
1328void
1329FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1330{
1331    fpRegfileWrites++;
1332    regFile.setFloatReg(reg_idx, val);
1333}
1334
1335template <class Impl>
1336void
1337FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1338{
1339    fpRegfileWrites++;
1340    regFile.setFloatRegBits(reg_idx, val);
1341}
1342
1343template <class Impl>
1344uint64_t
1345FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1346{
1347    intRegfileReads++;
1348    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1349
1350    return regFile.readIntReg(phys_reg);
1351}
1352
1353template <class Impl>
1354float
1355FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1356{
1357    fpRegfileReads++;
1358    int idx = reg_idx + TheISA::NumIntRegs;
1359    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1360
1361    return regFile.readFloatReg(phys_reg);
1362}
1363
1364template <class Impl>
1365uint64_t
1366FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1367{
1368    fpRegfileReads++;
1369    int idx = reg_idx + TheISA::NumIntRegs;
1370    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1371
1372    return regFile.readFloatRegBits(phys_reg);
1373}
1374
1375template <class Impl>
1376void
1377FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1378{
1379    intRegfileWrites++;
1380    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1381
1382    regFile.setIntReg(phys_reg, val);
1383}
1384
1385template <class Impl>
1386void
1387FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1388{
1389    fpRegfileWrites++;
1390    int idx = reg_idx + TheISA::NumIntRegs;
1391    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1392
1393    regFile.setFloatReg(phys_reg, val);
1394}
1395
1396template <class Impl>
1397void
1398FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1399{
1400    fpRegfileWrites++;
1401    int idx = reg_idx + TheISA::NumIntRegs;
1402    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1403
1404    regFile.setFloatRegBits(phys_reg, val);
1405}
1406
1407template <class Impl>
1408TheISA::PCState
1409FullO3CPU<Impl>::pcState(ThreadID tid)
1410{
1411    return commit.pcState(tid);
1412}
1413
1414template <class Impl>
1415void
1416FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1417{
1418    commit.pcState(val, tid);
1419}
1420
1421template <class Impl>
1422Addr
1423FullO3CPU<Impl>::instAddr(ThreadID tid)
1424{
1425    return commit.instAddr(tid);
1426}
1427
1428template <class Impl>
1429Addr
1430FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1431{
1432    return commit.nextInstAddr(tid);
1433}
1434
1435template <class Impl>
1436MicroPC
1437FullO3CPU<Impl>::microPC(ThreadID tid)
1438{
1439    return commit.microPC(tid);
1440}
1441
1442template <class Impl>
1443void
1444FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1445{
1446    this->thread[tid]->inSyscall = true;
1447    this->commit.generateTCEvent(tid);
1448}
1449
1450template <class Impl>
1451typename FullO3CPU<Impl>::ListIt
1452FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1453{
1454    instList.push_back(inst);
1455
1456    return --(instList.end());
1457}
1458
1459template <class Impl>
1460void
1461FullO3CPU<Impl>::instDone(ThreadID tid)
1462{
1463    // Keep an instruction count.
1464    thread[tid]->numInst++;
1465    thread[tid]->numInsts++;
1466    committedInsts[tid]++;
1467    totalCommittedInsts++;
1468    system->totalNumInsts++;
1469    // Check for instruction-count-based events.
1470    comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1471    system->instEventQueue.serviceEvents(system->totalNumInsts);
1472}
1473
1474template <class Impl>
1475void
1476FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1477{
1478    DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1479            "[sn:%lli]\n",
1480            inst->threadNumber, inst->pcState(), inst->seqNum);
1481
1482    removeInstsThisCycle = true;
1483
1484    // Remove the front instruction.
1485    removeList.push(inst->getInstListIt());
1486}
1487
1488template <class Impl>
1489void
1490FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1491{
1492    DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1493            " list.\n", tid);
1494
1495    ListIt end_it;
1496
1497    bool rob_empty = false;
1498
1499    if (instList.empty()) {
1500        return;
1501    } else if (rob.isEmpty(/*tid*/)) {
1502        DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1503        end_it = instList.begin();
1504        rob_empty = true;
1505    } else {
1506        end_it = (rob.readTailInst(tid))->getInstListIt();
1507        DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1508    }
1509
1510    removeInstsThisCycle = true;
1511
1512    ListIt inst_it = instList.end();
1513
1514    inst_it--;
1515
1516    // Walk through the instruction list, removing any instructions
1517    // that were inserted after the given instruction iterator, end_it.
1518    while (inst_it != end_it) {
1519        assert(!instList.empty());
1520
1521        squashInstIt(inst_it, tid);
1522
1523        inst_it--;
1524    }
1525
1526    // If the ROB was empty, then we actually need to remove the first
1527    // instruction as well.
1528    if (rob_empty) {
1529        squashInstIt(inst_it, tid);
1530    }
1531}
1532
1533template <class Impl>
1534void
1535FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1536{
1537    assert(!instList.empty());
1538
1539    removeInstsThisCycle = true;
1540
1541    ListIt inst_iter = instList.end();
1542
1543    inst_iter--;
1544
1545    DPRINTF(O3CPU, "Deleting instructions from instruction "
1546            "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1547            tid, seq_num, (*inst_iter)->seqNum);
1548
1549    while ((*inst_iter)->seqNum > seq_num) {
1550
1551        bool break_loop = (inst_iter == instList.begin());
1552
1553        squashInstIt(inst_iter, tid);
1554
1555        inst_iter--;
1556
1557        if (break_loop)
1558            break;
1559    }
1560}
1561
1562template <class Impl>
1563inline void
1564FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1565{
1566    if ((*instIt)->threadNumber == tid) {
1567        DPRINTF(O3CPU, "Squashing instruction, "
1568                "[tid:%i] [sn:%lli] PC %s\n",
1569                (*instIt)->threadNumber,
1570                (*instIt)->seqNum,
1571                (*instIt)->pcState());
1572
1573        // Mark it as squashed.
1574        (*instIt)->setSquashed();
1575
1576        // @todo: Formulate a consistent method for deleting
1577        // instructions from the instruction list
1578        // Remove the instruction from the list.
1579        removeList.push(instIt);
1580    }
1581}
1582
1583template <class Impl>
1584void
1585FullO3CPU<Impl>::cleanUpRemovedInsts()
1586{
1587    while (!removeList.empty()) {
1588        DPRINTF(O3CPU, "Removing instruction, "
1589                "[tid:%i] [sn:%lli] PC %s\n",
1590                (*removeList.front())->threadNumber,
1591                (*removeList.front())->seqNum,
1592                (*removeList.front())->pcState());
1593
1594        instList.erase(removeList.front());
1595
1596        removeList.pop();
1597    }
1598
1599    removeInstsThisCycle = false;
1600}
1601/*
1602template <class Impl>
1603void
1604FullO3CPU<Impl>::removeAllInsts()
1605{
1606    instList.clear();
1607}
1608*/
1609template <class Impl>
1610void
1611FullO3CPU<Impl>::dumpInsts()
1612{
1613    int num = 0;
1614
1615    ListIt inst_list_it = instList.begin();
1616
1617    cprintf("Dumping Instruction List\n");
1618
1619    while (inst_list_it != instList.end()) {
1620        cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1621                "Squashed:%i\n\n",
1622                num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1623                (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1624                (*inst_list_it)->isSquashed());
1625        inst_list_it++;
1626        ++num;
1627    }
1628}
1629/*
1630template <class Impl>
1631void
1632FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1633{
1634    iew.wakeDependents(inst);
1635}
1636*/
1637template <class Impl>
1638void
1639FullO3CPU<Impl>::wakeCPU()
1640{
1641    if (activityRec.active() || tickEvent.scheduled()) {
1642        DPRINTF(Activity, "CPU already running.\n");
1643        return;
1644    }
1645
1646    DPRINTF(Activity, "Waking up CPU\n");
1647
1648    idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1649    numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1650
1651    schedule(tickEvent, nextCycle());
1652}
1653
1654template <class Impl>
1655void
1656FullO3CPU<Impl>::wakeup()
1657{
1658    if (this->thread[0]->status() != ThreadContext::Suspended)
1659        return;
1660
1661    this->wakeCPU();
1662
1663    DPRINTF(Quiesce, "Suspended Processor woken\n");
1664    this->threadContexts[0]->activate();
1665}
1666
1667template <class Impl>
1668ThreadID
1669FullO3CPU<Impl>::getFreeTid()
1670{
1671    for (ThreadID tid = 0; tid < numThreads; tid++) {
1672        if (!tids[tid]) {
1673            tids[tid] = true;
1674            return tid;
1675        }
1676    }
1677
1678    return InvalidThreadID;
1679}
1680
1681template <class Impl>
1682void
1683FullO3CPU<Impl>::doContextSwitch()
1684{
1685    if (contextSwitch) {
1686
1687        //ADD CODE TO DEACTIVE THREAD HERE (???)
1688
1689        ThreadID size = cpuWaitList.size();
1690        for (ThreadID tid = 0; tid < size; tid++) {
1691            activateWhenReady(tid);
1692        }
1693
1694        if (cpuWaitList.size() == 0)
1695            contextSwitch = true;
1696    }
1697}
1698
1699template <class Impl>
1700void
1701FullO3CPU<Impl>::updateThreadPriority()
1702{
1703    if (activeThreads.size() > 1) {
1704        //DEFAULT TO ROUND ROBIN SCHEME
1705        //e.g. Move highest priority to end of thread list
1706        list<ThreadID>::iterator list_begin = activeThreads.begin();
1707
1708        unsigned high_thread = *list_begin;
1709
1710        activeThreads.erase(list_begin);
1711
1712        activeThreads.push_back(high_thread);
1713    }
1714}
1715
1716// Forward declaration of FullO3CPU.
1717template class FullO3CPU<O3CPUImpl>;
1718