cpu.cc revision 8795:0909f8ed7aa0 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 *          Korey Sewell
31 *          Rick Strong
32 */
33
34#include "arch/kernel_stats.hh"
35#include "config/the_isa.hh"
36#include "config/use_checker.hh"
37#include "cpu/o3/cpu.hh"
38#include "cpu/o3/isa_specific.hh"
39#include "cpu/o3/thread_context.hh"
40#include "cpu/activity.hh"
41#include "cpu/quiesce_event.hh"
42#include "cpu/simple_thread.hh"
43#include "cpu/thread_context.hh"
44#include "debug/Activity.hh"
45#include "debug/O3CPU.hh"
46#include "debug/Quiesce.hh"
47#include "enums/MemoryMode.hh"
48#include "sim/core.hh"
49#include "sim/full_system.hh"
50#include "sim/process.hh"
51#include "sim/stat_control.hh"
52#include "sim/system.hh"
53
54#if USE_CHECKER
55#include "cpu/checker/cpu.hh"
56#endif
57
58#if THE_ISA == ALPHA_ISA
59#include "arch/alpha/osfpal.hh"
60#include "debug/Activity.hh"
61#endif
62
63class BaseCPUParams;
64
65using namespace TheISA;
66using namespace std;
67
68BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
69    : BaseCPU(params)
70{
71}
72
73void
74BaseO3CPU::regStats()
75{
76    BaseCPU::regStats();
77}
78
79template <class Impl>
80FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
81    : Event(CPU_Tick_Pri), cpu(c)
82{
83}
84
85template <class Impl>
86void
87FullO3CPU<Impl>::TickEvent::process()
88{
89    cpu->tick();
90}
91
92template <class Impl>
93const char *
94FullO3CPU<Impl>::TickEvent::description() const
95{
96    return "FullO3CPU tick";
97}
98
99template <class Impl>
100FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
101    : Event(CPU_Switch_Pri)
102{
103}
104
105template <class Impl>
106void
107FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
108                                           FullO3CPU<Impl> *thread_cpu)
109{
110    tid = thread_num;
111    cpu = thread_cpu;
112}
113
114template <class Impl>
115void
116FullO3CPU<Impl>::ActivateThreadEvent::process()
117{
118    cpu->activateThread(tid);
119}
120
121template <class Impl>
122const char *
123FullO3CPU<Impl>::ActivateThreadEvent::description() const
124{
125    return "FullO3CPU \"Activate Thread\"";
126}
127
128template <class Impl>
129FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
130    : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
131{
132}
133
134template <class Impl>
135void
136FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
137                                              FullO3CPU<Impl> *thread_cpu)
138{
139    tid = thread_num;
140    cpu = thread_cpu;
141    remove = false;
142}
143
144template <class Impl>
145void
146FullO3CPU<Impl>::DeallocateContextEvent::process()
147{
148    cpu->deactivateThread(tid);
149    if (remove)
150        cpu->removeThread(tid);
151}
152
153template <class Impl>
154const char *
155FullO3CPU<Impl>::DeallocateContextEvent::description() const
156{
157    return "FullO3CPU \"Deallocate Context\"";
158}
159
160template <class Impl>
161FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
162    : BaseO3CPU(params),
163      itb(params->itb),
164      dtb(params->dtb),
165      tickEvent(this),
166#ifndef NDEBUG
167      instcount(0),
168#endif
169      removeInstsThisCycle(false),
170      fetch(this, params),
171      decode(this, params),
172      rename(this, params),
173      iew(this, params),
174      commit(this, params),
175
176      regFile(this, params->numPhysIntRegs,
177              params->numPhysFloatRegs),
178
179      freeList(params->numThreads,
180               TheISA::NumIntRegs, params->numPhysIntRegs,
181               TheISA::NumFloatRegs, params->numPhysFloatRegs),
182
183      rob(this,
184          params->numROBEntries, params->squashWidth,
185          params->smtROBPolicy, params->smtROBThreshold,
186          params->numThreads),
187
188      scoreboard(params->numThreads,
189                 TheISA::NumIntRegs, params->numPhysIntRegs,
190                 TheISA::NumFloatRegs, params->numPhysFloatRegs,
191                 TheISA::NumMiscRegs * numThreads,
192                 TheISA::ZeroReg),
193
194      timeBuffer(params->backComSize, params->forwardComSize),
195      fetchQueue(params->backComSize, params->forwardComSize),
196      decodeQueue(params->backComSize, params->forwardComSize),
197      renameQueue(params->backComSize, params->forwardComSize),
198      iewQueue(params->backComSize, params->forwardComSize),
199      activityRec(name(), NumStages,
200                  params->backComSize + params->forwardComSize,
201                  params->activity),
202
203      globalSeqNum(1),
204      system(params->system),
205      drainCount(0),
206      deferRegistration(params->defer_registration)
207{
208    if (!deferRegistration) {
209        _status = Running;
210    } else {
211        _status = Idle;
212    }
213
214#if USE_CHECKER
215    if (params->checker) {
216        BaseCPU *temp_checker = params->checker;
217        checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
218        checker->setSystem(params->system);
219    } else {
220        checker = NULL;
221    }
222#endif // USE_CHECKER
223
224    if (!FullSystem) {
225        thread.resize(numThreads);
226        tids.resize(numThreads);
227    }
228
229    // The stages also need their CPU pointer setup.  However this
230    // must be done at the upper level CPU because they have pointers
231    // to the upper level CPU, and not this FullO3CPU.
232
233    // Set up Pointers to the activeThreads list for each stage
234    fetch.setActiveThreads(&activeThreads);
235    decode.setActiveThreads(&activeThreads);
236    rename.setActiveThreads(&activeThreads);
237    iew.setActiveThreads(&activeThreads);
238    commit.setActiveThreads(&activeThreads);
239
240    // Give each of the stages the time buffer they will use.
241    fetch.setTimeBuffer(&timeBuffer);
242    decode.setTimeBuffer(&timeBuffer);
243    rename.setTimeBuffer(&timeBuffer);
244    iew.setTimeBuffer(&timeBuffer);
245    commit.setTimeBuffer(&timeBuffer);
246
247    // Also setup each of the stages' queues.
248    fetch.setFetchQueue(&fetchQueue);
249    decode.setFetchQueue(&fetchQueue);
250    commit.setFetchQueue(&fetchQueue);
251    decode.setDecodeQueue(&decodeQueue);
252    rename.setDecodeQueue(&decodeQueue);
253    rename.setRenameQueue(&renameQueue);
254    iew.setRenameQueue(&renameQueue);
255    iew.setIEWQueue(&iewQueue);
256    commit.setIEWQueue(&iewQueue);
257    commit.setRenameQueue(&renameQueue);
258
259    commit.setIEWStage(&iew);
260    rename.setIEWStage(&iew);
261    rename.setCommitStage(&commit);
262
263    ThreadID active_threads;
264    if (FullSystem) {
265        active_threads = 1;
266    } else {
267        active_threads = params->workload.size();
268
269        if (active_threads > Impl::MaxThreads) {
270            panic("Workload Size too large. Increase the 'MaxThreads' "
271                  "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
272                  "or edit your workload size.");
273        }
274    }
275
276    //Make Sure That this a Valid Architeture
277    assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
278    assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
279
280    rename.setScoreboard(&scoreboard);
281    iew.setScoreboard(&scoreboard);
282
283    // Setup the rename map for whichever stages need it.
284    PhysRegIndex lreg_idx = 0;
285    PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
286
287    for (ThreadID tid = 0; tid < numThreads; tid++) {
288        bool bindRegs = (tid <= active_threads - 1);
289
290        commitRenameMap[tid].init(TheISA::NumIntRegs,
291                                  params->numPhysIntRegs,
292                                  lreg_idx,            //Index for Logical. Regs
293
294                                  TheISA::NumFloatRegs,
295                                  params->numPhysFloatRegs,
296                                  freg_idx,            //Index for Float Regs
297
298                                  TheISA::NumMiscRegs,
299
300                                  TheISA::ZeroReg,
301                                  TheISA::ZeroReg,
302
303                                  tid,
304                                  false);
305
306        renameMap[tid].init(TheISA::NumIntRegs,
307                            params->numPhysIntRegs,
308                            lreg_idx,                  //Index for Logical. Regs
309
310                            TheISA::NumFloatRegs,
311                            params->numPhysFloatRegs,
312                            freg_idx,                  //Index for Float Regs
313
314                            TheISA::NumMiscRegs,
315
316                            TheISA::ZeroReg,
317                            TheISA::ZeroReg,
318
319                            tid,
320                            bindRegs);
321
322        activateThreadEvent[tid].init(tid, this);
323        deallocateContextEvent[tid].init(tid, this);
324    }
325
326    rename.setRenameMap(renameMap);
327    commit.setRenameMap(commitRenameMap);
328
329    // Give renameMap & rename stage access to the freeList;
330    for (ThreadID tid = 0; tid < numThreads; tid++)
331        renameMap[tid].setFreeList(&freeList);
332    rename.setFreeList(&freeList);
333
334    // Setup the ROB for whichever stages need it.
335    commit.setROB(&rob);
336
337    lastRunningCycle = curTick();
338
339    lastActivatedCycle = -1;
340#if 0
341    // Give renameMap & rename stage access to the freeList;
342    for (ThreadID tid = 0; tid < numThreads; tid++)
343        globalSeqNum[tid] = 1;
344#endif
345
346    contextSwitch = false;
347    DPRINTF(O3CPU, "Creating O3CPU object.\n");
348
349    // Setup any thread state.
350    this->thread.resize(this->numThreads);
351
352    for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
353        if (FullSystem) {
354            // SMT is not supported in FS mode yet.
355            assert(this->numThreads == 1);
356            this->thread[tid] = new Thread(this, 0, NULL);
357        } else {
358            if (tid < params->workload.size()) {
359                DPRINTF(O3CPU, "Workload[%i] process is %#x",
360                        tid, this->thread[tid]);
361                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
362                        (typename Impl::O3CPU *)(this),
363                        tid, params->workload[tid]);
364
365                //usedTids[tid] = true;
366                //threadMap[tid] = tid;
367            } else {
368                //Allocate Empty thread so M5 can use later
369                //when scheduling threads to CPU
370                Process* dummy_proc = NULL;
371
372                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
373                        (typename Impl::O3CPU *)(this),
374                        tid, dummy_proc);
375                //usedTids[tid] = false;
376            }
377        }
378
379        ThreadContext *tc;
380
381        // Setup the TC that will serve as the interface to the threads/CPU.
382        O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
383
384        tc = o3_tc;
385
386        // If we're using a checker, then the TC should be the
387        // CheckerThreadContext.
388#if USE_CHECKER
389        if (params->checker) {
390            tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
391                o3_tc, this->checker);
392        }
393#endif
394
395        o3_tc->cpu = (typename Impl::O3CPU *)(this);
396        assert(o3_tc->cpu);
397        o3_tc->thread = this->thread[tid];
398
399        if (FullSystem) {
400            // Setup quiesce event.
401            this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
402        }
403        // Give the thread the TC.
404        this->thread[tid]->tc = tc;
405
406        // Add the TC to the CPU's list of TC's.
407        this->threadContexts.push_back(tc);
408    }
409
410    for (ThreadID tid = 0; tid < this->numThreads; tid++)
411        this->thread[tid]->setFuncExeInst(0);
412
413    lockAddr = 0;
414    lockFlag = false;
415}
416
417template <class Impl>
418FullO3CPU<Impl>::~FullO3CPU()
419{
420}
421
422template <class Impl>
423void
424FullO3CPU<Impl>::regStats()
425{
426    BaseO3CPU::regStats();
427
428    // Register any of the O3CPU's stats here.
429    timesIdled
430        .name(name() + ".timesIdled")
431        .desc("Number of times that the entire CPU went into an idle state and"
432              " unscheduled itself")
433        .prereq(timesIdled);
434
435    idleCycles
436        .name(name() + ".idleCycles")
437        .desc("Total number of cycles that the CPU has spent unscheduled due "
438              "to idling")
439        .prereq(idleCycles);
440
441    // Number of Instructions simulated
442    // --------------------------------
443    // Should probably be in Base CPU but need templated
444    // MaxThreads so put in here instead
445    committedInsts
446        .init(numThreads)
447        .name(name() + ".committedInsts")
448        .desc("Number of Instructions Simulated");
449
450    totalCommittedInsts
451        .name(name() + ".committedInsts_total")
452        .desc("Number of Instructions Simulated");
453
454    cpi
455        .name(name() + ".cpi")
456        .desc("CPI: Cycles Per Instruction")
457        .precision(6);
458    cpi = numCycles / committedInsts;
459
460    totalCpi
461        .name(name() + ".cpi_total")
462        .desc("CPI: Total CPI of All Threads")
463        .precision(6);
464    totalCpi = numCycles / totalCommittedInsts;
465
466    ipc
467        .name(name() + ".ipc")
468        .desc("IPC: Instructions Per Cycle")
469        .precision(6);
470    ipc =  committedInsts / numCycles;
471
472    totalIpc
473        .name(name() + ".ipc_total")
474        .desc("IPC: Total IPC of All Threads")
475        .precision(6);
476    totalIpc =  totalCommittedInsts / numCycles;
477
478    this->fetch.regStats();
479    this->decode.regStats();
480    this->rename.regStats();
481    this->iew.regStats();
482    this->commit.regStats();
483    this->rob.regStats();
484
485    intRegfileReads
486        .name(name() + ".int_regfile_reads")
487        .desc("number of integer regfile reads")
488        .prereq(intRegfileReads);
489
490    intRegfileWrites
491        .name(name() + ".int_regfile_writes")
492        .desc("number of integer regfile writes")
493        .prereq(intRegfileWrites);
494
495    fpRegfileReads
496        .name(name() + ".fp_regfile_reads")
497        .desc("number of floating regfile reads")
498        .prereq(fpRegfileReads);
499
500    fpRegfileWrites
501        .name(name() + ".fp_regfile_writes")
502        .desc("number of floating regfile writes")
503        .prereq(fpRegfileWrites);
504
505    miscRegfileReads
506        .name(name() + ".misc_regfile_reads")
507        .desc("number of misc regfile reads")
508        .prereq(miscRegfileReads);
509
510    miscRegfileWrites
511        .name(name() + ".misc_regfile_writes")
512        .desc("number of misc regfile writes")
513        .prereq(miscRegfileWrites);
514}
515
516template <class Impl>
517Port *
518FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
519{
520    if (if_name == "dcache_port")
521        return iew.getDcachePort();
522    else if (if_name == "icache_port")
523        return fetch.getIcachePort();
524    else
525        panic("No Such Port\n");
526}
527
528template <class Impl>
529void
530FullO3CPU<Impl>::tick()
531{
532    DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
533
534    ++numCycles;
535
536//    activity = false;
537
538    //Tick each of the stages
539    fetch.tick();
540
541    decode.tick();
542
543    rename.tick();
544
545    iew.tick();
546
547    commit.tick();
548
549    if (!FullSystem)
550        doContextSwitch();
551
552    // Now advance the time buffers
553    timeBuffer.advance();
554
555    fetchQueue.advance();
556    decodeQueue.advance();
557    renameQueue.advance();
558    iewQueue.advance();
559
560    activityRec.advance();
561
562    if (removeInstsThisCycle) {
563        cleanUpRemovedInsts();
564    }
565
566    if (!tickEvent.scheduled()) {
567        if (_status == SwitchedOut ||
568            getState() == SimObject::Drained) {
569            DPRINTF(O3CPU, "Switched out!\n");
570            // increment stat
571            lastRunningCycle = curTick();
572        } else if (!activityRec.active() || _status == Idle) {
573            DPRINTF(O3CPU, "Idle!\n");
574            lastRunningCycle = curTick();
575            timesIdled++;
576        } else {
577            schedule(tickEvent, nextCycle(curTick() + ticks(1)));
578            DPRINTF(O3CPU, "Scheduling next tick!\n");
579        }
580    }
581
582    if (!FullSystem)
583        updateThreadPriority();
584}
585
586template <class Impl>
587void
588FullO3CPU<Impl>::init()
589{
590    BaseCPU::init();
591
592    // Set inSyscall so that the CPU doesn't squash when initially
593    // setting up registers.
594    for (ThreadID tid = 0; tid < numThreads; ++tid)
595        thread[tid]->inSyscall = true;
596
597    if (FullSystem) {
598        for (ThreadID tid = 0; tid < numThreads; tid++) {
599            ThreadContext *src_tc = threadContexts[tid];
600            TheISA::initCPU(src_tc, src_tc->contextId());
601        }
602    }
603
604    // Clear inSyscall.
605    for (int tid = 0; tid < numThreads; ++tid)
606        thread[tid]->inSyscall = false;
607
608    // Initialize stages.
609    fetch.initStage();
610    iew.initStage();
611    rename.initStage();
612    commit.initStage();
613
614    commit.setThreads(thread);
615}
616
617template <class Impl>
618void
619FullO3CPU<Impl>::activateThread(ThreadID tid)
620{
621    list<ThreadID>::iterator isActive =
622        std::find(activeThreads.begin(), activeThreads.end(), tid);
623
624    DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
625
626    if (isActive == activeThreads.end()) {
627        DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
628                tid);
629
630        activeThreads.push_back(tid);
631    }
632}
633
634template <class Impl>
635void
636FullO3CPU<Impl>::deactivateThread(ThreadID tid)
637{
638    //Remove From Active List, if Active
639    list<ThreadID>::iterator thread_it =
640        std::find(activeThreads.begin(), activeThreads.end(), tid);
641
642    DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
643
644    if (thread_it != activeThreads.end()) {
645        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
646                tid);
647        activeThreads.erase(thread_it);
648    }
649}
650
651template <class Impl>
652Counter
653FullO3CPU<Impl>::totalInstructions() const
654{
655    Counter total(0);
656
657    ThreadID size = thread.size();
658    for (ThreadID i = 0; i < size; i++)
659        total += thread[i]->numInst;
660
661    return total;
662}
663
664template <class Impl>
665void
666FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
667{
668    // Needs to set each stage to running as well.
669    if (delay){
670        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
671                "on cycle %d\n", tid, curTick() + ticks(delay));
672        scheduleActivateThreadEvent(tid, delay);
673    } else {
674        activateThread(tid);
675    }
676
677    if (lastActivatedCycle < curTick()) {
678        scheduleTickEvent(delay);
679
680        // Be sure to signal that there's some activity so the CPU doesn't
681        // deschedule itself.
682        activityRec.activity();
683        fetch.wakeFromQuiesce();
684
685        lastActivatedCycle = curTick();
686
687        _status = Running;
688    }
689}
690
691template <class Impl>
692bool
693FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay)
694{
695    // Schedule removal of thread data from CPU
696    if (delay){
697        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
698                "on cycle %d\n", tid, curTick() + ticks(delay));
699        scheduleDeallocateContextEvent(tid, remove, delay);
700        return false;
701    } else {
702        deactivateThread(tid);
703        if (remove)
704            removeThread(tid);
705        return true;
706    }
707}
708
709template <class Impl>
710void
711FullO3CPU<Impl>::suspendContext(ThreadID tid)
712{
713    DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
714    bool deallocated = deallocateContext(tid, false, 1);
715    // If this was the last thread then unschedule the tick event.
716    if ((activeThreads.size() == 1 && !deallocated) ||
717        activeThreads.size() == 0)
718        unscheduleTickEvent();
719    _status = Idle;
720}
721
722template <class Impl>
723void
724FullO3CPU<Impl>::haltContext(ThreadID tid)
725{
726    //For now, this is the same as deallocate
727    DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
728    deallocateContext(tid, true, 1);
729}
730
731template <class Impl>
732void
733FullO3CPU<Impl>::insertThread(ThreadID tid)
734{
735    DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
736    // Will change now that the PC and thread state is internal to the CPU
737    // and not in the ThreadContext.
738    ThreadContext *src_tc;
739    if (FullSystem)
740        src_tc = system->threadContexts[tid];
741    else
742        src_tc = tcBase(tid);
743
744    //Bind Int Regs to Rename Map
745    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
746        PhysRegIndex phys_reg = freeList.getIntReg();
747
748        renameMap[tid].setEntry(ireg,phys_reg);
749        scoreboard.setReg(phys_reg);
750    }
751
752    //Bind Float Regs to Rename Map
753    for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
754        PhysRegIndex phys_reg = freeList.getFloatReg();
755
756        renameMap[tid].setEntry(freg,phys_reg);
757        scoreboard.setReg(phys_reg);
758    }
759
760    //Copy Thread Data Into RegFile
761    //this->copyFromTC(tid);
762
763    //Set PC/NPC/NNPC
764    pcState(src_tc->pcState(), tid);
765
766    src_tc->setStatus(ThreadContext::Active);
767
768    activateContext(tid,1);
769
770    //Reset ROB/IQ/LSQ Entries
771    commit.rob->resetEntries();
772    iew.resetEntries();
773}
774
775template <class Impl>
776void
777FullO3CPU<Impl>::removeThread(ThreadID tid)
778{
779    DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
780
781    // Copy Thread Data From RegFile
782    // If thread is suspended, it might be re-allocated
783    // this->copyToTC(tid);
784
785
786    // @todo: 2-27-2008: Fix how we free up rename mappings
787    // here to alleviate the case for double-freeing registers
788    // in SMT workloads.
789
790    // Unbind Int Regs from Rename Map
791    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
792        PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
793
794        scoreboard.unsetReg(phys_reg);
795        freeList.addReg(phys_reg);
796    }
797
798    // Unbind Float Regs from Rename Map
799    for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
800        PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
801
802        scoreboard.unsetReg(phys_reg);
803        freeList.addReg(phys_reg);
804    }
805
806    // Squash Throughout Pipeline
807    DynInstPtr inst = commit.rob->readHeadInst(tid);
808    InstSeqNum squash_seq_num = inst->seqNum;
809    fetch.squash(0, squash_seq_num, inst, tid);
810    decode.squash(tid);
811    rename.squash(squash_seq_num, tid);
812    iew.squash(tid);
813    iew.ldstQueue.squash(squash_seq_num, tid);
814    commit.rob->squash(squash_seq_num, tid);
815
816
817    assert(iew.instQueue.getCount(tid) == 0);
818    assert(iew.ldstQueue.getCount(tid) == 0);
819
820    // Reset ROB/IQ/LSQ Entries
821
822    // Commented out for now.  This should be possible to do by
823    // telling all the pipeline stages to drain first, and then
824    // checking until the drain completes.  Once the pipeline is
825    // drained, call resetEntries(). - 10-09-06 ktlim
826/*
827    if (activeThreads.size() >= 1) {
828        commit.rob->resetEntries();
829        iew.resetEntries();
830    }
831*/
832}
833
834
835template <class Impl>
836void
837FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
838{
839    DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
840            "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
841            tid);
842
843    bool ready = true;
844
845    if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
846        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
847                "Phys. Int. Regs.\n",
848                tid);
849        ready = false;
850    } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
851        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
852                "Phys. Float. Regs.\n",
853                tid);
854        ready = false;
855    } else if (commit.rob->numFreeEntries() >=
856               commit.rob->entryAmount(activeThreads.size() + 1)) {
857        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
858                "ROB entries.\n",
859                tid);
860        ready = false;
861    } else if (iew.instQueue.numFreeEntries() >=
862               iew.instQueue.entryAmount(activeThreads.size() + 1)) {
863        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
864                "IQ entries.\n",
865                tid);
866        ready = false;
867    } else if (iew.ldstQueue.numFreeEntries() >=
868               iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
869        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
870                "LSQ entries.\n",
871                tid);
872        ready = false;
873    }
874
875    if (ready) {
876        insertThread(tid);
877
878        contextSwitch = false;
879
880        cpuWaitList.remove(tid);
881    } else {
882        suspendContext(tid);
883
884        //blocks fetch
885        contextSwitch = true;
886
887        //@todo: dont always add to waitlist
888        //do waitlist
889        cpuWaitList.push_back(tid);
890    }
891}
892
893template <class Impl>
894Fault
895FullO3CPU<Impl>::hwrei(ThreadID tid)
896{
897#if THE_ISA == ALPHA_ISA
898    // Need to clear the lock flag upon returning from an interrupt.
899    this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
900
901    this->thread[tid]->kernelStats->hwrei();
902
903    // FIXME: XXX check for interrupts? XXX
904#endif
905    return NoFault;
906}
907
908template <class Impl>
909bool
910FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
911{
912#if THE_ISA == ALPHA_ISA
913    if (this->thread[tid]->kernelStats)
914        this->thread[tid]->kernelStats->callpal(palFunc,
915                                                this->threadContexts[tid]);
916
917    switch (palFunc) {
918      case PAL::halt:
919        halt();
920        if (--System::numSystemsRunning == 0)
921            exitSimLoop("all cpus halted");
922        break;
923
924      case PAL::bpt:
925      case PAL::bugchk:
926        if (this->system->breakpoint())
927            return false;
928        break;
929    }
930#endif
931    return true;
932}
933
934template <class Impl>
935Fault
936FullO3CPU<Impl>::getInterrupts()
937{
938    // Check if there are any outstanding interrupts
939    return this->interrupts->getInterrupt(this->threadContexts[0]);
940}
941
942template <class Impl>
943void
944FullO3CPU<Impl>::processInterrupts(Fault interrupt)
945{
946    // Check for interrupts here.  For now can copy the code that
947    // exists within isa_fullsys_traits.hh.  Also assume that thread 0
948    // is the one that handles the interrupts.
949    // @todo: Possibly consolidate the interrupt checking code.
950    // @todo: Allow other threads to handle interrupts.
951
952    assert(interrupt != NoFault);
953    this->interrupts->updateIntrInfo(this->threadContexts[0]);
954
955    DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
956    this->trap(interrupt, 0, NULL);
957}
958
959template <class Impl>
960void
961FullO3CPU<Impl>::updateMemPorts()
962{
963    // Update all ThreadContext's memory ports (Functional/Virtual
964    // Ports)
965    ThreadID size = thread.size();
966    for (ThreadID i = 0; i < size; ++i)
967        thread[i]->connectMemPorts(thread[i]->getTC());
968}
969
970template <class Impl>
971void
972FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
973{
974    // Pass the thread's TC into the invoke method.
975    fault->invoke(this->threadContexts[tid], inst);
976}
977
978template <class Impl>
979void
980FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
981{
982    DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
983
984    DPRINTF(Activity,"Activity: syscall() called.\n");
985
986    // Temporarily increase this by one to account for the syscall
987    // instruction.
988    ++(this->thread[tid]->funcExeInst);
989
990    // Execute the actual syscall.
991    this->thread[tid]->syscall(callnum);
992
993    // Decrease funcExeInst by one as the normal commit will handle
994    // incrementing it.
995    --(this->thread[tid]->funcExeInst);
996}
997
998template <class Impl>
999void
1000FullO3CPU<Impl>::serialize(std::ostream &os)
1001{
1002    SimObject::State so_state = SimObject::getState();
1003    SERIALIZE_ENUM(so_state);
1004    BaseCPU::serialize(os);
1005    nameOut(os, csprintf("%s.tickEvent", name()));
1006    tickEvent.serialize(os);
1007
1008    // Use SimpleThread's ability to checkpoint to make it easier to
1009    // write out the registers.  Also make this static so it doesn't
1010    // get instantiated multiple times (causes a panic in statistics).
1011    static SimpleThread temp;
1012
1013    ThreadID size = thread.size();
1014    for (ThreadID i = 0; i < size; i++) {
1015        nameOut(os, csprintf("%s.xc.%i", name(), i));
1016        temp.copyTC(thread[i]->getTC());
1017        temp.serialize(os);
1018    }
1019}
1020
1021template <class Impl>
1022void
1023FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
1024{
1025    SimObject::State so_state;
1026    UNSERIALIZE_ENUM(so_state);
1027    BaseCPU::unserialize(cp, section);
1028    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1029
1030    // Use SimpleThread's ability to checkpoint to make it easier to
1031    // read in the registers.  Also make this static so it doesn't
1032    // get instantiated multiple times (causes a panic in statistics).
1033    static SimpleThread temp;
1034
1035    ThreadID size = thread.size();
1036    for (ThreadID i = 0; i < size; i++) {
1037        temp.copyTC(thread[i]->getTC());
1038        temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1039        thread[i]->getTC()->copyArchRegs(temp.getTC());
1040    }
1041}
1042
1043template <class Impl>
1044unsigned int
1045FullO3CPU<Impl>::drain(Event *drain_event)
1046{
1047    DPRINTF(O3CPU, "Switching out\n");
1048
1049    // If the CPU isn't doing anything, then return immediately.
1050    if (_status == Idle || _status == SwitchedOut) {
1051        return 0;
1052    }
1053
1054    drainCount = 0;
1055    fetch.drain();
1056    decode.drain();
1057    rename.drain();
1058    iew.drain();
1059    commit.drain();
1060
1061    // Wake the CPU and record activity so everything can drain out if
1062    // the CPU was not able to immediately drain.
1063    if (getState() != SimObject::Drained) {
1064        // A bit of a hack...set the drainEvent after all the drain()
1065        // calls have been made, that way if all of the stages drain
1066        // immediately, the signalDrained() function knows not to call
1067        // process on the drain event.
1068        drainEvent = drain_event;
1069
1070        wakeCPU();
1071        activityRec.activity();
1072
1073        return 1;
1074    } else {
1075        return 0;
1076    }
1077}
1078
1079template <class Impl>
1080void
1081FullO3CPU<Impl>::resume()
1082{
1083    fetch.resume();
1084    decode.resume();
1085    rename.resume();
1086    iew.resume();
1087    commit.resume();
1088
1089    changeState(SimObject::Running);
1090
1091    if (_status == SwitchedOut || _status == Idle)
1092        return;
1093
1094    assert(system->getMemoryMode() == Enums::timing);
1095
1096    if (!tickEvent.scheduled())
1097        schedule(tickEvent, nextCycle());
1098    _status = Running;
1099}
1100
1101template <class Impl>
1102void
1103FullO3CPU<Impl>::signalDrained()
1104{
1105    if (++drainCount == NumStages) {
1106        if (tickEvent.scheduled())
1107            tickEvent.squash();
1108
1109        changeState(SimObject::Drained);
1110
1111        BaseCPU::switchOut();
1112
1113        if (drainEvent) {
1114            drainEvent->process();
1115            drainEvent = NULL;
1116        }
1117    }
1118    assert(drainCount <= 5);
1119}
1120
1121template <class Impl>
1122void
1123FullO3CPU<Impl>::switchOut()
1124{
1125    fetch.switchOut();
1126    rename.switchOut();
1127    iew.switchOut();
1128    commit.switchOut();
1129    instList.clear();
1130    while (!removeList.empty()) {
1131        removeList.pop();
1132    }
1133
1134    _status = SwitchedOut;
1135#if USE_CHECKER
1136    if (checker)
1137        checker->switchOut();
1138#endif
1139    if (tickEvent.scheduled())
1140        tickEvent.squash();
1141}
1142
1143template <class Impl>
1144void
1145FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1146{
1147    // Flush out any old data from the time buffers.
1148    for (int i = 0; i < timeBuffer.getSize(); ++i) {
1149        timeBuffer.advance();
1150        fetchQueue.advance();
1151        decodeQueue.advance();
1152        renameQueue.advance();
1153        iewQueue.advance();
1154    }
1155
1156    activityRec.reset();
1157
1158    BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort());
1159
1160    fetch.takeOverFrom();
1161    decode.takeOverFrom();
1162    rename.takeOverFrom();
1163    iew.takeOverFrom();
1164    commit.takeOverFrom();
1165
1166    assert(!tickEvent.scheduled() || tickEvent.squashed());
1167
1168    // @todo: Figure out how to properly select the tid to put onto
1169    // the active threads list.
1170    ThreadID tid = 0;
1171
1172    list<ThreadID>::iterator isActive =
1173        std::find(activeThreads.begin(), activeThreads.end(), tid);
1174
1175    if (isActive == activeThreads.end()) {
1176        //May Need to Re-code this if the delay variable is the delay
1177        //needed for thread to activate
1178        DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1179                tid);
1180
1181        activeThreads.push_back(tid);
1182    }
1183
1184    // Set all statuses to active, schedule the CPU's tick event.
1185    // @todo: Fix up statuses so this is handled properly
1186    ThreadID size = threadContexts.size();
1187    for (ThreadID i = 0; i < size; ++i) {
1188        ThreadContext *tc = threadContexts[i];
1189        if (tc->status() == ThreadContext::Active && _status != Running) {
1190            _status = Running;
1191            reschedule(tickEvent, nextCycle(), true);
1192        }
1193    }
1194    if (!tickEvent.scheduled())
1195        schedule(tickEvent, nextCycle());
1196}
1197
1198template <class Impl>
1199TheISA::MiscReg
1200FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1201{
1202    return this->isa[tid].readMiscRegNoEffect(misc_reg);
1203}
1204
1205template <class Impl>
1206TheISA::MiscReg
1207FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1208{
1209    miscRegfileReads++;
1210    return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1211}
1212
1213template <class Impl>
1214void
1215FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1216        const TheISA::MiscReg &val, ThreadID tid)
1217{
1218    this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1219}
1220
1221template <class Impl>
1222void
1223FullO3CPU<Impl>::setMiscReg(int misc_reg,
1224        const TheISA::MiscReg &val, ThreadID tid)
1225{
1226    miscRegfileWrites++;
1227    this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1228}
1229
1230template <class Impl>
1231uint64_t
1232FullO3CPU<Impl>::readIntReg(int reg_idx)
1233{
1234    intRegfileReads++;
1235    return regFile.readIntReg(reg_idx);
1236}
1237
1238template <class Impl>
1239FloatReg
1240FullO3CPU<Impl>::readFloatReg(int reg_idx)
1241{
1242    fpRegfileReads++;
1243    return regFile.readFloatReg(reg_idx);
1244}
1245
1246template <class Impl>
1247FloatRegBits
1248FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1249{
1250    fpRegfileReads++;
1251    return regFile.readFloatRegBits(reg_idx);
1252}
1253
1254template <class Impl>
1255void
1256FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1257{
1258    intRegfileWrites++;
1259    regFile.setIntReg(reg_idx, val);
1260}
1261
1262template <class Impl>
1263void
1264FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1265{
1266    fpRegfileWrites++;
1267    regFile.setFloatReg(reg_idx, val);
1268}
1269
1270template <class Impl>
1271void
1272FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1273{
1274    fpRegfileWrites++;
1275    regFile.setFloatRegBits(reg_idx, val);
1276}
1277
1278template <class Impl>
1279uint64_t
1280FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1281{
1282    intRegfileReads++;
1283    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1284
1285    return regFile.readIntReg(phys_reg);
1286}
1287
1288template <class Impl>
1289float
1290FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1291{
1292    fpRegfileReads++;
1293    int idx = reg_idx + TheISA::NumIntRegs;
1294    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1295
1296    return regFile.readFloatReg(phys_reg);
1297}
1298
1299template <class Impl>
1300uint64_t
1301FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1302{
1303    fpRegfileReads++;
1304    int idx = reg_idx + TheISA::NumIntRegs;
1305    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1306
1307    return regFile.readFloatRegBits(phys_reg);
1308}
1309
1310template <class Impl>
1311void
1312FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1313{
1314    intRegfileWrites++;
1315    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1316
1317    regFile.setIntReg(phys_reg, val);
1318}
1319
1320template <class Impl>
1321void
1322FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1323{
1324    fpRegfileWrites++;
1325    int idx = reg_idx + TheISA::NumIntRegs;
1326    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1327
1328    regFile.setFloatReg(phys_reg, val);
1329}
1330
1331template <class Impl>
1332void
1333FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1334{
1335    fpRegfileWrites++;
1336    int idx = reg_idx + TheISA::NumIntRegs;
1337    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1338
1339    regFile.setFloatRegBits(phys_reg, val);
1340}
1341
1342template <class Impl>
1343TheISA::PCState
1344FullO3CPU<Impl>::pcState(ThreadID tid)
1345{
1346    return commit.pcState(tid);
1347}
1348
1349template <class Impl>
1350void
1351FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1352{
1353    commit.pcState(val, tid);
1354}
1355
1356template <class Impl>
1357Addr
1358FullO3CPU<Impl>::instAddr(ThreadID tid)
1359{
1360    return commit.instAddr(tid);
1361}
1362
1363template <class Impl>
1364Addr
1365FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1366{
1367    return commit.nextInstAddr(tid);
1368}
1369
1370template <class Impl>
1371MicroPC
1372FullO3CPU<Impl>::microPC(ThreadID tid)
1373{
1374    return commit.microPC(tid);
1375}
1376
1377template <class Impl>
1378void
1379FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1380{
1381    this->thread[tid]->inSyscall = true;
1382    this->commit.generateTCEvent(tid);
1383}
1384
1385template <class Impl>
1386typename FullO3CPU<Impl>::ListIt
1387FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1388{
1389    instList.push_back(inst);
1390
1391    return --(instList.end());
1392}
1393
1394template <class Impl>
1395void
1396FullO3CPU<Impl>::instDone(ThreadID tid)
1397{
1398    // Keep an instruction count.
1399    thread[tid]->numInst++;
1400    thread[tid]->numInsts++;
1401    committedInsts[tid]++;
1402    totalCommittedInsts++;
1403    system->totalNumInsts++;
1404    // Check for instruction-count-based events.
1405    comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1406    system->instEventQueue.serviceEvents(system->totalNumInsts);
1407}
1408
1409template <class Impl>
1410void
1411FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1412{
1413    DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1414            "[sn:%lli]\n",
1415            inst->threadNumber, inst->pcState(), inst->seqNum);
1416
1417    removeInstsThisCycle = true;
1418
1419    // Remove the front instruction.
1420    removeList.push(inst->getInstListIt());
1421}
1422
1423template <class Impl>
1424void
1425FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1426{
1427    DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1428            " list.\n", tid);
1429
1430    ListIt end_it;
1431
1432    bool rob_empty = false;
1433
1434    if (instList.empty()) {
1435        return;
1436    } else if (rob.isEmpty(/*tid*/)) {
1437        DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1438        end_it = instList.begin();
1439        rob_empty = true;
1440    } else {
1441        end_it = (rob.readTailInst(tid))->getInstListIt();
1442        DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1443    }
1444
1445    removeInstsThisCycle = true;
1446
1447    ListIt inst_it = instList.end();
1448
1449    inst_it--;
1450
1451    // Walk through the instruction list, removing any instructions
1452    // that were inserted after the given instruction iterator, end_it.
1453    while (inst_it != end_it) {
1454        assert(!instList.empty());
1455
1456        squashInstIt(inst_it, tid);
1457
1458        inst_it--;
1459    }
1460
1461    // If the ROB was empty, then we actually need to remove the first
1462    // instruction as well.
1463    if (rob_empty) {
1464        squashInstIt(inst_it, tid);
1465    }
1466}
1467
1468template <class Impl>
1469void
1470FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1471{
1472    assert(!instList.empty());
1473
1474    removeInstsThisCycle = true;
1475
1476    ListIt inst_iter = instList.end();
1477
1478    inst_iter--;
1479
1480    DPRINTF(O3CPU, "Deleting instructions from instruction "
1481            "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1482            tid, seq_num, (*inst_iter)->seqNum);
1483
1484    while ((*inst_iter)->seqNum > seq_num) {
1485
1486        bool break_loop = (inst_iter == instList.begin());
1487
1488        squashInstIt(inst_iter, tid);
1489
1490        inst_iter--;
1491
1492        if (break_loop)
1493            break;
1494    }
1495}
1496
1497template <class Impl>
1498inline void
1499FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1500{
1501    if ((*instIt)->threadNumber == tid) {
1502        DPRINTF(O3CPU, "Squashing instruction, "
1503                "[tid:%i] [sn:%lli] PC %s\n",
1504                (*instIt)->threadNumber,
1505                (*instIt)->seqNum,
1506                (*instIt)->pcState());
1507
1508        // Mark it as squashed.
1509        (*instIt)->setSquashed();
1510
1511        // @todo: Formulate a consistent method for deleting
1512        // instructions from the instruction list
1513        // Remove the instruction from the list.
1514        removeList.push(instIt);
1515    }
1516}
1517
1518template <class Impl>
1519void
1520FullO3CPU<Impl>::cleanUpRemovedInsts()
1521{
1522    while (!removeList.empty()) {
1523        DPRINTF(O3CPU, "Removing instruction, "
1524                "[tid:%i] [sn:%lli] PC %s\n",
1525                (*removeList.front())->threadNumber,
1526                (*removeList.front())->seqNum,
1527                (*removeList.front())->pcState());
1528
1529        instList.erase(removeList.front());
1530
1531        removeList.pop();
1532    }
1533
1534    removeInstsThisCycle = false;
1535}
1536/*
1537template <class Impl>
1538void
1539FullO3CPU<Impl>::removeAllInsts()
1540{
1541    instList.clear();
1542}
1543*/
1544template <class Impl>
1545void
1546FullO3CPU<Impl>::dumpInsts()
1547{
1548    int num = 0;
1549
1550    ListIt inst_list_it = instList.begin();
1551
1552    cprintf("Dumping Instruction List\n");
1553
1554    while (inst_list_it != instList.end()) {
1555        cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1556                "Squashed:%i\n\n",
1557                num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1558                (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1559                (*inst_list_it)->isSquashed());
1560        inst_list_it++;
1561        ++num;
1562    }
1563}
1564/*
1565template <class Impl>
1566void
1567FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1568{
1569    iew.wakeDependents(inst);
1570}
1571*/
1572template <class Impl>
1573void
1574FullO3CPU<Impl>::wakeCPU()
1575{
1576    if (activityRec.active() || tickEvent.scheduled()) {
1577        DPRINTF(Activity, "CPU already running.\n");
1578        return;
1579    }
1580
1581    DPRINTF(Activity, "Waking up CPU\n");
1582
1583    idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1584    numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1585
1586    schedule(tickEvent, nextCycle());
1587}
1588
1589template <class Impl>
1590void
1591FullO3CPU<Impl>::wakeup()
1592{
1593    if (this->thread[0]->status() != ThreadContext::Suspended)
1594        return;
1595
1596    this->wakeCPU();
1597
1598    DPRINTF(Quiesce, "Suspended Processor woken\n");
1599    this->threadContexts[0]->activate();
1600}
1601
1602template <class Impl>
1603ThreadID
1604FullO3CPU<Impl>::getFreeTid()
1605{
1606    for (ThreadID tid = 0; tid < numThreads; tid++) {
1607        if (!tids[tid]) {
1608            tids[tid] = true;
1609            return tid;
1610        }
1611    }
1612
1613    return InvalidThreadID;
1614}
1615
1616template <class Impl>
1617void
1618FullO3CPU<Impl>::doContextSwitch()
1619{
1620    if (contextSwitch) {
1621
1622        //ADD CODE TO DEACTIVE THREAD HERE (???)
1623
1624        ThreadID size = cpuWaitList.size();
1625        for (ThreadID tid = 0; tid < size; tid++) {
1626            activateWhenReady(tid);
1627        }
1628
1629        if (cpuWaitList.size() == 0)
1630            contextSwitch = true;
1631    }
1632}
1633
1634template <class Impl>
1635void
1636FullO3CPU<Impl>::updateThreadPriority()
1637{
1638    if (activeThreads.size() > 1) {
1639        //DEFAULT TO ROUND ROBIN SCHEME
1640        //e.g. Move highest priority to end of thread list
1641        list<ThreadID>::iterator list_begin = activeThreads.begin();
1642
1643        unsigned high_thread = *list_begin;
1644
1645        activeThreads.erase(list_begin);
1646
1647        activeThreads.push_back(high_thread);
1648    }
1649}
1650
1651// Forward declaration of FullO3CPU.
1652template class FullO3CPU<O3CPUImpl>;
1653