cpu.cc revision 8777:dd43f1c9fa0a 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 *          Korey Sewell
31 *          Rick Strong
32 */
33
34#include "config/full_system.hh"
35#include "config/the_isa.hh"
36#include "config/use_checker.hh"
37#include "cpu/o3/cpu.hh"
38#include "cpu/o3/isa_specific.hh"
39#include "cpu/o3/thread_context.hh"
40#include "cpu/activity.hh"
41#include "cpu/simple_thread.hh"
42#include "cpu/thread_context.hh"
43#include "debug/Activity.hh"
44#include "debug/O3CPU.hh"
45#include "debug/Quiesce.hh"
46#include "enums/MemoryMode.hh"
47#include "sim/core.hh"
48#include "sim/stat_control.hh"
49#include "sim/system.hh"
50
51#if FULL_SYSTEM
52#include "cpu/quiesce_event.hh"
53#else
54#include "sim/process.hh"
55#endif
56
57#if USE_CHECKER
58#include "cpu/checker/cpu.hh"
59#endif
60
61#if THE_ISA == ALPHA_ISA
62#include "arch/alpha/osfpal.hh"
63#include "debug/Activity.hh"
64#endif
65
66class BaseCPUParams;
67
68using namespace TheISA;
69using namespace std;
70
71BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
72    : BaseCPU(params)
73{
74}
75
76void
77BaseO3CPU::regStats()
78{
79    BaseCPU::regStats();
80}
81
82template <class Impl>
83FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
84    : Event(CPU_Tick_Pri), cpu(c)
85{
86}
87
88template <class Impl>
89void
90FullO3CPU<Impl>::TickEvent::process()
91{
92    cpu->tick();
93}
94
95template <class Impl>
96const char *
97FullO3CPU<Impl>::TickEvent::description() const
98{
99    return "FullO3CPU tick";
100}
101
102template <class Impl>
103FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
104    : Event(CPU_Switch_Pri)
105{
106}
107
108template <class Impl>
109void
110FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
111                                           FullO3CPU<Impl> *thread_cpu)
112{
113    tid = thread_num;
114    cpu = thread_cpu;
115}
116
117template <class Impl>
118void
119FullO3CPU<Impl>::ActivateThreadEvent::process()
120{
121    cpu->activateThread(tid);
122}
123
124template <class Impl>
125const char *
126FullO3CPU<Impl>::ActivateThreadEvent::description() const
127{
128    return "FullO3CPU \"Activate Thread\"";
129}
130
131template <class Impl>
132FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
133    : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
134{
135}
136
137template <class Impl>
138void
139FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
140                                              FullO3CPU<Impl> *thread_cpu)
141{
142    tid = thread_num;
143    cpu = thread_cpu;
144    remove = false;
145}
146
147template <class Impl>
148void
149FullO3CPU<Impl>::DeallocateContextEvent::process()
150{
151    cpu->deactivateThread(tid);
152    if (remove)
153        cpu->removeThread(tid);
154}
155
156template <class Impl>
157const char *
158FullO3CPU<Impl>::DeallocateContextEvent::description() const
159{
160    return "FullO3CPU \"Deallocate Context\"";
161}
162
163template <class Impl>
164FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
165    : BaseO3CPU(params),
166      itb(params->itb),
167      dtb(params->dtb),
168      tickEvent(this),
169#ifndef NDEBUG
170      instcount(0),
171#endif
172      removeInstsThisCycle(false),
173      fetch(this, params),
174      decode(this, params),
175      rename(this, params),
176      iew(this, params),
177      commit(this, params),
178
179      regFile(this, params->numPhysIntRegs,
180              params->numPhysFloatRegs),
181
182      freeList(params->numThreads,
183               TheISA::NumIntRegs, params->numPhysIntRegs,
184               TheISA::NumFloatRegs, params->numPhysFloatRegs),
185
186      rob(this,
187          params->numROBEntries, params->squashWidth,
188          params->smtROBPolicy, params->smtROBThreshold,
189          params->numThreads),
190
191      scoreboard(params->numThreads,
192                 TheISA::NumIntRegs, params->numPhysIntRegs,
193                 TheISA::NumFloatRegs, params->numPhysFloatRegs,
194                 TheISA::NumMiscRegs * numThreads,
195                 TheISA::ZeroReg),
196
197      timeBuffer(params->backComSize, params->forwardComSize),
198      fetchQueue(params->backComSize, params->forwardComSize),
199      decodeQueue(params->backComSize, params->forwardComSize),
200      renameQueue(params->backComSize, params->forwardComSize),
201      iewQueue(params->backComSize, params->forwardComSize),
202      activityRec(name(), NumStages,
203                  params->backComSize + params->forwardComSize,
204                  params->activity),
205
206      globalSeqNum(1),
207      system(params->system),
208      drainCount(0),
209      deferRegistration(params->defer_registration)
210{
211    if (!deferRegistration) {
212        _status = Running;
213    } else {
214        _status = Idle;
215    }
216
217#if USE_CHECKER
218    if (params->checker) {
219        BaseCPU *temp_checker = params->checker;
220        checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
221#if FULL_SYSTEM
222        checker->setSystem(params->system);
223#endif
224    } else {
225        checker = NULL;
226    }
227#endif // USE_CHECKER
228
229#if !FULL_SYSTEM
230    thread.resize(numThreads);
231    tids.resize(numThreads);
232#endif
233
234    // The stages also need their CPU pointer setup.  However this
235    // must be done at the upper level CPU because they have pointers
236    // to the upper level CPU, and not this FullO3CPU.
237
238    // Set up Pointers to the activeThreads list for each stage
239    fetch.setActiveThreads(&activeThreads);
240    decode.setActiveThreads(&activeThreads);
241    rename.setActiveThreads(&activeThreads);
242    iew.setActiveThreads(&activeThreads);
243    commit.setActiveThreads(&activeThreads);
244
245    // Give each of the stages the time buffer they will use.
246    fetch.setTimeBuffer(&timeBuffer);
247    decode.setTimeBuffer(&timeBuffer);
248    rename.setTimeBuffer(&timeBuffer);
249    iew.setTimeBuffer(&timeBuffer);
250    commit.setTimeBuffer(&timeBuffer);
251
252    // Also setup each of the stages' queues.
253    fetch.setFetchQueue(&fetchQueue);
254    decode.setFetchQueue(&fetchQueue);
255    commit.setFetchQueue(&fetchQueue);
256    decode.setDecodeQueue(&decodeQueue);
257    rename.setDecodeQueue(&decodeQueue);
258    rename.setRenameQueue(&renameQueue);
259    iew.setRenameQueue(&renameQueue);
260    iew.setIEWQueue(&iewQueue);
261    commit.setIEWQueue(&iewQueue);
262    commit.setRenameQueue(&renameQueue);
263
264    commit.setIEWStage(&iew);
265    rename.setIEWStage(&iew);
266    rename.setCommitStage(&commit);
267
268#if !FULL_SYSTEM
269    ThreadID active_threads = params->workload.size();
270
271    if (active_threads > Impl::MaxThreads) {
272        panic("Workload Size too large. Increase the 'MaxThreads'"
273              "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
274              "edit your workload size.");
275    }
276#else
277    ThreadID active_threads = 1;
278#endif
279
280    //Make Sure That this a Valid Architeture
281    assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
282    assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
283
284    rename.setScoreboard(&scoreboard);
285    iew.setScoreboard(&scoreboard);
286
287    // Setup the rename map for whichever stages need it.
288    PhysRegIndex lreg_idx = 0;
289    PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
290
291    for (ThreadID tid = 0; tid < numThreads; tid++) {
292        bool bindRegs = (tid <= active_threads - 1);
293
294        commitRenameMap[tid].init(TheISA::NumIntRegs,
295                                  params->numPhysIntRegs,
296                                  lreg_idx,            //Index for Logical. Regs
297
298                                  TheISA::NumFloatRegs,
299                                  params->numPhysFloatRegs,
300                                  freg_idx,            //Index for Float Regs
301
302                                  TheISA::NumMiscRegs,
303
304                                  TheISA::ZeroReg,
305                                  TheISA::ZeroReg,
306
307                                  tid,
308                                  false);
309
310        renameMap[tid].init(TheISA::NumIntRegs,
311                            params->numPhysIntRegs,
312                            lreg_idx,                  //Index for Logical. Regs
313
314                            TheISA::NumFloatRegs,
315                            params->numPhysFloatRegs,
316                            freg_idx,                  //Index for Float Regs
317
318                            TheISA::NumMiscRegs,
319
320                            TheISA::ZeroReg,
321                            TheISA::ZeroReg,
322
323                            tid,
324                            bindRegs);
325
326        activateThreadEvent[tid].init(tid, this);
327        deallocateContextEvent[tid].init(tid, this);
328    }
329
330    rename.setRenameMap(renameMap);
331    commit.setRenameMap(commitRenameMap);
332
333    // Give renameMap & rename stage access to the freeList;
334    for (ThreadID tid = 0; tid < numThreads; tid++)
335        renameMap[tid].setFreeList(&freeList);
336    rename.setFreeList(&freeList);
337
338    // Setup the ROB for whichever stages need it.
339    commit.setROB(&rob);
340
341    lastRunningCycle = curTick();
342
343    lastActivatedCycle = -1;
344#if 0
345    // Give renameMap & rename stage access to the freeList;
346    for (ThreadID tid = 0; tid < numThreads; tid++)
347        globalSeqNum[tid] = 1;
348#endif
349
350    contextSwitch = false;
351    DPRINTF(O3CPU, "Creating O3CPU object.\n");
352
353    // Setup any thread state.
354    this->thread.resize(this->numThreads);
355
356    for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
357#if FULL_SYSTEM
358        // SMT is not supported in FS mode yet.
359        assert(this->numThreads == 1);
360        this->thread[tid] = new Thread(this, 0, NULL);
361#else
362        if (tid < params->workload.size()) {
363            DPRINTF(O3CPU, "Workload[%i] process is %#x",
364                    tid, this->thread[tid]);
365            this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
366                    (typename Impl::O3CPU *)(this),
367                    tid, params->workload[tid]);
368
369            //usedTids[tid] = true;
370            //threadMap[tid] = tid;
371        } else {
372            //Allocate Empty thread so M5 can use later
373            //when scheduling threads to CPU
374            Process* dummy_proc = NULL;
375
376            this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
377                    (typename Impl::O3CPU *)(this),
378                    tid, dummy_proc);
379            //usedTids[tid] = false;
380        }
381#endif // !FULL_SYSTEM
382
383        ThreadContext *tc;
384
385        // Setup the TC that will serve as the interface to the threads/CPU.
386        O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
387
388        tc = o3_tc;
389
390        // If we're using a checker, then the TC should be the
391        // CheckerThreadContext.
392#if USE_CHECKER
393        if (params->checker) {
394            tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
395                o3_tc, this->checker);
396        }
397#endif
398
399        o3_tc->cpu = (typename Impl::O3CPU *)(this);
400        assert(o3_tc->cpu);
401        o3_tc->thread = this->thread[tid];
402
403#if FULL_SYSTEM
404        // Setup quiesce event.
405        this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
406#endif
407        // Give the thread the TC.
408        this->thread[tid]->tc = tc;
409
410        // Add the TC to the CPU's list of TC's.
411        this->threadContexts.push_back(tc);
412    }
413
414    for (ThreadID tid = 0; tid < this->numThreads; tid++)
415        this->thread[tid]->setFuncExeInst(0);
416
417    lockAddr = 0;
418    lockFlag = false;
419}
420
421template <class Impl>
422FullO3CPU<Impl>::~FullO3CPU()
423{
424}
425
426template <class Impl>
427void
428FullO3CPU<Impl>::regStats()
429{
430    BaseO3CPU::regStats();
431
432    // Register any of the O3CPU's stats here.
433    timesIdled
434        .name(name() + ".timesIdled")
435        .desc("Number of times that the entire CPU went into an idle state and"
436              " unscheduled itself")
437        .prereq(timesIdled);
438
439    idleCycles
440        .name(name() + ".idleCycles")
441        .desc("Total number of cycles that the CPU has spent unscheduled due "
442              "to idling")
443        .prereq(idleCycles);
444
445    // Number of Instructions simulated
446    // --------------------------------
447    // Should probably be in Base CPU but need templated
448    // MaxThreads so put in here instead
449    committedInsts
450        .init(numThreads)
451        .name(name() + ".committedInsts")
452        .desc("Number of Instructions Simulated");
453
454    totalCommittedInsts
455        .name(name() + ".committedInsts_total")
456        .desc("Number of Instructions Simulated");
457
458    cpi
459        .name(name() + ".cpi")
460        .desc("CPI: Cycles Per Instruction")
461        .precision(6);
462    cpi = numCycles / committedInsts;
463
464    totalCpi
465        .name(name() + ".cpi_total")
466        .desc("CPI: Total CPI of All Threads")
467        .precision(6);
468    totalCpi = numCycles / totalCommittedInsts;
469
470    ipc
471        .name(name() + ".ipc")
472        .desc("IPC: Instructions Per Cycle")
473        .precision(6);
474    ipc =  committedInsts / numCycles;
475
476    totalIpc
477        .name(name() + ".ipc_total")
478        .desc("IPC: Total IPC of All Threads")
479        .precision(6);
480    totalIpc =  totalCommittedInsts / numCycles;
481
482    this->fetch.regStats();
483    this->decode.regStats();
484    this->rename.regStats();
485    this->iew.regStats();
486    this->commit.regStats();
487    this->rob.regStats();
488
489    intRegfileReads
490        .name(name() + ".int_regfile_reads")
491        .desc("number of integer regfile reads")
492        .prereq(intRegfileReads);
493
494    intRegfileWrites
495        .name(name() + ".int_regfile_writes")
496        .desc("number of integer regfile writes")
497        .prereq(intRegfileWrites);
498
499    fpRegfileReads
500        .name(name() + ".fp_regfile_reads")
501        .desc("number of floating regfile reads")
502        .prereq(fpRegfileReads);
503
504    fpRegfileWrites
505        .name(name() + ".fp_regfile_writes")
506        .desc("number of floating regfile writes")
507        .prereq(fpRegfileWrites);
508
509    miscRegfileReads
510        .name(name() + ".misc_regfile_reads")
511        .desc("number of misc regfile reads")
512        .prereq(miscRegfileReads);
513
514    miscRegfileWrites
515        .name(name() + ".misc_regfile_writes")
516        .desc("number of misc regfile writes")
517        .prereq(miscRegfileWrites);
518}
519
520template <class Impl>
521Port *
522FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
523{
524    if (if_name == "dcache_port")
525        return iew.getDcachePort();
526    else if (if_name == "icache_port")
527        return fetch.getIcachePort();
528    else
529        panic("No Such Port\n");
530}
531
532template <class Impl>
533void
534FullO3CPU<Impl>::tick()
535{
536    DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
537
538    ++numCycles;
539
540//    activity = false;
541
542    //Tick each of the stages
543    fetch.tick();
544
545    decode.tick();
546
547    rename.tick();
548
549    iew.tick();
550
551    commit.tick();
552
553#if !FULL_SYSTEM
554    doContextSwitch();
555#endif
556
557    // Now advance the time buffers
558    timeBuffer.advance();
559
560    fetchQueue.advance();
561    decodeQueue.advance();
562    renameQueue.advance();
563    iewQueue.advance();
564
565    activityRec.advance();
566
567    if (removeInstsThisCycle) {
568        cleanUpRemovedInsts();
569    }
570
571    if (!tickEvent.scheduled()) {
572        if (_status == SwitchedOut ||
573            getState() == SimObject::Drained) {
574            DPRINTF(O3CPU, "Switched out!\n");
575            // increment stat
576            lastRunningCycle = curTick();
577        } else if (!activityRec.active() || _status == Idle) {
578            DPRINTF(O3CPU, "Idle!\n");
579            lastRunningCycle = curTick();
580            timesIdled++;
581        } else {
582            schedule(tickEvent, nextCycle(curTick() + ticks(1)));
583            DPRINTF(O3CPU, "Scheduling next tick!\n");
584        }
585    }
586
587#if !FULL_SYSTEM
588    updateThreadPriority();
589#endif
590}
591
592template <class Impl>
593void
594FullO3CPU<Impl>::init()
595{
596    BaseCPU::init();
597
598    // Set inSyscall so that the CPU doesn't squash when initially
599    // setting up registers.
600    for (ThreadID tid = 0; tid < numThreads; ++tid)
601        thread[tid]->inSyscall = true;
602
603#if FULL_SYSTEM
604    for (ThreadID tid = 0; tid < numThreads; tid++) {
605        ThreadContext *src_tc = threadContexts[tid];
606        TheISA::initCPU(src_tc, src_tc->contextId());
607    }
608#endif
609
610    // Clear inSyscall.
611    for (int tid = 0; tid < numThreads; ++tid)
612        thread[tid]->inSyscall = false;
613
614    // Initialize stages.
615    fetch.initStage();
616    iew.initStage();
617    rename.initStage();
618    commit.initStage();
619
620    commit.setThreads(thread);
621}
622
623template <class Impl>
624void
625FullO3CPU<Impl>::activateThread(ThreadID tid)
626{
627    list<ThreadID>::iterator isActive =
628        std::find(activeThreads.begin(), activeThreads.end(), tid);
629
630    DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
631
632    if (isActive == activeThreads.end()) {
633        DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
634                tid);
635
636        activeThreads.push_back(tid);
637    }
638}
639
640template <class Impl>
641void
642FullO3CPU<Impl>::deactivateThread(ThreadID tid)
643{
644    //Remove From Active List, if Active
645    list<ThreadID>::iterator thread_it =
646        std::find(activeThreads.begin(), activeThreads.end(), tid);
647
648    DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
649
650    if (thread_it != activeThreads.end()) {
651        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
652                tid);
653        activeThreads.erase(thread_it);
654    }
655}
656
657template <class Impl>
658Counter
659FullO3CPU<Impl>::totalInstructions() const
660{
661    Counter total(0);
662
663    ThreadID size = thread.size();
664    for (ThreadID i = 0; i < size; i++)
665        total += thread[i]->numInst;
666
667    return total;
668}
669
670template <class Impl>
671void
672FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
673{
674    // Needs to set each stage to running as well.
675    if (delay){
676        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
677                "on cycle %d\n", tid, curTick() + ticks(delay));
678        scheduleActivateThreadEvent(tid, delay);
679    } else {
680        activateThread(tid);
681    }
682
683    if (lastActivatedCycle < curTick()) {
684        scheduleTickEvent(delay);
685
686        // Be sure to signal that there's some activity so the CPU doesn't
687        // deschedule itself.
688        activityRec.activity();
689        fetch.wakeFromQuiesce();
690
691        lastActivatedCycle = curTick();
692
693        _status = Running;
694    }
695}
696
697template <class Impl>
698bool
699FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay)
700{
701    // Schedule removal of thread data from CPU
702    if (delay){
703        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
704                "on cycle %d\n", tid, curTick() + ticks(delay));
705        scheduleDeallocateContextEvent(tid, remove, delay);
706        return false;
707    } else {
708        deactivateThread(tid);
709        if (remove)
710            removeThread(tid);
711        return true;
712    }
713}
714
715template <class Impl>
716void
717FullO3CPU<Impl>::suspendContext(ThreadID tid)
718{
719    DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
720    bool deallocated = deallocateContext(tid, false, 1);
721    // If this was the last thread then unschedule the tick event.
722    if ((activeThreads.size() == 1 && !deallocated) ||
723        activeThreads.size() == 0)
724        unscheduleTickEvent();
725    _status = Idle;
726}
727
728template <class Impl>
729void
730FullO3CPU<Impl>::haltContext(ThreadID tid)
731{
732    //For now, this is the same as deallocate
733    DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
734    deallocateContext(tid, true, 1);
735}
736
737template <class Impl>
738void
739FullO3CPU<Impl>::insertThread(ThreadID tid)
740{
741    DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
742    // Will change now that the PC and thread state is internal to the CPU
743    // and not in the ThreadContext.
744#if FULL_SYSTEM
745    ThreadContext *src_tc = system->threadContexts[tid];
746#else
747    ThreadContext *src_tc = tcBase(tid);
748#endif
749
750    //Bind Int Regs to Rename Map
751    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
752        PhysRegIndex phys_reg = freeList.getIntReg();
753
754        renameMap[tid].setEntry(ireg,phys_reg);
755        scoreboard.setReg(phys_reg);
756    }
757
758    //Bind Float Regs to Rename Map
759    for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
760        PhysRegIndex phys_reg = freeList.getFloatReg();
761
762        renameMap[tid].setEntry(freg,phys_reg);
763        scoreboard.setReg(phys_reg);
764    }
765
766    //Copy Thread Data Into RegFile
767    //this->copyFromTC(tid);
768
769    //Set PC/NPC/NNPC
770    pcState(src_tc->pcState(), tid);
771
772    src_tc->setStatus(ThreadContext::Active);
773
774    activateContext(tid,1);
775
776    //Reset ROB/IQ/LSQ Entries
777    commit.rob->resetEntries();
778    iew.resetEntries();
779}
780
781template <class Impl>
782void
783FullO3CPU<Impl>::removeThread(ThreadID tid)
784{
785    DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
786
787    // Copy Thread Data From RegFile
788    // If thread is suspended, it might be re-allocated
789    // this->copyToTC(tid);
790
791
792    // @todo: 2-27-2008: Fix how we free up rename mappings
793    // here to alleviate the case for double-freeing registers
794    // in SMT workloads.
795
796    // Unbind Int Regs from Rename Map
797    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
798        PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
799
800        scoreboard.unsetReg(phys_reg);
801        freeList.addReg(phys_reg);
802    }
803
804    // Unbind Float Regs from Rename Map
805    for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
806        PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
807
808        scoreboard.unsetReg(phys_reg);
809        freeList.addReg(phys_reg);
810    }
811
812    // Squash Throughout Pipeline
813    DynInstPtr inst = commit.rob->readHeadInst(tid);
814    InstSeqNum squash_seq_num = inst->seqNum;
815    fetch.squash(0, squash_seq_num, inst, tid);
816    decode.squash(tid);
817    rename.squash(squash_seq_num, tid);
818    iew.squash(tid);
819    iew.ldstQueue.squash(squash_seq_num, tid);
820    commit.rob->squash(squash_seq_num, tid);
821
822
823    assert(iew.instQueue.getCount(tid) == 0);
824    assert(iew.ldstQueue.getCount(tid) == 0);
825
826    // Reset ROB/IQ/LSQ Entries
827
828    // Commented out for now.  This should be possible to do by
829    // telling all the pipeline stages to drain first, and then
830    // checking until the drain completes.  Once the pipeline is
831    // drained, call resetEntries(). - 10-09-06 ktlim
832/*
833    if (activeThreads.size() >= 1) {
834        commit.rob->resetEntries();
835        iew.resetEntries();
836    }
837*/
838}
839
840
841template <class Impl>
842void
843FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
844{
845    DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
846            "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
847            tid);
848
849    bool ready = true;
850
851    if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
852        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
853                "Phys. Int. Regs.\n",
854                tid);
855        ready = false;
856    } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
857        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
858                "Phys. Float. Regs.\n",
859                tid);
860        ready = false;
861    } else if (commit.rob->numFreeEntries() >=
862               commit.rob->entryAmount(activeThreads.size() + 1)) {
863        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
864                "ROB entries.\n",
865                tid);
866        ready = false;
867    } else if (iew.instQueue.numFreeEntries() >=
868               iew.instQueue.entryAmount(activeThreads.size() + 1)) {
869        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
870                "IQ entries.\n",
871                tid);
872        ready = false;
873    } else if (iew.ldstQueue.numFreeEntries() >=
874               iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
875        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
876                "LSQ entries.\n",
877                tid);
878        ready = false;
879    }
880
881    if (ready) {
882        insertThread(tid);
883
884        contextSwitch = false;
885
886        cpuWaitList.remove(tid);
887    } else {
888        suspendContext(tid);
889
890        //blocks fetch
891        contextSwitch = true;
892
893        //@todo: dont always add to waitlist
894        //do waitlist
895        cpuWaitList.push_back(tid);
896    }
897}
898
899#if FULL_SYSTEM
900template <class Impl>
901Fault
902FullO3CPU<Impl>::hwrei(ThreadID tid)
903{
904#if THE_ISA == ALPHA_ISA
905    // Need to clear the lock flag upon returning from an interrupt.
906    this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
907
908    this->thread[tid]->kernelStats->hwrei();
909
910    // FIXME: XXX check for interrupts? XXX
911#endif
912    return NoFault;
913}
914
915template <class Impl>
916bool
917FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
918{
919#if THE_ISA == ALPHA_ISA
920    if (this->thread[tid]->kernelStats)
921        this->thread[tid]->kernelStats->callpal(palFunc,
922                                                this->threadContexts[tid]);
923
924    switch (palFunc) {
925      case PAL::halt:
926        halt();
927        if (--System::numSystemsRunning == 0)
928            exitSimLoop("all cpus halted");
929        break;
930
931      case PAL::bpt:
932      case PAL::bugchk:
933        if (this->system->breakpoint())
934            return false;
935        break;
936    }
937#endif
938    return true;
939}
940
941template <class Impl>
942Fault
943FullO3CPU<Impl>::getInterrupts()
944{
945    // Check if there are any outstanding interrupts
946    return this->interrupts->getInterrupt(this->threadContexts[0]);
947}
948
949template <class Impl>
950void
951FullO3CPU<Impl>::processInterrupts(Fault interrupt)
952{
953    // Check for interrupts here.  For now can copy the code that
954    // exists within isa_fullsys_traits.hh.  Also assume that thread 0
955    // is the one that handles the interrupts.
956    // @todo: Possibly consolidate the interrupt checking code.
957    // @todo: Allow other threads to handle interrupts.
958
959    assert(interrupt != NoFault);
960    this->interrupts->updateIntrInfo(this->threadContexts[0]);
961
962    DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
963    this->trap(interrupt, 0, NULL);
964}
965
966template <class Impl>
967void
968FullO3CPU<Impl>::updateMemPorts()
969{
970    // Update all ThreadContext's memory ports (Functional/Virtual
971    // Ports)
972    ThreadID size = thread.size();
973    for (ThreadID i = 0; i < size; ++i)
974        thread[i]->connectMemPorts(thread[i]->getTC());
975}
976#endif
977
978template <class Impl>
979void
980FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
981{
982    // Pass the thread's TC into the invoke method.
983    fault->invoke(this->threadContexts[tid], inst);
984}
985
986template <class Impl>
987void
988FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
989{
990    DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
991
992    DPRINTF(Activity,"Activity: syscall() called.\n");
993
994    // Temporarily increase this by one to account for the syscall
995    // instruction.
996    ++(this->thread[tid]->funcExeInst);
997
998    // Execute the actual syscall.
999    this->thread[tid]->syscall(callnum);
1000
1001    // Decrease funcExeInst by one as the normal commit will handle
1002    // incrementing it.
1003    --(this->thread[tid]->funcExeInst);
1004}
1005
1006template <class Impl>
1007void
1008FullO3CPU<Impl>::serialize(std::ostream &os)
1009{
1010    SimObject::State so_state = SimObject::getState();
1011    SERIALIZE_ENUM(so_state);
1012    BaseCPU::serialize(os);
1013    nameOut(os, csprintf("%s.tickEvent", name()));
1014    tickEvent.serialize(os);
1015
1016    // Use SimpleThread's ability to checkpoint to make it easier to
1017    // write out the registers.  Also make this static so it doesn't
1018    // get instantiated multiple times (causes a panic in statistics).
1019    static SimpleThread temp;
1020
1021    ThreadID size = thread.size();
1022    for (ThreadID i = 0; i < size; i++) {
1023        nameOut(os, csprintf("%s.xc.%i", name(), i));
1024        temp.copyTC(thread[i]->getTC());
1025        temp.serialize(os);
1026    }
1027}
1028
1029template <class Impl>
1030void
1031FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
1032{
1033    SimObject::State so_state;
1034    UNSERIALIZE_ENUM(so_state);
1035    BaseCPU::unserialize(cp, section);
1036    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1037
1038    // Use SimpleThread's ability to checkpoint to make it easier to
1039    // read in the registers.  Also make this static so it doesn't
1040    // get instantiated multiple times (causes a panic in statistics).
1041    static SimpleThread temp;
1042
1043    ThreadID size = thread.size();
1044    for (ThreadID i = 0; i < size; i++) {
1045        temp.copyTC(thread[i]->getTC());
1046        temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1047        thread[i]->getTC()->copyArchRegs(temp.getTC());
1048    }
1049}
1050
1051template <class Impl>
1052unsigned int
1053FullO3CPU<Impl>::drain(Event *drain_event)
1054{
1055    DPRINTF(O3CPU, "Switching out\n");
1056
1057    // If the CPU isn't doing anything, then return immediately.
1058    if (_status == Idle || _status == SwitchedOut) {
1059        return 0;
1060    }
1061
1062    drainCount = 0;
1063    fetch.drain();
1064    decode.drain();
1065    rename.drain();
1066    iew.drain();
1067    commit.drain();
1068
1069    // Wake the CPU and record activity so everything can drain out if
1070    // the CPU was not able to immediately drain.
1071    if (getState() != SimObject::Drained) {
1072        // A bit of a hack...set the drainEvent after all the drain()
1073        // calls have been made, that way if all of the stages drain
1074        // immediately, the signalDrained() function knows not to call
1075        // process on the drain event.
1076        drainEvent = drain_event;
1077
1078        wakeCPU();
1079        activityRec.activity();
1080
1081        return 1;
1082    } else {
1083        return 0;
1084    }
1085}
1086
1087template <class Impl>
1088void
1089FullO3CPU<Impl>::resume()
1090{
1091    fetch.resume();
1092    decode.resume();
1093    rename.resume();
1094    iew.resume();
1095    commit.resume();
1096
1097    changeState(SimObject::Running);
1098
1099    if (_status == SwitchedOut || _status == Idle)
1100        return;
1101
1102    assert(system->getMemoryMode() == Enums::timing);
1103
1104    if (!tickEvent.scheduled())
1105        schedule(tickEvent, nextCycle());
1106    _status = Running;
1107}
1108
1109template <class Impl>
1110void
1111FullO3CPU<Impl>::signalDrained()
1112{
1113    if (++drainCount == NumStages) {
1114        if (tickEvent.scheduled())
1115            tickEvent.squash();
1116
1117        changeState(SimObject::Drained);
1118
1119        BaseCPU::switchOut();
1120
1121        if (drainEvent) {
1122            drainEvent->process();
1123            drainEvent = NULL;
1124        }
1125    }
1126    assert(drainCount <= 5);
1127}
1128
1129template <class Impl>
1130void
1131FullO3CPU<Impl>::switchOut()
1132{
1133    fetch.switchOut();
1134    rename.switchOut();
1135    iew.switchOut();
1136    commit.switchOut();
1137    instList.clear();
1138    while (!removeList.empty()) {
1139        removeList.pop();
1140    }
1141
1142    _status = SwitchedOut;
1143#if USE_CHECKER
1144    if (checker)
1145        checker->switchOut();
1146#endif
1147    if (tickEvent.scheduled())
1148        tickEvent.squash();
1149}
1150
1151template <class Impl>
1152void
1153FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1154{
1155    // Flush out any old data from the time buffers.
1156    for (int i = 0; i < timeBuffer.getSize(); ++i) {
1157        timeBuffer.advance();
1158        fetchQueue.advance();
1159        decodeQueue.advance();
1160        renameQueue.advance();
1161        iewQueue.advance();
1162    }
1163
1164    activityRec.reset();
1165
1166    BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort());
1167
1168    fetch.takeOverFrom();
1169    decode.takeOverFrom();
1170    rename.takeOverFrom();
1171    iew.takeOverFrom();
1172    commit.takeOverFrom();
1173
1174    assert(!tickEvent.scheduled() || tickEvent.squashed());
1175
1176    // @todo: Figure out how to properly select the tid to put onto
1177    // the active threads list.
1178    ThreadID tid = 0;
1179
1180    list<ThreadID>::iterator isActive =
1181        std::find(activeThreads.begin(), activeThreads.end(), tid);
1182
1183    if (isActive == activeThreads.end()) {
1184        //May Need to Re-code this if the delay variable is the delay
1185        //needed for thread to activate
1186        DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1187                tid);
1188
1189        activeThreads.push_back(tid);
1190    }
1191
1192    // Set all statuses to active, schedule the CPU's tick event.
1193    // @todo: Fix up statuses so this is handled properly
1194    ThreadID size = threadContexts.size();
1195    for (ThreadID i = 0; i < size; ++i) {
1196        ThreadContext *tc = threadContexts[i];
1197        if (tc->status() == ThreadContext::Active && _status != Running) {
1198            _status = Running;
1199            reschedule(tickEvent, nextCycle(), true);
1200        }
1201    }
1202    if (!tickEvent.scheduled())
1203        schedule(tickEvent, nextCycle());
1204}
1205
1206template <class Impl>
1207TheISA::MiscReg
1208FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1209{
1210    return this->isa[tid].readMiscRegNoEffect(misc_reg);
1211}
1212
1213template <class Impl>
1214TheISA::MiscReg
1215FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1216{
1217    miscRegfileReads++;
1218    return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1219}
1220
1221template <class Impl>
1222void
1223FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1224        const TheISA::MiscReg &val, ThreadID tid)
1225{
1226    this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1227}
1228
1229template <class Impl>
1230void
1231FullO3CPU<Impl>::setMiscReg(int misc_reg,
1232        const TheISA::MiscReg &val, ThreadID tid)
1233{
1234    miscRegfileWrites++;
1235    this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1236}
1237
1238template <class Impl>
1239uint64_t
1240FullO3CPU<Impl>::readIntReg(int reg_idx)
1241{
1242    intRegfileReads++;
1243    return regFile.readIntReg(reg_idx);
1244}
1245
1246template <class Impl>
1247FloatReg
1248FullO3CPU<Impl>::readFloatReg(int reg_idx)
1249{
1250    fpRegfileReads++;
1251    return regFile.readFloatReg(reg_idx);
1252}
1253
1254template <class Impl>
1255FloatRegBits
1256FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1257{
1258    fpRegfileReads++;
1259    return regFile.readFloatRegBits(reg_idx);
1260}
1261
1262template <class Impl>
1263void
1264FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1265{
1266    intRegfileWrites++;
1267    regFile.setIntReg(reg_idx, val);
1268}
1269
1270template <class Impl>
1271void
1272FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1273{
1274    fpRegfileWrites++;
1275    regFile.setFloatReg(reg_idx, val);
1276}
1277
1278template <class Impl>
1279void
1280FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1281{
1282    fpRegfileWrites++;
1283    regFile.setFloatRegBits(reg_idx, val);
1284}
1285
1286template <class Impl>
1287uint64_t
1288FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1289{
1290    intRegfileReads++;
1291    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1292
1293    return regFile.readIntReg(phys_reg);
1294}
1295
1296template <class Impl>
1297float
1298FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1299{
1300    fpRegfileReads++;
1301    int idx = reg_idx + TheISA::NumIntRegs;
1302    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1303
1304    return regFile.readFloatReg(phys_reg);
1305}
1306
1307template <class Impl>
1308uint64_t
1309FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1310{
1311    fpRegfileReads++;
1312    int idx = reg_idx + TheISA::NumIntRegs;
1313    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1314
1315    return regFile.readFloatRegBits(phys_reg);
1316}
1317
1318template <class Impl>
1319void
1320FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1321{
1322    intRegfileWrites++;
1323    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1324
1325    regFile.setIntReg(phys_reg, val);
1326}
1327
1328template <class Impl>
1329void
1330FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1331{
1332    fpRegfileWrites++;
1333    int idx = reg_idx + TheISA::NumIntRegs;
1334    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1335
1336    regFile.setFloatReg(phys_reg, val);
1337}
1338
1339template <class Impl>
1340void
1341FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1342{
1343    fpRegfileWrites++;
1344    int idx = reg_idx + TheISA::NumIntRegs;
1345    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1346
1347    regFile.setFloatRegBits(phys_reg, val);
1348}
1349
1350template <class Impl>
1351TheISA::PCState
1352FullO3CPU<Impl>::pcState(ThreadID tid)
1353{
1354    return commit.pcState(tid);
1355}
1356
1357template <class Impl>
1358void
1359FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1360{
1361    commit.pcState(val, tid);
1362}
1363
1364template <class Impl>
1365Addr
1366FullO3CPU<Impl>::instAddr(ThreadID tid)
1367{
1368    return commit.instAddr(tid);
1369}
1370
1371template <class Impl>
1372Addr
1373FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1374{
1375    return commit.nextInstAddr(tid);
1376}
1377
1378template <class Impl>
1379MicroPC
1380FullO3CPU<Impl>::microPC(ThreadID tid)
1381{
1382    return commit.microPC(tid);
1383}
1384
1385template <class Impl>
1386void
1387FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1388{
1389    this->thread[tid]->inSyscall = true;
1390    this->commit.generateTCEvent(tid);
1391}
1392
1393template <class Impl>
1394typename FullO3CPU<Impl>::ListIt
1395FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1396{
1397    instList.push_back(inst);
1398
1399    return --(instList.end());
1400}
1401
1402template <class Impl>
1403void
1404FullO3CPU<Impl>::instDone(ThreadID tid)
1405{
1406    // Keep an instruction count.
1407    thread[tid]->numInst++;
1408    thread[tid]->numInsts++;
1409    committedInsts[tid]++;
1410    totalCommittedInsts++;
1411    system->totalNumInsts++;
1412    // Check for instruction-count-based events.
1413    comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1414    system->instEventQueue.serviceEvents(system->totalNumInsts);
1415}
1416
1417template <class Impl>
1418void
1419FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1420{
1421    DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1422            "[sn:%lli]\n",
1423            inst->threadNumber, inst->pcState(), inst->seqNum);
1424
1425    removeInstsThisCycle = true;
1426
1427    // Remove the front instruction.
1428    removeList.push(inst->getInstListIt());
1429}
1430
1431template <class Impl>
1432void
1433FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1434{
1435    DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1436            " list.\n", tid);
1437
1438    ListIt end_it;
1439
1440    bool rob_empty = false;
1441
1442    if (instList.empty()) {
1443        return;
1444    } else if (rob.isEmpty(/*tid*/)) {
1445        DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1446        end_it = instList.begin();
1447        rob_empty = true;
1448    } else {
1449        end_it = (rob.readTailInst(tid))->getInstListIt();
1450        DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1451    }
1452
1453    removeInstsThisCycle = true;
1454
1455    ListIt inst_it = instList.end();
1456
1457    inst_it--;
1458
1459    // Walk through the instruction list, removing any instructions
1460    // that were inserted after the given instruction iterator, end_it.
1461    while (inst_it != end_it) {
1462        assert(!instList.empty());
1463
1464        squashInstIt(inst_it, tid);
1465
1466        inst_it--;
1467    }
1468
1469    // If the ROB was empty, then we actually need to remove the first
1470    // instruction as well.
1471    if (rob_empty) {
1472        squashInstIt(inst_it, tid);
1473    }
1474}
1475
1476template <class Impl>
1477void
1478FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1479{
1480    assert(!instList.empty());
1481
1482    removeInstsThisCycle = true;
1483
1484    ListIt inst_iter = instList.end();
1485
1486    inst_iter--;
1487
1488    DPRINTF(O3CPU, "Deleting instructions from instruction "
1489            "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1490            tid, seq_num, (*inst_iter)->seqNum);
1491
1492    while ((*inst_iter)->seqNum > seq_num) {
1493
1494        bool break_loop = (inst_iter == instList.begin());
1495
1496        squashInstIt(inst_iter, tid);
1497
1498        inst_iter--;
1499
1500        if (break_loop)
1501            break;
1502    }
1503}
1504
1505template <class Impl>
1506inline void
1507FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1508{
1509    if ((*instIt)->threadNumber == tid) {
1510        DPRINTF(O3CPU, "Squashing instruction, "
1511                "[tid:%i] [sn:%lli] PC %s\n",
1512                (*instIt)->threadNumber,
1513                (*instIt)->seqNum,
1514                (*instIt)->pcState());
1515
1516        // Mark it as squashed.
1517        (*instIt)->setSquashed();
1518
1519        // @todo: Formulate a consistent method for deleting
1520        // instructions from the instruction list
1521        // Remove the instruction from the list.
1522        removeList.push(instIt);
1523    }
1524}
1525
1526template <class Impl>
1527void
1528FullO3CPU<Impl>::cleanUpRemovedInsts()
1529{
1530    while (!removeList.empty()) {
1531        DPRINTF(O3CPU, "Removing instruction, "
1532                "[tid:%i] [sn:%lli] PC %s\n",
1533                (*removeList.front())->threadNumber,
1534                (*removeList.front())->seqNum,
1535                (*removeList.front())->pcState());
1536
1537        instList.erase(removeList.front());
1538
1539        removeList.pop();
1540    }
1541
1542    removeInstsThisCycle = false;
1543}
1544/*
1545template <class Impl>
1546void
1547FullO3CPU<Impl>::removeAllInsts()
1548{
1549    instList.clear();
1550}
1551*/
1552template <class Impl>
1553void
1554FullO3CPU<Impl>::dumpInsts()
1555{
1556    int num = 0;
1557
1558    ListIt inst_list_it = instList.begin();
1559
1560    cprintf("Dumping Instruction List\n");
1561
1562    while (inst_list_it != instList.end()) {
1563        cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1564                "Squashed:%i\n\n",
1565                num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1566                (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1567                (*inst_list_it)->isSquashed());
1568        inst_list_it++;
1569        ++num;
1570    }
1571}
1572/*
1573template <class Impl>
1574void
1575FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1576{
1577    iew.wakeDependents(inst);
1578}
1579*/
1580template <class Impl>
1581void
1582FullO3CPU<Impl>::wakeCPU()
1583{
1584    if (activityRec.active() || tickEvent.scheduled()) {
1585        DPRINTF(Activity, "CPU already running.\n");
1586        return;
1587    }
1588
1589    DPRINTF(Activity, "Waking up CPU\n");
1590
1591    idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1592    numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1593
1594    schedule(tickEvent, nextCycle());
1595}
1596
1597#if FULL_SYSTEM
1598template <class Impl>
1599void
1600FullO3CPU<Impl>::wakeup()
1601{
1602    if (this->thread[0]->status() != ThreadContext::Suspended)
1603        return;
1604
1605    this->wakeCPU();
1606
1607    DPRINTF(Quiesce, "Suspended Processor woken\n");
1608    this->threadContexts[0]->activate();
1609}
1610#endif
1611
1612template <class Impl>
1613ThreadID
1614FullO3CPU<Impl>::getFreeTid()
1615{
1616    for (ThreadID tid = 0; tid < numThreads; tid++) {
1617        if (!tids[tid]) {
1618            tids[tid] = true;
1619            return tid;
1620        }
1621    }
1622
1623    return InvalidThreadID;
1624}
1625
1626template <class Impl>
1627void
1628FullO3CPU<Impl>::doContextSwitch()
1629{
1630    if (contextSwitch) {
1631
1632        //ADD CODE TO DEACTIVE THREAD HERE (???)
1633
1634        ThreadID size = cpuWaitList.size();
1635        for (ThreadID tid = 0; tid < size; tid++) {
1636            activateWhenReady(tid);
1637        }
1638
1639        if (cpuWaitList.size() == 0)
1640            contextSwitch = true;
1641    }
1642}
1643
1644template <class Impl>
1645void
1646FullO3CPU<Impl>::updateThreadPriority()
1647{
1648    if (activeThreads.size() > 1) {
1649        //DEFAULT TO ROUND ROBIN SCHEME
1650        //e.g. Move highest priority to end of thread list
1651        list<ThreadID>::iterator list_begin = activeThreads.begin();
1652        list<ThreadID>::iterator list_end   = activeThreads.end();
1653
1654        unsigned high_thread = *list_begin;
1655
1656        activeThreads.erase(list_begin);
1657
1658        activeThreads.push_back(high_thread);
1659    }
1660}
1661
1662// Forward declaration of FullO3CPU.
1663template class FullO3CPU<O3CPUImpl>;
1664