cpu.cc revision 8737:770ccf3af571 
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Korey Sewell
43 *          Rick Strong
44 */
45
46#include "config/full_system.hh"
47#include "config/the_isa.hh"
48#include "config/use_checker.hh"
49#include "cpu/o3/cpu.hh"
50#include "cpu/o3/isa_specific.hh"
51#include "cpu/o3/thread_context.hh"
52#include "cpu/activity.hh"
53#include "cpu/simple_thread.hh"
54#include "cpu/thread_context.hh"
55#include "debug/Activity.hh"
56#include "debug/O3CPU.hh"
57#include "debug/Quiesce.hh"
58#include "enums/MemoryMode.hh"
59#include "sim/core.hh"
60#include "sim/stat_control.hh"
61#include "sim/system.hh"
62
63#if FULL_SYSTEM
64#include "cpu/quiesce_event.hh"
65#else
66#include "sim/process.hh"
67#endif
68
69#if USE_CHECKER
70#include "cpu/checker/cpu.hh"
71#include "cpu/checker/thread_context.hh"
72#endif
73
74#if THE_ISA == ALPHA_ISA
75#include "arch/alpha/osfpal.hh"
76#include "debug/Activity.hh"
77#endif
78
79struct BaseCPUParams;
80
81using namespace TheISA;
82using namespace std;
83
84BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
85    : BaseCPU(params)
86{
87}
88
89void
90BaseO3CPU::regStats()
91{
92    BaseCPU::regStats();
93}
94
95template<class Impl>
96bool
97FullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt)
98{
99    DPRINTF(O3CPU, "Fetch unit received timing\n");
100    if (pkt->isResponse()) {
101        // We shouldn't ever get a block in ownership state
102        assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
103
104        fetch->processCacheCompletion(pkt);
105    }
106    //else Snooped a coherence request, just return
107    return true;
108}
109
110template<class Impl>
111void
112FullO3CPU<Impl>::IcachePort::recvRetry()
113{
114    fetch->recvRetry();
115}
116
117template <class Impl>
118bool
119FullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt)
120{
121    return lsq->recvTiming(pkt);
122}
123
124template <class Impl>
125void
126FullO3CPU<Impl>::DcachePort::recvRetry()
127{
128    lsq->recvRetry();
129}
130
131template <class Impl>
132FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
133    : Event(CPU_Tick_Pri), cpu(c)
134{
135}
136
137template <class Impl>
138void
139FullO3CPU<Impl>::TickEvent::process()
140{
141    cpu->tick();
142}
143
144template <class Impl>
145const char *
146FullO3CPU<Impl>::TickEvent::description() const
147{
148    return "FullO3CPU tick";
149}
150
151template <class Impl>
152FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
153    : Event(CPU_Switch_Pri)
154{
155}
156
157template <class Impl>
158void
159FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
160                                           FullO3CPU<Impl> *thread_cpu)
161{
162    tid = thread_num;
163    cpu = thread_cpu;
164}
165
166template <class Impl>
167void
168FullO3CPU<Impl>::ActivateThreadEvent::process()
169{
170    cpu->activateThread(tid);
171}
172
173template <class Impl>
174const char *
175FullO3CPU<Impl>::ActivateThreadEvent::description() const
176{
177    return "FullO3CPU \"Activate Thread\"";
178}
179
180template <class Impl>
181FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
182    : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
183{
184}
185
186template <class Impl>
187void
188FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
189                                              FullO3CPU<Impl> *thread_cpu)
190{
191    tid = thread_num;
192    cpu = thread_cpu;
193    remove = false;
194}
195
196template <class Impl>
197void
198FullO3CPU<Impl>::DeallocateContextEvent::process()
199{
200    cpu->deactivateThread(tid);
201    if (remove)
202        cpu->removeThread(tid);
203}
204
205template <class Impl>
206const char *
207FullO3CPU<Impl>::DeallocateContextEvent::description() const
208{
209    return "FullO3CPU \"Deallocate Context\"";
210}
211
212template <class Impl>
213FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
214    : BaseO3CPU(params),
215      itb(params->itb),
216      dtb(params->dtb),
217      tickEvent(this),
218#ifndef NDEBUG
219      instcount(0),
220#endif
221      removeInstsThisCycle(false),
222      fetch(this, params),
223      decode(this, params),
224      rename(this, params),
225      iew(this, params),
226      commit(this, params),
227
228      regFile(this, params->numPhysIntRegs,
229              params->numPhysFloatRegs),
230
231      freeList(params->numThreads,
232               TheISA::NumIntRegs, params->numPhysIntRegs,
233               TheISA::NumFloatRegs, params->numPhysFloatRegs),
234
235      rob(this,
236          params->numROBEntries, params->squashWidth,
237          params->smtROBPolicy, params->smtROBThreshold,
238          params->numThreads),
239
240      scoreboard(params->numThreads,
241                 TheISA::NumIntRegs, params->numPhysIntRegs,
242                 TheISA::NumFloatRegs, params->numPhysFloatRegs,
243                 TheISA::NumMiscRegs * numThreads,
244                 TheISA::ZeroReg),
245
246      icachePort(&fetch, this),
247      dcachePort(&iew.ldstQueue, this),
248
249      timeBuffer(params->backComSize, params->forwardComSize),
250      fetchQueue(params->backComSize, params->forwardComSize),
251      decodeQueue(params->backComSize, params->forwardComSize),
252      renameQueue(params->backComSize, params->forwardComSize),
253      iewQueue(params->backComSize, params->forwardComSize),
254      activityRec(name(), NumStages,
255                  params->backComSize + params->forwardComSize,
256                  params->activity),
257
258      globalSeqNum(1),
259      system(params->system),
260      drainCount(0),
261      deferRegistration(params->defer_registration)
262{
263    if (!deferRegistration) {
264        _status = Running;
265    } else {
266        _status = Idle;
267    }
268
269#if USE_CHECKER
270    if (params->checker) {
271        BaseCPU *temp_checker = params->checker;
272        checker = dynamic_cast<Checker<Impl> *>(temp_checker);
273        checker->setIcachePort(&icachePort);
274#if FULL_SYSTEM
275        checker->setSystem(params->system);
276#endif
277    } else {
278        checker = NULL;
279    }
280#endif // USE_CHECKER
281
282#if !FULL_SYSTEM
283    thread.resize(numThreads);
284    tids.resize(numThreads);
285#endif
286
287    // The stages also need their CPU pointer setup.  However this
288    // must be done at the upper level CPU because they have pointers
289    // to the upper level CPU, and not this FullO3CPU.
290
291    // Set up Pointers to the activeThreads list for each stage
292    fetch.setActiveThreads(&activeThreads);
293    decode.setActiveThreads(&activeThreads);
294    rename.setActiveThreads(&activeThreads);
295    iew.setActiveThreads(&activeThreads);
296    commit.setActiveThreads(&activeThreads);
297
298    // Give each of the stages the time buffer they will use.
299    fetch.setTimeBuffer(&timeBuffer);
300    decode.setTimeBuffer(&timeBuffer);
301    rename.setTimeBuffer(&timeBuffer);
302    iew.setTimeBuffer(&timeBuffer);
303    commit.setTimeBuffer(&timeBuffer);
304
305    // Also setup each of the stages' queues.
306    fetch.setFetchQueue(&fetchQueue);
307    decode.setFetchQueue(&fetchQueue);
308    commit.setFetchQueue(&fetchQueue);
309    decode.setDecodeQueue(&decodeQueue);
310    rename.setDecodeQueue(&decodeQueue);
311    rename.setRenameQueue(&renameQueue);
312    iew.setRenameQueue(&renameQueue);
313    iew.setIEWQueue(&iewQueue);
314    commit.setIEWQueue(&iewQueue);
315    commit.setRenameQueue(&renameQueue);
316
317    commit.setIEWStage(&iew);
318    rename.setIEWStage(&iew);
319    rename.setCommitStage(&commit);
320
321#if !FULL_SYSTEM
322    ThreadID active_threads = params->workload.size();
323
324    if (active_threads > Impl::MaxThreads) {
325        panic("Workload Size too large. Increase the 'MaxThreads'"
326              "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
327              "edit your workload size.");
328    }
329#else
330    ThreadID active_threads = 1;
331#endif
332
333    //Make Sure That this a Valid Architeture
334    assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
335    assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
336
337    rename.setScoreboard(&scoreboard);
338    iew.setScoreboard(&scoreboard);
339
340    // Setup the rename map for whichever stages need it.
341    PhysRegIndex lreg_idx = 0;
342    PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
343
344    for (ThreadID tid = 0; tid < numThreads; tid++) {
345        bool bindRegs = (tid <= active_threads - 1);
346
347        commitRenameMap[tid].init(TheISA::NumIntRegs,
348                                  params->numPhysIntRegs,
349                                  lreg_idx,            //Index for Logical. Regs
350
351                                  TheISA::NumFloatRegs,
352                                  params->numPhysFloatRegs,
353                                  freg_idx,            //Index for Float Regs
354
355                                  TheISA::NumMiscRegs,
356
357                                  TheISA::ZeroReg,
358                                  TheISA::ZeroReg,
359
360                                  tid,
361                                  false);
362
363        renameMap[tid].init(TheISA::NumIntRegs,
364                            params->numPhysIntRegs,
365                            lreg_idx,                  //Index for Logical. Regs
366
367                            TheISA::NumFloatRegs,
368                            params->numPhysFloatRegs,
369                            freg_idx,                  //Index for Float Regs
370
371                            TheISA::NumMiscRegs,
372
373                            TheISA::ZeroReg,
374                            TheISA::ZeroReg,
375
376                            tid,
377                            bindRegs);
378
379        activateThreadEvent[tid].init(tid, this);
380        deallocateContextEvent[tid].init(tid, this);
381    }
382
383    rename.setRenameMap(renameMap);
384    commit.setRenameMap(commitRenameMap);
385
386    // Give renameMap & rename stage access to the freeList;
387    for (ThreadID tid = 0; tid < numThreads; tid++)
388        renameMap[tid].setFreeList(&freeList);
389    rename.setFreeList(&freeList);
390
391    // Setup the ROB for whichever stages need it.
392    commit.setROB(&rob);
393
394    lastRunningCycle = curTick();
395
396    lastActivatedCycle = -1;
397#if 0
398    // Give renameMap & rename stage access to the freeList;
399    for (ThreadID tid = 0; tid < numThreads; tid++)
400        globalSeqNum[tid] = 1;
401#endif
402
403    contextSwitch = false;
404    DPRINTF(O3CPU, "Creating O3CPU object.\n");
405
406    // Setup any thread state.
407    this->thread.resize(this->numThreads);
408
409    for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
410#if FULL_SYSTEM
411        // SMT is not supported in FS mode yet.
412        assert(this->numThreads == 1);
413        this->thread[tid] = new Thread(this, 0);
414#else
415        if (tid < params->workload.size()) {
416            DPRINTF(O3CPU, "Workload[%i] process is %#x",
417                    tid, this->thread[tid]);
418            this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
419                    (typename Impl::O3CPU *)(this),
420                    tid, params->workload[tid]);
421
422            //usedTids[tid] = true;
423            //threadMap[tid] = tid;
424        } else {
425            //Allocate Empty thread so M5 can use later
426            //when scheduling threads to CPU
427            Process* dummy_proc = NULL;
428
429            this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
430                    (typename Impl::O3CPU *)(this),
431                    tid, dummy_proc);
432            //usedTids[tid] = false;
433        }
434#endif // !FULL_SYSTEM
435
436        ThreadContext *tc;
437
438        // Setup the TC that will serve as the interface to the threads/CPU.
439        O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
440
441        tc = o3_tc;
442
443        // If we're using a checker, then the TC should be the
444        // CheckerThreadContext.
445#if USE_CHECKER
446        if (params->checker) {
447            tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
448                o3_tc, this->checker);
449        }
450#endif
451
452        o3_tc->cpu = (typename Impl::O3CPU *)(this);
453        assert(o3_tc->cpu);
454        o3_tc->thread = this->thread[tid];
455
456#if FULL_SYSTEM
457        // Setup quiesce event.
458        this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
459#endif
460        // Give the thread the TC.
461        this->thread[tid]->tc = tc;
462
463        // Add the TC to the CPU's list of TC's.
464        this->threadContexts.push_back(tc);
465    }
466
467    for (ThreadID tid = 0; tid < this->numThreads; tid++)
468        this->thread[tid]->setFuncExeInst(0);
469
470    lockAddr = 0;
471    lockFlag = false;
472}
473
474template <class Impl>
475FullO3CPU<Impl>::~FullO3CPU()
476{
477}
478
479template <class Impl>
480void
481FullO3CPU<Impl>::regStats()
482{
483    BaseO3CPU::regStats();
484
485    // Register any of the O3CPU's stats here.
486    timesIdled
487        .name(name() + ".timesIdled")
488        .desc("Number of times that the entire CPU went into an idle state and"
489              " unscheduled itself")
490        .prereq(timesIdled);
491
492    idleCycles
493        .name(name() + ".idleCycles")
494        .desc("Total number of cycles that the CPU has spent unscheduled due "
495              "to idling")
496        .prereq(idleCycles);
497
498    quiesceCycles
499        .name(name() + ".quiesceCycles")
500        .desc("Total number of cycles that CPU has spent quiesced or waiting "
501              "for an interrupt")
502        .prereq(quiesceCycles);
503
504    // Number of Instructions simulated
505    // --------------------------------
506    // Should probably be in Base CPU but need templated
507    // MaxThreads so put in here instead
508    committedInsts
509        .init(numThreads)
510        .name(name() + ".committedInsts")
511        .desc("Number of Instructions Simulated");
512
513    totalCommittedInsts
514        .name(name() + ".committedInsts_total")
515        .desc("Number of Instructions Simulated");
516
517    cpi
518        .name(name() + ".cpi")
519        .desc("CPI: Cycles Per Instruction")
520        .precision(6);
521    cpi = numCycles / committedInsts;
522
523    totalCpi
524        .name(name() + ".cpi_total")
525        .desc("CPI: Total CPI of All Threads")
526        .precision(6);
527    totalCpi = numCycles / totalCommittedInsts;
528
529    ipc
530        .name(name() + ".ipc")
531        .desc("IPC: Instructions Per Cycle")
532        .precision(6);
533    ipc =  committedInsts / numCycles;
534
535    totalIpc
536        .name(name() + ".ipc_total")
537        .desc("IPC: Total IPC of All Threads")
538        .precision(6);
539    totalIpc =  totalCommittedInsts / numCycles;
540
541    this->fetch.regStats();
542    this->decode.regStats();
543    this->rename.regStats();
544    this->iew.regStats();
545    this->commit.regStats();
546    this->rob.regStats();
547
548    intRegfileReads
549        .name(name() + ".int_regfile_reads")
550        .desc("number of integer regfile reads")
551        .prereq(intRegfileReads);
552
553    intRegfileWrites
554        .name(name() + ".int_regfile_writes")
555        .desc("number of integer regfile writes")
556        .prereq(intRegfileWrites);
557
558    fpRegfileReads
559        .name(name() + ".fp_regfile_reads")
560        .desc("number of floating regfile reads")
561        .prereq(fpRegfileReads);
562
563    fpRegfileWrites
564        .name(name() + ".fp_regfile_writes")
565        .desc("number of floating regfile writes")
566        .prereq(fpRegfileWrites);
567
568    miscRegfileReads
569        .name(name() + ".misc_regfile_reads")
570        .desc("number of misc regfile reads")
571        .prereq(miscRegfileReads);
572
573    miscRegfileWrites
574        .name(name() + ".misc_regfile_writes")
575        .desc("number of misc regfile writes")
576        .prereq(miscRegfileWrites);
577}
578
579template <class Impl>
580Port *
581FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
582{
583    if (if_name == "dcache_port")
584        return &dcachePort;
585    else if (if_name == "icache_port")
586        return &icachePort;
587    else
588        panic("No Such Port\n");
589}
590
591template <class Impl>
592void
593FullO3CPU<Impl>::tick()
594{
595    DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
596
597    ++numCycles;
598
599//    activity = false;
600
601    //Tick each of the stages
602    fetch.tick();
603
604    decode.tick();
605
606    rename.tick();
607
608    iew.tick();
609
610    commit.tick();
611
612#if !FULL_SYSTEM
613    doContextSwitch();
614#endif
615
616    // Now advance the time buffers
617    timeBuffer.advance();
618
619    fetchQueue.advance();
620    decodeQueue.advance();
621    renameQueue.advance();
622    iewQueue.advance();
623
624    activityRec.advance();
625
626    if (removeInstsThisCycle) {
627        cleanUpRemovedInsts();
628    }
629
630    if (!tickEvent.scheduled()) {
631        if (_status == SwitchedOut ||
632            getState() == SimObject::Drained) {
633            DPRINTF(O3CPU, "Switched out!\n");
634            // increment stat
635            lastRunningCycle = curTick();
636        } else if (!activityRec.active() || _status == Idle) {
637            DPRINTF(O3CPU, "Idle!\n");
638            lastRunningCycle = curTick();
639            timesIdled++;
640        } else {
641            schedule(tickEvent, nextCycle(curTick() + ticks(1)));
642            DPRINTF(O3CPU, "Scheduling next tick!\n");
643        }
644    }
645
646#if !FULL_SYSTEM
647    updateThreadPriority();
648#endif
649}
650
651template <class Impl>
652void
653FullO3CPU<Impl>::init()
654{
655    BaseCPU::init();
656
657    // Set inSyscall so that the CPU doesn't squash when initially
658    // setting up registers.
659    for (ThreadID tid = 0; tid < numThreads; ++tid)
660        thread[tid]->inSyscall = true;
661
662    // this CPU could still be unconnected if we are restoring from a
663    // checkpoint and this CPU is to be switched in, thus we can only
664    // do this here if the instruction port is actually connected, if
665    // not we have to do it as part of takeOverFrom
666    if (icachePort.isConnected())
667        fetch.setIcache();
668
669#if FULL_SYSTEM
670    for (ThreadID tid = 0; tid < numThreads; tid++) {
671        ThreadContext *src_tc = threadContexts[tid];
672        TheISA::initCPU(src_tc, src_tc->contextId());
673        // Initialise the ThreadContext's memory proxies
674        thread[tid]->initMemProxies(thread[tid]->getTC());
675    }
676#endif
677
678    // Clear inSyscall.
679    for (int tid = 0; tid < numThreads; ++tid)
680        thread[tid]->inSyscall = false;
681
682    // Initialize stages.
683    fetch.initStage();
684    iew.initStage();
685    rename.initStage();
686    commit.initStage();
687
688    commit.setThreads(thread);
689}
690
691template <class Impl>
692void
693FullO3CPU<Impl>::activateThread(ThreadID tid)
694{
695    list<ThreadID>::iterator isActive =
696        std::find(activeThreads.begin(), activeThreads.end(), tid);
697
698    DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
699
700    if (isActive == activeThreads.end()) {
701        DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
702                tid);
703
704        activeThreads.push_back(tid);
705    }
706}
707
708template <class Impl>
709void
710FullO3CPU<Impl>::deactivateThread(ThreadID tid)
711{
712    //Remove From Active List, if Active
713    list<ThreadID>::iterator thread_it =
714        std::find(activeThreads.begin(), activeThreads.end(), tid);
715
716    DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
717
718    if (thread_it != activeThreads.end()) {
719        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
720                tid);
721        activeThreads.erase(thread_it);
722    }
723}
724
725template <class Impl>
726Counter
727FullO3CPU<Impl>::totalInstructions() const
728{
729    Counter total(0);
730
731    ThreadID size = thread.size();
732    for (ThreadID i = 0; i < size; i++)
733        total += thread[i]->numInst;
734
735    return total;
736}
737
738template <class Impl>
739void
740FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
741{
742    // Needs to set each stage to running as well.
743    if (delay){
744        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
745                "on cycle %d\n", tid, curTick() + ticks(delay));
746        scheduleActivateThreadEvent(tid, delay);
747    } else {
748        activateThread(tid);
749    }
750
751    if (lastActivatedCycle < curTick()) {
752        scheduleTickEvent(delay);
753
754        // Be sure to signal that there's some activity so the CPU doesn't
755        // deschedule itself.
756        activityRec.activity();
757        fetch.wakeFromQuiesce();
758
759        quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
760
761        lastActivatedCycle = curTick();
762
763        _status = Running;
764    }
765}
766
767template <class Impl>
768bool
769FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove,
770                                           int delay)
771{
772    // Schedule removal of thread data from CPU
773    if (delay){
774        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
775                "on cycle %d\n", tid, curTick() + ticks(delay));
776        scheduleDeallocateContextEvent(tid, remove, delay);
777        return false;
778    } else {
779        deactivateThread(tid);
780        if (remove)
781            removeThread(tid);
782        return true;
783    }
784}
785
786template <class Impl>
787void
788FullO3CPU<Impl>::suspendContext(ThreadID tid)
789{
790    DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
791    bool deallocated = scheduleDeallocateContext(tid, false, 1);
792    // If this was the last thread then unschedule the tick event.
793    if ((activeThreads.size() == 1 && !deallocated) ||
794        activeThreads.size() == 0)
795        unscheduleTickEvent();
796
797    DPRINTF(Quiesce, "Suspending Context\n");
798    lastRunningCycle = curTick();
799    _status = Idle;
800}
801
802template <class Impl>
803void
804FullO3CPU<Impl>::haltContext(ThreadID tid)
805{
806    //For now, this is the same as deallocate
807    DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
808    scheduleDeallocateContext(tid, true, 1);
809}
810
811template <class Impl>
812void
813FullO3CPU<Impl>::insertThread(ThreadID tid)
814{
815    DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
816    // Will change now that the PC and thread state is internal to the CPU
817    // and not in the ThreadContext.
818#if FULL_SYSTEM
819    ThreadContext *src_tc = system->threadContexts[tid];
820#else
821    ThreadContext *src_tc = tcBase(tid);
822#endif
823
824    //Bind Int Regs to Rename Map
825    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
826        PhysRegIndex phys_reg = freeList.getIntReg();
827
828        renameMap[tid].setEntry(ireg,phys_reg);
829        scoreboard.setReg(phys_reg);
830    }
831
832    //Bind Float Regs to Rename Map
833    for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
834        PhysRegIndex phys_reg = freeList.getFloatReg();
835
836        renameMap[tid].setEntry(freg,phys_reg);
837        scoreboard.setReg(phys_reg);
838    }
839
840    //Copy Thread Data Into RegFile
841    //this->copyFromTC(tid);
842
843    //Set PC/NPC/NNPC
844    pcState(src_tc->pcState(), tid);
845
846    src_tc->setStatus(ThreadContext::Active);
847
848    activateContext(tid,1);
849
850    //Reset ROB/IQ/LSQ Entries
851    commit.rob->resetEntries();
852    iew.resetEntries();
853}
854
855template <class Impl>
856void
857FullO3CPU<Impl>::removeThread(ThreadID tid)
858{
859    DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
860
861    // Copy Thread Data From RegFile
862    // If thread is suspended, it might be re-allocated
863    // this->copyToTC(tid);
864
865
866    // @todo: 2-27-2008: Fix how we free up rename mappings
867    // here to alleviate the case for double-freeing registers
868    // in SMT workloads.
869
870    // Unbind Int Regs from Rename Map
871    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
872        PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
873
874        scoreboard.unsetReg(phys_reg);
875        freeList.addReg(phys_reg);
876    }
877
878    // Unbind Float Regs from Rename Map
879    for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
880        PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
881
882        scoreboard.unsetReg(phys_reg);
883        freeList.addReg(phys_reg);
884    }
885
886    // Squash Throughout Pipeline
887    DynInstPtr inst = commit.rob->readHeadInst(tid);
888    InstSeqNum squash_seq_num = inst->seqNum;
889    fetch.squash(0, squash_seq_num, inst, tid);
890    decode.squash(tid);
891    rename.squash(squash_seq_num, tid);
892    iew.squash(tid);
893    iew.ldstQueue.squash(squash_seq_num, tid);
894    commit.rob->squash(squash_seq_num, tid);
895
896
897    assert(iew.instQueue.getCount(tid) == 0);
898    assert(iew.ldstQueue.getCount(tid) == 0);
899
900    // Reset ROB/IQ/LSQ Entries
901
902    // Commented out for now.  This should be possible to do by
903    // telling all the pipeline stages to drain first, and then
904    // checking until the drain completes.  Once the pipeline is
905    // drained, call resetEntries(). - 10-09-06 ktlim
906/*
907    if (activeThreads.size() >= 1) {
908        commit.rob->resetEntries();
909        iew.resetEntries();
910    }
911*/
912}
913
914
915template <class Impl>
916void
917FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
918{
919    DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
920            "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
921            tid);
922
923    bool ready = true;
924
925    if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
926        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
927                "Phys. Int. Regs.\n",
928                tid);
929        ready = false;
930    } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
931        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
932                "Phys. Float. Regs.\n",
933                tid);
934        ready = false;
935    } else if (commit.rob->numFreeEntries() >=
936               commit.rob->entryAmount(activeThreads.size() + 1)) {
937        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
938                "ROB entries.\n",
939                tid);
940        ready = false;
941    } else if (iew.instQueue.numFreeEntries() >=
942               iew.instQueue.entryAmount(activeThreads.size() + 1)) {
943        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
944                "IQ entries.\n",
945                tid);
946        ready = false;
947    } else if (iew.ldstQueue.numFreeEntries() >=
948               iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
949        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
950                "LSQ entries.\n",
951                tid);
952        ready = false;
953    }
954
955    if (ready) {
956        insertThread(tid);
957
958        contextSwitch = false;
959
960        cpuWaitList.remove(tid);
961    } else {
962        suspendContext(tid);
963
964        //blocks fetch
965        contextSwitch = true;
966
967        //@todo: dont always add to waitlist
968        //do waitlist
969        cpuWaitList.push_back(tid);
970    }
971}
972
973#if FULL_SYSTEM
974template <class Impl>
975Fault
976FullO3CPU<Impl>::hwrei(ThreadID tid)
977{
978#if THE_ISA == ALPHA_ISA
979    // Need to clear the lock flag upon returning from an interrupt.
980    this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
981
982    this->thread[tid]->kernelStats->hwrei();
983
984    // FIXME: XXX check for interrupts? XXX
985#endif
986    return NoFault;
987}
988
989template <class Impl>
990bool
991FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
992{
993#if THE_ISA == ALPHA_ISA
994    if (this->thread[tid]->kernelStats)
995        this->thread[tid]->kernelStats->callpal(palFunc,
996                                                this->threadContexts[tid]);
997
998    switch (palFunc) {
999      case PAL::halt:
1000        halt();
1001        if (--System::numSystemsRunning == 0)
1002            exitSimLoop("all cpus halted");
1003        break;
1004
1005      case PAL::bpt:
1006      case PAL::bugchk:
1007        if (this->system->breakpoint())
1008            return false;
1009        break;
1010    }
1011#endif
1012    return true;
1013}
1014
1015template <class Impl>
1016Fault
1017FullO3CPU<Impl>::getInterrupts()
1018{
1019    // Check if there are any outstanding interrupts
1020    return this->interrupts->getInterrupt(this->threadContexts[0]);
1021}
1022
1023template <class Impl>
1024void
1025FullO3CPU<Impl>::processInterrupts(Fault interrupt)
1026{
1027    // Check for interrupts here.  For now can copy the code that
1028    // exists within isa_fullsys_traits.hh.  Also assume that thread 0
1029    // is the one that handles the interrupts.
1030    // @todo: Possibly consolidate the interrupt checking code.
1031    // @todo: Allow other threads to handle interrupts.
1032
1033    assert(interrupt != NoFault);
1034    this->interrupts->updateIntrInfo(this->threadContexts[0]);
1035
1036    DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
1037    this->trap(interrupt, 0, NULL);
1038}
1039
1040#endif
1041
1042template <class Impl>
1043void
1044FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
1045{
1046    // Pass the thread's TC into the invoke method.
1047    fault->invoke(this->threadContexts[tid], inst);
1048}
1049
1050#if !FULL_SYSTEM
1051
1052template <class Impl>
1053void
1054FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
1055{
1056    DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1057
1058    DPRINTF(Activity,"Activity: syscall() called.\n");
1059
1060    // Temporarily increase this by one to account for the syscall
1061    // instruction.
1062    ++(this->thread[tid]->funcExeInst);
1063
1064    // Execute the actual syscall.
1065    this->thread[tid]->syscall(callnum);
1066
1067    // Decrease funcExeInst by one as the normal commit will handle
1068    // incrementing it.
1069    --(this->thread[tid]->funcExeInst);
1070}
1071
1072#endif
1073
1074template <class Impl>
1075void
1076FullO3CPU<Impl>::serialize(std::ostream &os)
1077{
1078    SimObject::State so_state = SimObject::getState();
1079    SERIALIZE_ENUM(so_state);
1080    BaseCPU::serialize(os);
1081    nameOut(os, csprintf("%s.tickEvent", name()));
1082    tickEvent.serialize(os);
1083
1084    // Use SimpleThread's ability to checkpoint to make it easier to
1085    // write out the registers.  Also make this static so it doesn't
1086    // get instantiated multiple times (causes a panic in statistics).
1087    static SimpleThread temp;
1088
1089    ThreadID size = thread.size();
1090    for (ThreadID i = 0; i < size; i++) {
1091        nameOut(os, csprintf("%s.xc.%i", name(), i));
1092        temp.copyTC(thread[i]->getTC());
1093        temp.serialize(os);
1094    }
1095}
1096
1097template <class Impl>
1098void
1099FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
1100{
1101    SimObject::State so_state;
1102    UNSERIALIZE_ENUM(so_state);
1103    BaseCPU::unserialize(cp, section);
1104    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1105
1106    // Use SimpleThread's ability to checkpoint to make it easier to
1107    // read in the registers.  Also make this static so it doesn't
1108    // get instantiated multiple times (causes a panic in statistics).
1109    static SimpleThread temp;
1110
1111    ThreadID size = thread.size();
1112    for (ThreadID i = 0; i < size; i++) {
1113        temp.copyTC(thread[i]->getTC());
1114        temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1115        thread[i]->getTC()->copyArchRegs(temp.getTC());
1116    }
1117}
1118
1119template <class Impl>
1120unsigned int
1121FullO3CPU<Impl>::drain(Event *drain_event)
1122{
1123    DPRINTF(O3CPU, "Switching out\n");
1124
1125    // If the CPU isn't doing anything, then return immediately.
1126    if (_status == Idle || _status == SwitchedOut) {
1127        return 0;
1128    }
1129
1130    drainCount = 0;
1131    fetch.drain();
1132    decode.drain();
1133    rename.drain();
1134    iew.drain();
1135    commit.drain();
1136
1137    // Wake the CPU and record activity so everything can drain out if
1138    // the CPU was not able to immediately drain.
1139    if (getState() != SimObject::Drained) {
1140        // A bit of a hack...set the drainEvent after all the drain()
1141        // calls have been made, that way if all of the stages drain
1142        // immediately, the signalDrained() function knows not to call
1143        // process on the drain event.
1144        drainEvent = drain_event;
1145
1146        wakeCPU();
1147        activityRec.activity();
1148
1149        return 1;
1150    } else {
1151        return 0;
1152    }
1153}
1154
1155template <class Impl>
1156void
1157FullO3CPU<Impl>::resume()
1158{
1159    fetch.resume();
1160    decode.resume();
1161    rename.resume();
1162    iew.resume();
1163    commit.resume();
1164
1165    changeState(SimObject::Running);
1166
1167    if (_status == SwitchedOut || _status == Idle)
1168        return;
1169
1170    assert(system->getMemoryMode() == Enums::timing);
1171
1172    if (!tickEvent.scheduled())
1173        schedule(tickEvent, nextCycle());
1174    _status = Running;
1175}
1176
1177template <class Impl>
1178void
1179FullO3CPU<Impl>::signalDrained()
1180{
1181    if (++drainCount == NumStages) {
1182        if (tickEvent.scheduled())
1183            tickEvent.squash();
1184
1185        changeState(SimObject::Drained);
1186
1187        BaseCPU::switchOut();
1188
1189        if (drainEvent) {
1190            drainEvent->process();
1191            drainEvent = NULL;
1192        }
1193    }
1194    assert(drainCount <= 5);
1195}
1196
1197template <class Impl>
1198void
1199FullO3CPU<Impl>::switchOut()
1200{
1201    fetch.switchOut();
1202    rename.switchOut();
1203    iew.switchOut();
1204    commit.switchOut();
1205    instList.clear();
1206    while (!removeList.empty()) {
1207        removeList.pop();
1208    }
1209
1210    _status = SwitchedOut;
1211#if USE_CHECKER
1212    if (checker)
1213        checker->switchOut();
1214#endif
1215    if (tickEvent.scheduled())
1216        tickEvent.squash();
1217}
1218
1219template <class Impl>
1220void
1221FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1222{
1223    // Flush out any old data from the time buffers.
1224    for (int i = 0; i < timeBuffer.getSize(); ++i) {
1225        timeBuffer.advance();
1226        fetchQueue.advance();
1227        decodeQueue.advance();
1228        renameQueue.advance();
1229        iewQueue.advance();
1230    }
1231
1232    activityRec.reset();
1233
1234    BaseCPU::takeOverFrom(oldCPU);
1235
1236    fetch.takeOverFrom();
1237    decode.takeOverFrom();
1238    rename.takeOverFrom();
1239    iew.takeOverFrom();
1240    commit.takeOverFrom();
1241
1242    assert(!tickEvent.scheduled() || tickEvent.squashed());
1243
1244    // @todo: Figure out how to properly select the tid to put onto
1245    // the active threads list.
1246    ThreadID tid = 0;
1247
1248    list<ThreadID>::iterator isActive =
1249        std::find(activeThreads.begin(), activeThreads.end(), tid);
1250
1251    if (isActive == activeThreads.end()) {
1252        //May Need to Re-code this if the delay variable is the delay
1253        //needed for thread to activate
1254        DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1255                tid);
1256
1257        activeThreads.push_back(tid);
1258    }
1259
1260    // Set all statuses to active, schedule the CPU's tick event.
1261    // @todo: Fix up statuses so this is handled properly
1262    ThreadID size = threadContexts.size();
1263    for (ThreadID i = 0; i < size; ++i) {
1264        ThreadContext *tc = threadContexts[i];
1265        if (tc->status() == ThreadContext::Active && _status != Running) {
1266            _status = Running;
1267            reschedule(tickEvent, nextCycle(), true);
1268        }
1269    }
1270    if (!tickEvent.scheduled())
1271        schedule(tickEvent, nextCycle());
1272
1273    lastRunningCycle = curTick();
1274}
1275
1276template <class Impl>
1277TheISA::MiscReg
1278FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1279{
1280    return this->isa[tid].readMiscRegNoEffect(misc_reg);
1281}
1282
1283template <class Impl>
1284TheISA::MiscReg
1285FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1286{
1287    miscRegfileReads++;
1288    return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1289}
1290
1291template <class Impl>
1292void
1293FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1294        const TheISA::MiscReg &val, ThreadID tid)
1295{
1296    this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1297}
1298
1299template <class Impl>
1300void
1301FullO3CPU<Impl>::setMiscReg(int misc_reg,
1302        const TheISA::MiscReg &val, ThreadID tid)
1303{
1304    miscRegfileWrites++;
1305    this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1306}
1307
1308template <class Impl>
1309uint64_t
1310FullO3CPU<Impl>::readIntReg(int reg_idx)
1311{
1312    intRegfileReads++;
1313    return regFile.readIntReg(reg_idx);
1314}
1315
1316template <class Impl>
1317FloatReg
1318FullO3CPU<Impl>::readFloatReg(int reg_idx)
1319{
1320    fpRegfileReads++;
1321    return regFile.readFloatReg(reg_idx);
1322}
1323
1324template <class Impl>
1325FloatRegBits
1326FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1327{
1328    fpRegfileReads++;
1329    return regFile.readFloatRegBits(reg_idx);
1330}
1331
1332template <class Impl>
1333void
1334FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1335{
1336    intRegfileWrites++;
1337    regFile.setIntReg(reg_idx, val);
1338}
1339
1340template <class Impl>
1341void
1342FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1343{
1344    fpRegfileWrites++;
1345    regFile.setFloatReg(reg_idx, val);
1346}
1347
1348template <class Impl>
1349void
1350FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1351{
1352    fpRegfileWrites++;
1353    regFile.setFloatRegBits(reg_idx, val);
1354}
1355
1356template <class Impl>
1357uint64_t
1358FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1359{
1360    intRegfileReads++;
1361    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1362
1363    return regFile.readIntReg(phys_reg);
1364}
1365
1366template <class Impl>
1367float
1368FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1369{
1370    fpRegfileReads++;
1371    int idx = reg_idx + TheISA::NumIntRegs;
1372    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1373
1374    return regFile.readFloatReg(phys_reg);
1375}
1376
1377template <class Impl>
1378uint64_t
1379FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1380{
1381    fpRegfileReads++;
1382    int idx = reg_idx + TheISA::NumIntRegs;
1383    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1384
1385    return regFile.readFloatRegBits(phys_reg);
1386}
1387
1388template <class Impl>
1389void
1390FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1391{
1392    intRegfileWrites++;
1393    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1394
1395    regFile.setIntReg(phys_reg, val);
1396}
1397
1398template <class Impl>
1399void
1400FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1401{
1402    fpRegfileWrites++;
1403    int idx = reg_idx + TheISA::NumIntRegs;
1404    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1405
1406    regFile.setFloatReg(phys_reg, val);
1407}
1408
1409template <class Impl>
1410void
1411FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1412{
1413    fpRegfileWrites++;
1414    int idx = reg_idx + TheISA::NumIntRegs;
1415    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1416
1417    regFile.setFloatRegBits(phys_reg, val);
1418}
1419
1420template <class Impl>
1421TheISA::PCState
1422FullO3CPU<Impl>::pcState(ThreadID tid)
1423{
1424    return commit.pcState(tid);
1425}
1426
1427template <class Impl>
1428void
1429FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1430{
1431    commit.pcState(val, tid);
1432}
1433
1434template <class Impl>
1435Addr
1436FullO3CPU<Impl>::instAddr(ThreadID tid)
1437{
1438    return commit.instAddr(tid);
1439}
1440
1441template <class Impl>
1442Addr
1443FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1444{
1445    return commit.nextInstAddr(tid);
1446}
1447
1448template <class Impl>
1449MicroPC
1450FullO3CPU<Impl>::microPC(ThreadID tid)
1451{
1452    return commit.microPC(tid);
1453}
1454
1455template <class Impl>
1456void
1457FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1458{
1459    this->thread[tid]->inSyscall = true;
1460    this->commit.generateTCEvent(tid);
1461}
1462
1463template <class Impl>
1464typename FullO3CPU<Impl>::ListIt
1465FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1466{
1467    instList.push_back(inst);
1468
1469    return --(instList.end());
1470}
1471
1472template <class Impl>
1473void
1474FullO3CPU<Impl>::instDone(ThreadID tid)
1475{
1476    // Keep an instruction count.
1477    thread[tid]->numInst++;
1478    thread[tid]->numInsts++;
1479    committedInsts[tid]++;
1480    totalCommittedInsts++;
1481    system->totalNumInsts++;
1482    // Check for instruction-count-based events.
1483    comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1484    system->instEventQueue.serviceEvents(system->totalNumInsts);
1485}
1486
1487template <class Impl>
1488void
1489FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1490{
1491    DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1492            "[sn:%lli]\n",
1493            inst->threadNumber, inst->pcState(), inst->seqNum);
1494
1495    removeInstsThisCycle = true;
1496
1497    // Remove the front instruction.
1498    removeList.push(inst->getInstListIt());
1499}
1500
1501template <class Impl>
1502void
1503FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1504{
1505    DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1506            " list.\n", tid);
1507
1508    ListIt end_it;
1509
1510    bool rob_empty = false;
1511
1512    if (instList.empty()) {
1513        return;
1514    } else if (rob.isEmpty(/*tid*/)) {
1515        DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1516        end_it = instList.begin();
1517        rob_empty = true;
1518    } else {
1519        end_it = (rob.readTailInst(tid))->getInstListIt();
1520        DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1521    }
1522
1523    removeInstsThisCycle = true;
1524
1525    ListIt inst_it = instList.end();
1526
1527    inst_it--;
1528
1529    // Walk through the instruction list, removing any instructions
1530    // that were inserted after the given instruction iterator, end_it.
1531    while (inst_it != end_it) {
1532        assert(!instList.empty());
1533
1534        squashInstIt(inst_it, tid);
1535
1536        inst_it--;
1537    }
1538
1539    // If the ROB was empty, then we actually need to remove the first
1540    // instruction as well.
1541    if (rob_empty) {
1542        squashInstIt(inst_it, tid);
1543    }
1544}
1545
1546template <class Impl>
1547void
1548FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1549{
1550    assert(!instList.empty());
1551
1552    removeInstsThisCycle = true;
1553
1554    ListIt inst_iter = instList.end();
1555
1556    inst_iter--;
1557
1558    DPRINTF(O3CPU, "Deleting instructions from instruction "
1559            "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1560            tid, seq_num, (*inst_iter)->seqNum);
1561
1562    while ((*inst_iter)->seqNum > seq_num) {
1563
1564        bool break_loop = (inst_iter == instList.begin());
1565
1566        squashInstIt(inst_iter, tid);
1567
1568        inst_iter--;
1569
1570        if (break_loop)
1571            break;
1572    }
1573}
1574
1575template <class Impl>
1576inline void
1577FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1578{
1579    if ((*instIt)->threadNumber == tid) {
1580        DPRINTF(O3CPU, "Squashing instruction, "
1581                "[tid:%i] [sn:%lli] PC %s\n",
1582                (*instIt)->threadNumber,
1583                (*instIt)->seqNum,
1584                (*instIt)->pcState());
1585
1586        // Mark it as squashed.
1587        (*instIt)->setSquashed();
1588
1589        // @todo: Formulate a consistent method for deleting
1590        // instructions from the instruction list
1591        // Remove the instruction from the list.
1592        removeList.push(instIt);
1593    }
1594}
1595
1596template <class Impl>
1597void
1598FullO3CPU<Impl>::cleanUpRemovedInsts()
1599{
1600    while (!removeList.empty()) {
1601        DPRINTF(O3CPU, "Removing instruction, "
1602                "[tid:%i] [sn:%lli] PC %s\n",
1603                (*removeList.front())->threadNumber,
1604                (*removeList.front())->seqNum,
1605                (*removeList.front())->pcState());
1606
1607        instList.erase(removeList.front());
1608
1609        removeList.pop();
1610    }
1611
1612    removeInstsThisCycle = false;
1613}
1614/*
1615template <class Impl>
1616void
1617FullO3CPU<Impl>::removeAllInsts()
1618{
1619    instList.clear();
1620}
1621*/
1622template <class Impl>
1623void
1624FullO3CPU<Impl>::dumpInsts()
1625{
1626    int num = 0;
1627
1628    ListIt inst_list_it = instList.begin();
1629
1630    cprintf("Dumping Instruction List\n");
1631
1632    while (inst_list_it != instList.end()) {
1633        cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1634                "Squashed:%i\n\n",
1635                num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1636                (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1637                (*inst_list_it)->isSquashed());
1638        inst_list_it++;
1639        ++num;
1640    }
1641}
1642/*
1643template <class Impl>
1644void
1645FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1646{
1647    iew.wakeDependents(inst);
1648}
1649*/
1650template <class Impl>
1651void
1652FullO3CPU<Impl>::wakeCPU()
1653{
1654    if (activityRec.active() || tickEvent.scheduled()) {
1655        DPRINTF(Activity, "CPU already running.\n");
1656        return;
1657    }
1658
1659    DPRINTF(Activity, "Waking up CPU\n");
1660
1661    idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1662    numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1663
1664    schedule(tickEvent, nextCycle());
1665}
1666
1667#if FULL_SYSTEM
1668template <class Impl>
1669void
1670FullO3CPU<Impl>::wakeup()
1671{
1672    if (this->thread[0]->status() != ThreadContext::Suspended)
1673        return;
1674
1675    this->wakeCPU();
1676
1677    DPRINTF(Quiesce, "Suspended Processor woken\n");
1678    this->threadContexts[0]->activate();
1679}
1680#endif
1681
1682template <class Impl>
1683ThreadID
1684FullO3CPU<Impl>::getFreeTid()
1685{
1686    for (ThreadID tid = 0; tid < numThreads; tid++) {
1687        if (!tids[tid]) {
1688            tids[tid] = true;
1689            return tid;
1690        }
1691    }
1692
1693    return InvalidThreadID;
1694}
1695
1696template <class Impl>
1697void
1698FullO3CPU<Impl>::doContextSwitch()
1699{
1700    if (contextSwitch) {
1701
1702        //ADD CODE TO DEACTIVE THREAD HERE (???)
1703
1704        ThreadID size = cpuWaitList.size();
1705        for (ThreadID tid = 0; tid < size; tid++) {
1706            activateWhenReady(tid);
1707        }
1708
1709        if (cpuWaitList.size() == 0)
1710            contextSwitch = true;
1711    }
1712}
1713
1714template <class Impl>
1715void
1716FullO3CPU<Impl>::updateThreadPriority()
1717{
1718    if (activeThreads.size() > 1) {
1719        //DEFAULT TO ROUND ROBIN SCHEME
1720        //e.g. Move highest priority to end of thread list
1721        list<ThreadID>::iterator list_begin = activeThreads.begin();
1722
1723        unsigned high_thread = *list_begin;
1724
1725        activeThreads.erase(list_begin);
1726
1727        activeThreads.push_back(high_thread);
1728    }
1729}
1730
1731// Forward declaration of FullO3CPU.
1732template class FullO3CPU<O3CPUImpl>;
1733