cpu.cc revision 8607:5fb918115c07 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 *          Korey Sewell
31 *          Rick Strong
32 */
33
34#include "config/full_system.hh"
35#include "config/the_isa.hh"
36#include "config/use_checker.hh"
37#include "cpu/o3/cpu.hh"
38#include "cpu/o3/isa_specific.hh"
39#include "cpu/o3/thread_context.hh"
40#include "cpu/activity.hh"
41#include "cpu/simple_thread.hh"
42#include "cpu/thread_context.hh"
43#include "debug/Activity.hh"
44#include "debug/O3CPU.hh"
45#include "debug/Quiesce.hh"
46#include "enums/MemoryMode.hh"
47#include "sim/core.hh"
48#include "sim/stat_control.hh"
49#include "sim/system.hh"
50
51#if FULL_SYSTEM
52#include "cpu/quiesce_event.hh"
53#else
54#include "sim/process.hh"
55#endif
56
57#if USE_CHECKER
58#include "cpu/checker/cpu.hh"
59#endif
60
61#if THE_ISA == ALPHA_ISA
62#include "arch/alpha/osfpal.hh"
63#include "debug/Activity.hh"
64#endif
65
66class BaseCPUParams;
67
68using namespace TheISA;
69using namespace std;
70
71BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
72    : BaseCPU(params)
73{
74}
75
76void
77BaseO3CPU::regStats()
78{
79    BaseCPU::regStats();
80}
81
82template <class Impl>
83FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
84    : Event(CPU_Tick_Pri), cpu(c)
85{
86}
87
88template <class Impl>
89void
90FullO3CPU<Impl>::TickEvent::process()
91{
92    cpu->tick();
93}
94
95template <class Impl>
96const char *
97FullO3CPU<Impl>::TickEvent::description() const
98{
99    return "FullO3CPU tick";
100}
101
102template <class Impl>
103FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
104    : Event(CPU_Switch_Pri)
105{
106}
107
108template <class Impl>
109void
110FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
111                                           FullO3CPU<Impl> *thread_cpu)
112{
113    tid = thread_num;
114    cpu = thread_cpu;
115}
116
117template <class Impl>
118void
119FullO3CPU<Impl>::ActivateThreadEvent::process()
120{
121    cpu->activateThread(tid);
122}
123
124template <class Impl>
125const char *
126FullO3CPU<Impl>::ActivateThreadEvent::description() const
127{
128    return "FullO3CPU \"Activate Thread\"";
129}
130
131template <class Impl>
132FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
133    : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
134{
135}
136
137template <class Impl>
138void
139FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
140                                              FullO3CPU<Impl> *thread_cpu)
141{
142    tid = thread_num;
143    cpu = thread_cpu;
144    remove = false;
145}
146
147template <class Impl>
148void
149FullO3CPU<Impl>::DeallocateContextEvent::process()
150{
151    cpu->deactivateThread(tid);
152    if (remove)
153        cpu->removeThread(tid);
154}
155
156template <class Impl>
157const char *
158FullO3CPU<Impl>::DeallocateContextEvent::description() const
159{
160    return "FullO3CPU \"Deallocate Context\"";
161}
162
163template <class Impl>
164FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
165    : BaseO3CPU(params),
166      itb(params->itb),
167      dtb(params->dtb),
168      tickEvent(this),
169#ifndef NDEBUG
170      instcount(0),
171#endif
172      removeInstsThisCycle(false),
173      fetch(this, params),
174      decode(this, params),
175      rename(this, params),
176      iew(this, params),
177      commit(this, params),
178
179      regFile(this, params->numPhysIntRegs,
180              params->numPhysFloatRegs),
181
182      freeList(params->numThreads,
183               TheISA::NumIntRegs, params->numPhysIntRegs,
184               TheISA::NumFloatRegs, params->numPhysFloatRegs),
185
186      rob(this,
187          params->numROBEntries, params->squashWidth,
188          params->smtROBPolicy, params->smtROBThreshold,
189          params->numThreads),
190
191      scoreboard(params->numThreads,
192                 TheISA::NumIntRegs, params->numPhysIntRegs,
193                 TheISA::NumFloatRegs, params->numPhysFloatRegs,
194                 TheISA::NumMiscRegs * numThreads,
195                 TheISA::ZeroReg),
196
197      timeBuffer(params->backComSize, params->forwardComSize),
198      fetchQueue(params->backComSize, params->forwardComSize),
199      decodeQueue(params->backComSize, params->forwardComSize),
200      renameQueue(params->backComSize, params->forwardComSize),
201      iewQueue(params->backComSize, params->forwardComSize),
202      activityRec(name(), NumStages,
203                  params->backComSize + params->forwardComSize,
204                  params->activity),
205
206      globalSeqNum(1),
207      system(params->system),
208      drainCount(0),
209      deferRegistration(params->defer_registration)
210{
211    if (!deferRegistration) {
212        _status = Running;
213    } else {
214        _status = Idle;
215    }
216
217#if USE_CHECKER
218    if (params->checker) {
219        BaseCPU *temp_checker = params->checker;
220        checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
221#if FULL_SYSTEM
222        checker->setSystem(params->system);
223#endif
224    } else {
225        checker = NULL;
226    }
227#endif // USE_CHECKER
228
229#if !FULL_SYSTEM
230    thread.resize(numThreads);
231    tids.resize(numThreads);
232#endif
233
234    // The stages also need their CPU pointer setup.  However this
235    // must be done at the upper level CPU because they have pointers
236    // to the upper level CPU, and not this FullO3CPU.
237
238    // Set up Pointers to the activeThreads list for each stage
239    fetch.setActiveThreads(&activeThreads);
240    decode.setActiveThreads(&activeThreads);
241    rename.setActiveThreads(&activeThreads);
242    iew.setActiveThreads(&activeThreads);
243    commit.setActiveThreads(&activeThreads);
244
245    // Give each of the stages the time buffer they will use.
246    fetch.setTimeBuffer(&timeBuffer);
247    decode.setTimeBuffer(&timeBuffer);
248    rename.setTimeBuffer(&timeBuffer);
249    iew.setTimeBuffer(&timeBuffer);
250    commit.setTimeBuffer(&timeBuffer);
251
252    // Also setup each of the stages' queues.
253    fetch.setFetchQueue(&fetchQueue);
254    decode.setFetchQueue(&fetchQueue);
255    commit.setFetchQueue(&fetchQueue);
256    decode.setDecodeQueue(&decodeQueue);
257    rename.setDecodeQueue(&decodeQueue);
258    rename.setRenameQueue(&renameQueue);
259    iew.setRenameQueue(&renameQueue);
260    iew.setIEWQueue(&iewQueue);
261    commit.setIEWQueue(&iewQueue);
262    commit.setRenameQueue(&renameQueue);
263
264    commit.setIEWStage(&iew);
265    rename.setIEWStage(&iew);
266    rename.setCommitStage(&commit);
267
268#if !FULL_SYSTEM
269    ThreadID active_threads = params->workload.size();
270
271    if (active_threads > Impl::MaxThreads) {
272        panic("Workload Size too large. Increase the 'MaxThreads'"
273              "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
274              "edit your workload size.");
275    }
276#else
277    ThreadID active_threads = 1;
278#endif
279
280    //Make Sure That this a Valid Architeture
281    assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
282    assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
283
284    rename.setScoreboard(&scoreboard);
285    iew.setScoreboard(&scoreboard);
286
287    // Setup the rename map for whichever stages need it.
288    PhysRegIndex lreg_idx = 0;
289    PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
290
291    for (ThreadID tid = 0; tid < numThreads; tid++) {
292        bool bindRegs = (tid <= active_threads - 1);
293
294        commitRenameMap[tid].init(TheISA::NumIntRegs,
295                                  params->numPhysIntRegs,
296                                  lreg_idx,            //Index for Logical. Regs
297
298                                  TheISA::NumFloatRegs,
299                                  params->numPhysFloatRegs,
300                                  freg_idx,            //Index for Float Regs
301
302                                  TheISA::NumMiscRegs,
303
304                                  TheISA::ZeroReg,
305                                  TheISA::ZeroReg,
306
307                                  tid,
308                                  false);
309
310        renameMap[tid].init(TheISA::NumIntRegs,
311                            params->numPhysIntRegs,
312                            lreg_idx,                  //Index for Logical. Regs
313
314                            TheISA::NumFloatRegs,
315                            params->numPhysFloatRegs,
316                            freg_idx,                  //Index for Float Regs
317
318                            TheISA::NumMiscRegs,
319
320                            TheISA::ZeroReg,
321                            TheISA::ZeroReg,
322
323                            tid,
324                            bindRegs);
325
326        activateThreadEvent[tid].init(tid, this);
327        deallocateContextEvent[tid].init(tid, this);
328    }
329
330    rename.setRenameMap(renameMap);
331    commit.setRenameMap(commitRenameMap);
332
333    // Give renameMap & rename stage access to the freeList;
334    for (ThreadID tid = 0; tid < numThreads; tid++)
335        renameMap[tid].setFreeList(&freeList);
336    rename.setFreeList(&freeList);
337
338    // Setup the ROB for whichever stages need it.
339    commit.setROB(&rob);
340
341    lastRunningCycle = curTick();
342
343    lastActivatedCycle = -1;
344#if 0
345    // Give renameMap & rename stage access to the freeList;
346    for (ThreadID tid = 0; tid < numThreads; tid++)
347        globalSeqNum[tid] = 1;
348#endif
349
350    contextSwitch = false;
351    DPRINTF(O3CPU, "Creating O3CPU object.\n");
352
353    // Setup any thread state.
354    this->thread.resize(this->numThreads);
355
356    for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
357#if FULL_SYSTEM
358        // SMT is not supported in FS mode yet.
359        assert(this->numThreads == 1);
360        this->thread[tid] = new Thread(this, 0);
361#else
362        if (tid < params->workload.size()) {
363            DPRINTF(O3CPU, "Workload[%i] process is %#x",
364                    tid, this->thread[tid]);
365            this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
366                    (typename Impl::O3CPU *)(this),
367                    tid, params->workload[tid]);
368
369            //usedTids[tid] = true;
370            //threadMap[tid] = tid;
371        } else {
372            //Allocate Empty thread so M5 can use later
373            //when scheduling threads to CPU
374            Process* dummy_proc = NULL;
375
376            this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
377                    (typename Impl::O3CPU *)(this),
378                    tid, dummy_proc);
379            //usedTids[tid] = false;
380        }
381#endif // !FULL_SYSTEM
382
383        ThreadContext *tc;
384
385        // Setup the TC that will serve as the interface to the threads/CPU.
386        O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
387
388        tc = o3_tc;
389
390        // If we're using a checker, then the TC should be the
391        // CheckerThreadContext.
392#if USE_CHECKER
393        if (params->checker) {
394            tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
395                o3_tc, this->checker);
396        }
397#endif
398
399        o3_tc->cpu = (typename Impl::O3CPU *)(this);
400        assert(o3_tc->cpu);
401        o3_tc->thread = this->thread[tid];
402
403#if FULL_SYSTEM
404        // Setup quiesce event.
405        this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
406#endif
407        // Give the thread the TC.
408        this->thread[tid]->tc = tc;
409
410        // Add the TC to the CPU's list of TC's.
411        this->threadContexts.push_back(tc);
412    }
413
414    for (ThreadID tid = 0; tid < this->numThreads; tid++)
415        this->thread[tid]->setFuncExeInst(0);
416
417    lockAddr = 0;
418    lockFlag = false;
419}
420
421template <class Impl>
422FullO3CPU<Impl>::~FullO3CPU()
423{
424}
425
426template <class Impl>
427void
428FullO3CPU<Impl>::regStats()
429{
430    BaseO3CPU::regStats();
431
432    // Register any of the O3CPU's stats here.
433    timesIdled
434        .name(name() + ".timesIdled")
435        .desc("Number of times that the entire CPU went into an idle state and"
436              " unscheduled itself")
437        .prereq(timesIdled);
438
439    idleCycles
440        .name(name() + ".idleCycles")
441        .desc("Total number of cycles that the CPU has spent unscheduled due "
442              "to idling")
443        .prereq(idleCycles);
444
445    // Number of Instructions simulated
446    // --------------------------------
447    // Should probably be in Base CPU but need templated
448    // MaxThreads so put in here instead
449    committedInsts
450        .init(numThreads)
451        .name(name() + ".committedInsts")
452        .desc("Number of Instructions Simulated");
453
454    totalCommittedInsts
455        .name(name() + ".committedInsts_total")
456        .desc("Number of Instructions Simulated");
457
458    cpi
459        .name(name() + ".cpi")
460        .desc("CPI: Cycles Per Instruction")
461        .precision(6);
462    cpi = numCycles / committedInsts;
463
464    totalCpi
465        .name(name() + ".cpi_total")
466        .desc("CPI: Total CPI of All Threads")
467        .precision(6);
468    totalCpi = numCycles / totalCommittedInsts;
469
470    ipc
471        .name(name() + ".ipc")
472        .desc("IPC: Instructions Per Cycle")
473        .precision(6);
474    ipc =  committedInsts / numCycles;
475
476    totalIpc
477        .name(name() + ".ipc_total")
478        .desc("IPC: Total IPC of All Threads")
479        .precision(6);
480    totalIpc =  totalCommittedInsts / numCycles;
481
482    this->fetch.regStats();
483    this->decode.regStats();
484    this->rename.regStats();
485    this->iew.regStats();
486    this->commit.regStats();
487    this->rob.regStats();
488
489    intRegfileReads
490        .name(name() + ".int_regfile_reads")
491        .desc("number of integer regfile reads")
492        .prereq(intRegfileReads);
493
494    intRegfileWrites
495        .name(name() + ".int_regfile_writes")
496        .desc("number of integer regfile writes")
497        .prereq(intRegfileWrites);
498
499    fpRegfileReads
500        .name(name() + ".fp_regfile_reads")
501        .desc("number of floating regfile reads")
502        .prereq(fpRegfileReads);
503
504    fpRegfileWrites
505        .name(name() + ".fp_regfile_writes")
506        .desc("number of floating regfile writes")
507        .prereq(fpRegfileWrites);
508
509    miscRegfileReads
510        .name(name() + ".misc_regfile_reads")
511        .desc("number of misc regfile reads")
512        .prereq(miscRegfileReads);
513
514    miscRegfileWrites
515        .name(name() + ".misc_regfile_writes")
516        .desc("number of misc regfile writes")
517        .prereq(miscRegfileWrites);
518}
519
520template <class Impl>
521Port *
522FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
523{
524    if (if_name == "dcache_port")
525        return iew.getDcachePort();
526    else if (if_name == "icache_port")
527        return fetch.getIcachePort();
528    else
529        panic("No Such Port\n");
530}
531
532template <class Impl>
533void
534FullO3CPU<Impl>::tick()
535{
536    DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
537
538    ++numCycles;
539
540//    activity = false;
541
542    //Tick each of the stages
543    fetch.tick();
544
545    decode.tick();
546
547    rename.tick();
548
549    iew.tick();
550
551    commit.tick();
552
553#if !FULL_SYSTEM
554    doContextSwitch();
555#endif
556
557    // Now advance the time buffers
558    timeBuffer.advance();
559
560    fetchQueue.advance();
561    decodeQueue.advance();
562    renameQueue.advance();
563    iewQueue.advance();
564
565    activityRec.advance();
566
567    if (removeInstsThisCycle) {
568        cleanUpRemovedInsts();
569    }
570
571    if (!tickEvent.scheduled()) {
572        if (_status == SwitchedOut ||
573            getState() == SimObject::Drained) {
574            DPRINTF(O3CPU, "Switched out!\n");
575            // increment stat
576            lastRunningCycle = curTick();
577        } else if (!activityRec.active() || _status == Idle) {
578            DPRINTF(O3CPU, "Idle!\n");
579            lastRunningCycle = curTick();
580            timesIdled++;
581        } else {
582            schedule(tickEvent, nextCycle(curTick() + ticks(1)));
583            DPRINTF(O3CPU, "Scheduling next tick!\n");
584        }
585    }
586
587#if !FULL_SYSTEM
588    updateThreadPriority();
589#endif
590}
591
592template <class Impl>
593void
594FullO3CPU<Impl>::init()
595{
596    BaseCPU::init();
597
598    // Set inSyscall so that the CPU doesn't squash when initially
599    // setting up registers.
600    for (ThreadID tid = 0; tid < numThreads; ++tid)
601        thread[tid]->inSyscall = true;
602
603#if FULL_SYSTEM
604    for (ThreadID tid = 0; tid < numThreads; tid++) {
605        ThreadContext *src_tc = threadContexts[tid];
606        TheISA::initCPU(src_tc, src_tc->contextId());
607    }
608#endif
609
610    // Clear inSyscall.
611    for (int tid = 0; tid < numThreads; ++tid)
612        thread[tid]->inSyscall = false;
613
614    // Initialize stages.
615    fetch.initStage();
616    iew.initStage();
617    rename.initStage();
618    commit.initStage();
619
620    commit.setThreads(thread);
621}
622
623template <class Impl>
624void
625FullO3CPU<Impl>::activateThread(ThreadID tid)
626{
627    list<ThreadID>::iterator isActive =
628        std::find(activeThreads.begin(), activeThreads.end(), tid);
629
630    DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
631
632    if (isActive == activeThreads.end()) {
633        DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
634                tid);
635
636        activeThreads.push_back(tid);
637    }
638}
639
640template <class Impl>
641void
642FullO3CPU<Impl>::deactivateThread(ThreadID tid)
643{
644    //Remove From Active List, if Active
645    list<ThreadID>::iterator thread_it =
646        std::find(activeThreads.begin(), activeThreads.end(), tid);
647
648    DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
649
650    if (thread_it != activeThreads.end()) {
651        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
652                tid);
653        activeThreads.erase(thread_it);
654    }
655}
656
657template <class Impl>
658Counter
659FullO3CPU<Impl>::totalInstructions() const
660{
661    Counter total(0);
662
663    ThreadID size = thread.size();
664    for (ThreadID i = 0; i < size; i++)
665        total += thread[i]->numInst;
666
667    return total;
668}
669
670template <class Impl>
671void
672FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
673{
674    // Needs to set each stage to running as well.
675    if (delay){
676        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
677                "on cycle %d\n", tid, curTick() + ticks(delay));
678        scheduleActivateThreadEvent(tid, delay);
679    } else {
680        activateThread(tid);
681    }
682
683    if (lastActivatedCycle < curTick()) {
684        scheduleTickEvent(delay);
685
686        // Be sure to signal that there's some activity so the CPU doesn't
687        // deschedule itself.
688        activityRec.activity();
689        fetch.wakeFromQuiesce();
690
691        lastActivatedCycle = curTick();
692
693        _status = Running;
694    }
695}
696
697template <class Impl>
698bool
699FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay)
700{
701    // Schedule removal of thread data from CPU
702    if (delay){
703        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
704                "on cycle %d\n", tid, curTick() + ticks(delay));
705        scheduleDeallocateContextEvent(tid, remove, delay);
706        return false;
707    } else {
708        deactivateThread(tid);
709        if (remove)
710            removeThread(tid);
711        return true;
712    }
713}
714
715template <class Impl>
716void
717FullO3CPU<Impl>::suspendContext(ThreadID tid)
718{
719    DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
720    bool deallocated = deallocateContext(tid, false, 1);
721    // If this was the last thread then unschedule the tick event.
722    if ((activeThreads.size() == 1 && !deallocated) ||
723        activeThreads.size() == 0)
724        unscheduleTickEvent();
725    _status = Idle;
726}
727
728template <class Impl>
729void
730FullO3CPU<Impl>::haltContext(ThreadID tid)
731{
732    //For now, this is the same as deallocate
733    DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
734    deallocateContext(tid, true, 1);
735}
736
737template <class Impl>
738void
739FullO3CPU<Impl>::insertThread(ThreadID tid)
740{
741    DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
742    // Will change now that the PC and thread state is internal to the CPU
743    // and not in the ThreadContext.
744#if FULL_SYSTEM
745    ThreadContext *src_tc = system->threadContexts[tid];
746#else
747    ThreadContext *src_tc = tcBase(tid);
748#endif
749
750    //Bind Int Regs to Rename Map
751    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
752        PhysRegIndex phys_reg = freeList.getIntReg();
753
754        renameMap[tid].setEntry(ireg,phys_reg);
755        scoreboard.setReg(phys_reg);
756    }
757
758    //Bind Float Regs to Rename Map
759    for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
760        PhysRegIndex phys_reg = freeList.getFloatReg();
761
762        renameMap[tid].setEntry(freg,phys_reg);
763        scoreboard.setReg(phys_reg);
764    }
765
766    //Copy Thread Data Into RegFile
767    //this->copyFromTC(tid);
768
769    //Set PC/NPC/NNPC
770    pcState(src_tc->pcState(), tid);
771
772    src_tc->setStatus(ThreadContext::Active);
773
774    activateContext(tid,1);
775
776    //Reset ROB/IQ/LSQ Entries
777    commit.rob->resetEntries();
778    iew.resetEntries();
779}
780
781template <class Impl>
782void
783FullO3CPU<Impl>::removeThread(ThreadID tid)
784{
785    DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
786
787    // Copy Thread Data From RegFile
788    // If thread is suspended, it might be re-allocated
789    // this->copyToTC(tid);
790
791
792    // @todo: 2-27-2008: Fix how we free up rename mappings
793    // here to alleviate the case for double-freeing registers
794    // in SMT workloads.
795
796    // Unbind Int Regs from Rename Map
797    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
798        PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
799
800        scoreboard.unsetReg(phys_reg);
801        freeList.addReg(phys_reg);
802    }
803
804    // Unbind Float Regs from Rename Map
805    for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
806        PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
807
808        scoreboard.unsetReg(phys_reg);
809        freeList.addReg(phys_reg);
810    }
811
812    // Squash Throughout Pipeline
813    DynInstPtr inst = commit.rob->readHeadInst(tid);
814    InstSeqNum squash_seq_num = inst->seqNum;
815    fetch.squash(0, squash_seq_num, inst, tid);
816    decode.squash(tid);
817    rename.squash(squash_seq_num, tid);
818    iew.squash(tid);
819    iew.ldstQueue.squash(squash_seq_num, tid);
820    commit.rob->squash(squash_seq_num, tid);
821
822
823    assert(iew.instQueue.getCount(tid) == 0);
824    assert(iew.ldstQueue.getCount(tid) == 0);
825
826    // Reset ROB/IQ/LSQ Entries
827
828    // Commented out for now.  This should be possible to do by
829    // telling all the pipeline stages to drain first, and then
830    // checking until the drain completes.  Once the pipeline is
831    // drained, call resetEntries(). - 10-09-06 ktlim
832/*
833    if (activeThreads.size() >= 1) {
834        commit.rob->resetEntries();
835        iew.resetEntries();
836    }
837*/
838}
839
840
841template <class Impl>
842void
843FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
844{
845    DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
846            "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
847            tid);
848
849    bool ready = true;
850
851    if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
852        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
853                "Phys. Int. Regs.\n",
854                tid);
855        ready = false;
856    } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
857        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
858                "Phys. Float. Regs.\n",
859                tid);
860        ready = false;
861    } else if (commit.rob->numFreeEntries() >=
862               commit.rob->entryAmount(activeThreads.size() + 1)) {
863        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
864                "ROB entries.\n",
865                tid);
866        ready = false;
867    } else if (iew.instQueue.numFreeEntries() >=
868               iew.instQueue.entryAmount(activeThreads.size() + 1)) {
869        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
870                "IQ entries.\n",
871                tid);
872        ready = false;
873    } else if (iew.ldstQueue.numFreeEntries() >=
874               iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
875        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
876                "LSQ entries.\n",
877                tid);
878        ready = false;
879    }
880
881    if (ready) {
882        insertThread(tid);
883
884        contextSwitch = false;
885
886        cpuWaitList.remove(tid);
887    } else {
888        suspendContext(tid);
889
890        //blocks fetch
891        contextSwitch = true;
892
893        //@todo: dont always add to waitlist
894        //do waitlist
895        cpuWaitList.push_back(tid);
896    }
897}
898
899#if FULL_SYSTEM
900template <class Impl>
901Fault
902FullO3CPU<Impl>::hwrei(ThreadID tid)
903{
904#if THE_ISA == ALPHA_ISA
905    // Need to clear the lock flag upon returning from an interrupt.
906    this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
907
908    this->thread[tid]->kernelStats->hwrei();
909
910    // FIXME: XXX check for interrupts? XXX
911#endif
912    return NoFault;
913}
914
915template <class Impl>
916bool
917FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
918{
919#if THE_ISA == ALPHA_ISA
920    if (this->thread[tid]->kernelStats)
921        this->thread[tid]->kernelStats->callpal(palFunc,
922                                                this->threadContexts[tid]);
923
924    switch (palFunc) {
925      case PAL::halt:
926        halt();
927        if (--System::numSystemsRunning == 0)
928            exitSimLoop("all cpus halted");
929        break;
930
931      case PAL::bpt:
932      case PAL::bugchk:
933        if (this->system->breakpoint())
934            return false;
935        break;
936    }
937#endif
938    return true;
939}
940
941template <class Impl>
942Fault
943FullO3CPU<Impl>::getInterrupts()
944{
945    // Check if there are any outstanding interrupts
946    return this->interrupts->getInterrupt(this->threadContexts[0]);
947}
948
949template <class Impl>
950void
951FullO3CPU<Impl>::processInterrupts(Fault interrupt)
952{
953    // Check for interrupts here.  For now can copy the code that
954    // exists within isa_fullsys_traits.hh.  Also assume that thread 0
955    // is the one that handles the interrupts.
956    // @todo: Possibly consolidate the interrupt checking code.
957    // @todo: Allow other threads to handle interrupts.
958
959    assert(interrupt != NoFault);
960    this->interrupts->updateIntrInfo(this->threadContexts[0]);
961
962    DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
963    this->trap(interrupt, 0, NULL);
964}
965
966template <class Impl>
967void
968FullO3CPU<Impl>::updateMemPorts()
969{
970    // Update all ThreadContext's memory ports (Functional/Virtual
971    // Ports)
972    ThreadID size = thread.size();
973    for (ThreadID i = 0; i < size; ++i)
974        thread[i]->connectMemPorts(thread[i]->getTC());
975}
976#endif
977
978template <class Impl>
979void
980FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
981{
982    // Pass the thread's TC into the invoke method.
983    fault->invoke(this->threadContexts[tid], inst);
984}
985
986#if !FULL_SYSTEM
987
988template <class Impl>
989void
990FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
991{
992    DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
993
994    DPRINTF(Activity,"Activity: syscall() called.\n");
995
996    // Temporarily increase this by one to account for the syscall
997    // instruction.
998    ++(this->thread[tid]->funcExeInst);
999
1000    // Execute the actual syscall.
1001    this->thread[tid]->syscall(callnum);
1002
1003    // Decrease funcExeInst by one as the normal commit will handle
1004    // incrementing it.
1005    --(this->thread[tid]->funcExeInst);
1006}
1007
1008#endif
1009
1010template <class Impl>
1011void
1012FullO3CPU<Impl>::serialize(std::ostream &os)
1013{
1014    SimObject::State so_state = SimObject::getState();
1015    SERIALIZE_ENUM(so_state);
1016    BaseCPU::serialize(os);
1017    nameOut(os, csprintf("%s.tickEvent", name()));
1018    tickEvent.serialize(os);
1019
1020    // Use SimpleThread's ability to checkpoint to make it easier to
1021    // write out the registers.  Also make this static so it doesn't
1022    // get instantiated multiple times (causes a panic in statistics).
1023    static SimpleThread temp;
1024
1025    ThreadID size = thread.size();
1026    for (ThreadID i = 0; i < size; i++) {
1027        nameOut(os, csprintf("%s.xc.%i", name(), i));
1028        temp.copyTC(thread[i]->getTC());
1029        temp.serialize(os);
1030    }
1031}
1032
1033template <class Impl>
1034void
1035FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
1036{
1037    SimObject::State so_state;
1038    UNSERIALIZE_ENUM(so_state);
1039    BaseCPU::unserialize(cp, section);
1040    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1041
1042    // Use SimpleThread's ability to checkpoint to make it easier to
1043    // read in the registers.  Also make this static so it doesn't
1044    // get instantiated multiple times (causes a panic in statistics).
1045    static SimpleThread temp;
1046
1047    ThreadID size = thread.size();
1048    for (ThreadID i = 0; i < size; i++) {
1049        temp.copyTC(thread[i]->getTC());
1050        temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1051        thread[i]->getTC()->copyArchRegs(temp.getTC());
1052    }
1053}
1054
1055template <class Impl>
1056unsigned int
1057FullO3CPU<Impl>::drain(Event *drain_event)
1058{
1059    DPRINTF(O3CPU, "Switching out\n");
1060
1061    // If the CPU isn't doing anything, then return immediately.
1062    if (_status == Idle || _status == SwitchedOut) {
1063        return 0;
1064    }
1065
1066    drainCount = 0;
1067    fetch.drain();
1068    decode.drain();
1069    rename.drain();
1070    iew.drain();
1071    commit.drain();
1072
1073    // Wake the CPU and record activity so everything can drain out if
1074    // the CPU was not able to immediately drain.
1075    if (getState() != SimObject::Drained) {
1076        // A bit of a hack...set the drainEvent after all the drain()
1077        // calls have been made, that way if all of the stages drain
1078        // immediately, the signalDrained() function knows not to call
1079        // process on the drain event.
1080        drainEvent = drain_event;
1081
1082        wakeCPU();
1083        activityRec.activity();
1084
1085        return 1;
1086    } else {
1087        return 0;
1088    }
1089}
1090
1091template <class Impl>
1092void
1093FullO3CPU<Impl>::resume()
1094{
1095    fetch.resume();
1096    decode.resume();
1097    rename.resume();
1098    iew.resume();
1099    commit.resume();
1100
1101    changeState(SimObject::Running);
1102
1103    if (_status == SwitchedOut || _status == Idle)
1104        return;
1105
1106    assert(system->getMemoryMode() == Enums::timing);
1107
1108    if (!tickEvent.scheduled())
1109        schedule(tickEvent, nextCycle());
1110    _status = Running;
1111}
1112
1113template <class Impl>
1114void
1115FullO3CPU<Impl>::signalDrained()
1116{
1117    if (++drainCount == NumStages) {
1118        if (tickEvent.scheduled())
1119            tickEvent.squash();
1120
1121        changeState(SimObject::Drained);
1122
1123        BaseCPU::switchOut();
1124
1125        if (drainEvent) {
1126            drainEvent->process();
1127            drainEvent = NULL;
1128        }
1129    }
1130    assert(drainCount <= 5);
1131}
1132
1133template <class Impl>
1134void
1135FullO3CPU<Impl>::switchOut()
1136{
1137    fetch.switchOut();
1138    rename.switchOut();
1139    iew.switchOut();
1140    commit.switchOut();
1141    instList.clear();
1142    while (!removeList.empty()) {
1143        removeList.pop();
1144    }
1145
1146    _status = SwitchedOut;
1147#if USE_CHECKER
1148    if (checker)
1149        checker->switchOut();
1150#endif
1151    if (tickEvent.scheduled())
1152        tickEvent.squash();
1153}
1154
1155template <class Impl>
1156void
1157FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1158{
1159    // Flush out any old data from the time buffers.
1160    for (int i = 0; i < timeBuffer.getSize(); ++i) {
1161        timeBuffer.advance();
1162        fetchQueue.advance();
1163        decodeQueue.advance();
1164        renameQueue.advance();
1165        iewQueue.advance();
1166    }
1167
1168    activityRec.reset();
1169
1170    BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort());
1171
1172    fetch.takeOverFrom();
1173    decode.takeOverFrom();
1174    rename.takeOverFrom();
1175    iew.takeOverFrom();
1176    commit.takeOverFrom();
1177
1178    assert(!tickEvent.scheduled() || tickEvent.squashed());
1179
1180    // @todo: Figure out how to properly select the tid to put onto
1181    // the active threads list.
1182    ThreadID tid = 0;
1183
1184    list<ThreadID>::iterator isActive =
1185        std::find(activeThreads.begin(), activeThreads.end(), tid);
1186
1187    if (isActive == activeThreads.end()) {
1188        //May Need to Re-code this if the delay variable is the delay
1189        //needed for thread to activate
1190        DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1191                tid);
1192
1193        activeThreads.push_back(tid);
1194    }
1195
1196    // Set all statuses to active, schedule the CPU's tick event.
1197    // @todo: Fix up statuses so this is handled properly
1198    ThreadID size = threadContexts.size();
1199    for (ThreadID i = 0; i < size; ++i) {
1200        ThreadContext *tc = threadContexts[i];
1201        if (tc->status() == ThreadContext::Active && _status != Running) {
1202            _status = Running;
1203            reschedule(tickEvent, nextCycle(), true);
1204        }
1205    }
1206    if (!tickEvent.scheduled())
1207        schedule(tickEvent, nextCycle());
1208}
1209
1210template <class Impl>
1211TheISA::MiscReg
1212FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1213{
1214    return this->isa[tid].readMiscRegNoEffect(misc_reg);
1215}
1216
1217template <class Impl>
1218TheISA::MiscReg
1219FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1220{
1221    miscRegfileReads++;
1222    return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1223}
1224
1225template <class Impl>
1226void
1227FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1228        const TheISA::MiscReg &val, ThreadID tid)
1229{
1230    this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1231}
1232
1233template <class Impl>
1234void
1235FullO3CPU<Impl>::setMiscReg(int misc_reg,
1236        const TheISA::MiscReg &val, ThreadID tid)
1237{
1238    miscRegfileWrites++;
1239    this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1240}
1241
1242template <class Impl>
1243uint64_t
1244FullO3CPU<Impl>::readIntReg(int reg_idx)
1245{
1246    intRegfileReads++;
1247    return regFile.readIntReg(reg_idx);
1248}
1249
1250template <class Impl>
1251FloatReg
1252FullO3CPU<Impl>::readFloatReg(int reg_idx)
1253{
1254    fpRegfileReads++;
1255    return regFile.readFloatReg(reg_idx);
1256}
1257
1258template <class Impl>
1259FloatRegBits
1260FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1261{
1262    fpRegfileReads++;
1263    return regFile.readFloatRegBits(reg_idx);
1264}
1265
1266template <class Impl>
1267void
1268FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1269{
1270    intRegfileWrites++;
1271    regFile.setIntReg(reg_idx, val);
1272}
1273
1274template <class Impl>
1275void
1276FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1277{
1278    fpRegfileWrites++;
1279    regFile.setFloatReg(reg_idx, val);
1280}
1281
1282template <class Impl>
1283void
1284FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1285{
1286    fpRegfileWrites++;
1287    regFile.setFloatRegBits(reg_idx, val);
1288}
1289
1290template <class Impl>
1291uint64_t
1292FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1293{
1294    intRegfileReads++;
1295    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1296
1297    return regFile.readIntReg(phys_reg);
1298}
1299
1300template <class Impl>
1301float
1302FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1303{
1304    fpRegfileReads++;
1305    int idx = reg_idx + TheISA::NumIntRegs;
1306    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1307
1308    return regFile.readFloatReg(phys_reg);
1309}
1310
1311template <class Impl>
1312uint64_t
1313FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1314{
1315    fpRegfileReads++;
1316    int idx = reg_idx + TheISA::NumIntRegs;
1317    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1318
1319    return regFile.readFloatRegBits(phys_reg);
1320}
1321
1322template <class Impl>
1323void
1324FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1325{
1326    intRegfileWrites++;
1327    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1328
1329    regFile.setIntReg(phys_reg, val);
1330}
1331
1332template <class Impl>
1333void
1334FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1335{
1336    fpRegfileWrites++;
1337    int idx = reg_idx + TheISA::NumIntRegs;
1338    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1339
1340    regFile.setFloatReg(phys_reg, val);
1341}
1342
1343template <class Impl>
1344void
1345FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1346{
1347    fpRegfileWrites++;
1348    int idx = reg_idx + TheISA::NumIntRegs;
1349    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1350
1351    regFile.setFloatRegBits(phys_reg, val);
1352}
1353
1354template <class Impl>
1355TheISA::PCState
1356FullO3CPU<Impl>::pcState(ThreadID tid)
1357{
1358    return commit.pcState(tid);
1359}
1360
1361template <class Impl>
1362void
1363FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1364{
1365    commit.pcState(val, tid);
1366}
1367
1368template <class Impl>
1369Addr
1370FullO3CPU<Impl>::instAddr(ThreadID tid)
1371{
1372    return commit.instAddr(tid);
1373}
1374
1375template <class Impl>
1376Addr
1377FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1378{
1379    return commit.nextInstAddr(tid);
1380}
1381
1382template <class Impl>
1383MicroPC
1384FullO3CPU<Impl>::microPC(ThreadID tid)
1385{
1386    return commit.microPC(tid);
1387}
1388
1389template <class Impl>
1390void
1391FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1392{
1393    this->thread[tid]->inSyscall = true;
1394    this->commit.generateTCEvent(tid);
1395}
1396
1397template <class Impl>
1398typename FullO3CPU<Impl>::ListIt
1399FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1400{
1401    instList.push_back(inst);
1402
1403    return --(instList.end());
1404}
1405
1406template <class Impl>
1407void
1408FullO3CPU<Impl>::instDone(ThreadID tid)
1409{
1410    // Keep an instruction count.
1411    thread[tid]->numInst++;
1412    thread[tid]->numInsts++;
1413    committedInsts[tid]++;
1414    totalCommittedInsts++;
1415    system->totalNumInsts++;
1416    // Check for instruction-count-based events.
1417    comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1418    system->instEventQueue.serviceEvents(system->totalNumInsts);
1419}
1420
1421template <class Impl>
1422void
1423FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1424{
1425    DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1426            "[sn:%lli]\n",
1427            inst->threadNumber, inst->pcState(), inst->seqNum);
1428
1429    removeInstsThisCycle = true;
1430
1431    // Remove the front instruction.
1432    removeList.push(inst->getInstListIt());
1433}
1434
1435template <class Impl>
1436void
1437FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1438{
1439    DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1440            " list.\n", tid);
1441
1442    ListIt end_it;
1443
1444    bool rob_empty = false;
1445
1446    if (instList.empty()) {
1447        return;
1448    } else if (rob.isEmpty(/*tid*/)) {
1449        DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1450        end_it = instList.begin();
1451        rob_empty = true;
1452    } else {
1453        end_it = (rob.readTailInst(tid))->getInstListIt();
1454        DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1455    }
1456
1457    removeInstsThisCycle = true;
1458
1459    ListIt inst_it = instList.end();
1460
1461    inst_it--;
1462
1463    // Walk through the instruction list, removing any instructions
1464    // that were inserted after the given instruction iterator, end_it.
1465    while (inst_it != end_it) {
1466        assert(!instList.empty());
1467
1468        squashInstIt(inst_it, tid);
1469
1470        inst_it--;
1471    }
1472
1473    // If the ROB was empty, then we actually need to remove the first
1474    // instruction as well.
1475    if (rob_empty) {
1476        squashInstIt(inst_it, tid);
1477    }
1478}
1479
1480template <class Impl>
1481void
1482FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1483{
1484    assert(!instList.empty());
1485
1486    removeInstsThisCycle = true;
1487
1488    ListIt inst_iter = instList.end();
1489
1490    inst_iter--;
1491
1492    DPRINTF(O3CPU, "Deleting instructions from instruction "
1493            "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1494            tid, seq_num, (*inst_iter)->seqNum);
1495
1496    while ((*inst_iter)->seqNum > seq_num) {
1497
1498        bool break_loop = (inst_iter == instList.begin());
1499
1500        squashInstIt(inst_iter, tid);
1501
1502        inst_iter--;
1503
1504        if (break_loop)
1505            break;
1506    }
1507}
1508
1509template <class Impl>
1510inline void
1511FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1512{
1513    if ((*instIt)->threadNumber == tid) {
1514        DPRINTF(O3CPU, "Squashing instruction, "
1515                "[tid:%i] [sn:%lli] PC %s\n",
1516                (*instIt)->threadNumber,
1517                (*instIt)->seqNum,
1518                (*instIt)->pcState());
1519
1520        // Mark it as squashed.
1521        (*instIt)->setSquashed();
1522
1523        // @todo: Formulate a consistent method for deleting
1524        // instructions from the instruction list
1525        // Remove the instruction from the list.
1526        removeList.push(instIt);
1527    }
1528}
1529
1530template <class Impl>
1531void
1532FullO3CPU<Impl>::cleanUpRemovedInsts()
1533{
1534    while (!removeList.empty()) {
1535        DPRINTF(O3CPU, "Removing instruction, "
1536                "[tid:%i] [sn:%lli] PC %s\n",
1537                (*removeList.front())->threadNumber,
1538                (*removeList.front())->seqNum,
1539                (*removeList.front())->pcState());
1540
1541        instList.erase(removeList.front());
1542
1543        removeList.pop();
1544    }
1545
1546    removeInstsThisCycle = false;
1547}
1548/*
1549template <class Impl>
1550void
1551FullO3CPU<Impl>::removeAllInsts()
1552{
1553    instList.clear();
1554}
1555*/
1556template <class Impl>
1557void
1558FullO3CPU<Impl>::dumpInsts()
1559{
1560    int num = 0;
1561
1562    ListIt inst_list_it = instList.begin();
1563
1564    cprintf("Dumping Instruction List\n");
1565
1566    while (inst_list_it != instList.end()) {
1567        cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1568                "Squashed:%i\n\n",
1569                num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1570                (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1571                (*inst_list_it)->isSquashed());
1572        inst_list_it++;
1573        ++num;
1574    }
1575}
1576/*
1577template <class Impl>
1578void
1579FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1580{
1581    iew.wakeDependents(inst);
1582}
1583*/
1584template <class Impl>
1585void
1586FullO3CPU<Impl>::wakeCPU()
1587{
1588    if (activityRec.active() || tickEvent.scheduled()) {
1589        DPRINTF(Activity, "CPU already running.\n");
1590        return;
1591    }
1592
1593    DPRINTF(Activity, "Waking up CPU\n");
1594
1595    idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1596    numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1597
1598    schedule(tickEvent, nextCycle());
1599}
1600
1601#if FULL_SYSTEM
1602template <class Impl>
1603void
1604FullO3CPU<Impl>::wakeup()
1605{
1606    if (this->thread[0]->status() != ThreadContext::Suspended)
1607        return;
1608
1609    this->wakeCPU();
1610
1611    DPRINTF(Quiesce, "Suspended Processor woken\n");
1612    this->threadContexts[0]->activate();
1613}
1614#endif
1615
1616template <class Impl>
1617ThreadID
1618FullO3CPU<Impl>::getFreeTid()
1619{
1620    for (ThreadID tid = 0; tid < numThreads; tid++) {
1621        if (!tids[tid]) {
1622            tids[tid] = true;
1623            return tid;
1624        }
1625    }
1626
1627    return InvalidThreadID;
1628}
1629
1630template <class Impl>
1631void
1632FullO3CPU<Impl>::doContextSwitch()
1633{
1634    if (contextSwitch) {
1635
1636        //ADD CODE TO DEACTIVE THREAD HERE (???)
1637
1638        ThreadID size = cpuWaitList.size();
1639        for (ThreadID tid = 0; tid < size; tid++) {
1640            activateWhenReady(tid);
1641        }
1642
1643        if (cpuWaitList.size() == 0)
1644            contextSwitch = true;
1645    }
1646}
1647
1648template <class Impl>
1649void
1650FullO3CPU<Impl>::updateThreadPriority()
1651{
1652    if (activeThreads.size() > 1) {
1653        //DEFAULT TO ROUND ROBIN SCHEME
1654        //e.g. Move highest priority to end of thread list
1655        list<ThreadID>::iterator list_begin = activeThreads.begin();
1656
1657        unsigned high_thread = *list_begin;
1658
1659        activeThreads.erase(list_begin);
1660
1661        activeThreads.push_back(high_thread);
1662    }
1663}
1664
1665// Forward declaration of FullO3CPU.
1666template class FullO3CPU<O3CPUImpl>;
1667