cpu.cc revision 6658:f4de76601762
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include "config/full_system.hh" 33#include "config/the_isa.hh" 34#include "config/use_checker.hh" 35#include "cpu/activity.hh" 36#include "cpu/simple_thread.hh" 37#include "cpu/thread_context.hh" 38#include "cpu/o3/isa_specific.hh" 39#include "cpu/o3/cpu.hh" 40#include "cpu/o3/thread_context.hh" 41#include "enums/MemoryMode.hh" 42#include "sim/core.hh" 43#include "sim/stat_control.hh" 44 45#if FULL_SYSTEM 46#include "cpu/quiesce_event.hh" 47#include "sim/system.hh" 48#else 49#include "sim/process.hh" 50#endif 51 52#if USE_CHECKER 53#include "cpu/checker/cpu.hh" 54#endif 55 56#if THE_ISA == ALPHA_ISA 57#include "arch/alpha/osfpal.hh" 58#endif 59 60class BaseCPUParams; 61 62using namespace TheISA; 63using namespace std; 64 65BaseO3CPU::BaseO3CPU(BaseCPUParams *params) 66 : BaseCPU(params) 67{ 68} 69 70void 71BaseO3CPU::regStats() 72{ 73 BaseCPU::regStats(); 74} 75 76template <class Impl> 77FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 78 : Event(CPU_Tick_Pri), cpu(c) 79{ 80} 81 82template <class Impl> 83void 84FullO3CPU<Impl>::TickEvent::process() 85{ 86 cpu->tick(); 87} 88 89template <class Impl> 90const char * 91FullO3CPU<Impl>::TickEvent::description() const 92{ 93 return "FullO3CPU tick"; 94} 95 96template <class Impl> 97FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 98 : Event(CPU_Switch_Pri) 99{ 100} 101 102template <class Impl> 103void 104FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 105 FullO3CPU<Impl> *thread_cpu) 106{ 107 tid = thread_num; 108 cpu = thread_cpu; 109} 110 111template <class Impl> 112void 113FullO3CPU<Impl>::ActivateThreadEvent::process() 114{ 115 cpu->activateThread(tid); 116} 117 118template <class Impl> 119const char * 120FullO3CPU<Impl>::ActivateThreadEvent::description() const 121{ 122 return "FullO3CPU \"Activate Thread\""; 123} 124 125template <class Impl> 126FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 127 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 128{ 129} 130 131template <class Impl> 132void 133FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 134 FullO3CPU<Impl> *thread_cpu) 135{ 136 tid = thread_num; 137 cpu = thread_cpu; 138 remove = false; 139} 140 141template <class Impl> 142void 143FullO3CPU<Impl>::DeallocateContextEvent::process() 144{ 145 cpu->deactivateThread(tid); 146 if (remove) 147 cpu->removeThread(tid); 148} 149 150template <class Impl> 151const char * 152FullO3CPU<Impl>::DeallocateContextEvent::description() const 153{ 154 return "FullO3CPU \"Deallocate Context\""; 155} 156 157template <class Impl> 158FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 159 : BaseO3CPU(params), 160 itb(params->itb), 161 dtb(params->dtb), 162 tickEvent(this), 163#ifndef NDEBUG 164 instcount(0), 165#endif 166 removeInstsThisCycle(false), 167 fetch(this, params), 168 decode(this, params), 169 rename(this, params), 170 iew(this, params), 171 commit(this, params), 172 173 regFile(this, params->numPhysIntRegs, 174 params->numPhysFloatRegs), 175 176 freeList(params->numThreads, 177 TheISA::NumIntRegs, params->numPhysIntRegs, 178 TheISA::NumFloatRegs, params->numPhysFloatRegs), 179 180 rob(this, 181 params->numROBEntries, params->squashWidth, 182 params->smtROBPolicy, params->smtROBThreshold, 183 params->numThreads), 184 185 scoreboard(params->numThreads, 186 TheISA::NumIntRegs, params->numPhysIntRegs, 187 TheISA::NumFloatRegs, params->numPhysFloatRegs, 188 TheISA::NumMiscRegs * numThreads, 189 TheISA::ZeroReg), 190 191 timeBuffer(params->backComSize, params->forwardComSize), 192 fetchQueue(params->backComSize, params->forwardComSize), 193 decodeQueue(params->backComSize, params->forwardComSize), 194 renameQueue(params->backComSize, params->forwardComSize), 195 iewQueue(params->backComSize, params->forwardComSize), 196 activityRec(name(), NumStages, 197 params->backComSize + params->forwardComSize, 198 params->activity), 199 200 globalSeqNum(1), 201#if FULL_SYSTEM 202 system(params->system), 203 physmem(system->physmem), 204#endif // FULL_SYSTEM 205 drainCount(0), 206 deferRegistration(params->defer_registration) 207{ 208 if (!deferRegistration) { 209 _status = Running; 210 } else { 211 _status = Idle; 212 } 213 214#if USE_CHECKER 215 if (params->checker) { 216 BaseCPU *temp_checker = params->checker; 217 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 218#if FULL_SYSTEM 219 checker->setSystem(params->system); 220#endif 221 } else { 222 checker = NULL; 223 } 224#endif // USE_CHECKER 225 226#if !FULL_SYSTEM 227 thread.resize(numThreads); 228 tids.resize(numThreads); 229#endif 230 231 // The stages also need their CPU pointer setup. However this 232 // must be done at the upper level CPU because they have pointers 233 // to the upper level CPU, and not this FullO3CPU. 234 235 // Set up Pointers to the activeThreads list for each stage 236 fetch.setActiveThreads(&activeThreads); 237 decode.setActiveThreads(&activeThreads); 238 rename.setActiveThreads(&activeThreads); 239 iew.setActiveThreads(&activeThreads); 240 commit.setActiveThreads(&activeThreads); 241 242 // Give each of the stages the time buffer they will use. 243 fetch.setTimeBuffer(&timeBuffer); 244 decode.setTimeBuffer(&timeBuffer); 245 rename.setTimeBuffer(&timeBuffer); 246 iew.setTimeBuffer(&timeBuffer); 247 commit.setTimeBuffer(&timeBuffer); 248 249 // Also setup each of the stages' queues. 250 fetch.setFetchQueue(&fetchQueue); 251 decode.setFetchQueue(&fetchQueue); 252 commit.setFetchQueue(&fetchQueue); 253 decode.setDecodeQueue(&decodeQueue); 254 rename.setDecodeQueue(&decodeQueue); 255 rename.setRenameQueue(&renameQueue); 256 iew.setRenameQueue(&renameQueue); 257 iew.setIEWQueue(&iewQueue); 258 commit.setIEWQueue(&iewQueue); 259 commit.setRenameQueue(&renameQueue); 260 261 commit.setIEWStage(&iew); 262 rename.setIEWStage(&iew); 263 rename.setCommitStage(&commit); 264 265#if !FULL_SYSTEM 266 ThreadID active_threads = params->workload.size(); 267 268 if (active_threads > Impl::MaxThreads) { 269 panic("Workload Size too large. Increase the 'MaxThreads'" 270 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 271 "edit your workload size."); 272 } 273#else 274 ThreadID active_threads = 1; 275#endif 276 277 //Make Sure That this a Valid Architeture 278 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 279 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 280 281 rename.setScoreboard(&scoreboard); 282 iew.setScoreboard(&scoreboard); 283 284 // Setup the rename map for whichever stages need it. 285 PhysRegIndex lreg_idx = 0; 286 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 287 288 for (ThreadID tid = 0; tid < numThreads; tid++) { 289 bool bindRegs = (tid <= active_threads - 1); 290 291 commitRenameMap[tid].init(TheISA::NumIntRegs, 292 params->numPhysIntRegs, 293 lreg_idx, //Index for Logical. Regs 294 295 TheISA::NumFloatRegs, 296 params->numPhysFloatRegs, 297 freg_idx, //Index for Float Regs 298 299 TheISA::NumMiscRegs, 300 301 TheISA::ZeroReg, 302 TheISA::ZeroReg, 303 304 tid, 305 false); 306 307 renameMap[tid].init(TheISA::NumIntRegs, 308 params->numPhysIntRegs, 309 lreg_idx, //Index for Logical. Regs 310 311 TheISA::NumFloatRegs, 312 params->numPhysFloatRegs, 313 freg_idx, //Index for Float Regs 314 315 TheISA::NumMiscRegs, 316 317 TheISA::ZeroReg, 318 TheISA::ZeroReg, 319 320 tid, 321 bindRegs); 322 323 activateThreadEvent[tid].init(tid, this); 324 deallocateContextEvent[tid].init(tid, this); 325 } 326 327 rename.setRenameMap(renameMap); 328 commit.setRenameMap(commitRenameMap); 329 330 // Give renameMap & rename stage access to the freeList; 331 for (ThreadID tid = 0; tid < numThreads; tid++) 332 renameMap[tid].setFreeList(&freeList); 333 rename.setFreeList(&freeList); 334 335 // Setup the ROB for whichever stages need it. 336 commit.setROB(&rob); 337 338 lastRunningCycle = curTick; 339 340 lastActivatedCycle = -1; 341#if 0 342 // Give renameMap & rename stage access to the freeList; 343 for (ThreadID tid = 0; tid < numThreads; tid++) 344 globalSeqNum[tid] = 1; 345#endif 346 347 contextSwitch = false; 348 DPRINTF(O3CPU, "Creating O3CPU object.\n"); 349 350 // Setup any thread state. 351 this->thread.resize(this->numThreads); 352 353 for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 354#if FULL_SYSTEM 355 // SMT is not supported in FS mode yet. 356 assert(this->numThreads == 1); 357 this->thread[tid] = new Thread(this, 0); 358#else 359 if (tid < params->workload.size()) { 360 DPRINTF(O3CPU, "Workload[%i] process is %#x", 361 tid, this->thread[tid]); 362 this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 363 (typename Impl::O3CPU *)(this), 364 tid, params->workload[tid]); 365 366 //usedTids[tid] = true; 367 //threadMap[tid] = tid; 368 } else { 369 //Allocate Empty thread so M5 can use later 370 //when scheduling threads to CPU 371 Process* dummy_proc = NULL; 372 373 this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 374 (typename Impl::O3CPU *)(this), 375 tid, dummy_proc); 376 //usedTids[tid] = false; 377 } 378#endif // !FULL_SYSTEM 379 380 ThreadContext *tc; 381 382 // Setup the TC that will serve as the interface to the threads/CPU. 383 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 384 385 tc = o3_tc; 386 387 // If we're using a checker, then the TC should be the 388 // CheckerThreadContext. 389#if USE_CHECKER 390 if (params->checker) { 391 tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 392 o3_tc, this->checker); 393 } 394#endif 395 396 o3_tc->cpu = (typename Impl::O3CPU *)(this); 397 assert(o3_tc->cpu); 398 o3_tc->thread = this->thread[tid]; 399 400#if FULL_SYSTEM 401 // Setup quiesce event. 402 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 403#endif 404 // Give the thread the TC. 405 this->thread[tid]->tc = tc; 406 407 // Add the TC to the CPU's list of TC's. 408 this->threadContexts.push_back(tc); 409 } 410 411 for (ThreadID tid = 0; tid < this->numThreads; tid++) 412 this->thread[tid]->setFuncExeInst(0); 413 414 lockAddr = 0; 415 lockFlag = false; 416} 417 418template <class Impl> 419FullO3CPU<Impl>::~FullO3CPU() 420{ 421} 422 423template <class Impl> 424void 425FullO3CPU<Impl>::regStats() 426{ 427 BaseO3CPU::regStats(); 428 429 // Register any of the O3CPU's stats here. 430 timesIdled 431 .name(name() + ".timesIdled") 432 .desc("Number of times that the entire CPU went into an idle state and" 433 " unscheduled itself") 434 .prereq(timesIdled); 435 436 idleCycles 437 .name(name() + ".idleCycles") 438 .desc("Total number of cycles that the CPU has spent unscheduled due " 439 "to idling") 440 .prereq(idleCycles); 441 442 // Number of Instructions simulated 443 // -------------------------------- 444 // Should probably be in Base CPU but need templated 445 // MaxThreads so put in here instead 446 committedInsts 447 .init(numThreads) 448 .name(name() + ".committedInsts") 449 .desc("Number of Instructions Simulated"); 450 451 totalCommittedInsts 452 .name(name() + ".committedInsts_total") 453 .desc("Number of Instructions Simulated"); 454 455 cpi 456 .name(name() + ".cpi") 457 .desc("CPI: Cycles Per Instruction") 458 .precision(6); 459 cpi = numCycles / committedInsts; 460 461 totalCpi 462 .name(name() + ".cpi_total") 463 .desc("CPI: Total CPI of All Threads") 464 .precision(6); 465 totalCpi = numCycles / totalCommittedInsts; 466 467 ipc 468 .name(name() + ".ipc") 469 .desc("IPC: Instructions Per Cycle") 470 .precision(6); 471 ipc = committedInsts / numCycles; 472 473 totalIpc 474 .name(name() + ".ipc_total") 475 .desc("IPC: Total IPC of All Threads") 476 .precision(6); 477 totalIpc = totalCommittedInsts / numCycles; 478 479 this->fetch.regStats(); 480 this->decode.regStats(); 481 this->rename.regStats(); 482 this->iew.regStats(); 483 this->commit.regStats(); 484} 485 486template <class Impl> 487Port * 488FullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 489{ 490 if (if_name == "dcache_port") 491 return iew.getDcachePort(); 492 else if (if_name == "icache_port") 493 return fetch.getIcachePort(); 494 else 495 panic("No Such Port\n"); 496} 497 498template <class Impl> 499void 500FullO3CPU<Impl>::tick() 501{ 502 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 503 504 ++numCycles; 505 506// activity = false; 507 508 //Tick each of the stages 509 fetch.tick(); 510 511 decode.tick(); 512 513 rename.tick(); 514 515 iew.tick(); 516 517 commit.tick(); 518 519#if !FULL_SYSTEM 520 doContextSwitch(); 521#endif 522 523 // Now advance the time buffers 524 timeBuffer.advance(); 525 526 fetchQueue.advance(); 527 decodeQueue.advance(); 528 renameQueue.advance(); 529 iewQueue.advance(); 530 531 activityRec.advance(); 532 533 if (removeInstsThisCycle) { 534 cleanUpRemovedInsts(); 535 } 536 537 if (!tickEvent.scheduled()) { 538 if (_status == SwitchedOut || 539 getState() == SimObject::Drained) { 540 DPRINTF(O3CPU, "Switched out!\n"); 541 // increment stat 542 lastRunningCycle = curTick; 543 } else if (!activityRec.active() || _status == Idle) { 544 DPRINTF(O3CPU, "Idle!\n"); 545 lastRunningCycle = curTick; 546 timesIdled++; 547 } else { 548 schedule(tickEvent, nextCycle(curTick + ticks(1))); 549 DPRINTF(O3CPU, "Scheduling next tick!\n"); 550 } 551 } 552 553#if !FULL_SYSTEM 554 updateThreadPriority(); 555#endif 556} 557 558template <class Impl> 559void 560FullO3CPU<Impl>::init() 561{ 562 BaseCPU::init(); 563 564 // Set inSyscall so that the CPU doesn't squash when initially 565 // setting up registers. 566 for (ThreadID tid = 0; tid < numThreads; ++tid) 567 thread[tid]->inSyscall = true; 568 569#if FULL_SYSTEM 570 for (ThreadID tid = 0; tid < numThreads; tid++) { 571 ThreadContext *src_tc = threadContexts[tid]; 572 TheISA::initCPU(src_tc, src_tc->contextId()); 573 } 574#endif 575 576 // Clear inSyscall. 577 for (int tid = 0; tid < numThreads; ++tid) 578 thread[tid]->inSyscall = false; 579 580 // Initialize stages. 581 fetch.initStage(); 582 iew.initStage(); 583 rename.initStage(); 584 commit.initStage(); 585 586 commit.setThreads(thread); 587} 588 589template <class Impl> 590void 591FullO3CPU<Impl>::activateThread(ThreadID tid) 592{ 593 list<ThreadID>::iterator isActive = 594 std::find(activeThreads.begin(), activeThreads.end(), tid); 595 596 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 597 598 if (isActive == activeThreads.end()) { 599 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 600 tid); 601 602 activeThreads.push_back(tid); 603 } 604} 605 606template <class Impl> 607void 608FullO3CPU<Impl>::deactivateThread(ThreadID tid) 609{ 610 //Remove From Active List, if Active 611 list<ThreadID>::iterator thread_it = 612 std::find(activeThreads.begin(), activeThreads.end(), tid); 613 614 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 615 616 if (thread_it != activeThreads.end()) { 617 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 618 tid); 619 activeThreads.erase(thread_it); 620 } 621} 622 623template <class Impl> 624Counter 625FullO3CPU<Impl>::totalInstructions() const 626{ 627 Counter total(0); 628 629 ThreadID size = thread.size(); 630 for (ThreadID i = 0; i < size; i++) 631 total += thread[i]->numInst; 632 633 return total; 634} 635 636template <class Impl> 637void 638FullO3CPU<Impl>::activateContext(ThreadID tid, int delay) 639{ 640 // Needs to set each stage to running as well. 641 if (delay){ 642 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 643 "on cycle %d\n", tid, curTick + ticks(delay)); 644 scheduleActivateThreadEvent(tid, delay); 645 } else { 646 activateThread(tid); 647 } 648 649 if (lastActivatedCycle < curTick) { 650 scheduleTickEvent(delay); 651 652 // Be sure to signal that there's some activity so the CPU doesn't 653 // deschedule itself. 654 activityRec.activity(); 655 fetch.wakeFromQuiesce(); 656 657 lastActivatedCycle = curTick; 658 659 _status = Running; 660 } 661} 662 663template <class Impl> 664bool 665FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay) 666{ 667 // Schedule removal of thread data from CPU 668 if (delay){ 669 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 670 "on cycle %d\n", tid, curTick + ticks(delay)); 671 scheduleDeallocateContextEvent(tid, remove, delay); 672 return false; 673 } else { 674 deactivateThread(tid); 675 if (remove) 676 removeThread(tid); 677 return true; 678 } 679} 680 681template <class Impl> 682void 683FullO3CPU<Impl>::suspendContext(ThreadID tid) 684{ 685 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 686 bool deallocated = deallocateContext(tid, false, 1); 687 // If this was the last thread then unschedule the tick event. 688 if ((activeThreads.size() == 1 && !deallocated) || 689 activeThreads.size() == 0) 690 unscheduleTickEvent(); 691 _status = Idle; 692} 693 694template <class Impl> 695void 696FullO3CPU<Impl>::haltContext(ThreadID tid) 697{ 698 //For now, this is the same as deallocate 699 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 700 deallocateContext(tid, true, 1); 701} 702 703template <class Impl> 704void 705FullO3CPU<Impl>::insertThread(ThreadID tid) 706{ 707 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 708 // Will change now that the PC and thread state is internal to the CPU 709 // and not in the ThreadContext. 710#if FULL_SYSTEM 711 ThreadContext *src_tc = system->threadContexts[tid]; 712#else 713 ThreadContext *src_tc = tcBase(tid); 714#endif 715 716 //Bind Int Regs to Rename Map 717 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 718 PhysRegIndex phys_reg = freeList.getIntReg(); 719 720 renameMap[tid].setEntry(ireg,phys_reg); 721 scoreboard.setReg(phys_reg); 722 } 723 724 //Bind Float Regs to Rename Map 725 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 726 PhysRegIndex phys_reg = freeList.getFloatReg(); 727 728 renameMap[tid].setEntry(freg,phys_reg); 729 scoreboard.setReg(phys_reg); 730 } 731 732 //Copy Thread Data Into RegFile 733 //this->copyFromTC(tid); 734 735 //Set PC/NPC/NNPC 736 setPC(src_tc->readPC(), tid); 737 setNextPC(src_tc->readNextPC(), tid); 738 setNextNPC(src_tc->readNextNPC(), tid); 739 740 src_tc->setStatus(ThreadContext::Active); 741 742 activateContext(tid,1); 743 744 //Reset ROB/IQ/LSQ Entries 745 commit.rob->resetEntries(); 746 iew.resetEntries(); 747} 748 749template <class Impl> 750void 751FullO3CPU<Impl>::removeThread(ThreadID tid) 752{ 753 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 754 755 // Copy Thread Data From RegFile 756 // If thread is suspended, it might be re-allocated 757 // this->copyToTC(tid); 758 759 760 // @todo: 2-27-2008: Fix how we free up rename mappings 761 // here to alleviate the case for double-freeing registers 762 // in SMT workloads. 763 764 // Unbind Int Regs from Rename Map 765 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 766 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 767 768 scoreboard.unsetReg(phys_reg); 769 freeList.addReg(phys_reg); 770 } 771 772 // Unbind Float Regs from Rename Map 773 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 774 PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 775 776 scoreboard.unsetReg(phys_reg); 777 freeList.addReg(phys_reg); 778 } 779 780 // Squash Throughout Pipeline 781 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 782 fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid); 783 decode.squash(tid); 784 rename.squash(squash_seq_num, tid); 785 iew.squash(tid); 786 iew.ldstQueue.squash(squash_seq_num, tid); 787 commit.rob->squash(squash_seq_num, tid); 788 789 790 assert(iew.instQueue.getCount(tid) == 0); 791 assert(iew.ldstQueue.getCount(tid) == 0); 792 793 // Reset ROB/IQ/LSQ Entries 794 795 // Commented out for now. This should be possible to do by 796 // telling all the pipeline stages to drain first, and then 797 // checking until the drain completes. Once the pipeline is 798 // drained, call resetEntries(). - 10-09-06 ktlim 799/* 800 if (activeThreads.size() >= 1) { 801 commit.rob->resetEntries(); 802 iew.resetEntries(); 803 } 804*/ 805} 806 807 808template <class Impl> 809void 810FullO3CPU<Impl>::activateWhenReady(ThreadID tid) 811{ 812 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 813 "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 814 tid); 815 816 bool ready = true; 817 818 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 819 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 820 "Phys. Int. Regs.\n", 821 tid); 822 ready = false; 823 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 824 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 825 "Phys. Float. Regs.\n", 826 tid); 827 ready = false; 828 } else if (commit.rob->numFreeEntries() >= 829 commit.rob->entryAmount(activeThreads.size() + 1)) { 830 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 831 "ROB entries.\n", 832 tid); 833 ready = false; 834 } else if (iew.instQueue.numFreeEntries() >= 835 iew.instQueue.entryAmount(activeThreads.size() + 1)) { 836 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 837 "IQ entries.\n", 838 tid); 839 ready = false; 840 } else if (iew.ldstQueue.numFreeEntries() >= 841 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 842 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 843 "LSQ entries.\n", 844 tid); 845 ready = false; 846 } 847 848 if (ready) { 849 insertThread(tid); 850 851 contextSwitch = false; 852 853 cpuWaitList.remove(tid); 854 } else { 855 suspendContext(tid); 856 857 //blocks fetch 858 contextSwitch = true; 859 860 //@todo: dont always add to waitlist 861 //do waitlist 862 cpuWaitList.push_back(tid); 863 } 864} 865 866#if FULL_SYSTEM 867template <class Impl> 868Fault 869FullO3CPU<Impl>::hwrei(ThreadID tid) 870{ 871#if THE_ISA == ALPHA_ISA 872 // Need to clear the lock flag upon returning from an interrupt. 873 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 874 875 this->thread[tid]->kernelStats->hwrei(); 876 877 // FIXME: XXX check for interrupts? XXX 878#endif 879 return NoFault; 880} 881 882template <class Impl> 883bool 884FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 885{ 886#if THE_ISA == ALPHA_ISA 887 if (this->thread[tid]->kernelStats) 888 this->thread[tid]->kernelStats->callpal(palFunc, 889 this->threadContexts[tid]); 890 891 switch (palFunc) { 892 case PAL::halt: 893 halt(); 894 if (--System::numSystemsRunning == 0) 895 exitSimLoop("all cpus halted"); 896 break; 897 898 case PAL::bpt: 899 case PAL::bugchk: 900 if (this->system->breakpoint()) 901 return false; 902 break; 903 } 904#endif 905 return true; 906} 907 908template <class Impl> 909Fault 910FullO3CPU<Impl>::getInterrupts() 911{ 912 // Check if there are any outstanding interrupts 913 return this->interrupts->getInterrupt(this->threadContexts[0]); 914} 915 916template <class Impl> 917void 918FullO3CPU<Impl>::processInterrupts(Fault interrupt) 919{ 920 // Check for interrupts here. For now can copy the code that 921 // exists within isa_fullsys_traits.hh. Also assume that thread 0 922 // is the one that handles the interrupts. 923 // @todo: Possibly consolidate the interrupt checking code. 924 // @todo: Allow other threads to handle interrupts. 925 926 assert(interrupt != NoFault); 927 this->interrupts->updateIntrInfo(this->threadContexts[0]); 928 929 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 930 this->trap(interrupt, 0); 931} 932 933template <class Impl> 934void 935FullO3CPU<Impl>::updateMemPorts() 936{ 937 // Update all ThreadContext's memory ports (Functional/Virtual 938 // Ports) 939 ThreadID size = thread.size(); 940 for (ThreadID i = 0; i < size; ++i) 941 thread[i]->connectMemPorts(thread[i]->getTC()); 942} 943#endif 944 945template <class Impl> 946void 947FullO3CPU<Impl>::trap(Fault fault, ThreadID tid) 948{ 949 // Pass the thread's TC into the invoke method. 950 fault->invoke(this->threadContexts[tid]); 951} 952 953#if !FULL_SYSTEM 954 955template <class Impl> 956void 957FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 958{ 959 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 960 961 DPRINTF(Activity,"Activity: syscall() called.\n"); 962 963 // Temporarily increase this by one to account for the syscall 964 // instruction. 965 ++(this->thread[tid]->funcExeInst); 966 967 // Execute the actual syscall. 968 this->thread[tid]->syscall(callnum); 969 970 // Decrease funcExeInst by one as the normal commit will handle 971 // incrementing it. 972 --(this->thread[tid]->funcExeInst); 973} 974 975#endif 976 977template <class Impl> 978void 979FullO3CPU<Impl>::serialize(std::ostream &os) 980{ 981 SimObject::State so_state = SimObject::getState(); 982 SERIALIZE_ENUM(so_state); 983 BaseCPU::serialize(os); 984 nameOut(os, csprintf("%s.tickEvent", name())); 985 tickEvent.serialize(os); 986 987 // Use SimpleThread's ability to checkpoint to make it easier to 988 // write out the registers. Also make this static so it doesn't 989 // get instantiated multiple times (causes a panic in statistics). 990 static SimpleThread temp; 991 992 ThreadID size = thread.size(); 993 for (ThreadID i = 0; i < size; i++) { 994 nameOut(os, csprintf("%s.xc.%i", name(), i)); 995 temp.copyTC(thread[i]->getTC()); 996 temp.serialize(os); 997 } 998} 999 1000template <class Impl> 1001void 1002FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 1003{ 1004 SimObject::State so_state; 1005 UNSERIALIZE_ENUM(so_state); 1006 BaseCPU::unserialize(cp, section); 1007 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1008 1009 // Use SimpleThread's ability to checkpoint to make it easier to 1010 // read in the registers. Also make this static so it doesn't 1011 // get instantiated multiple times (causes a panic in statistics). 1012 static SimpleThread temp; 1013 1014 ThreadID size = thread.size(); 1015 for (ThreadID i = 0; i < size; i++) { 1016 temp.copyTC(thread[i]->getTC()); 1017 temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 1018 thread[i]->getTC()->copyArchRegs(temp.getTC()); 1019 } 1020} 1021 1022template <class Impl> 1023unsigned int 1024FullO3CPU<Impl>::drain(Event *drain_event) 1025{ 1026 DPRINTF(O3CPU, "Switching out\n"); 1027 1028 // If the CPU isn't doing anything, then return immediately. 1029 if (_status == Idle || _status == SwitchedOut) { 1030 return 0; 1031 } 1032 1033 drainCount = 0; 1034 fetch.drain(); 1035 decode.drain(); 1036 rename.drain(); 1037 iew.drain(); 1038 commit.drain(); 1039 1040 // Wake the CPU and record activity so everything can drain out if 1041 // the CPU was not able to immediately drain. 1042 if (getState() != SimObject::Drained) { 1043 // A bit of a hack...set the drainEvent after all the drain() 1044 // calls have been made, that way if all of the stages drain 1045 // immediately, the signalDrained() function knows not to call 1046 // process on the drain event. 1047 drainEvent = drain_event; 1048 1049 wakeCPU(); 1050 activityRec.activity(); 1051 1052 return 1; 1053 } else { 1054 return 0; 1055 } 1056} 1057 1058template <class Impl> 1059void 1060FullO3CPU<Impl>::resume() 1061{ 1062 fetch.resume(); 1063 decode.resume(); 1064 rename.resume(); 1065 iew.resume(); 1066 commit.resume(); 1067 1068 changeState(SimObject::Running); 1069 1070 if (_status == SwitchedOut || _status == Idle) 1071 return; 1072 1073#if FULL_SYSTEM 1074 assert(system->getMemoryMode() == Enums::timing); 1075#endif 1076 1077 if (!tickEvent.scheduled()) 1078 schedule(tickEvent, nextCycle()); 1079 _status = Running; 1080} 1081 1082template <class Impl> 1083void 1084FullO3CPU<Impl>::signalDrained() 1085{ 1086 if (++drainCount == NumStages) { 1087 if (tickEvent.scheduled()) 1088 tickEvent.squash(); 1089 1090 changeState(SimObject::Drained); 1091 1092 BaseCPU::switchOut(); 1093 1094 if (drainEvent) { 1095 drainEvent->process(); 1096 drainEvent = NULL; 1097 } 1098 } 1099 assert(drainCount <= 5); 1100} 1101 1102template <class Impl> 1103void 1104FullO3CPU<Impl>::switchOut() 1105{ 1106 fetch.switchOut(); 1107 rename.switchOut(); 1108 iew.switchOut(); 1109 commit.switchOut(); 1110 instList.clear(); 1111 while (!removeList.empty()) { 1112 removeList.pop(); 1113 } 1114 1115 _status = SwitchedOut; 1116#if USE_CHECKER 1117 if (checker) 1118 checker->switchOut(); 1119#endif 1120 if (tickEvent.scheduled()) 1121 tickEvent.squash(); 1122} 1123 1124template <class Impl> 1125void 1126FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 1127{ 1128 // Flush out any old data from the time buffers. 1129 for (int i = 0; i < timeBuffer.getSize(); ++i) { 1130 timeBuffer.advance(); 1131 fetchQueue.advance(); 1132 decodeQueue.advance(); 1133 renameQueue.advance(); 1134 iewQueue.advance(); 1135 } 1136 1137 activityRec.reset(); 1138 1139 BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 1140 1141 fetch.takeOverFrom(); 1142 decode.takeOverFrom(); 1143 rename.takeOverFrom(); 1144 iew.takeOverFrom(); 1145 commit.takeOverFrom(); 1146 1147 assert(!tickEvent.scheduled()); 1148 1149 // @todo: Figure out how to properly select the tid to put onto 1150 // the active threads list. 1151 ThreadID tid = 0; 1152 1153 list<ThreadID>::iterator isActive = 1154 std::find(activeThreads.begin(), activeThreads.end(), tid); 1155 1156 if (isActive == activeThreads.end()) { 1157 //May Need to Re-code this if the delay variable is the delay 1158 //needed for thread to activate 1159 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 1160 tid); 1161 1162 activeThreads.push_back(tid); 1163 } 1164 1165 // Set all statuses to active, schedule the CPU's tick event. 1166 // @todo: Fix up statuses so this is handled properly 1167 ThreadID size = threadContexts.size(); 1168 for (ThreadID i = 0; i < size; ++i) { 1169 ThreadContext *tc = threadContexts[i]; 1170 if (tc->status() == ThreadContext::Active && _status != Running) { 1171 _status = Running; 1172 schedule(tickEvent, nextCycle()); 1173 } 1174 } 1175 if (!tickEvent.scheduled()) 1176 schedule(tickEvent, nextCycle()); 1177} 1178 1179template <class Impl> 1180TheISA::MiscReg 1181FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 1182{ 1183 return this->isa[tid].readMiscRegNoEffect(misc_reg); 1184} 1185 1186template <class Impl> 1187TheISA::MiscReg 1188FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 1189{ 1190 return this->isa[tid].readMiscReg(misc_reg, tcBase(tid)); 1191} 1192 1193template <class Impl> 1194void 1195FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 1196 const TheISA::MiscReg &val, ThreadID tid) 1197{ 1198 this->isa[tid].setMiscRegNoEffect(misc_reg, val); 1199} 1200 1201template <class Impl> 1202void 1203FullO3CPU<Impl>::setMiscReg(int misc_reg, 1204 const TheISA::MiscReg &val, ThreadID tid) 1205{ 1206 this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); 1207} 1208 1209template <class Impl> 1210uint64_t 1211FullO3CPU<Impl>::readIntReg(int reg_idx) 1212{ 1213 return regFile.readIntReg(reg_idx); 1214} 1215 1216template <class Impl> 1217FloatReg 1218FullO3CPU<Impl>::readFloatReg(int reg_idx) 1219{ 1220 return regFile.readFloatReg(reg_idx); 1221} 1222 1223template <class Impl> 1224FloatRegBits 1225FullO3CPU<Impl>::readFloatRegBits(int reg_idx) 1226{ 1227 return regFile.readFloatRegBits(reg_idx); 1228} 1229 1230template <class Impl> 1231void 1232FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 1233{ 1234 regFile.setIntReg(reg_idx, val); 1235} 1236 1237template <class Impl> 1238void 1239FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 1240{ 1241 regFile.setFloatReg(reg_idx, val); 1242} 1243 1244template <class Impl> 1245void 1246FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 1247{ 1248 regFile.setFloatRegBits(reg_idx, val); 1249} 1250 1251template <class Impl> 1252uint64_t 1253FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 1254{ 1255 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 1256 1257 return regFile.readIntReg(phys_reg); 1258} 1259 1260template <class Impl> 1261float 1262FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 1263{ 1264 int idx = reg_idx + TheISA::NumIntRegs; 1265 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1266 1267 return regFile.readFloatReg(phys_reg); 1268} 1269 1270template <class Impl> 1271uint64_t 1272FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 1273{ 1274 int idx = reg_idx + TheISA::NumIntRegs; 1275 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1276 1277 return regFile.readFloatRegBits(phys_reg); 1278} 1279 1280template <class Impl> 1281void 1282FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 1283{ 1284 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 1285 1286 regFile.setIntReg(phys_reg, val); 1287} 1288 1289template <class Impl> 1290void 1291FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 1292{ 1293 int idx = reg_idx + TheISA::NumIntRegs; 1294 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1295 1296 regFile.setFloatReg(phys_reg, val); 1297} 1298 1299template <class Impl> 1300void 1301FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 1302{ 1303 int idx = reg_idx + TheISA::NumIntRegs; 1304 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1305 1306 regFile.setFloatRegBits(phys_reg, val); 1307} 1308 1309template <class Impl> 1310uint64_t 1311FullO3CPU<Impl>::readPC(ThreadID tid) 1312{ 1313 return commit.readPC(tid); 1314} 1315 1316template <class Impl> 1317void 1318FullO3CPU<Impl>::setPC(Addr new_PC, ThreadID tid) 1319{ 1320 commit.setPC(new_PC, tid); 1321} 1322 1323template <class Impl> 1324uint64_t 1325FullO3CPU<Impl>::readMicroPC(ThreadID tid) 1326{ 1327 return commit.readMicroPC(tid); 1328} 1329 1330template <class Impl> 1331void 1332FullO3CPU<Impl>::setMicroPC(Addr new_PC, ThreadID tid) 1333{ 1334 commit.setMicroPC(new_PC, tid); 1335} 1336 1337template <class Impl> 1338uint64_t 1339FullO3CPU<Impl>::readNextPC(ThreadID tid) 1340{ 1341 return commit.readNextPC(tid); 1342} 1343 1344template <class Impl> 1345void 1346FullO3CPU<Impl>::setNextPC(uint64_t val, ThreadID tid) 1347{ 1348 commit.setNextPC(val, tid); 1349} 1350 1351template <class Impl> 1352uint64_t 1353FullO3CPU<Impl>::readNextNPC(ThreadID tid) 1354{ 1355 return commit.readNextNPC(tid); 1356} 1357 1358template <class Impl> 1359void 1360FullO3CPU<Impl>::setNextNPC(uint64_t val, ThreadID tid) 1361{ 1362 commit.setNextNPC(val, tid); 1363} 1364 1365template <class Impl> 1366uint64_t 1367FullO3CPU<Impl>::readNextMicroPC(ThreadID tid) 1368{ 1369 return commit.readNextMicroPC(tid); 1370} 1371 1372template <class Impl> 1373void 1374FullO3CPU<Impl>::setNextMicroPC(Addr new_PC, ThreadID tid) 1375{ 1376 commit.setNextMicroPC(new_PC, tid); 1377} 1378 1379template <class Impl> 1380void 1381FullO3CPU<Impl>::squashFromTC(ThreadID tid) 1382{ 1383 this->thread[tid]->inSyscall = true; 1384 this->commit.generateTCEvent(tid); 1385} 1386 1387template <class Impl> 1388typename FullO3CPU<Impl>::ListIt 1389FullO3CPU<Impl>::addInst(DynInstPtr &inst) 1390{ 1391 instList.push_back(inst); 1392 1393 return --(instList.end()); 1394} 1395 1396template <class Impl> 1397void 1398FullO3CPU<Impl>::instDone(ThreadID tid) 1399{ 1400 // Keep an instruction count. 1401 thread[tid]->numInst++; 1402 thread[tid]->numInsts++; 1403 committedInsts[tid]++; 1404 totalCommittedInsts++; 1405 1406 // Check for instruction-count-based events. 1407 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 1408} 1409 1410template <class Impl> 1411void 1412FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 1413{ 1414 removeInstsThisCycle = true; 1415 1416 removeList.push(inst->getInstListIt()); 1417} 1418 1419template <class Impl> 1420void 1421FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 1422{ 1423 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 1424 "[sn:%lli]\n", 1425 inst->threadNumber, inst->readPC(), inst->seqNum); 1426 1427 removeInstsThisCycle = true; 1428 1429 // Remove the front instruction. 1430 removeList.push(inst->getInstListIt()); 1431} 1432 1433template <class Impl> 1434void 1435FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 1436{ 1437 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 1438 " list.\n", tid); 1439 1440 ListIt end_it; 1441 1442 bool rob_empty = false; 1443 1444 if (instList.empty()) { 1445 return; 1446 } else if (rob.isEmpty(/*tid*/)) { 1447 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 1448 end_it = instList.begin(); 1449 rob_empty = true; 1450 } else { 1451 end_it = (rob.readTailInst(tid))->getInstListIt(); 1452 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 1453 } 1454 1455 removeInstsThisCycle = true; 1456 1457 ListIt inst_it = instList.end(); 1458 1459 inst_it--; 1460 1461 // Walk through the instruction list, removing any instructions 1462 // that were inserted after the given instruction iterator, end_it. 1463 while (inst_it != end_it) { 1464 assert(!instList.empty()); 1465 1466 squashInstIt(inst_it, tid); 1467 1468 inst_it--; 1469 } 1470 1471 // If the ROB was empty, then we actually need to remove the first 1472 // instruction as well. 1473 if (rob_empty) { 1474 squashInstIt(inst_it, tid); 1475 } 1476} 1477 1478template <class Impl> 1479void 1480FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 1481{ 1482 assert(!instList.empty()); 1483 1484 removeInstsThisCycle = true; 1485 1486 ListIt inst_iter = instList.end(); 1487 1488 inst_iter--; 1489 1490 DPRINTF(O3CPU, "Deleting instructions from instruction " 1491 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 1492 tid, seq_num, (*inst_iter)->seqNum); 1493 1494 while ((*inst_iter)->seqNum > seq_num) { 1495 1496 bool break_loop = (inst_iter == instList.begin()); 1497 1498 squashInstIt(inst_iter, tid); 1499 1500 inst_iter--; 1501 1502 if (break_loop) 1503 break; 1504 } 1505} 1506 1507template <class Impl> 1508inline void 1509FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 1510{ 1511 if ((*instIt)->threadNumber == tid) { 1512 DPRINTF(O3CPU, "Squashing instruction, " 1513 "[tid:%i] [sn:%lli] PC %#x\n", 1514 (*instIt)->threadNumber, 1515 (*instIt)->seqNum, 1516 (*instIt)->readPC()); 1517 1518 // Mark it as squashed. 1519 (*instIt)->setSquashed(); 1520 1521 // @todo: Formulate a consistent method for deleting 1522 // instructions from the instruction list 1523 // Remove the instruction from the list. 1524 removeList.push(instIt); 1525 } 1526} 1527 1528template <class Impl> 1529void 1530FullO3CPU<Impl>::cleanUpRemovedInsts() 1531{ 1532 while (!removeList.empty()) { 1533 DPRINTF(O3CPU, "Removing instruction, " 1534 "[tid:%i] [sn:%lli] PC %#x\n", 1535 (*removeList.front())->threadNumber, 1536 (*removeList.front())->seqNum, 1537 (*removeList.front())->readPC()); 1538 1539 instList.erase(removeList.front()); 1540 1541 removeList.pop(); 1542 } 1543 1544 removeInstsThisCycle = false; 1545} 1546/* 1547template <class Impl> 1548void 1549FullO3CPU<Impl>::removeAllInsts() 1550{ 1551 instList.clear(); 1552} 1553*/ 1554template <class Impl> 1555void 1556FullO3CPU<Impl>::dumpInsts() 1557{ 1558 int num = 0; 1559 1560 ListIt inst_list_it = instList.begin(); 1561 1562 cprintf("Dumping Instruction List\n"); 1563 1564 while (inst_list_it != instList.end()) { 1565 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 1566 "Squashed:%i\n\n", 1567 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 1568 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 1569 (*inst_list_it)->isSquashed()); 1570 inst_list_it++; 1571 ++num; 1572 } 1573} 1574/* 1575template <class Impl> 1576void 1577FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 1578{ 1579 iew.wakeDependents(inst); 1580} 1581*/ 1582template <class Impl> 1583void 1584FullO3CPU<Impl>::wakeCPU() 1585{ 1586 if (activityRec.active() || tickEvent.scheduled()) { 1587 DPRINTF(Activity, "CPU already running.\n"); 1588 return; 1589 } 1590 1591 DPRINTF(Activity, "Waking up CPU\n"); 1592 1593 idleCycles += tickToCycles((curTick - 1) - lastRunningCycle); 1594 numCycles += tickToCycles((curTick - 1) - lastRunningCycle); 1595 1596 schedule(tickEvent, nextCycle()); 1597} 1598 1599#if FULL_SYSTEM 1600template <class Impl> 1601void 1602FullO3CPU<Impl>::wakeup() 1603{ 1604 if (this->thread[0]->status() != ThreadContext::Suspended) 1605 return; 1606 1607 this->wakeCPU(); 1608 1609 DPRINTF(Quiesce, "Suspended Processor woken\n"); 1610 this->threadContexts[0]->activate(); 1611} 1612#endif 1613 1614template <class Impl> 1615ThreadID 1616FullO3CPU<Impl>::getFreeTid() 1617{ 1618 for (ThreadID tid = 0; tid < numThreads; tid++) { 1619 if (!tids[tid]) { 1620 tids[tid] = true; 1621 return tid; 1622 } 1623 } 1624 1625 return InvalidThreadID; 1626} 1627 1628template <class Impl> 1629void 1630FullO3CPU<Impl>::doContextSwitch() 1631{ 1632 if (contextSwitch) { 1633 1634 //ADD CODE TO DEACTIVE THREAD HERE (???) 1635 1636 ThreadID size = cpuWaitList.size(); 1637 for (ThreadID tid = 0; tid < size; tid++) { 1638 activateWhenReady(tid); 1639 } 1640 1641 if (cpuWaitList.size() == 0) 1642 contextSwitch = true; 1643 } 1644} 1645 1646template <class Impl> 1647void 1648FullO3CPU<Impl>::updateThreadPriority() 1649{ 1650 if (activeThreads.size() > 1) { 1651 //DEFAULT TO ROUND ROBIN SCHEME 1652 //e.g. Move highest priority to end of thread list 1653 list<ThreadID>::iterator list_begin = activeThreads.begin(); 1654 list<ThreadID>::iterator list_end = activeThreads.end(); 1655 1656 unsigned high_thread = *list_begin; 1657 1658 activeThreads.erase(list_begin); 1659 1660 activeThreads.push_back(high_thread); 1661 } 1662} 1663 1664// Forward declaration of FullO3CPU. 1665template class FullO3CPU<O3CPUImpl>; 1666