cpu.cc revision 5807
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include "config/full_system.hh" 33#include "config/use_checker.hh" 34 35#include "cpu/activity.hh" 36#include "cpu/simple_thread.hh" 37#include "cpu/thread_context.hh" 38#include "cpu/o3/isa_specific.hh" 39#include "cpu/o3/cpu.hh" 40#include "cpu/o3/thread_context.hh" 41#include "enums/MemoryMode.hh" 42#include "sim/core.hh" 43#include "sim/stat_control.hh" 44 45#if FULL_SYSTEM 46#include "cpu/quiesce_event.hh" 47#include "sim/system.hh" 48#else 49#include "sim/process.hh" 50#endif 51 52#if USE_CHECKER 53#include "cpu/checker/cpu.hh" 54#endif 55 56#if THE_ISA == ALPHA_ISA 57#include "arch/alpha/osfpal.hh" 58#endif 59 60class BaseCPUParams; 61 62using namespace TheISA; 63 64BaseO3CPU::BaseO3CPU(BaseCPUParams *params) 65 : BaseCPU(params) 66{ 67} 68 69void 70BaseO3CPU::regStats() 71{ 72 BaseCPU::regStats(); 73} 74 75template <class Impl> 76FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 77 : Event(CPU_Tick_Pri), cpu(c) 78{ 79} 80 81template <class Impl> 82void 83FullO3CPU<Impl>::TickEvent::process() 84{ 85 cpu->tick(); 86} 87 88template <class Impl> 89const char * 90FullO3CPU<Impl>::TickEvent::description() const 91{ 92 return "FullO3CPU tick"; 93} 94 95template <class Impl> 96FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 97 : Event(CPU_Switch_Pri) 98{ 99} 100 101template <class Impl> 102void 103FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 104 FullO3CPU<Impl> *thread_cpu) 105{ 106 tid = thread_num; 107 cpu = thread_cpu; 108} 109 110template <class Impl> 111void 112FullO3CPU<Impl>::ActivateThreadEvent::process() 113{ 114 cpu->activateThread(tid); 115} 116 117template <class Impl> 118const char * 119FullO3CPU<Impl>::ActivateThreadEvent::description() const 120{ 121 return "FullO3CPU \"Activate Thread\""; 122} 123 124template <class Impl> 125FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 126 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 127{ 128} 129 130template <class Impl> 131void 132FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 133 FullO3CPU<Impl> *thread_cpu) 134{ 135 tid = thread_num; 136 cpu = thread_cpu; 137 remove = false; 138} 139 140template <class Impl> 141void 142FullO3CPU<Impl>::DeallocateContextEvent::process() 143{ 144 cpu->deactivateThread(tid); 145 if (remove) 146 cpu->removeThread(tid); 147} 148 149template <class Impl> 150const char * 151FullO3CPU<Impl>::DeallocateContextEvent::description() const 152{ 153 return "FullO3CPU \"Deallocate Context\""; 154} 155 156template <class Impl> 157FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 158 : BaseO3CPU(params), 159 itb(params->itb), 160 dtb(params->dtb), 161 tickEvent(this), 162#ifndef NDEBUG 163 instcount(0), 164#endif 165 removeInstsThisCycle(false), 166 fetch(this, params), 167 decode(this, params), 168 rename(this, params), 169 iew(this, params), 170 commit(this, params), 171 172 regFile(this, params->numPhysIntRegs, 173 params->numPhysFloatRegs), 174 175 freeList(params->numThreads, 176 TheISA::NumIntRegs, params->numPhysIntRegs, 177 TheISA::NumFloatRegs, params->numPhysFloatRegs), 178 179 rob(this, 180 params->numROBEntries, params->squashWidth, 181 params->smtROBPolicy, params->smtROBThreshold, 182 params->numThreads), 183 184 scoreboard(params->numThreads, 185 TheISA::NumIntRegs, params->numPhysIntRegs, 186 TheISA::NumFloatRegs, params->numPhysFloatRegs, 187 TheISA::NumMiscRegs * number_of_threads, 188 TheISA::ZeroReg), 189 190 timeBuffer(params->backComSize, params->forwardComSize), 191 fetchQueue(params->backComSize, params->forwardComSize), 192 decodeQueue(params->backComSize, params->forwardComSize), 193 renameQueue(params->backComSize, params->forwardComSize), 194 iewQueue(params->backComSize, params->forwardComSize), 195 activityRec(name(), NumStages, 196 params->backComSize + params->forwardComSize, 197 params->activity), 198 199 globalSeqNum(1), 200#if FULL_SYSTEM 201 system(params->system), 202 physmem(system->physmem), 203#endif // FULL_SYSTEM 204 drainCount(0), 205 deferRegistration(params->defer_registration), 206 numThreads(number_of_threads) 207{ 208 if (!deferRegistration) { 209 _status = Running; 210 } else { 211 _status = Idle; 212 } 213 214#if USE_CHECKER 215 if (params->checker) { 216 BaseCPU *temp_checker = params->checker; 217 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 218#if FULL_SYSTEM 219 checker->setSystem(params->system); 220#endif 221 } else { 222 checker = NULL; 223 } 224#endif // USE_CHECKER 225 226#if !FULL_SYSTEM 227 thread.resize(number_of_threads); 228 tids.resize(number_of_threads); 229#endif 230 231 // The stages also need their CPU pointer setup. However this 232 // must be done at the upper level CPU because they have pointers 233 // to the upper level CPU, and not this FullO3CPU. 234 235 // Set up Pointers to the activeThreads list for each stage 236 fetch.setActiveThreads(&activeThreads); 237 decode.setActiveThreads(&activeThreads); 238 rename.setActiveThreads(&activeThreads); 239 iew.setActiveThreads(&activeThreads); 240 commit.setActiveThreads(&activeThreads); 241 242 // Give each of the stages the time buffer they will use. 243 fetch.setTimeBuffer(&timeBuffer); 244 decode.setTimeBuffer(&timeBuffer); 245 rename.setTimeBuffer(&timeBuffer); 246 iew.setTimeBuffer(&timeBuffer); 247 commit.setTimeBuffer(&timeBuffer); 248 249 // Also setup each of the stages' queues. 250 fetch.setFetchQueue(&fetchQueue); 251 decode.setFetchQueue(&fetchQueue); 252 commit.setFetchQueue(&fetchQueue); 253 decode.setDecodeQueue(&decodeQueue); 254 rename.setDecodeQueue(&decodeQueue); 255 rename.setRenameQueue(&renameQueue); 256 iew.setRenameQueue(&renameQueue); 257 iew.setIEWQueue(&iewQueue); 258 commit.setIEWQueue(&iewQueue); 259 commit.setRenameQueue(&renameQueue); 260 261 commit.setIEWStage(&iew); 262 rename.setIEWStage(&iew); 263 rename.setCommitStage(&commit); 264 265#if !FULL_SYSTEM 266 int active_threads = params->workload.size(); 267 268 if (active_threads > Impl::MaxThreads) { 269 panic("Workload Size too large. Increase the 'MaxThreads'" 270 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 271 "edit your workload size."); 272 } 273#else 274 int active_threads = 1; 275#endif 276 277 //Make Sure That this a Valid Architeture 278 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 279 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 280 281 rename.setScoreboard(&scoreboard); 282 iew.setScoreboard(&scoreboard); 283 284 // Setup the rename map for whichever stages need it. 285 PhysRegIndex lreg_idx = 0; 286 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 287 288 for (int tid=0; tid < numThreads; tid++) { 289 bool bindRegs = (tid <= active_threads - 1); 290 291 commitRenameMap[tid].init(TheISA::NumIntRegs, 292 params->numPhysIntRegs, 293 lreg_idx, //Index for Logical. Regs 294 295 TheISA::NumFloatRegs, 296 params->numPhysFloatRegs, 297 freg_idx, //Index for Float Regs 298 299 TheISA::NumMiscRegs, 300 301 TheISA::ZeroReg, 302 TheISA::ZeroReg, 303 304 tid, 305 false); 306 307 renameMap[tid].init(TheISA::NumIntRegs, 308 params->numPhysIntRegs, 309 lreg_idx, //Index for Logical. Regs 310 311 TheISA::NumFloatRegs, 312 params->numPhysFloatRegs, 313 freg_idx, //Index for Float Regs 314 315 TheISA::NumMiscRegs, 316 317 TheISA::ZeroReg, 318 TheISA::ZeroReg, 319 320 tid, 321 bindRegs); 322 323 activateThreadEvent[tid].init(tid, this); 324 deallocateContextEvent[tid].init(tid, this); 325 } 326 327 rename.setRenameMap(renameMap); 328 commit.setRenameMap(commitRenameMap); 329 330 // Give renameMap & rename stage access to the freeList; 331 for (int i=0; i < numThreads; i++) { 332 renameMap[i].setFreeList(&freeList); 333 } 334 rename.setFreeList(&freeList); 335 336 // Setup the ROB for whichever stages need it. 337 commit.setROB(&rob); 338 339 lastRunningCycle = curTick; 340 341 lastActivatedCycle = -1; 342 343 // Give renameMap & rename stage access to the freeList; 344 //for (int i=0; i < numThreads; i++) { 345 //globalSeqNum[i] = 1; 346 //} 347 348 contextSwitch = false; 349 DPRINTF(O3CPU, "Creating O3CPU object.\n"); 350 351 // Setup any thread state. 352 this->thread.resize(this->numThreads); 353 354 for (int i = 0; i < this->numThreads; ++i) { 355#if FULL_SYSTEM 356 // SMT is not supported in FS mode yet. 357 assert(this->numThreads == 1); 358 this->thread[i] = new Thread(this, 0); 359 this->thread[i]->setStatus(ThreadContext::Suspended); 360#else 361 if (i < params->workload.size()) { 362 DPRINTF(O3CPU, "Workload[%i] process is %#x", 363 i, this->thread[i]); 364 this->thread[i] = new typename FullO3CPU<Impl>::Thread( 365 (typename Impl::O3CPU *)(this), 366 i, params->workload[i], i); 367 368 this->thread[i]->setStatus(ThreadContext::Suspended); 369 370 //usedTids[i] = true; 371 //threadMap[i] = i; 372 } else { 373 //Allocate Empty thread so M5 can use later 374 //when scheduling threads to CPU 375 Process* dummy_proc = NULL; 376 377 this->thread[i] = new typename FullO3CPU<Impl>::Thread( 378 (typename Impl::O3CPU *)(this), 379 i, dummy_proc, i); 380 //usedTids[i] = false; 381 } 382#endif // !FULL_SYSTEM 383 384 ThreadContext *tc; 385 386 // Setup the TC that will serve as the interface to the threads/CPU. 387 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 388 389 tc = o3_tc; 390 391 // If we're using a checker, then the TC should be the 392 // CheckerThreadContext. 393#if USE_CHECKER 394 if (params->checker) { 395 tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 396 o3_tc, this->checker); 397 } 398#endif 399 400 o3_tc->cpu = (typename Impl::O3CPU *)(this); 401 assert(o3_tc->cpu); 402 o3_tc->thread = this->thread[i]; 403 404#if FULL_SYSTEM 405 // Setup quiesce event. 406 this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc); 407#endif 408 // Give the thread the TC. 409 this->thread[i]->tc = tc; 410 411 // Add the TC to the CPU's list of TC's. 412 this->threadContexts.push_back(tc); 413 } 414 415 for (int i=0; i < this->numThreads; i++) { 416 this->thread[i]->setFuncExeInst(0); 417 } 418 419 lockAddr = 0; 420 lockFlag = false; 421} 422 423#if !FULL_SYSTEM 424 425template <class Impl> 426TheISA::IntReg 427FullO3CPU<Impl>::getSyscallArg(int i, int tid) 428{ 429 assert(i < TheISA::NumArgumentRegs); 430 TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), 431 TheISA::ArgumentReg[i]); 432 TheISA::IntReg val = this->readArchIntReg(idx, tid); 433#if THE_ISA == SPARC_ISA 434 if (bits(this->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE, tid), 3, 3)) 435 val = bits(val, 31, 0); 436#endif 437 return val; 438} 439 440template <class Impl> 441void 442FullO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid) 443{ 444 assert(i < TheISA::NumArgumentRegs); 445 TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), 446 TheISA::ArgumentReg[i]); 447 this->setArchIntReg(idx, val, tid); 448} 449#endif 450 451template <class Impl> 452FullO3CPU<Impl>::~FullO3CPU() 453{ 454} 455 456template <class Impl> 457void 458FullO3CPU<Impl>::regStats() 459{ 460 BaseO3CPU::regStats(); 461 462 // Register any of the O3CPU's stats here. 463 timesIdled 464 .name(name() + ".timesIdled") 465 .desc("Number of times that the entire CPU went into an idle state and" 466 " unscheduled itself") 467 .prereq(timesIdled); 468 469 idleCycles 470 .name(name() + ".idleCycles") 471 .desc("Total number of cycles that the CPU has spent unscheduled due " 472 "to idling") 473 .prereq(idleCycles); 474 475 // Number of Instructions simulated 476 // -------------------------------- 477 // Should probably be in Base CPU but need templated 478 // MaxThreads so put in here instead 479 committedInsts 480 .init(numThreads) 481 .name(name() + ".committedInsts") 482 .desc("Number of Instructions Simulated"); 483 484 totalCommittedInsts 485 .name(name() + ".committedInsts_total") 486 .desc("Number of Instructions Simulated"); 487 488 cpi 489 .name(name() + ".cpi") 490 .desc("CPI: Cycles Per Instruction") 491 .precision(6); 492 cpi = numCycles / committedInsts; 493 494 totalCpi 495 .name(name() + ".cpi_total") 496 .desc("CPI: Total CPI of All Threads") 497 .precision(6); 498 totalCpi = numCycles / totalCommittedInsts; 499 500 ipc 501 .name(name() + ".ipc") 502 .desc("IPC: Instructions Per Cycle") 503 .precision(6); 504 ipc = committedInsts / numCycles; 505 506 totalIpc 507 .name(name() + ".ipc_total") 508 .desc("IPC: Total IPC of All Threads") 509 .precision(6); 510 totalIpc = totalCommittedInsts / numCycles; 511 512 this->fetch.regStats(); 513 this->decode.regStats(); 514 this->rename.regStats(); 515 this->iew.regStats(); 516 this->commit.regStats(); 517} 518 519template <class Impl> 520Port * 521FullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 522{ 523 if (if_name == "dcache_port") 524 return iew.getDcachePort(); 525 else if (if_name == "icache_port") 526 return fetch.getIcachePort(); 527 else 528 panic("No Such Port\n"); 529} 530 531template <class Impl> 532void 533FullO3CPU<Impl>::tick() 534{ 535 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 536 537 ++numCycles; 538 539// activity = false; 540 541 //Tick each of the stages 542 fetch.tick(); 543 544 decode.tick(); 545 546 rename.tick(); 547 548 iew.tick(); 549 550 commit.tick(); 551 552#if !FULL_SYSTEM 553 doContextSwitch(); 554#endif 555 556 // Now advance the time buffers 557 timeBuffer.advance(); 558 559 fetchQueue.advance(); 560 decodeQueue.advance(); 561 renameQueue.advance(); 562 iewQueue.advance(); 563 564 activityRec.advance(); 565 566 if (removeInstsThisCycle) { 567 cleanUpRemovedInsts(); 568 } 569 570 if (!tickEvent.scheduled()) { 571 if (_status == SwitchedOut || 572 getState() == SimObject::Drained) { 573 DPRINTF(O3CPU, "Switched out!\n"); 574 // increment stat 575 lastRunningCycle = curTick; 576 } else if (!activityRec.active() || _status == Idle) { 577 DPRINTF(O3CPU, "Idle!\n"); 578 lastRunningCycle = curTick; 579 timesIdled++; 580 } else { 581 schedule(tickEvent, nextCycle(curTick + ticks(1))); 582 DPRINTF(O3CPU, "Scheduling next tick!\n"); 583 } 584 } 585 586#if !FULL_SYSTEM 587 updateThreadPriority(); 588#endif 589} 590 591template <class Impl> 592void 593FullO3CPU<Impl>::init() 594{ 595 BaseCPU::init(); 596 597 // Set inSyscall so that the CPU doesn't squash when initially 598 // setting up registers. 599 for (int i = 0; i < number_of_threads; ++i) 600 thread[i]->inSyscall = true; 601 602 for (int tid=0; tid < number_of_threads; tid++) { 603#if FULL_SYSTEM 604 ThreadContext *src_tc = threadContexts[tid]; 605#else 606 ThreadContext *src_tc = thread[tid]->getTC(); 607#endif 608 // Threads start in the Suspended State 609 if (src_tc->status() != ThreadContext::Suspended) { 610 continue; 611 } 612 613#if FULL_SYSTEM 614 TheISA::initCPU(src_tc, src_tc->contextId()); 615#endif 616 } 617 618 // Clear inSyscall. 619 for (int i = 0; i < number_of_threads; ++i) 620 thread[i]->inSyscall = false; 621 622 // Initialize stages. 623 fetch.initStage(); 624 iew.initStage(); 625 rename.initStage(); 626 commit.initStage(); 627 628 commit.setThreads(thread); 629} 630 631template <class Impl> 632void 633FullO3CPU<Impl>::activateThread(unsigned tid) 634{ 635 std::list<unsigned>::iterator isActive = 636 std::find(activeThreads.begin(), activeThreads.end(), tid); 637 638 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 639 640 if (isActive == activeThreads.end()) { 641 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 642 tid); 643 644 activeThreads.push_back(tid); 645 } 646} 647 648template <class Impl> 649void 650FullO3CPU<Impl>::deactivateThread(unsigned tid) 651{ 652 //Remove From Active List, if Active 653 std::list<unsigned>::iterator thread_it = 654 std::find(activeThreads.begin(), activeThreads.end(), tid); 655 656 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 657 658 if (thread_it != activeThreads.end()) { 659 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 660 tid); 661 activeThreads.erase(thread_it); 662 } 663} 664 665template <class Impl> 666void 667FullO3CPU<Impl>::activateContext(int tid, int delay) 668{ 669 // Needs to set each stage to running as well. 670 if (delay){ 671 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 672 "on cycle %d\n", tid, curTick + ticks(delay)); 673 scheduleActivateThreadEvent(tid, delay); 674 } else { 675 activateThread(tid); 676 } 677 678 if (lastActivatedCycle < curTick) { 679 scheduleTickEvent(delay); 680 681 // Be sure to signal that there's some activity so the CPU doesn't 682 // deschedule itself. 683 activityRec.activity(); 684 fetch.wakeFromQuiesce(); 685 686 lastActivatedCycle = curTick; 687 688 _status = Running; 689 } 690} 691 692template <class Impl> 693bool 694FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay) 695{ 696 // Schedule removal of thread data from CPU 697 if (delay){ 698 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 699 "on cycle %d\n", tid, curTick + ticks(delay)); 700 scheduleDeallocateContextEvent(tid, remove, delay); 701 return false; 702 } else { 703 deactivateThread(tid); 704 if (remove) 705 removeThread(tid); 706 return true; 707 } 708} 709 710template <class Impl> 711void 712FullO3CPU<Impl>::suspendContext(int tid) 713{ 714 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 715 bool deallocated = deallocateContext(tid, false, 1); 716 // If this was the last thread then unschedule the tick event. 717 if ((activeThreads.size() == 1 && !deallocated) || 718 activeThreads.size() == 0) 719 unscheduleTickEvent(); 720 _status = Idle; 721} 722 723template <class Impl> 724void 725FullO3CPU<Impl>::haltContext(int tid) 726{ 727 //For now, this is the same as deallocate 728 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 729 deallocateContext(tid, true, 1); 730} 731 732template <class Impl> 733void 734FullO3CPU<Impl>::insertThread(unsigned tid) 735{ 736 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 737 // Will change now that the PC and thread state is internal to the CPU 738 // and not in the ThreadContext. 739#if FULL_SYSTEM 740 ThreadContext *src_tc = system->threadContexts[tid]; 741#else 742 ThreadContext *src_tc = tcBase(tid); 743#endif 744 745 //Bind Int Regs to Rename Map 746 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 747 PhysRegIndex phys_reg = freeList.getIntReg(); 748 749 renameMap[tid].setEntry(ireg,phys_reg); 750 scoreboard.setReg(phys_reg); 751 } 752 753 //Bind Float Regs to Rename Map 754 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 755 PhysRegIndex phys_reg = freeList.getFloatReg(); 756 757 renameMap[tid].setEntry(freg,phys_reg); 758 scoreboard.setReg(phys_reg); 759 } 760 761 //Copy Thread Data Into RegFile 762 //this->copyFromTC(tid); 763 764 //Set PC/NPC/NNPC 765 setPC(src_tc->readPC(), tid); 766 setNextPC(src_tc->readNextPC(), tid); 767 setNextNPC(src_tc->readNextNPC(), tid); 768 769 src_tc->setStatus(ThreadContext::Active); 770 771 activateContext(tid,1); 772 773 //Reset ROB/IQ/LSQ Entries 774 commit.rob->resetEntries(); 775 iew.resetEntries(); 776} 777 778template <class Impl> 779void 780FullO3CPU<Impl>::removeThread(unsigned tid) 781{ 782 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 783 784 // Copy Thread Data From RegFile 785 // If thread is suspended, it might be re-allocated 786 // this->copyToTC(tid); 787 788 789 // @todo: 2-27-2008: Fix how we free up rename mappings 790 // here to alleviate the case for double-freeing registers 791 // in SMT workloads. 792 793 // Unbind Int Regs from Rename Map 794 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 795 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 796 797 scoreboard.unsetReg(phys_reg); 798 freeList.addReg(phys_reg); 799 } 800 801 // Unbind Float Regs from Rename Map 802 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 803 PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 804 805 scoreboard.unsetReg(phys_reg); 806 freeList.addReg(phys_reg); 807 } 808 809 // Squash Throughout Pipeline 810 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 811 fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid); 812 decode.squash(tid); 813 rename.squash(squash_seq_num, tid); 814 iew.squash(tid); 815 iew.ldstQueue.squash(squash_seq_num, tid); 816 commit.rob->squash(squash_seq_num, tid); 817 818 819 assert(iew.instQueue.getCount(tid) == 0); 820 assert(iew.ldstQueue.getCount(tid) == 0); 821 822 // Reset ROB/IQ/LSQ Entries 823 824 // Commented out for now. This should be possible to do by 825 // telling all the pipeline stages to drain first, and then 826 // checking until the drain completes. Once the pipeline is 827 // drained, call resetEntries(). - 10-09-06 ktlim 828/* 829 if (activeThreads.size() >= 1) { 830 commit.rob->resetEntries(); 831 iew.resetEntries(); 832 } 833*/ 834} 835 836 837template <class Impl> 838void 839FullO3CPU<Impl>::activateWhenReady(int tid) 840{ 841 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 842 "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 843 tid); 844 845 bool ready = true; 846 847 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 848 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 849 "Phys. Int. Regs.\n", 850 tid); 851 ready = false; 852 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 853 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 854 "Phys. Float. Regs.\n", 855 tid); 856 ready = false; 857 } else if (commit.rob->numFreeEntries() >= 858 commit.rob->entryAmount(activeThreads.size() + 1)) { 859 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 860 "ROB entries.\n", 861 tid); 862 ready = false; 863 } else if (iew.instQueue.numFreeEntries() >= 864 iew.instQueue.entryAmount(activeThreads.size() + 1)) { 865 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 866 "IQ entries.\n", 867 tid); 868 ready = false; 869 } else if (iew.ldstQueue.numFreeEntries() >= 870 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 871 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 872 "LSQ entries.\n", 873 tid); 874 ready = false; 875 } 876 877 if (ready) { 878 insertThread(tid); 879 880 contextSwitch = false; 881 882 cpuWaitList.remove(tid); 883 } else { 884 suspendContext(tid); 885 886 //blocks fetch 887 contextSwitch = true; 888 889 //@todo: dont always add to waitlist 890 //do waitlist 891 cpuWaitList.push_back(tid); 892 } 893} 894 895#if FULL_SYSTEM 896template <class Impl> 897Fault 898FullO3CPU<Impl>::hwrei(unsigned tid) 899{ 900#if THE_ISA == ALPHA_ISA 901 // Need to clear the lock flag upon returning from an interrupt. 902 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 903 904 this->thread[tid]->kernelStats->hwrei(); 905 906 // FIXME: XXX check for interrupts? XXX 907#endif 908 return NoFault; 909} 910 911template <class Impl> 912bool 913FullO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid) 914{ 915#if THE_ISA == ALPHA_ISA 916 if (this->thread[tid]->kernelStats) 917 this->thread[tid]->kernelStats->callpal(palFunc, 918 this->threadContexts[tid]); 919 920 switch (palFunc) { 921 case PAL::halt: 922 halt(); 923 if (--System::numSystemsRunning == 0) 924 exitSimLoop("all cpus halted"); 925 break; 926 927 case PAL::bpt: 928 case PAL::bugchk: 929 if (this->system->breakpoint()) 930 return false; 931 break; 932 } 933#endif 934 return true; 935} 936 937template <class Impl> 938Fault 939FullO3CPU<Impl>::getInterrupts() 940{ 941 // Check if there are any outstanding interrupts 942 return this->interrupts->getInterrupt(this->threadContexts[0]); 943} 944 945template <class Impl> 946void 947FullO3CPU<Impl>::processInterrupts(Fault interrupt) 948{ 949 // Check for interrupts here. For now can copy the code that 950 // exists within isa_fullsys_traits.hh. Also assume that thread 0 951 // is the one that handles the interrupts. 952 // @todo: Possibly consolidate the interrupt checking code. 953 // @todo: Allow other threads to handle interrupts. 954 955 assert(interrupt != NoFault); 956 this->interrupts->updateIntrInfo(this->threadContexts[0]); 957 958 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 959 this->trap(interrupt, 0); 960} 961 962template <class Impl> 963void 964FullO3CPU<Impl>::updateMemPorts() 965{ 966 // Update all ThreadContext's memory ports (Functional/Virtual 967 // Ports) 968 for (int i = 0; i < thread.size(); ++i) 969 thread[i]->connectMemPorts(thread[i]->getTC()); 970} 971#endif 972 973template <class Impl> 974void 975FullO3CPU<Impl>::trap(Fault fault, unsigned tid) 976{ 977 // Pass the thread's TC into the invoke method. 978 fault->invoke(this->threadContexts[tid]); 979} 980 981#if !FULL_SYSTEM 982 983template <class Impl> 984void 985FullO3CPU<Impl>::syscall(int64_t callnum, int tid) 986{ 987 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 988 989 DPRINTF(Activity,"Activity: syscall() called.\n"); 990 991 // Temporarily increase this by one to account for the syscall 992 // instruction. 993 ++(this->thread[tid]->funcExeInst); 994 995 // Execute the actual syscall. 996 this->thread[tid]->syscall(callnum); 997 998 // Decrease funcExeInst by one as the normal commit will handle 999 // incrementing it. 1000 --(this->thread[tid]->funcExeInst); 1001} 1002 1003template <class Impl> 1004void 1005FullO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid) 1006{ 1007 TheISA::setSyscallReturn(return_value, this->tcBase(tid)); 1008} 1009 1010#endif 1011 1012template <class Impl> 1013void 1014FullO3CPU<Impl>::serialize(std::ostream &os) 1015{ 1016 SimObject::State so_state = SimObject::getState(); 1017 SERIALIZE_ENUM(so_state); 1018 BaseCPU::serialize(os); 1019 nameOut(os, csprintf("%s.tickEvent", name())); 1020 tickEvent.serialize(os); 1021 1022 // Use SimpleThread's ability to checkpoint to make it easier to 1023 // write out the registers. Also make this static so it doesn't 1024 // get instantiated multiple times (causes a panic in statistics). 1025 static SimpleThread temp; 1026 1027 for (int i = 0; i < thread.size(); i++) { 1028 nameOut(os, csprintf("%s.xc.%i", name(), i)); 1029 temp.copyTC(thread[i]->getTC()); 1030 temp.serialize(os); 1031 } 1032} 1033 1034template <class Impl> 1035void 1036FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 1037{ 1038 SimObject::State so_state; 1039 UNSERIALIZE_ENUM(so_state); 1040 BaseCPU::unserialize(cp, section); 1041 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1042 1043 // Use SimpleThread's ability to checkpoint to make it easier to 1044 // read in the registers. Also make this static so it doesn't 1045 // get instantiated multiple times (causes a panic in statistics). 1046 static SimpleThread temp; 1047 1048 for (int i = 0; i < thread.size(); i++) { 1049 temp.copyTC(thread[i]->getTC()); 1050 temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 1051 thread[i]->getTC()->copyArchRegs(temp.getTC()); 1052 } 1053} 1054 1055template <class Impl> 1056unsigned int 1057FullO3CPU<Impl>::drain(Event *drain_event) 1058{ 1059 DPRINTF(O3CPU, "Switching out\n"); 1060 1061 // If the CPU isn't doing anything, then return immediately. 1062 if (_status == Idle || _status == SwitchedOut) { 1063 return 0; 1064 } 1065 1066 drainCount = 0; 1067 fetch.drain(); 1068 decode.drain(); 1069 rename.drain(); 1070 iew.drain(); 1071 commit.drain(); 1072 1073 // Wake the CPU and record activity so everything can drain out if 1074 // the CPU was not able to immediately drain. 1075 if (getState() != SimObject::Drained) { 1076 // A bit of a hack...set the drainEvent after all the drain() 1077 // calls have been made, that way if all of the stages drain 1078 // immediately, the signalDrained() function knows not to call 1079 // process on the drain event. 1080 drainEvent = drain_event; 1081 1082 wakeCPU(); 1083 activityRec.activity(); 1084 1085 return 1; 1086 } else { 1087 return 0; 1088 } 1089} 1090 1091template <class Impl> 1092void 1093FullO3CPU<Impl>::resume() 1094{ 1095 fetch.resume(); 1096 decode.resume(); 1097 rename.resume(); 1098 iew.resume(); 1099 commit.resume(); 1100 1101 changeState(SimObject::Running); 1102 1103 if (_status == SwitchedOut || _status == Idle) 1104 return; 1105 1106#if FULL_SYSTEM 1107 assert(system->getMemoryMode() == Enums::timing); 1108#endif 1109 1110 if (!tickEvent.scheduled()) 1111 schedule(tickEvent, nextCycle()); 1112 _status = Running; 1113} 1114 1115template <class Impl> 1116void 1117FullO3CPU<Impl>::signalDrained() 1118{ 1119 if (++drainCount == NumStages) { 1120 if (tickEvent.scheduled()) 1121 tickEvent.squash(); 1122 1123 changeState(SimObject::Drained); 1124 1125 BaseCPU::switchOut(); 1126 1127 if (drainEvent) { 1128 drainEvent->process(); 1129 drainEvent = NULL; 1130 } 1131 } 1132 assert(drainCount <= 5); 1133} 1134 1135template <class Impl> 1136void 1137FullO3CPU<Impl>::switchOut() 1138{ 1139 fetch.switchOut(); 1140 rename.switchOut(); 1141 iew.switchOut(); 1142 commit.switchOut(); 1143 instList.clear(); 1144 while (!removeList.empty()) { 1145 removeList.pop(); 1146 } 1147 1148 _status = SwitchedOut; 1149#if USE_CHECKER 1150 if (checker) 1151 checker->switchOut(); 1152#endif 1153 if (tickEvent.scheduled()) 1154 tickEvent.squash(); 1155} 1156 1157template <class Impl> 1158void 1159FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 1160{ 1161 // Flush out any old data from the time buffers. 1162 for (int i = 0; i < timeBuffer.getSize(); ++i) { 1163 timeBuffer.advance(); 1164 fetchQueue.advance(); 1165 decodeQueue.advance(); 1166 renameQueue.advance(); 1167 iewQueue.advance(); 1168 } 1169 1170 activityRec.reset(); 1171 1172 BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 1173 1174 fetch.takeOverFrom(); 1175 decode.takeOverFrom(); 1176 rename.takeOverFrom(); 1177 iew.takeOverFrom(); 1178 commit.takeOverFrom(); 1179 1180 assert(!tickEvent.scheduled()); 1181 1182 // @todo: Figure out how to properly select the tid to put onto 1183 // the active threads list. 1184 int tid = 0; 1185 1186 std::list<unsigned>::iterator isActive = 1187 std::find(activeThreads.begin(), activeThreads.end(), tid); 1188 1189 if (isActive == activeThreads.end()) { 1190 //May Need to Re-code this if the delay variable is the delay 1191 //needed for thread to activate 1192 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 1193 tid); 1194 1195 activeThreads.push_back(tid); 1196 } 1197 1198 // Set all statuses to active, schedule the CPU's tick event. 1199 // @todo: Fix up statuses so this is handled properly 1200 for (int i = 0; i < threadContexts.size(); ++i) { 1201 ThreadContext *tc = threadContexts[i]; 1202 if (tc->status() == ThreadContext::Active && _status != Running) { 1203 _status = Running; 1204 schedule(tickEvent, nextCycle()); 1205 } 1206 } 1207 if (!tickEvent.scheduled()) 1208 schedule(tickEvent, nextCycle()); 1209} 1210 1211template <class Impl> 1212TheISA::MiscReg 1213FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid) 1214{ 1215 return this->regFile.readMiscRegNoEffect(misc_reg, tid); 1216} 1217 1218template <class Impl> 1219TheISA::MiscReg 1220FullO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) 1221{ 1222 return this->regFile.readMiscReg(misc_reg, tid); 1223} 1224 1225template <class Impl> 1226void 1227FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 1228 const TheISA::MiscReg &val, unsigned tid) 1229{ 1230 this->regFile.setMiscRegNoEffect(misc_reg, val, tid); 1231} 1232 1233template <class Impl> 1234void 1235FullO3CPU<Impl>::setMiscReg(int misc_reg, 1236 const TheISA::MiscReg &val, unsigned tid) 1237{ 1238 this->regFile.setMiscReg(misc_reg, val, tid); 1239} 1240 1241template <class Impl> 1242uint64_t 1243FullO3CPU<Impl>::readIntReg(int reg_idx) 1244{ 1245 return regFile.readIntReg(reg_idx); 1246} 1247 1248template <class Impl> 1249FloatReg 1250FullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 1251{ 1252 return regFile.readFloatReg(reg_idx, width); 1253} 1254 1255template <class Impl> 1256FloatReg 1257FullO3CPU<Impl>::readFloatReg(int reg_idx) 1258{ 1259 return regFile.readFloatReg(reg_idx); 1260} 1261 1262template <class Impl> 1263FloatRegBits 1264FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 1265{ 1266 return regFile.readFloatRegBits(reg_idx, width); 1267} 1268 1269template <class Impl> 1270FloatRegBits 1271FullO3CPU<Impl>::readFloatRegBits(int reg_idx) 1272{ 1273 return regFile.readFloatRegBits(reg_idx); 1274} 1275 1276template <class Impl> 1277void 1278FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 1279{ 1280 regFile.setIntReg(reg_idx, val); 1281} 1282 1283template <class Impl> 1284void 1285FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 1286{ 1287 regFile.setFloatReg(reg_idx, val, width); 1288} 1289 1290template <class Impl> 1291void 1292FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 1293{ 1294 regFile.setFloatReg(reg_idx, val); 1295} 1296 1297template <class Impl> 1298void 1299FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 1300{ 1301 regFile.setFloatRegBits(reg_idx, val, width); 1302} 1303 1304template <class Impl> 1305void 1306FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 1307{ 1308 regFile.setFloatRegBits(reg_idx, val); 1309} 1310 1311template <class Impl> 1312uint64_t 1313FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 1314{ 1315 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 1316 1317 return regFile.readIntReg(phys_reg); 1318} 1319 1320template <class Impl> 1321float 1322FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 1323{ 1324 int idx = reg_idx + TheISA::FP_Base_DepTag; 1325 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1326 1327 return regFile.readFloatReg(phys_reg); 1328} 1329 1330template <class Impl> 1331double 1332FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 1333{ 1334 int idx = reg_idx + TheISA::FP_Base_DepTag; 1335 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1336 1337 return regFile.readFloatReg(phys_reg, 64); 1338} 1339 1340template <class Impl> 1341uint64_t 1342FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 1343{ 1344 int idx = reg_idx + TheISA::FP_Base_DepTag; 1345 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1346 1347 return regFile.readFloatRegBits(phys_reg); 1348} 1349 1350template <class Impl> 1351void 1352FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 1353{ 1354 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 1355 1356 regFile.setIntReg(phys_reg, val); 1357} 1358 1359template <class Impl> 1360void 1361FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 1362{ 1363 int idx = reg_idx + TheISA::FP_Base_DepTag; 1364 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1365 1366 regFile.setFloatReg(phys_reg, val); 1367} 1368 1369template <class Impl> 1370void 1371FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 1372{ 1373 int idx = reg_idx + TheISA::FP_Base_DepTag; 1374 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1375 1376 regFile.setFloatReg(phys_reg, val, 64); 1377} 1378 1379template <class Impl> 1380void 1381FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 1382{ 1383 int idx = reg_idx + TheISA::FP_Base_DepTag; 1384 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1385 1386 regFile.setFloatRegBits(phys_reg, val); 1387} 1388 1389template <class Impl> 1390uint64_t 1391FullO3CPU<Impl>::readPC(unsigned tid) 1392{ 1393 return commit.readPC(tid); 1394} 1395 1396template <class Impl> 1397void 1398FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 1399{ 1400 commit.setPC(new_PC, tid); 1401} 1402 1403template <class Impl> 1404uint64_t 1405FullO3CPU<Impl>::readMicroPC(unsigned tid) 1406{ 1407 return commit.readMicroPC(tid); 1408} 1409 1410template <class Impl> 1411void 1412FullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid) 1413{ 1414 commit.setMicroPC(new_PC, tid); 1415} 1416 1417template <class Impl> 1418uint64_t 1419FullO3CPU<Impl>::readNextPC(unsigned tid) 1420{ 1421 return commit.readNextPC(tid); 1422} 1423 1424template <class Impl> 1425void 1426FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 1427{ 1428 commit.setNextPC(val, tid); 1429} 1430 1431template <class Impl> 1432uint64_t 1433FullO3CPU<Impl>::readNextNPC(unsigned tid) 1434{ 1435 return commit.readNextNPC(tid); 1436} 1437 1438template <class Impl> 1439void 1440FullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) 1441{ 1442 commit.setNextNPC(val, tid); 1443} 1444 1445template <class Impl> 1446uint64_t 1447FullO3CPU<Impl>::readNextMicroPC(unsigned tid) 1448{ 1449 return commit.readNextMicroPC(tid); 1450} 1451 1452template <class Impl> 1453void 1454FullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid) 1455{ 1456 commit.setNextMicroPC(new_PC, tid); 1457} 1458 1459template <class Impl> 1460void 1461FullO3CPU<Impl>::squashFromTC(unsigned tid) 1462{ 1463 this->thread[tid]->inSyscall = true; 1464 this->commit.generateTCEvent(tid); 1465} 1466 1467template <class Impl> 1468typename FullO3CPU<Impl>::ListIt 1469FullO3CPU<Impl>::addInst(DynInstPtr &inst) 1470{ 1471 instList.push_back(inst); 1472 1473 return --(instList.end()); 1474} 1475 1476template <class Impl> 1477void 1478FullO3CPU<Impl>::instDone(unsigned tid) 1479{ 1480 // Keep an instruction count. 1481 thread[tid]->numInst++; 1482 thread[tid]->numInsts++; 1483 committedInsts[tid]++; 1484 totalCommittedInsts++; 1485 1486 // Check for instruction-count-based events. 1487 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 1488} 1489 1490template <class Impl> 1491void 1492FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 1493{ 1494 removeInstsThisCycle = true; 1495 1496 removeList.push(inst->getInstListIt()); 1497} 1498 1499template <class Impl> 1500void 1501FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 1502{ 1503 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 1504 "[sn:%lli]\n", 1505 inst->threadNumber, inst->readPC(), inst->seqNum); 1506 1507 removeInstsThisCycle = true; 1508 1509 // Remove the front instruction. 1510 removeList.push(inst->getInstListIt()); 1511} 1512 1513template <class Impl> 1514void 1515FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 1516{ 1517 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 1518 " list.\n", tid); 1519 1520 ListIt end_it; 1521 1522 bool rob_empty = false; 1523 1524 if (instList.empty()) { 1525 return; 1526 } else if (rob.isEmpty(/*tid*/)) { 1527 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 1528 end_it = instList.begin(); 1529 rob_empty = true; 1530 } else { 1531 end_it = (rob.readTailInst(tid))->getInstListIt(); 1532 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 1533 } 1534 1535 removeInstsThisCycle = true; 1536 1537 ListIt inst_it = instList.end(); 1538 1539 inst_it--; 1540 1541 // Walk through the instruction list, removing any instructions 1542 // that were inserted after the given instruction iterator, end_it. 1543 while (inst_it != end_it) { 1544 assert(!instList.empty()); 1545 1546 squashInstIt(inst_it, tid); 1547 1548 inst_it--; 1549 } 1550 1551 // If the ROB was empty, then we actually need to remove the first 1552 // instruction as well. 1553 if (rob_empty) { 1554 squashInstIt(inst_it, tid); 1555 } 1556} 1557 1558template <class Impl> 1559void 1560FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 1561 unsigned tid) 1562{ 1563 assert(!instList.empty()); 1564 1565 removeInstsThisCycle = true; 1566 1567 ListIt inst_iter = instList.end(); 1568 1569 inst_iter--; 1570 1571 DPRINTF(O3CPU, "Deleting instructions from instruction " 1572 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 1573 tid, seq_num, (*inst_iter)->seqNum); 1574 1575 while ((*inst_iter)->seqNum > seq_num) { 1576 1577 bool break_loop = (inst_iter == instList.begin()); 1578 1579 squashInstIt(inst_iter, tid); 1580 1581 inst_iter--; 1582 1583 if (break_loop) 1584 break; 1585 } 1586} 1587 1588template <class Impl> 1589inline void 1590FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 1591{ 1592 if ((*instIt)->threadNumber == tid) { 1593 DPRINTF(O3CPU, "Squashing instruction, " 1594 "[tid:%i] [sn:%lli] PC %#x\n", 1595 (*instIt)->threadNumber, 1596 (*instIt)->seqNum, 1597 (*instIt)->readPC()); 1598 1599 // Mark it as squashed. 1600 (*instIt)->setSquashed(); 1601 1602 // @todo: Formulate a consistent method for deleting 1603 // instructions from the instruction list 1604 // Remove the instruction from the list. 1605 removeList.push(instIt); 1606 } 1607} 1608 1609template <class Impl> 1610void 1611FullO3CPU<Impl>::cleanUpRemovedInsts() 1612{ 1613 while (!removeList.empty()) { 1614 DPRINTF(O3CPU, "Removing instruction, " 1615 "[tid:%i] [sn:%lli] PC %#x\n", 1616 (*removeList.front())->threadNumber, 1617 (*removeList.front())->seqNum, 1618 (*removeList.front())->readPC()); 1619 1620 instList.erase(removeList.front()); 1621 1622 removeList.pop(); 1623 } 1624 1625 removeInstsThisCycle = false; 1626} 1627/* 1628template <class Impl> 1629void 1630FullO3CPU<Impl>::removeAllInsts() 1631{ 1632 instList.clear(); 1633} 1634*/ 1635template <class Impl> 1636void 1637FullO3CPU<Impl>::dumpInsts() 1638{ 1639 int num = 0; 1640 1641 ListIt inst_list_it = instList.begin(); 1642 1643 cprintf("Dumping Instruction List\n"); 1644 1645 while (inst_list_it != instList.end()) { 1646 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 1647 "Squashed:%i\n\n", 1648 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 1649 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 1650 (*inst_list_it)->isSquashed()); 1651 inst_list_it++; 1652 ++num; 1653 } 1654} 1655/* 1656template <class Impl> 1657void 1658FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 1659{ 1660 iew.wakeDependents(inst); 1661} 1662*/ 1663template <class Impl> 1664void 1665FullO3CPU<Impl>::wakeCPU() 1666{ 1667 if (activityRec.active() || tickEvent.scheduled()) { 1668 DPRINTF(Activity, "CPU already running.\n"); 1669 return; 1670 } 1671 1672 DPRINTF(Activity, "Waking up CPU\n"); 1673 1674 idleCycles += tickToCycles((curTick - 1) - lastRunningCycle); 1675 numCycles += tickToCycles((curTick - 1) - lastRunningCycle); 1676 1677 schedule(tickEvent, nextCycle()); 1678} 1679 1680#if FULL_SYSTEM 1681template <class Impl> 1682void 1683FullO3CPU<Impl>::wakeup() 1684{ 1685 if (this->thread[0]->status() != ThreadContext::Suspended) 1686 return; 1687 1688 this->wakeCPU(); 1689 1690 DPRINTF(Quiesce, "Suspended Processor woken\n"); 1691 this->threadContexts[0]->activate(); 1692} 1693#endif 1694 1695template <class Impl> 1696int 1697FullO3CPU<Impl>::getFreeTid() 1698{ 1699 for (int i=0; i < numThreads; i++) { 1700 if (!tids[i]) { 1701 tids[i] = true; 1702 return i; 1703 } 1704 } 1705 1706 return -1; 1707} 1708 1709template <class Impl> 1710void 1711FullO3CPU<Impl>::doContextSwitch() 1712{ 1713 if (contextSwitch) { 1714 1715 //ADD CODE TO DEACTIVE THREAD HERE (???) 1716 1717 for (int tid=0; tid < cpuWaitList.size(); tid++) { 1718 activateWhenReady(tid); 1719 } 1720 1721 if (cpuWaitList.size() == 0) 1722 contextSwitch = true; 1723 } 1724} 1725 1726template <class Impl> 1727void 1728FullO3CPU<Impl>::updateThreadPriority() 1729{ 1730 if (activeThreads.size() > 1) 1731 { 1732 //DEFAULT TO ROUND ROBIN SCHEME 1733 //e.g. Move highest priority to end of thread list 1734 std::list<unsigned>::iterator list_begin = activeThreads.begin(); 1735 std::list<unsigned>::iterator list_end = activeThreads.end(); 1736 1737 unsigned high_thread = *list_begin; 1738 1739 activeThreads.erase(list_begin); 1740 1741 activeThreads.push_back(high_thread); 1742 } 1743} 1744 1745// Forward declaration of FullO3CPU. 1746template class FullO3CPU<O3CPUImpl>; 1747