cpu.cc revision 5595:6ebdae3f619b 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#include "cpu/activity.hh"
36#include "cpu/simple_thread.hh"
37#include "cpu/thread_context.hh"
38#include "cpu/o3/isa_specific.hh"
39#include "cpu/o3/cpu.hh"
40#include "cpu/o3/thread_context.hh"
41#include "enums/MemoryMode.hh"
42#include "sim/core.hh"
43#include "sim/stat_control.hh"
44
45#if FULL_SYSTEM
46#include "cpu/quiesce_event.hh"
47#include "sim/system.hh"
48#else
49#include "sim/process.hh"
50#endif
51
52#if USE_CHECKER
53#include "cpu/checker/cpu.hh"
54#endif
55
56#if THE_ISA == ALPHA_ISA
57#include "arch/alpha/osfpal.hh"
58#endif
59
60class BaseCPUParams;
61
62using namespace TheISA;
63
64BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
65    : BaseCPU(params), cpu_id(0)
66{
67}
68
69void
70BaseO3CPU::regStats()
71{
72    BaseCPU::regStats();
73}
74
75template <class Impl>
76FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
77    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
78{
79}
80
81template <class Impl>
82void
83FullO3CPU<Impl>::TickEvent::process()
84{
85    cpu->tick();
86}
87
88template <class Impl>
89const char *
90FullO3CPU<Impl>::TickEvent::description() const
91{
92    return "FullO3CPU tick";
93}
94
95template <class Impl>
96FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
97    : Event(&mainEventQueue, CPU_Switch_Pri)
98{
99}
100
101template <class Impl>
102void
103FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
104                                           FullO3CPU<Impl> *thread_cpu)
105{
106    tid = thread_num;
107    cpu = thread_cpu;
108}
109
110template <class Impl>
111void
112FullO3CPU<Impl>::ActivateThreadEvent::process()
113{
114    cpu->activateThread(tid);
115}
116
117template <class Impl>
118const char *
119FullO3CPU<Impl>::ActivateThreadEvent::description() const
120{
121    return "FullO3CPU \"Activate Thread\"";
122}
123
124template <class Impl>
125FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
126    : Event(&mainEventQueue, CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
127{
128}
129
130template <class Impl>
131void
132FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
133                                              FullO3CPU<Impl> *thread_cpu)
134{
135    tid = thread_num;
136    cpu = thread_cpu;
137    remove = false;
138}
139
140template <class Impl>
141void
142FullO3CPU<Impl>::DeallocateContextEvent::process()
143{
144    cpu->deactivateThread(tid);
145    if (remove)
146        cpu->removeThread(tid);
147}
148
149template <class Impl>
150const char *
151FullO3CPU<Impl>::DeallocateContextEvent::description() const
152{
153    return "FullO3CPU \"Deallocate Context\"";
154}
155
156template <class Impl>
157FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
158    : BaseO3CPU(params),
159      itb(params->itb),
160      dtb(params->dtb),
161      tickEvent(this),
162      removeInstsThisCycle(false),
163      fetch(this, params),
164      decode(this, params),
165      rename(this, params),
166      iew(this, params),
167      commit(this, params),
168
169      regFile(this, params->numPhysIntRegs,
170              params->numPhysFloatRegs),
171
172      freeList(params->numThreads,
173               TheISA::NumIntRegs, params->numPhysIntRegs,
174               TheISA::NumFloatRegs, params->numPhysFloatRegs),
175
176      rob(this,
177          params->numROBEntries, params->squashWidth,
178          params->smtROBPolicy, params->smtROBThreshold,
179          params->numThreads),
180
181      scoreboard(params->numThreads,
182                 TheISA::NumIntRegs, params->numPhysIntRegs,
183                 TheISA::NumFloatRegs, params->numPhysFloatRegs,
184                 TheISA::NumMiscRegs * number_of_threads,
185                 TheISA::ZeroReg),
186
187      timeBuffer(params->backComSize, params->forwardComSize),
188      fetchQueue(params->backComSize, params->forwardComSize),
189      decodeQueue(params->backComSize, params->forwardComSize),
190      renameQueue(params->backComSize, params->forwardComSize),
191      iewQueue(params->backComSize, params->forwardComSize),
192      activityRec(NumStages,
193                  params->backComSize + params->forwardComSize,
194                  params->activity),
195
196      globalSeqNum(1),
197#if FULL_SYSTEM
198      system(params->system),
199      physmem(system->physmem),
200#endif // FULL_SYSTEM
201      drainCount(0),
202      deferRegistration(params->defer_registration),
203      numThreads(number_of_threads)
204{
205    if (!deferRegistration) {
206        _status = Running;
207    } else {
208        _status = Idle;
209    }
210
211#if USE_CHECKER
212    if (params->checker) {
213        BaseCPU *temp_checker = params->checker;
214        checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
215#if FULL_SYSTEM
216        checker->setSystem(params->system);
217#endif
218    } else {
219        checker = NULL;
220    }
221#endif // USE_CHECKER
222
223#if !FULL_SYSTEM
224    thread.resize(number_of_threads);
225    tids.resize(number_of_threads);
226#endif
227
228    // The stages also need their CPU pointer setup.  However this
229    // must be done at the upper level CPU because they have pointers
230    // to the upper level CPU, and not this FullO3CPU.
231
232    // Set up Pointers to the activeThreads list for each stage
233    fetch.setActiveThreads(&activeThreads);
234    decode.setActiveThreads(&activeThreads);
235    rename.setActiveThreads(&activeThreads);
236    iew.setActiveThreads(&activeThreads);
237    commit.setActiveThreads(&activeThreads);
238
239    // Give each of the stages the time buffer they will use.
240    fetch.setTimeBuffer(&timeBuffer);
241    decode.setTimeBuffer(&timeBuffer);
242    rename.setTimeBuffer(&timeBuffer);
243    iew.setTimeBuffer(&timeBuffer);
244    commit.setTimeBuffer(&timeBuffer);
245
246    // Also setup each of the stages' queues.
247    fetch.setFetchQueue(&fetchQueue);
248    decode.setFetchQueue(&fetchQueue);
249    commit.setFetchQueue(&fetchQueue);
250    decode.setDecodeQueue(&decodeQueue);
251    rename.setDecodeQueue(&decodeQueue);
252    rename.setRenameQueue(&renameQueue);
253    iew.setRenameQueue(&renameQueue);
254    iew.setIEWQueue(&iewQueue);
255    commit.setIEWQueue(&iewQueue);
256    commit.setRenameQueue(&renameQueue);
257
258    commit.setIEWStage(&iew);
259    rename.setIEWStage(&iew);
260    rename.setCommitStage(&commit);
261
262#if !FULL_SYSTEM
263    int active_threads = params->workload.size();
264
265    if (active_threads > Impl::MaxThreads) {
266        panic("Workload Size too large. Increase the 'MaxThreads'"
267              "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
268              "edit your workload size.");
269    }
270#else
271    int active_threads = 1;
272#endif
273
274    //Make Sure That this a Valid Architeture
275    assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
276    assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
277
278    rename.setScoreboard(&scoreboard);
279    iew.setScoreboard(&scoreboard);
280
281    // Setup the rename map for whichever stages need it.
282    PhysRegIndex lreg_idx = 0;
283    PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
284
285    for (int tid=0; tid < numThreads; tid++) {
286        bool bindRegs = (tid <= active_threads - 1);
287
288        commitRenameMap[tid].init(TheISA::NumIntRegs,
289                                  params->numPhysIntRegs,
290                                  lreg_idx,            //Index for Logical. Regs
291
292                                  TheISA::NumFloatRegs,
293                                  params->numPhysFloatRegs,
294                                  freg_idx,            //Index for Float Regs
295
296                                  TheISA::NumMiscRegs,
297
298                                  TheISA::ZeroReg,
299                                  TheISA::ZeroReg,
300
301                                  tid,
302                                  false);
303
304        renameMap[tid].init(TheISA::NumIntRegs,
305                            params->numPhysIntRegs,
306                            lreg_idx,                  //Index for Logical. Regs
307
308                            TheISA::NumFloatRegs,
309                            params->numPhysFloatRegs,
310                            freg_idx,                  //Index for Float Regs
311
312                            TheISA::NumMiscRegs,
313
314                            TheISA::ZeroReg,
315                            TheISA::ZeroReg,
316
317                            tid,
318                            bindRegs);
319
320        activateThreadEvent[tid].init(tid, this);
321        deallocateContextEvent[tid].init(tid, this);
322    }
323
324    rename.setRenameMap(renameMap);
325    commit.setRenameMap(commitRenameMap);
326
327    // Give renameMap & rename stage access to the freeList;
328    for (int i=0; i < numThreads; i++) {
329        renameMap[i].setFreeList(&freeList);
330    }
331    rename.setFreeList(&freeList);
332
333    // Setup the ROB for whichever stages need it.
334    commit.setROB(&rob);
335
336    lastRunningCycle = curTick;
337
338    lastActivatedCycle = -1;
339
340    // Give renameMap & rename stage access to the freeList;
341    //for (int i=0; i < numThreads; i++) {
342        //globalSeqNum[i] = 1;
343        //}
344
345    contextSwitch = false;
346    DPRINTF(O3CPU, "Creating O3CPU object.\n");
347
348    // Setup any thread state.
349    this->thread.resize(this->numThreads);
350
351    for (int i = 0; i < this->numThreads; ++i) {
352#if FULL_SYSTEM
353        // SMT is not supported in FS mode yet.
354        assert(this->numThreads == 1);
355        this->thread[i] = new Thread(this, 0);
356        this->thread[i]->setStatus(ThreadContext::Suspended);
357#else
358        if (i < params->workload.size()) {
359            DPRINTF(O3CPU, "Workload[%i] process is %#x",
360                    i, this->thread[i]);
361            this->thread[i] = new typename FullO3CPU<Impl>::Thread(
362                    (typename Impl::O3CPU *)(this),
363                    i, params->workload[i], i);
364
365            this->thread[i]->setStatus(ThreadContext::Suspended);
366
367            //usedTids[i] = true;
368            //threadMap[i] = i;
369        } else {
370            //Allocate Empty thread so M5 can use later
371            //when scheduling threads to CPU
372            Process* dummy_proc = NULL;
373
374            this->thread[i] = new typename FullO3CPU<Impl>::Thread(
375                    (typename Impl::O3CPU *)(this),
376                    i, dummy_proc, i);
377            //usedTids[i] = false;
378        }
379#endif // !FULL_SYSTEM
380
381        ThreadContext *tc;
382
383        // Setup the TC that will serve as the interface to the threads/CPU.
384        O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
385
386        tc = o3_tc;
387
388        // If we're using a checker, then the TC should be the
389        // CheckerThreadContext.
390#if USE_CHECKER
391        if (params->checker) {
392            tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
393                o3_tc, this->checker);
394        }
395#endif
396
397        o3_tc->cpu = (typename Impl::O3CPU *)(this);
398        assert(o3_tc->cpu);
399        o3_tc->thread = this->thread[i];
400
401#if FULL_SYSTEM
402        // Setup quiesce event.
403        this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc);
404#endif
405        // Give the thread the TC.
406        this->thread[i]->tc = tc;
407        this->thread[i]->setCpuId(params->cpu_id);
408
409        // Add the TC to the CPU's list of TC's.
410        this->threadContexts.push_back(tc);
411    }
412
413    for (int i=0; i < this->numThreads; i++) {
414        this->thread[i]->setFuncExeInst(0);
415    }
416
417    lockAddr = 0;
418    lockFlag = false;
419}
420
421#if !FULL_SYSTEM
422
423template <class Impl>
424TheISA::IntReg
425FullO3CPU<Impl>::getSyscallArg(int i, int tid)
426{
427    assert(i < TheISA::NumArgumentRegs);
428    TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
429            TheISA::ArgumentReg[i]);
430    TheISA::IntReg val = this->readArchIntReg(idx, tid);
431#if THE_ISA == SPARC_ISA
432    if (bits(this->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE, tid), 3, 3))
433        val = bits(val, 31, 0);
434#endif
435    return val;
436}
437
438template <class Impl>
439void
440FullO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid)
441{
442    assert(i < TheISA::NumArgumentRegs);
443    TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
444            TheISA::ArgumentReg[i]);
445    this->setArchIntReg(idx, val, tid);
446}
447#endif
448
449template <class Impl>
450FullO3CPU<Impl>::~FullO3CPU()
451{
452}
453
454template <class Impl>
455void
456FullO3CPU<Impl>::regStats()
457{
458    BaseO3CPU::regStats();
459
460    // Register any of the O3CPU's stats here.
461    timesIdled
462        .name(name() + ".timesIdled")
463        .desc("Number of times that the entire CPU went into an idle state and"
464              " unscheduled itself")
465        .prereq(timesIdled);
466
467    idleCycles
468        .name(name() + ".idleCycles")
469        .desc("Total number of cycles that the CPU has spent unscheduled due "
470              "to idling")
471        .prereq(idleCycles);
472
473    // Number of Instructions simulated
474    // --------------------------------
475    // Should probably be in Base CPU but need templated
476    // MaxThreads so put in here instead
477    committedInsts
478        .init(numThreads)
479        .name(name() + ".committedInsts")
480        .desc("Number of Instructions Simulated");
481
482    totalCommittedInsts
483        .name(name() + ".committedInsts_total")
484        .desc("Number of Instructions Simulated");
485
486    cpi
487        .name(name() + ".cpi")
488        .desc("CPI: Cycles Per Instruction")
489        .precision(6);
490    cpi = numCycles / committedInsts;
491
492    totalCpi
493        .name(name() + ".cpi_total")
494        .desc("CPI: Total CPI of All Threads")
495        .precision(6);
496    totalCpi = numCycles / totalCommittedInsts;
497
498    ipc
499        .name(name() + ".ipc")
500        .desc("IPC: Instructions Per Cycle")
501        .precision(6);
502    ipc =  committedInsts / numCycles;
503
504    totalIpc
505        .name(name() + ".ipc_total")
506        .desc("IPC: Total IPC of All Threads")
507        .precision(6);
508    totalIpc =  totalCommittedInsts / numCycles;
509
510    this->fetch.regStats();
511    this->decode.regStats();
512    this->rename.regStats();
513    this->iew.regStats();
514    this->commit.regStats();
515}
516
517template <class Impl>
518Port *
519FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
520{
521    if (if_name == "dcache_port")
522        return iew.getDcachePort();
523    else if (if_name == "icache_port")
524        return fetch.getIcachePort();
525    else
526        panic("No Such Port\n");
527}
528
529template <class Impl>
530void
531FullO3CPU<Impl>::tick()
532{
533    DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
534
535    ++numCycles;
536
537//    activity = false;
538
539    //Tick each of the stages
540    fetch.tick();
541
542    decode.tick();
543
544    rename.tick();
545
546    iew.tick();
547
548    commit.tick();
549
550#if !FULL_SYSTEM
551    doContextSwitch();
552#endif
553
554    // Now advance the time buffers
555    timeBuffer.advance();
556
557    fetchQueue.advance();
558    decodeQueue.advance();
559    renameQueue.advance();
560    iewQueue.advance();
561
562    activityRec.advance();
563
564    if (removeInstsThisCycle) {
565        cleanUpRemovedInsts();
566    }
567
568    if (!tickEvent.scheduled()) {
569        if (_status == SwitchedOut ||
570            getState() == SimObject::Drained) {
571            DPRINTF(O3CPU, "Switched out!\n");
572            // increment stat
573            lastRunningCycle = curTick;
574        } else if (!activityRec.active() || _status == Idle) {
575            DPRINTF(O3CPU, "Idle!\n");
576            lastRunningCycle = curTick;
577            timesIdled++;
578        } else {
579            tickEvent.schedule(nextCycle(curTick + ticks(1)));
580            DPRINTF(O3CPU, "Scheduling next tick!\n");
581        }
582    }
583
584#if !FULL_SYSTEM
585    updateThreadPriority();
586#endif
587
588}
589
590template <class Impl>
591void
592FullO3CPU<Impl>::init()
593{
594    if (!deferRegistration) {
595        registerThreadContexts();
596    }
597
598    // Set inSyscall so that the CPU doesn't squash when initially
599    // setting up registers.
600    for (int i = 0; i < number_of_threads; ++i)
601        thread[i]->inSyscall = true;
602
603    for (int tid=0; tid < number_of_threads; tid++) {
604#if FULL_SYSTEM
605        ThreadContext *src_tc = threadContexts[tid];
606#else
607        ThreadContext *src_tc = thread[tid]->getTC();
608#endif
609        // Threads start in the Suspended State
610        if (src_tc->status() != ThreadContext::Suspended) {
611            continue;
612        }
613
614#if FULL_SYSTEM
615        TheISA::initCPU(src_tc, src_tc->readCpuId());
616#endif
617    }
618
619    // Clear inSyscall.
620    for (int i = 0; i < number_of_threads; ++i)
621        thread[i]->inSyscall = false;
622
623    // Initialize stages.
624    fetch.initStage();
625    iew.initStage();
626    rename.initStage();
627    commit.initStage();
628
629    commit.setThreads(thread);
630}
631
632template <class Impl>
633void
634FullO3CPU<Impl>::activateThread(unsigned tid)
635{
636    std::list<unsigned>::iterator isActive =
637        std::find(activeThreads.begin(), activeThreads.end(), tid);
638
639    DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
640
641    if (isActive == activeThreads.end()) {
642        DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
643                tid);
644
645        activeThreads.push_back(tid);
646    }
647}
648
649template <class Impl>
650void
651FullO3CPU<Impl>::deactivateThread(unsigned tid)
652{
653    //Remove From Active List, if Active
654    std::list<unsigned>::iterator thread_it =
655        std::find(activeThreads.begin(), activeThreads.end(), tid);
656
657    DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
658
659    if (thread_it != activeThreads.end()) {
660        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
661                tid);
662        activeThreads.erase(thread_it);
663    }
664}
665
666template <class Impl>
667void
668FullO3CPU<Impl>::activateContext(int tid, int delay)
669{
670    // Needs to set each stage to running as well.
671    if (delay){
672        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
673                "on cycle %d\n", tid, curTick + ticks(delay));
674        scheduleActivateThreadEvent(tid, delay);
675    } else {
676        activateThread(tid);
677    }
678
679    if (lastActivatedCycle < curTick) {
680        scheduleTickEvent(delay);
681
682        // Be sure to signal that there's some activity so the CPU doesn't
683        // deschedule itself.
684        activityRec.activity();
685        fetch.wakeFromQuiesce();
686
687        lastActivatedCycle = curTick;
688
689        _status = Running;
690    }
691}
692
693template <class Impl>
694bool
695FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay)
696{
697    // Schedule removal of thread data from CPU
698    if (delay){
699        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
700                "on cycle %d\n", tid, curTick + ticks(delay));
701        scheduleDeallocateContextEvent(tid, remove, delay);
702        return false;
703    } else {
704        deactivateThread(tid);
705        if (remove)
706            removeThread(tid);
707        return true;
708    }
709}
710
711template <class Impl>
712void
713FullO3CPU<Impl>::suspendContext(int tid)
714{
715    DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
716    bool deallocated = deallocateContext(tid, false, 1);
717    // If this was the last thread then unschedule the tick event.
718    if ((activeThreads.size() == 1 && !deallocated) ||
719        activeThreads.size() == 0)
720        unscheduleTickEvent();
721    _status = Idle;
722}
723
724template <class Impl>
725void
726FullO3CPU<Impl>::haltContext(int tid)
727{
728    //For now, this is the same as deallocate
729    DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
730    deallocateContext(tid, true, 1);
731}
732
733template <class Impl>
734void
735FullO3CPU<Impl>::insertThread(unsigned tid)
736{
737    DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
738    // Will change now that the PC and thread state is internal to the CPU
739    // and not in the ThreadContext.
740#if FULL_SYSTEM
741    ThreadContext *src_tc = system->threadContexts[tid];
742#else
743    ThreadContext *src_tc = tcBase(tid);
744#endif
745
746    //Bind Int Regs to Rename Map
747    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
748        PhysRegIndex phys_reg = freeList.getIntReg();
749
750        renameMap[tid].setEntry(ireg,phys_reg);
751        scoreboard.setReg(phys_reg);
752    }
753
754    //Bind Float Regs to Rename Map
755    for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
756        PhysRegIndex phys_reg = freeList.getFloatReg();
757
758        renameMap[tid].setEntry(freg,phys_reg);
759        scoreboard.setReg(phys_reg);
760    }
761
762    //Copy Thread Data Into RegFile
763    //this->copyFromTC(tid);
764
765    //Set PC/NPC/NNPC
766    setPC(src_tc->readPC(), tid);
767    setNextPC(src_tc->readNextPC(), tid);
768    setNextNPC(src_tc->readNextNPC(), tid);
769
770    src_tc->setStatus(ThreadContext::Active);
771
772    activateContext(tid,1);
773
774    //Reset ROB/IQ/LSQ Entries
775    commit.rob->resetEntries();
776    iew.resetEntries();
777}
778
779template <class Impl>
780void
781FullO3CPU<Impl>::removeThread(unsigned tid)
782{
783    DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
784
785    // Copy Thread Data From RegFile
786    // If thread is suspended, it might be re-allocated
787    // this->copyToTC(tid);
788
789
790    // @todo: 2-27-2008: Fix how we free up rename mappings
791    // here to alleviate the case for double-freeing registers
792    // in SMT workloads.
793
794    // Unbind Int Regs from Rename Map
795    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
796        PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
797
798        scoreboard.unsetReg(phys_reg);
799        freeList.addReg(phys_reg);
800    }
801
802    // Unbind Float Regs from Rename Map
803    for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
804        PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
805
806        scoreboard.unsetReg(phys_reg);
807        freeList.addReg(phys_reg);
808    }
809
810    // Squash Throughout Pipeline
811    InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
812    fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid);
813    decode.squash(tid);
814    rename.squash(squash_seq_num, tid);
815    iew.squash(tid);
816    iew.ldstQueue.squash(squash_seq_num, tid);
817    commit.rob->squash(squash_seq_num, tid);
818
819
820    assert(iew.instQueue.getCount(tid) == 0);
821    assert(iew.ldstQueue.getCount(tid) == 0);
822
823    // Reset ROB/IQ/LSQ Entries
824
825    // Commented out for now.  This should be possible to do by
826    // telling all the pipeline stages to drain first, and then
827    // checking until the drain completes.  Once the pipeline is
828    // drained, call resetEntries(). - 10-09-06 ktlim
829/*
830    if (activeThreads.size() >= 1) {
831        commit.rob->resetEntries();
832        iew.resetEntries();
833    }
834*/
835}
836
837
838template <class Impl>
839void
840FullO3CPU<Impl>::activateWhenReady(int tid)
841{
842    DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
843            "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
844            tid);
845
846    bool ready = true;
847
848    if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
849        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
850                "Phys. Int. Regs.\n",
851                tid);
852        ready = false;
853    } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
854        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
855                "Phys. Float. Regs.\n",
856                tid);
857        ready = false;
858    } else if (commit.rob->numFreeEntries() >=
859               commit.rob->entryAmount(activeThreads.size() + 1)) {
860        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
861                "ROB entries.\n",
862                tid);
863        ready = false;
864    } else if (iew.instQueue.numFreeEntries() >=
865               iew.instQueue.entryAmount(activeThreads.size() + 1)) {
866        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
867                "IQ entries.\n",
868                tid);
869        ready = false;
870    } else if (iew.ldstQueue.numFreeEntries() >=
871               iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
872        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
873                "LSQ entries.\n",
874                tid);
875        ready = false;
876    }
877
878    if (ready) {
879        insertThread(tid);
880
881        contextSwitch = false;
882
883        cpuWaitList.remove(tid);
884    } else {
885        suspendContext(tid);
886
887        //blocks fetch
888        contextSwitch = true;
889
890        //@todo: dont always add to waitlist
891        //do waitlist
892        cpuWaitList.push_back(tid);
893    }
894}
895
896#if FULL_SYSTEM
897template <class Impl>
898void
899FullO3CPU<Impl>::post_interrupt(int int_num, int index)
900{
901    BaseCPU::post_interrupt(int_num, index);
902
903    if (this->thread[0]->status() == ThreadContext::Suspended) {
904        DPRINTF(IPI,"Suspended Processor awoke\n");
905        this->threadContexts[0]->activate();
906    }
907}
908
909template <class Impl>
910Fault
911FullO3CPU<Impl>::hwrei(unsigned tid)
912{
913#if THE_ISA == ALPHA_ISA
914    // Need to clear the lock flag upon returning from an interrupt.
915    this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
916
917    this->thread[tid]->kernelStats->hwrei();
918
919    // FIXME: XXX check for interrupts? XXX
920#endif
921    return NoFault;
922}
923
924template <class Impl>
925bool
926FullO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid)
927{
928#if THE_ISA == ALPHA_ISA
929    if (this->thread[tid]->kernelStats)
930        this->thread[tid]->kernelStats->callpal(palFunc,
931                                                this->threadContexts[tid]);
932
933    switch (palFunc) {
934      case PAL::halt:
935        halt();
936        if (--System::numSystemsRunning == 0)
937            exitSimLoop("all cpus halted");
938        break;
939
940      case PAL::bpt:
941      case PAL::bugchk:
942        if (this->system->breakpoint())
943            return false;
944        break;
945    }
946#endif
947    return true;
948}
949
950template <class Impl>
951Fault
952FullO3CPU<Impl>::getInterrupts()
953{
954    // Check if there are any outstanding interrupts
955    return this->interrupts.getInterrupt(this->threadContexts[0]);
956}
957
958template <class Impl>
959void
960FullO3CPU<Impl>::processInterrupts(Fault interrupt)
961{
962    // Check for interrupts here.  For now can copy the code that
963    // exists within isa_fullsys_traits.hh.  Also assume that thread 0
964    // is the one that handles the interrupts.
965    // @todo: Possibly consolidate the interrupt checking code.
966    // @todo: Allow other threads to handle interrupts.
967
968    assert(interrupt != NoFault);
969    this->interrupts.updateIntrInfo(this->threadContexts[0]);
970
971    DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
972    this->trap(interrupt, 0);
973}
974
975template <class Impl>
976void
977FullO3CPU<Impl>::updateMemPorts()
978{
979    // Update all ThreadContext's memory ports (Functional/Virtual
980    // Ports)
981    for (int i = 0; i < thread.size(); ++i)
982        thread[i]->connectMemPorts(thread[i]->getTC());
983}
984#endif
985
986template <class Impl>
987void
988FullO3CPU<Impl>::trap(Fault fault, unsigned tid)
989{
990    // Pass the thread's TC into the invoke method.
991    fault->invoke(this->threadContexts[tid]);
992}
993
994#if !FULL_SYSTEM
995
996template <class Impl>
997void
998FullO3CPU<Impl>::syscall(int64_t callnum, int tid)
999{
1000    DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1001
1002    DPRINTF(Activity,"Activity: syscall() called.\n");
1003
1004    // Temporarily increase this by one to account for the syscall
1005    // instruction.
1006    ++(this->thread[tid]->funcExeInst);
1007
1008    // Execute the actual syscall.
1009    this->thread[tid]->syscall(callnum);
1010
1011    // Decrease funcExeInst by one as the normal commit will handle
1012    // incrementing it.
1013    --(this->thread[tid]->funcExeInst);
1014}
1015
1016template <class Impl>
1017void
1018FullO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
1019{
1020    TheISA::setSyscallReturn(return_value, this->tcBase(tid));
1021}
1022
1023#endif
1024
1025template <class Impl>
1026void
1027FullO3CPU<Impl>::serialize(std::ostream &os)
1028{
1029    SimObject::State so_state = SimObject::getState();
1030    SERIALIZE_ENUM(so_state);
1031    BaseCPU::serialize(os);
1032    nameOut(os, csprintf("%s.tickEvent", name()));
1033    tickEvent.serialize(os);
1034
1035    // Use SimpleThread's ability to checkpoint to make it easier to
1036    // write out the registers.  Also make this static so it doesn't
1037    // get instantiated multiple times (causes a panic in statistics).
1038    static SimpleThread temp;
1039
1040    for (int i = 0; i < thread.size(); i++) {
1041        nameOut(os, csprintf("%s.xc.%i", name(), i));
1042        temp.copyTC(thread[i]->getTC());
1043        temp.serialize(os);
1044    }
1045}
1046
1047template <class Impl>
1048void
1049FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
1050{
1051    SimObject::State so_state;
1052    UNSERIALIZE_ENUM(so_state);
1053    BaseCPU::unserialize(cp, section);
1054    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1055
1056    // Use SimpleThread's ability to checkpoint to make it easier to
1057    // read in the registers.  Also make this static so it doesn't
1058    // get instantiated multiple times (causes a panic in statistics).
1059    static SimpleThread temp;
1060
1061    for (int i = 0; i < thread.size(); i++) {
1062        temp.copyTC(thread[i]->getTC());
1063        temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1064        thread[i]->getTC()->copyArchRegs(temp.getTC());
1065    }
1066}
1067
1068template <class Impl>
1069unsigned int
1070FullO3CPU<Impl>::drain(Event *drain_event)
1071{
1072    DPRINTF(O3CPU, "Switching out\n");
1073
1074    // If the CPU isn't doing anything, then return immediately.
1075    if (_status == Idle || _status == SwitchedOut) {
1076        return 0;
1077    }
1078
1079    drainCount = 0;
1080    fetch.drain();
1081    decode.drain();
1082    rename.drain();
1083    iew.drain();
1084    commit.drain();
1085
1086    // Wake the CPU and record activity so everything can drain out if
1087    // the CPU was not able to immediately drain.
1088    if (getState() != SimObject::Drained) {
1089        // A bit of a hack...set the drainEvent after all the drain()
1090        // calls have been made, that way if all of the stages drain
1091        // immediately, the signalDrained() function knows not to call
1092        // process on the drain event.
1093        drainEvent = drain_event;
1094
1095        wakeCPU();
1096        activityRec.activity();
1097
1098        return 1;
1099    } else {
1100        return 0;
1101    }
1102}
1103
1104template <class Impl>
1105void
1106FullO3CPU<Impl>::resume()
1107{
1108    fetch.resume();
1109    decode.resume();
1110    rename.resume();
1111    iew.resume();
1112    commit.resume();
1113
1114    changeState(SimObject::Running);
1115
1116    if (_status == SwitchedOut || _status == Idle)
1117        return;
1118
1119#if FULL_SYSTEM
1120    assert(system->getMemoryMode() == Enums::timing);
1121#endif
1122
1123    if (!tickEvent.scheduled())
1124        tickEvent.schedule(nextCycle());
1125    _status = Running;
1126}
1127
1128template <class Impl>
1129void
1130FullO3CPU<Impl>::signalDrained()
1131{
1132    if (++drainCount == NumStages) {
1133        if (tickEvent.scheduled())
1134            tickEvent.squash();
1135
1136        changeState(SimObject::Drained);
1137
1138        BaseCPU::switchOut();
1139
1140        if (drainEvent) {
1141            drainEvent->process();
1142            drainEvent = NULL;
1143        }
1144    }
1145    assert(drainCount <= 5);
1146}
1147
1148template <class Impl>
1149void
1150FullO3CPU<Impl>::switchOut()
1151{
1152    fetch.switchOut();
1153    rename.switchOut();
1154    iew.switchOut();
1155    commit.switchOut();
1156    instList.clear();
1157    while (!removeList.empty()) {
1158        removeList.pop();
1159    }
1160
1161    _status = SwitchedOut;
1162#if USE_CHECKER
1163    if (checker)
1164        checker->switchOut();
1165#endif
1166    if (tickEvent.scheduled())
1167        tickEvent.squash();
1168}
1169
1170template <class Impl>
1171void
1172FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1173{
1174    // Flush out any old data from the time buffers.
1175    for (int i = 0; i < timeBuffer.getSize(); ++i) {
1176        timeBuffer.advance();
1177        fetchQueue.advance();
1178        decodeQueue.advance();
1179        renameQueue.advance();
1180        iewQueue.advance();
1181    }
1182
1183    activityRec.reset();
1184
1185    BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort());
1186
1187    fetch.takeOverFrom();
1188    decode.takeOverFrom();
1189    rename.takeOverFrom();
1190    iew.takeOverFrom();
1191    commit.takeOverFrom();
1192
1193    assert(!tickEvent.scheduled());
1194
1195    // @todo: Figure out how to properly select the tid to put onto
1196    // the active threads list.
1197    int tid = 0;
1198
1199    std::list<unsigned>::iterator isActive =
1200        std::find(activeThreads.begin(), activeThreads.end(), tid);
1201
1202    if (isActive == activeThreads.end()) {
1203        //May Need to Re-code this if the delay variable is the delay
1204        //needed for thread to activate
1205        DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1206                tid);
1207
1208        activeThreads.push_back(tid);
1209    }
1210
1211    // Set all statuses to active, schedule the CPU's tick event.
1212    // @todo: Fix up statuses so this is handled properly
1213    for (int i = 0; i < threadContexts.size(); ++i) {
1214        ThreadContext *tc = threadContexts[i];
1215        if (tc->status() == ThreadContext::Active && _status != Running) {
1216            _status = Running;
1217            tickEvent.schedule(nextCycle());
1218        }
1219    }
1220    if (!tickEvent.scheduled())
1221        tickEvent.schedule(nextCycle());
1222}
1223
1224template <class Impl>
1225TheISA::MiscReg
1226FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid)
1227{
1228    return this->regFile.readMiscRegNoEffect(misc_reg, tid);
1229}
1230
1231template <class Impl>
1232TheISA::MiscReg
1233FullO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
1234{
1235    return this->regFile.readMiscReg(misc_reg, tid);
1236}
1237
1238template <class Impl>
1239void
1240FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1241        const TheISA::MiscReg &val, unsigned tid)
1242{
1243    this->regFile.setMiscRegNoEffect(misc_reg, val, tid);
1244}
1245
1246template <class Impl>
1247void
1248FullO3CPU<Impl>::setMiscReg(int misc_reg,
1249        const TheISA::MiscReg &val, unsigned tid)
1250{
1251    this->regFile.setMiscReg(misc_reg, val, tid);
1252}
1253
1254template <class Impl>
1255uint64_t
1256FullO3CPU<Impl>::readIntReg(int reg_idx)
1257{
1258    return regFile.readIntReg(reg_idx);
1259}
1260
1261template <class Impl>
1262FloatReg
1263FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
1264{
1265    return regFile.readFloatReg(reg_idx, width);
1266}
1267
1268template <class Impl>
1269FloatReg
1270FullO3CPU<Impl>::readFloatReg(int reg_idx)
1271{
1272    return regFile.readFloatReg(reg_idx);
1273}
1274
1275template <class Impl>
1276FloatRegBits
1277FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
1278{
1279    return regFile.readFloatRegBits(reg_idx, width);
1280}
1281
1282template <class Impl>
1283FloatRegBits
1284FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1285{
1286    return regFile.readFloatRegBits(reg_idx);
1287}
1288
1289template <class Impl>
1290void
1291FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1292{
1293    regFile.setIntReg(reg_idx, val);
1294}
1295
1296template <class Impl>
1297void
1298FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
1299{
1300    regFile.setFloatReg(reg_idx, val, width);
1301}
1302
1303template <class Impl>
1304void
1305FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1306{
1307    regFile.setFloatReg(reg_idx, val);
1308}
1309
1310template <class Impl>
1311void
1312FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
1313{
1314    regFile.setFloatRegBits(reg_idx, val, width);
1315}
1316
1317template <class Impl>
1318void
1319FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1320{
1321    regFile.setFloatRegBits(reg_idx, val);
1322}
1323
1324template <class Impl>
1325uint64_t
1326FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid)
1327{
1328    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1329
1330    return regFile.readIntReg(phys_reg);
1331}
1332
1333template <class Impl>
1334float
1335FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid)
1336{
1337    int idx = reg_idx + TheISA::FP_Base_DepTag;
1338    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1339
1340    return regFile.readFloatReg(phys_reg);
1341}
1342
1343template <class Impl>
1344double
1345FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid)
1346{
1347    int idx = reg_idx + TheISA::FP_Base_DepTag;
1348    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1349
1350    return regFile.readFloatReg(phys_reg, 64);
1351}
1352
1353template <class Impl>
1354uint64_t
1355FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid)
1356{
1357    int idx = reg_idx + TheISA::FP_Base_DepTag;
1358    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1359
1360    return regFile.readFloatRegBits(phys_reg);
1361}
1362
1363template <class Impl>
1364void
1365FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid)
1366{
1367    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1368
1369    regFile.setIntReg(phys_reg, val);
1370}
1371
1372template <class Impl>
1373void
1374FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
1375{
1376    int idx = reg_idx + TheISA::FP_Base_DepTag;
1377    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1378
1379    regFile.setFloatReg(phys_reg, val);
1380}
1381
1382template <class Impl>
1383void
1384FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
1385{
1386    int idx = reg_idx + TheISA::FP_Base_DepTag;
1387    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1388
1389    regFile.setFloatReg(phys_reg, val, 64);
1390}
1391
1392template <class Impl>
1393void
1394FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
1395{
1396    int idx = reg_idx + TheISA::FP_Base_DepTag;
1397    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1398
1399    regFile.setFloatRegBits(phys_reg, val);
1400}
1401
1402template <class Impl>
1403uint64_t
1404FullO3CPU<Impl>::readPC(unsigned tid)
1405{
1406    return commit.readPC(tid);
1407}
1408
1409template <class Impl>
1410void
1411FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid)
1412{
1413    commit.setPC(new_PC, tid);
1414}
1415
1416template <class Impl>
1417uint64_t
1418FullO3CPU<Impl>::readMicroPC(unsigned tid)
1419{
1420    return commit.readMicroPC(tid);
1421}
1422
1423template <class Impl>
1424void
1425FullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid)
1426{
1427    commit.setMicroPC(new_PC, tid);
1428}
1429
1430template <class Impl>
1431uint64_t
1432FullO3CPU<Impl>::readNextPC(unsigned tid)
1433{
1434    return commit.readNextPC(tid);
1435}
1436
1437template <class Impl>
1438void
1439FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
1440{
1441    commit.setNextPC(val, tid);
1442}
1443
1444template <class Impl>
1445uint64_t
1446FullO3CPU<Impl>::readNextNPC(unsigned tid)
1447{
1448    return commit.readNextNPC(tid);
1449}
1450
1451template <class Impl>
1452void
1453FullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid)
1454{
1455    commit.setNextNPC(val, tid);
1456}
1457
1458template <class Impl>
1459uint64_t
1460FullO3CPU<Impl>::readNextMicroPC(unsigned tid)
1461{
1462    return commit.readNextMicroPC(tid);
1463}
1464
1465template <class Impl>
1466void
1467FullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid)
1468{
1469    commit.setNextMicroPC(new_PC, tid);
1470}
1471
1472template <class Impl>
1473void
1474FullO3CPU<Impl>::squashFromTC(unsigned tid)
1475{
1476    this->thread[tid]->inSyscall = true;
1477    this->commit.generateTCEvent(tid);
1478}
1479
1480template <class Impl>
1481typename FullO3CPU<Impl>::ListIt
1482FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1483{
1484    instList.push_back(inst);
1485
1486    return --(instList.end());
1487}
1488
1489template <class Impl>
1490void
1491FullO3CPU<Impl>::instDone(unsigned tid)
1492{
1493    // Keep an instruction count.
1494    thread[tid]->numInst++;
1495    thread[tid]->numInsts++;
1496    committedInsts[tid]++;
1497    totalCommittedInsts++;
1498
1499    // Check for instruction-count-based events.
1500    comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1501}
1502
1503template <class Impl>
1504void
1505FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst)
1506{
1507    removeInstsThisCycle = true;
1508
1509    removeList.push(inst->getInstListIt());
1510}
1511
1512template <class Impl>
1513void
1514FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1515{
1516    DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
1517            "[sn:%lli]\n",
1518            inst->threadNumber, inst->readPC(), inst->seqNum);
1519
1520    removeInstsThisCycle = true;
1521
1522    // Remove the front instruction.
1523    removeList.push(inst->getInstListIt());
1524}
1525
1526template <class Impl>
1527void
1528FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
1529{
1530    DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1531            " list.\n", tid);
1532
1533    ListIt end_it;
1534
1535    bool rob_empty = false;
1536
1537    if (instList.empty()) {
1538        return;
1539    } else if (rob.isEmpty(/*tid*/)) {
1540        DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1541        end_it = instList.begin();
1542        rob_empty = true;
1543    } else {
1544        end_it = (rob.readTailInst(tid))->getInstListIt();
1545        DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1546    }
1547
1548    removeInstsThisCycle = true;
1549
1550    ListIt inst_it = instList.end();
1551
1552    inst_it--;
1553
1554    // Walk through the instruction list, removing any instructions
1555    // that were inserted after the given instruction iterator, end_it.
1556    while (inst_it != end_it) {
1557        assert(!instList.empty());
1558
1559        squashInstIt(inst_it, tid);
1560
1561        inst_it--;
1562    }
1563
1564    // If the ROB was empty, then we actually need to remove the first
1565    // instruction as well.
1566    if (rob_empty) {
1567        squashInstIt(inst_it, tid);
1568    }
1569}
1570
1571template <class Impl>
1572void
1573FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
1574                                  unsigned tid)
1575{
1576    assert(!instList.empty());
1577
1578    removeInstsThisCycle = true;
1579
1580    ListIt inst_iter = instList.end();
1581
1582    inst_iter--;
1583
1584    DPRINTF(O3CPU, "Deleting instructions from instruction "
1585            "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1586            tid, seq_num, (*inst_iter)->seqNum);
1587
1588    while ((*inst_iter)->seqNum > seq_num) {
1589
1590        bool break_loop = (inst_iter == instList.begin());
1591
1592        squashInstIt(inst_iter, tid);
1593
1594        inst_iter--;
1595
1596        if (break_loop)
1597            break;
1598    }
1599}
1600
1601template <class Impl>
1602inline void
1603FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
1604{
1605    if ((*instIt)->threadNumber == tid) {
1606        DPRINTF(O3CPU, "Squashing instruction, "
1607                "[tid:%i] [sn:%lli] PC %#x\n",
1608                (*instIt)->threadNumber,
1609                (*instIt)->seqNum,
1610                (*instIt)->readPC());
1611
1612        // Mark it as squashed.
1613        (*instIt)->setSquashed();
1614
1615        // @todo: Formulate a consistent method for deleting
1616        // instructions from the instruction list
1617        // Remove the instruction from the list.
1618        removeList.push(instIt);
1619    }
1620}
1621
1622template <class Impl>
1623void
1624FullO3CPU<Impl>::cleanUpRemovedInsts()
1625{
1626    while (!removeList.empty()) {
1627        DPRINTF(O3CPU, "Removing instruction, "
1628                "[tid:%i] [sn:%lli] PC %#x\n",
1629                (*removeList.front())->threadNumber,
1630                (*removeList.front())->seqNum,
1631                (*removeList.front())->readPC());
1632
1633        instList.erase(removeList.front());
1634
1635        removeList.pop();
1636    }
1637
1638    removeInstsThisCycle = false;
1639}
1640/*
1641template <class Impl>
1642void
1643FullO3CPU<Impl>::removeAllInsts()
1644{
1645    instList.clear();
1646}
1647*/
1648template <class Impl>
1649void
1650FullO3CPU<Impl>::dumpInsts()
1651{
1652    int num = 0;
1653
1654    ListIt inst_list_it = instList.begin();
1655
1656    cprintf("Dumping Instruction List\n");
1657
1658    while (inst_list_it != instList.end()) {
1659        cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1660                "Squashed:%i\n\n",
1661                num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
1662                (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1663                (*inst_list_it)->isSquashed());
1664        inst_list_it++;
1665        ++num;
1666    }
1667}
1668/*
1669template <class Impl>
1670void
1671FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1672{
1673    iew.wakeDependents(inst);
1674}
1675*/
1676template <class Impl>
1677void
1678FullO3CPU<Impl>::wakeCPU()
1679{
1680    if (activityRec.active() || tickEvent.scheduled()) {
1681        DPRINTF(Activity, "CPU already running.\n");
1682        return;
1683    }
1684
1685    DPRINTF(Activity, "Waking up CPU\n");
1686
1687    idleCycles += tickToCycles((curTick - 1) - lastRunningCycle);
1688    numCycles += tickToCycles((curTick - 1) - lastRunningCycle);
1689
1690    tickEvent.schedule(nextCycle());
1691}
1692
1693template <class Impl>
1694int
1695FullO3CPU<Impl>::getFreeTid()
1696{
1697    for (int i=0; i < numThreads; i++) {
1698        if (!tids[i]) {
1699            tids[i] = true;
1700            return i;
1701        }
1702    }
1703
1704    return -1;
1705}
1706
1707template <class Impl>
1708void
1709FullO3CPU<Impl>::doContextSwitch()
1710{
1711    if (contextSwitch) {
1712
1713        //ADD CODE TO DEACTIVE THREAD HERE (???)
1714
1715        for (int tid=0; tid < cpuWaitList.size(); tid++) {
1716            activateWhenReady(tid);
1717        }
1718
1719        if (cpuWaitList.size() == 0)
1720            contextSwitch = true;
1721    }
1722}
1723
1724template <class Impl>
1725void
1726FullO3CPU<Impl>::updateThreadPriority()
1727{
1728    if (activeThreads.size() > 1)
1729    {
1730        //DEFAULT TO ROUND ROBIN SCHEME
1731        //e.g. Move highest priority to end of thread list
1732        std::list<unsigned>::iterator list_begin = activeThreads.begin();
1733        std::list<unsigned>::iterator list_end   = activeThreads.end();
1734
1735        unsigned high_thread = *list_begin;
1736
1737        activeThreads.erase(list_begin);
1738
1739        activeThreads.push_back(high_thread);
1740    }
1741}
1742
1743// Forward declaration of FullO3CPU.
1744template class FullO3CPU<O3CPUImpl>;
1745