cpu.cc revision 4762
12SN/A/* 22188SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 292665SN/A * Korey Sewell 302665SN/A */ 312665SN/A 322SN/A#include "config/full_system.hh" 332SN/A#include "config/use_checker.hh" 342SN/A 352SN/A#include "cpu/activity.hh" 362465SN/A#include "cpu/simple_thread.hh" 371717SN/A#include "cpu/thread_context.hh" 382683Sktlim@umich.edu#include "cpu/o3/isa_specific.hh" 392680SN/A#include "cpu/o3/cpu.hh" 402SN/A#include "enums/MemoryMode.hh" 411858SN/A#include "sim/core.hh" 423565Sgblack@eecs.umich.edu#include "sim/stat_control.hh" 431917SN/A 441070SN/A#if FULL_SYSTEM 451917SN/A#include "cpu/quiesce_event.hh" 462188SN/A#include "sim/system.hh" 471917SN/A#else 482290SN/A#include "sim/process.hh" 491070SN/A#endif 501917SN/A 512170SN/A#if USE_CHECKER 522SN/A#include "cpu/checker/cpu.hh" 53360SN/A#endif 542519SN/A 552420SN/Ausing namespace std; 562SN/Ausing namespace TheISA; 572SN/A 582SN/ABaseO3CPU::BaseO3CPU(Params *params) 592SN/A : BaseCPU(params), cpu_id(0) 602SN/A{ 611858SN/A} 622683Sktlim@umich.edu 633453Sgblack@eecs.umich.eduvoid 642683Sktlim@umich.eduBaseO3CPU::regStats() 653402Sktlim@umich.edu{ 662683Sktlim@umich.edu BaseCPU::regStats(); 672521SN/A} 682SN/A 692683Sktlim@umich.edutemplate <class Impl> 702190SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 712680SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 722290SN/A{ 732526SN/A} 741917SN/A 751917SN/Atemplate <class Impl> 761982SN/Avoid 771917SN/AFullO3CPU<Impl>::TickEvent::process() 782683Sktlim@umich.edu{ 792683Sktlim@umich.edu cpu->tick(); 801917SN/A} 811917SN/A 821917SN/Atemplate <class Impl> 831917SN/Aconst char * 841917SN/AFullO3CPU<Impl>::TickEvent::description() 851917SN/A{ 861917SN/A return "FullO3CPU tick event"; 871917SN/A} 882521SN/A 892341SN/Atemplate <class Impl> 903548Sgblack@eecs.umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 912341SN/A : Event(&mainEventQueue, CPU_Switch_Pri) 922341SN/A{ 932341SN/A} 942SN/A 952SN/Atemplate <class Impl> 962683Sktlim@umich.eduvoid 973402Sktlim@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 983402Sktlim@umich.edu FullO3CPU<Impl> *thread_cpu) 992683Sktlim@umich.edu{ 1002SN/A tid = thread_num; 1012526SN/A cpu = thread_cpu; 1022683Sktlim@umich.edu} 1032SN/A 1042190SN/Atemplate <class Impl> 1052862Sktlim@umich.eduvoid 1062862Sktlim@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1072864Sktlim@umich.edu{ 1082862Sktlim@umich.edu cpu->activateThread(tid); 1093402Sktlim@umich.edu} 1102862Sktlim@umich.edu 1113402Sktlim@umich.edutemplate <class Impl> 1122862Sktlim@umich.educonst char * 1132190SN/AFullO3CPU<Impl>::ActivateThreadEvent::description() 1142683Sktlim@umich.edu{ 1152862Sktlim@umich.edu return "FullO3CPU \"Activate Thread\" event"; 1162190SN/A} 1172190SN/A 1182683Sktlim@umich.edutemplate <class Impl> 1191070SN/AFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1203486Sktlim@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1213486Sktlim@umich.edu{ 1223486Sktlim@umich.edu} 1233486Sktlim@umich.edu 1242680SN/Atemplate <class Impl> 1251070SN/Avoid 1261070SN/AFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1271917SN/A FullO3CPU<Impl> *thread_cpu) 1282683Sktlim@umich.edu{ 129180SN/A tid = thread_num; 130180SN/A cpu = thread_cpu; 1311858SN/A remove = false; 1322235SN/A} 133180SN/A 1342235SN/Atemplate <class Impl> 135180SN/Avoid 136180SN/AFullO3CPU<Impl>::DeallocateContextEvent::process() 1372862Sktlim@umich.edu{ 1382862Sktlim@umich.edu cpu->deactivateThread(tid); 1392313SN/A if (remove) 1402313SN/A cpu->removeThread(tid); 1412680SN/A} 1422313SN/A 1432680SN/Atemplate <class Impl> 1442313SN/Aconst char * 1452313SN/AFullO3CPU<Impl>::DeallocateContextEvent::description() 1462680SN/A{ 1472313SN/A return "FullO3CPU \"Deallocate Context\" event"; 1482361SN/A} 1493548Sgblack@eecs.umich.edu 1502361SN/Atemplate <class Impl> 1512361SN/AFullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params) 1522361SN/A : BaseO3CPU(params), 1532235SN/A#if FULL_SYSTEM 154180SN/A itb(params->itb), 155180SN/A dtb(params->dtb), 156180SN/A#endif 1572680SN/A tickEvent(this), 158180SN/A removeInstsThisCycle(false), 159180SN/A fetch(o3_cpu, params), 1602SN/A decode(o3_cpu, params), 1612864Sktlim@umich.edu rename(o3_cpu, params), 1622864Sktlim@umich.edu iew(o3_cpu, params), 1632864Sktlim@umich.edu commit(o3_cpu, params), 1642864Sktlim@umich.edu 1652864Sktlim@umich.edu regFile(o3_cpu, params->numPhysIntRegs, 1662864Sktlim@umich.edu params->numPhysFloatRegs), 1672864Sktlim@umich.edu 1682864Sktlim@umich.edu freeList(params->numberOfThreads, 1692864Sktlim@umich.edu TheISA::NumIntRegs, params->numPhysIntRegs, 1703548Sgblack@eecs.umich.edu TheISA::NumFloatRegs, params->numPhysFloatRegs), 1712864Sktlim@umich.edu 1722864Sktlim@umich.edu rob(o3_cpu, 1732864Sktlim@umich.edu params->numROBEntries, params->squashWidth, 1742864Sktlim@umich.edu params->smtROBPolicy, params->smtROBThreshold, 1752864Sktlim@umich.edu params->numberOfThreads), 1762864Sktlim@umich.edu 1772864Sktlim@umich.edu scoreboard(params->numberOfThreads, 1782862Sktlim@umich.edu TheISA::NumIntRegs, params->numPhysIntRegs, 1792862Sktlim@umich.edu TheISA::NumFloatRegs, params->numPhysFloatRegs, 1802862Sktlim@umich.edu TheISA::NumMiscRegs * number_of_threads, 1812862Sktlim@umich.edu TheISA::ZeroReg), 1822862Sktlim@umich.edu 1832862Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1842862Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1852862Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1862862Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1872915Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1882862Sktlim@umich.edu activityRec(NumStages, 1892862Sktlim@umich.edu params->backComSize + params->forwardComSize, 1902862Sktlim@umich.edu params->activity), 1912683Sktlim@umich.edu 192217SN/A globalSeqNum(1), 1932862Sktlim@umich.edu#if FULL_SYSTEM 194223SN/A system(params->system), 195223SN/A physmem(system->physmem), 196217SN/A#endif // FULL_SYSTEM 197217SN/A drainCount(0), 198217SN/A deferRegistration(params->deferRegistration), 199217SN/A numThreads(number_of_threads) 2002683Sktlim@umich.edu{ 201217SN/A if (!deferRegistration) { 2022862Sktlim@umich.edu _status = Running; 203237SN/A } else { 204223SN/A _status = Idle; 205217SN/A } 206217SN/A 2072683Sktlim@umich.edu#if USE_CHECKER 2082683Sktlim@umich.edu if (params->checker) { 2092683Sktlim@umich.edu BaseCPU *temp_checker = params->checker; 2102683Sktlim@umich.edu checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2112683Sktlim@umich.edu#if FULL_SYSTEM 2122683Sktlim@umich.edu checker->setSystem(params->system); 2132683Sktlim@umich.edu#endif 2142683Sktlim@umich.edu } else { 215217SN/A checker = NULL; 216217SN/A } 2172683Sktlim@umich.edu#endif // USE_CHECKER 2182SN/A 2192680SN/A#if !FULL_SYSTEM 2202SN/A thread.resize(number_of_threads); 2212SN/A tids.resize(number_of_threads); 2222188SN/A#endif 2232188SN/A 2244400Srdreslin@umich.edu // The stages also need their CPU pointer setup. However this 2254400Srdreslin@umich.edu // must be done at the upper level CPU because they have pointers 2264400Srdreslin@umich.edu // to the upper level CPU, and not this FullO3CPU. 2274400Srdreslin@umich.edu 2282290SN/A // Set up Pointers to the activeThreads list for each stage 2292680SN/A fetch.setActiveThreads(&activeThreads); 2302290SN/A decode.setActiveThreads(&activeThreads); 2312290SN/A rename.setActiveThreads(&activeThreads); 2322683Sktlim@umich.edu iew.setActiveThreads(&activeThreads); 233393SN/A commit.setActiveThreads(&activeThreads); 234393SN/A 235393SN/A // Give each of the stages the time buffer they will use. 2362683Sktlim@umich.edu fetch.setTimeBuffer(&timeBuffer); 237393SN/A decode.setTimeBuffer(&timeBuffer); 2382680SN/A rename.setTimeBuffer(&timeBuffer); 239393SN/A iew.setTimeBuffer(&timeBuffer); 240393SN/A commit.setTimeBuffer(&timeBuffer); 2412188SN/A 2422188SN/A // Also setup each of the stages' queues. 2432188SN/A fetch.setFetchQueue(&fetchQueue); 2441858SN/A decode.setFetchQueue(&fetchQueue); 2452SN/A commit.setFetchQueue(&fetchQueue); 246393SN/A decode.setDecodeQueue(&decodeQueue); 2472680SN/A rename.setDecodeQueue(&decodeQueue); 2482SN/A rename.setRenameQueue(&renameQueue); 2492SN/A iew.setRenameQueue(&renameQueue); 2502SN/A iew.setIEWQueue(&iewQueue); 2512188SN/A commit.setIEWQueue(&iewQueue); 2522680SN/A commit.setRenameQueue(&renameQueue); 2532683Sktlim@umich.edu 2542SN/A commit.setIEWStage(&iew); 2552SN/A rename.setIEWStage(&iew); 2562SN/A rename.setCommitStage(&commit); 2572683Sktlim@umich.edu 258393SN/A#if !FULL_SYSTEM 2592680SN/A int active_threads = params->workload.size(); 260393SN/A 261393SN/A if (active_threads > Impl::MaxThreads) { 2622680SN/A panic("Workload Size too large. Increase the 'MaxThreads'" 2632683Sktlim@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 264393SN/A "edit your workload size."); 265393SN/A } 266393SN/A#else 2672683Sktlim@umich.edu int active_threads = 1; 268393SN/A#endif 2692680SN/A 270393SN/A //Make Sure That this a Valid Architeture 271393SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2722680SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2732683Sktlim@umich.edu 274393SN/A rename.setScoreboard(&scoreboard); 275393SN/A iew.setScoreboard(&scoreboard); 276393SN/A 277393SN/A // Setup the rename map for whichever stages need it. 2782683Sktlim@umich.edu PhysRegIndex lreg_idx = 0; 2792SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2802330SN/A 2812341SN/A for (int tid=0; tid < numThreads; tid++) { 2822341SN/A bool bindRegs = (tid <= active_threads - 1); 2832330SN/A 2842SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 285716SN/A params->numPhysIntRegs, 286716SN/A lreg_idx, //Index for Logical. Regs 2872683Sktlim@umich.edu 2882190SN/A TheISA::NumFloatRegs, 2892680SN/A params->numPhysFloatRegs, 2902190SN/A freg_idx, //Index for Float Regs 2912190SN/A 2922521SN/A TheISA::NumMiscRegs, 2932521SN/A 2942683Sktlim@umich.edu TheISA::ZeroReg, 2952521SN/A TheISA::ZeroReg, 2962680SN/A 2972521SN/A tid, 2982521SN/A false); 2993486Sktlim@umich.edu 3003675Sktlim@umich.edu renameMap[tid].init(TheISA::NumIntRegs, 3012521SN/A params->numPhysIntRegs, 3022521SN/A lreg_idx, //Index for Logical. Regs 3032521SN/A 3042521SN/A TheISA::NumFloatRegs, 3052683Sktlim@umich.edu params->numPhysFloatRegs, 3062521SN/A freg_idx, //Index for Float Regs 3072684Ssaidi@eecs.umich.edu 3084217Ssaidi@eecs.umich.edu TheISA::NumMiscRegs, 3092684Ssaidi@eecs.umich.edu 3102684Ssaidi@eecs.umich.edu TheISA::ZeroReg, 3112521SN/A TheISA::ZeroReg, 3122521SN/A 3132521SN/A tid, 3142521SN/A bindRegs); 315 316 activateThreadEvent[tid].init(tid, this); 317 deallocateContextEvent[tid].init(tid, this); 318 } 319 320 rename.setRenameMap(renameMap); 321 commit.setRenameMap(commitRenameMap); 322 323 // Give renameMap & rename stage access to the freeList; 324 for (int i=0; i < numThreads; i++) { 325 renameMap[i].setFreeList(&freeList); 326 } 327 rename.setFreeList(&freeList); 328 329 // Setup the ROB for whichever stages need it. 330 commit.setROB(&rob); 331 332 lastRunningCycle = curTick; 333 334 lastActivatedCycle = -1; 335 336 // Give renameMap & rename stage access to the freeList; 337 //for (int i=0; i < numThreads; i++) { 338 //globalSeqNum[i] = 1; 339 //} 340 341 contextSwitch = false; 342} 343 344template <class Impl> 345FullO3CPU<Impl>::~FullO3CPU() 346{ 347} 348 349template <class Impl> 350void 351FullO3CPU<Impl>::fullCPURegStats() 352{ 353 BaseO3CPU::regStats(); 354 355 // Register any of the O3CPU's stats here. 356 timesIdled 357 .name(name() + ".timesIdled") 358 .desc("Number of times that the entire CPU went into an idle state and" 359 " unscheduled itself") 360 .prereq(timesIdled); 361 362 idleCycles 363 .name(name() + ".idleCycles") 364 .desc("Total number of cycles that the CPU has spent unscheduled due " 365 "to idling") 366 .prereq(idleCycles); 367 368 // Number of Instructions simulated 369 // -------------------------------- 370 // Should probably be in Base CPU but need templated 371 // MaxThreads so put in here instead 372 committedInsts 373 .init(numThreads) 374 .name(name() + ".committedInsts") 375 .desc("Number of Instructions Simulated"); 376 377 totalCommittedInsts 378 .name(name() + ".committedInsts_total") 379 .desc("Number of Instructions Simulated"); 380 381 cpi 382 .name(name() + ".cpi") 383 .desc("CPI: Cycles Per Instruction") 384 .precision(6); 385 cpi = numCycles / committedInsts; 386 387 totalCpi 388 .name(name() + ".cpi_total") 389 .desc("CPI: Total CPI of All Threads") 390 .precision(6); 391 totalCpi = numCycles / totalCommittedInsts; 392 393 ipc 394 .name(name() + ".ipc") 395 .desc("IPC: Instructions Per Cycle") 396 .precision(6); 397 ipc = committedInsts / numCycles; 398 399 totalIpc 400 .name(name() + ".ipc_total") 401 .desc("IPC: Total IPC of All Threads") 402 .precision(6); 403 totalIpc = totalCommittedInsts / numCycles; 404 405} 406 407template <class Impl> 408Port * 409FullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 410{ 411 if (if_name == "dcache_port") 412 return iew.getDcachePort(); 413 else if (if_name == "icache_port") 414 return fetch.getIcachePort(); 415 else 416 panic("No Such Port\n"); 417} 418 419template <class Impl> 420void 421FullO3CPU<Impl>::tick() 422{ 423 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 424 425 ++numCycles; 426 427// activity = false; 428 429 //Tick each of the stages 430 fetch.tick(); 431 432 decode.tick(); 433 434 rename.tick(); 435 436 iew.tick(); 437 438 commit.tick(); 439 440#if !FULL_SYSTEM 441 doContextSwitch(); 442#endif 443 444 // Now advance the time buffers 445 timeBuffer.advance(); 446 447 fetchQueue.advance(); 448 decodeQueue.advance(); 449 renameQueue.advance(); 450 iewQueue.advance(); 451 452 activityRec.advance(); 453 454 if (removeInstsThisCycle) { 455 cleanUpRemovedInsts(); 456 } 457 458 if (!tickEvent.scheduled()) { 459 if (_status == SwitchedOut || 460 getState() == SimObject::Drained) { 461 DPRINTF(O3CPU, "Switched out!\n"); 462 // increment stat 463 lastRunningCycle = curTick; 464 } else if (!activityRec.active() || _status == Idle) { 465 DPRINTF(O3CPU, "Idle!\n"); 466 lastRunningCycle = curTick; 467 timesIdled++; 468 } else { 469 tickEvent.schedule(nextCycle(curTick + cycles(1))); 470 DPRINTF(O3CPU, "Scheduling next tick!\n"); 471 } 472 } 473 474#if !FULL_SYSTEM 475 updateThreadPriority(); 476#endif 477 478} 479 480template <class Impl> 481void 482FullO3CPU<Impl>::init() 483{ 484 if (!deferRegistration) { 485 registerThreadContexts(); 486 } 487 488 // Set inSyscall so that the CPU doesn't squash when initially 489 // setting up registers. 490 for (int i = 0; i < number_of_threads; ++i) 491 thread[i]->inSyscall = true; 492 493 for (int tid=0; tid < number_of_threads; tid++) { 494#if FULL_SYSTEM 495 ThreadContext *src_tc = threadContexts[tid]; 496#else 497 ThreadContext *src_tc = thread[tid]->getTC(); 498#endif 499 // Threads start in the Suspended State 500 if (src_tc->status() != ThreadContext::Suspended) { 501 continue; 502 } 503 504#if FULL_SYSTEM 505 TheISA::initCPU(src_tc, src_tc->readCpuId()); 506#endif 507 } 508 509 // Clear inSyscall. 510 for (int i = 0; i < number_of_threads; ++i) 511 thread[i]->inSyscall = false; 512 513 // Initialize stages. 514 fetch.initStage(); 515 iew.initStage(); 516 rename.initStage(); 517 commit.initStage(); 518 519 commit.setThreads(thread); 520} 521 522template <class Impl> 523void 524FullO3CPU<Impl>::activateThread(unsigned tid) 525{ 526 list<unsigned>::iterator isActive = find( 527 activeThreads.begin(), activeThreads.end(), tid); 528 529 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 530 531 if (isActive == activeThreads.end()) { 532 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 533 tid); 534 535 activeThreads.push_back(tid); 536 } 537} 538 539template <class Impl> 540void 541FullO3CPU<Impl>::deactivateThread(unsigned tid) 542{ 543 //Remove From Active List, if Active 544 list<unsigned>::iterator thread_it = 545 find(activeThreads.begin(), activeThreads.end(), tid); 546 547 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 548 549 if (thread_it != activeThreads.end()) { 550 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 551 tid); 552 activeThreads.erase(thread_it); 553 } 554} 555 556template <class Impl> 557void 558FullO3CPU<Impl>::activateContext(int tid, int delay) 559{ 560 // Needs to set each stage to running as well. 561 if (delay){ 562 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 563 "on cycle %d\n", tid, curTick + cycles(delay)); 564 scheduleActivateThreadEvent(tid, delay); 565 } else { 566 activateThread(tid); 567 } 568 569 if (lastActivatedCycle < curTick) { 570 scheduleTickEvent(delay); 571 572 // Be sure to signal that there's some activity so the CPU doesn't 573 // deschedule itself. 574 activityRec.activity(); 575 fetch.wakeFromQuiesce(); 576 577 lastActivatedCycle = curTick; 578 579 _status = Running; 580 } 581} 582 583template <class Impl> 584bool 585FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay) 586{ 587 // Schedule removal of thread data from CPU 588 if (delay){ 589 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 590 "on cycle %d\n", tid, curTick + cycles(delay)); 591 scheduleDeallocateContextEvent(tid, remove, delay); 592 return false; 593 } else { 594 deactivateThread(tid); 595 if (remove) 596 removeThread(tid); 597 return true; 598 } 599} 600 601template <class Impl> 602void 603FullO3CPU<Impl>::suspendContext(int tid) 604{ 605 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 606 bool deallocated = deallocateContext(tid, false, 1); 607 // If this was the last thread then unschedule the tick event. 608 if (activeThreads.size() == 1 && !deallocated || 609 activeThreads.size() == 0) 610 unscheduleTickEvent(); 611 _status = Idle; 612} 613 614template <class Impl> 615void 616FullO3CPU<Impl>::haltContext(int tid) 617{ 618 //For now, this is the same as deallocate 619 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 620 deallocateContext(tid, true, 1); 621} 622 623template <class Impl> 624void 625FullO3CPU<Impl>::insertThread(unsigned tid) 626{ 627 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 628 // Will change now that the PC and thread state is internal to the CPU 629 // and not in the ThreadContext. 630#if FULL_SYSTEM 631 ThreadContext *src_tc = system->threadContexts[tid]; 632#else 633 ThreadContext *src_tc = tcBase(tid); 634#endif 635 636 //Bind Int Regs to Rename Map 637 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 638 PhysRegIndex phys_reg = freeList.getIntReg(); 639 640 renameMap[tid].setEntry(ireg,phys_reg); 641 scoreboard.setReg(phys_reg); 642 } 643 644 //Bind Float Regs to Rename Map 645 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 646 PhysRegIndex phys_reg = freeList.getFloatReg(); 647 648 renameMap[tid].setEntry(freg,phys_reg); 649 scoreboard.setReg(phys_reg); 650 } 651 652 //Copy Thread Data Into RegFile 653 //this->copyFromTC(tid); 654 655 //Set PC/NPC/NNPC 656 setPC(src_tc->readPC(), tid); 657 setNextPC(src_tc->readNextPC(), tid); 658 setNextNPC(src_tc->readNextNPC(), tid); 659 660 src_tc->setStatus(ThreadContext::Active); 661 662 activateContext(tid,1); 663 664 //Reset ROB/IQ/LSQ Entries 665 commit.rob->resetEntries(); 666 iew.resetEntries(); 667} 668 669template <class Impl> 670void 671FullO3CPU<Impl>::removeThread(unsigned tid) 672{ 673 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 674 675 // Copy Thread Data From RegFile 676 // If thread is suspended, it might be re-allocated 677 //this->copyToTC(tid); 678 679 // Unbind Int Regs from Rename Map 680 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 681 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 682 683 scoreboard.unsetReg(phys_reg); 684 freeList.addReg(phys_reg); 685 } 686 687 // Unbind Float Regs from Rename Map 688 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 689 PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 690 691 scoreboard.unsetReg(phys_reg); 692 freeList.addReg(phys_reg); 693 } 694 695 // Squash Throughout Pipeline 696 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 697 fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid); 698 decode.squash(tid); 699 rename.squash(squash_seq_num, tid); 700 iew.squash(tid); 701 commit.rob->squash(squash_seq_num, tid); 702 703 assert(iew.ldstQueue.getCount(tid) == 0); 704 705 // Reset ROB/IQ/LSQ Entries 706 707 // Commented out for now. This should be possible to do by 708 // telling all the pipeline stages to drain first, and then 709 // checking until the drain completes. Once the pipeline is 710 // drained, call resetEntries(). - 10-09-06 ktlim 711/* 712 if (activeThreads.size() >= 1) { 713 commit.rob->resetEntries(); 714 iew.resetEntries(); 715 } 716*/ 717} 718 719 720template <class Impl> 721void 722FullO3CPU<Impl>::activateWhenReady(int tid) 723{ 724 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 725 "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 726 tid); 727 728 bool ready = true; 729 730 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 731 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 732 "Phys. Int. Regs.\n", 733 tid); 734 ready = false; 735 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 736 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 737 "Phys. Float. Regs.\n", 738 tid); 739 ready = false; 740 } else if (commit.rob->numFreeEntries() >= 741 commit.rob->entryAmount(activeThreads.size() + 1)) { 742 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 743 "ROB entries.\n", 744 tid); 745 ready = false; 746 } else if (iew.instQueue.numFreeEntries() >= 747 iew.instQueue.entryAmount(activeThreads.size() + 1)) { 748 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 749 "IQ entries.\n", 750 tid); 751 ready = false; 752 } else if (iew.ldstQueue.numFreeEntries() >= 753 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 754 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 755 "LSQ entries.\n", 756 tid); 757 ready = false; 758 } 759 760 if (ready) { 761 insertThread(tid); 762 763 contextSwitch = false; 764 765 cpuWaitList.remove(tid); 766 } else { 767 suspendContext(tid); 768 769 //blocks fetch 770 contextSwitch = true; 771 772 //@todo: dont always add to waitlist 773 //do waitlist 774 cpuWaitList.push_back(tid); 775 } 776} 777 778#if FULL_SYSTEM 779template <class Impl> 780void 781FullO3CPU<Impl>::updateMemPorts() 782{ 783 // Update all ThreadContext's memory ports (Functional/Virtual 784 // Ports) 785 for (int i = 0; i < thread.size(); ++i) 786 thread[i]->connectMemPorts(); 787} 788#endif 789 790template <class Impl> 791void 792FullO3CPU<Impl>::serialize(std::ostream &os) 793{ 794 SimObject::State so_state = SimObject::getState(); 795 SERIALIZE_ENUM(so_state); 796 BaseCPU::serialize(os); 797 nameOut(os, csprintf("%s.tickEvent", name())); 798 tickEvent.serialize(os); 799 800 // Use SimpleThread's ability to checkpoint to make it easier to 801 // write out the registers. Also make this static so it doesn't 802 // get instantiated multiple times (causes a panic in statistics). 803 static SimpleThread temp; 804 805 for (int i = 0; i < thread.size(); i++) { 806 nameOut(os, csprintf("%s.xc.%i", name(), i)); 807 temp.copyTC(thread[i]->getTC()); 808 temp.serialize(os); 809 } 810} 811 812template <class Impl> 813void 814FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 815{ 816 SimObject::State so_state; 817 UNSERIALIZE_ENUM(so_state); 818 BaseCPU::unserialize(cp, section); 819 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 820 821 // Use SimpleThread's ability to checkpoint to make it easier to 822 // read in the registers. Also make this static so it doesn't 823 // get instantiated multiple times (causes a panic in statistics). 824 static SimpleThread temp; 825 826 for (int i = 0; i < thread.size(); i++) { 827 temp.copyTC(thread[i]->getTC()); 828 temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 829 thread[i]->getTC()->copyArchRegs(temp.getTC()); 830 } 831} 832 833template <class Impl> 834unsigned int 835FullO3CPU<Impl>::drain(Event *drain_event) 836{ 837 DPRINTF(O3CPU, "Switching out\n"); 838 839 // If the CPU isn't doing anything, then return immediately. 840 if (_status == Idle || _status == SwitchedOut) { 841 return 0; 842 } 843 844 drainCount = 0; 845 fetch.drain(); 846 decode.drain(); 847 rename.drain(); 848 iew.drain(); 849 commit.drain(); 850 851 // Wake the CPU and record activity so everything can drain out if 852 // the CPU was not able to immediately drain. 853 if (getState() != SimObject::Drained) { 854 // A bit of a hack...set the drainEvent after all the drain() 855 // calls have been made, that way if all of the stages drain 856 // immediately, the signalDrained() function knows not to call 857 // process on the drain event. 858 drainEvent = drain_event; 859 860 wakeCPU(); 861 activityRec.activity(); 862 863 return 1; 864 } else { 865 return 0; 866 } 867} 868 869template <class Impl> 870void 871FullO3CPU<Impl>::resume() 872{ 873 fetch.resume(); 874 decode.resume(); 875 rename.resume(); 876 iew.resume(); 877 commit.resume(); 878 879 changeState(SimObject::Running); 880 881 if (_status == SwitchedOut || _status == Idle) 882 return; 883 884#if FULL_SYSTEM 885 assert(system->getMemoryMode() == Enums::timing); 886#endif 887 888 if (!tickEvent.scheduled()) 889 tickEvent.schedule(nextCycle()); 890 _status = Running; 891} 892 893template <class Impl> 894void 895FullO3CPU<Impl>::signalDrained() 896{ 897 if (++drainCount == NumStages) { 898 if (tickEvent.scheduled()) 899 tickEvent.squash(); 900 901 changeState(SimObject::Drained); 902 903 BaseCPU::switchOut(); 904 905 if (drainEvent) { 906 drainEvent->process(); 907 drainEvent = NULL; 908 } 909 } 910 assert(drainCount <= 5); 911} 912 913template <class Impl> 914void 915FullO3CPU<Impl>::switchOut() 916{ 917 fetch.switchOut(); 918 rename.switchOut(); 919 iew.switchOut(); 920 commit.switchOut(); 921 instList.clear(); 922 while (!removeList.empty()) { 923 removeList.pop(); 924 } 925 926 _status = SwitchedOut; 927#if USE_CHECKER 928 if (checker) 929 checker->switchOut(); 930#endif 931 if (tickEvent.scheduled()) 932 tickEvent.squash(); 933} 934 935template <class Impl> 936void 937FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 938{ 939 // Flush out any old data from the time buffers. 940 for (int i = 0; i < timeBuffer.getSize(); ++i) { 941 timeBuffer.advance(); 942 fetchQueue.advance(); 943 decodeQueue.advance(); 944 renameQueue.advance(); 945 iewQueue.advance(); 946 } 947 948 activityRec.reset(); 949 950 BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 951 952 fetch.takeOverFrom(); 953 decode.takeOverFrom(); 954 rename.takeOverFrom(); 955 iew.takeOverFrom(); 956 commit.takeOverFrom(); 957 958 assert(!tickEvent.scheduled()); 959 960 // @todo: Figure out how to properly select the tid to put onto 961 // the active threads list. 962 int tid = 0; 963 964 list<unsigned>::iterator isActive = find( 965 activeThreads.begin(), activeThreads.end(), tid); 966 967 if (isActive == activeThreads.end()) { 968 //May Need to Re-code this if the delay variable is the delay 969 //needed for thread to activate 970 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 971 tid); 972 973 activeThreads.push_back(tid); 974 } 975 976 // Set all statuses to active, schedule the CPU's tick event. 977 // @todo: Fix up statuses so this is handled properly 978 for (int i = 0; i < threadContexts.size(); ++i) { 979 ThreadContext *tc = threadContexts[i]; 980 if (tc->status() == ThreadContext::Active && _status != Running) { 981 _status = Running; 982 tickEvent.schedule(nextCycle()); 983 } 984 } 985 if (!tickEvent.scheduled()) 986 tickEvent.schedule(nextCycle()); 987} 988 989template <class Impl> 990uint64_t 991FullO3CPU<Impl>::readIntReg(int reg_idx) 992{ 993 return regFile.readIntReg(reg_idx); 994} 995 996template <class Impl> 997FloatReg 998FullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 999{ 1000 return regFile.readFloatReg(reg_idx, width); 1001} 1002 1003template <class Impl> 1004FloatReg 1005FullO3CPU<Impl>::readFloatReg(int reg_idx) 1006{ 1007 return regFile.readFloatReg(reg_idx); 1008} 1009 1010template <class Impl> 1011FloatRegBits 1012FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 1013{ 1014 return regFile.readFloatRegBits(reg_idx, width); 1015} 1016 1017template <class Impl> 1018FloatRegBits 1019FullO3CPU<Impl>::readFloatRegBits(int reg_idx) 1020{ 1021 return regFile.readFloatRegBits(reg_idx); 1022} 1023 1024template <class Impl> 1025void 1026FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 1027{ 1028 regFile.setIntReg(reg_idx, val); 1029} 1030 1031template <class Impl> 1032void 1033FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 1034{ 1035 regFile.setFloatReg(reg_idx, val, width); 1036} 1037 1038template <class Impl> 1039void 1040FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 1041{ 1042 regFile.setFloatReg(reg_idx, val); 1043} 1044 1045template <class Impl> 1046void 1047FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 1048{ 1049 regFile.setFloatRegBits(reg_idx, val, width); 1050} 1051 1052template <class Impl> 1053void 1054FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 1055{ 1056 regFile.setFloatRegBits(reg_idx, val); 1057} 1058 1059template <class Impl> 1060uint64_t 1061FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 1062{ 1063 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 1064 1065 return regFile.readIntReg(phys_reg); 1066} 1067 1068template <class Impl> 1069float 1070FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 1071{ 1072 int idx = reg_idx + TheISA::FP_Base_DepTag; 1073 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1074 1075 return regFile.readFloatReg(phys_reg); 1076} 1077 1078template <class Impl> 1079double 1080FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 1081{ 1082 int idx = reg_idx + TheISA::FP_Base_DepTag; 1083 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1084 1085 return regFile.readFloatReg(phys_reg, 64); 1086} 1087 1088template <class Impl> 1089uint64_t 1090FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 1091{ 1092 int idx = reg_idx + TheISA::FP_Base_DepTag; 1093 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1094 1095 return regFile.readFloatRegBits(phys_reg); 1096} 1097 1098template <class Impl> 1099void 1100FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 1101{ 1102 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 1103 1104 regFile.setIntReg(phys_reg, val); 1105} 1106 1107template <class Impl> 1108void 1109FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 1110{ 1111 int idx = reg_idx + TheISA::FP_Base_DepTag; 1112 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1113 1114 regFile.setFloatReg(phys_reg, val); 1115} 1116 1117template <class Impl> 1118void 1119FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 1120{ 1121 int idx = reg_idx + TheISA::FP_Base_DepTag; 1122 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1123 1124 regFile.setFloatReg(phys_reg, val, 64); 1125} 1126 1127template <class Impl> 1128void 1129FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 1130{ 1131 int idx = reg_idx + TheISA::FP_Base_DepTag; 1132 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1133 1134 regFile.setFloatRegBits(phys_reg, val); 1135} 1136 1137template <class Impl> 1138uint64_t 1139FullO3CPU<Impl>::readPC(unsigned tid) 1140{ 1141 return commit.readPC(tid); 1142} 1143 1144template <class Impl> 1145void 1146FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 1147{ 1148 commit.setPC(new_PC, tid); 1149} 1150 1151template <class Impl> 1152uint64_t 1153FullO3CPU<Impl>::readMicroPC(unsigned tid) 1154{ 1155 return commit.readMicroPC(tid); 1156} 1157 1158template <class Impl> 1159void 1160FullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid) 1161{ 1162 commit.setMicroPC(new_PC, tid); 1163} 1164 1165template <class Impl> 1166uint64_t 1167FullO3CPU<Impl>::readNextPC(unsigned tid) 1168{ 1169 return commit.readNextPC(tid); 1170} 1171 1172template <class Impl> 1173void 1174FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 1175{ 1176 commit.setNextPC(val, tid); 1177} 1178 1179template <class Impl> 1180uint64_t 1181FullO3CPU<Impl>::readNextNPC(unsigned tid) 1182{ 1183 return commit.readNextNPC(tid); 1184} 1185 1186template <class Impl> 1187void 1188FullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) 1189{ 1190 commit.setNextNPC(val, tid); 1191} 1192 1193template <class Impl> 1194uint64_t 1195FullO3CPU<Impl>::readNextMicroPC(unsigned tid) 1196{ 1197 return commit.readNextMicroPC(tid); 1198} 1199 1200template <class Impl> 1201void 1202FullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid) 1203{ 1204 commit.setNextMicroPC(new_PC, tid); 1205} 1206 1207template <class Impl> 1208typename FullO3CPU<Impl>::ListIt 1209FullO3CPU<Impl>::addInst(DynInstPtr &inst) 1210{ 1211 instList.push_back(inst); 1212 1213 return --(instList.end()); 1214} 1215 1216template <class Impl> 1217void 1218FullO3CPU<Impl>::instDone(unsigned tid) 1219{ 1220 // Keep an instruction count. 1221 thread[tid]->numInst++; 1222 thread[tid]->numInsts++; 1223 committedInsts[tid]++; 1224 totalCommittedInsts++; 1225 1226 // Check for instruction-count-based events. 1227 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 1228} 1229 1230template <class Impl> 1231void 1232FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 1233{ 1234 removeInstsThisCycle = true; 1235 1236 removeList.push(inst->getInstListIt()); 1237} 1238 1239template <class Impl> 1240void 1241FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 1242{ 1243 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 1244 "[sn:%lli]\n", 1245 inst->threadNumber, inst->readPC(), inst->seqNum); 1246 1247 removeInstsThisCycle = true; 1248 1249 // Remove the front instruction. 1250 removeList.push(inst->getInstListIt()); 1251} 1252 1253template <class Impl> 1254void 1255FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 1256{ 1257 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 1258 " list.\n", tid); 1259 1260 ListIt end_it; 1261 1262 bool rob_empty = false; 1263 1264 if (instList.empty()) { 1265 return; 1266 } else if (rob.isEmpty(/*tid*/)) { 1267 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 1268 end_it = instList.begin(); 1269 rob_empty = true; 1270 } else { 1271 end_it = (rob.readTailInst(tid))->getInstListIt(); 1272 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 1273 } 1274 1275 removeInstsThisCycle = true; 1276 1277 ListIt inst_it = instList.end(); 1278 1279 inst_it--; 1280 1281 // Walk through the instruction list, removing any instructions 1282 // that were inserted after the given instruction iterator, end_it. 1283 while (inst_it != end_it) { 1284 assert(!instList.empty()); 1285 1286 squashInstIt(inst_it, tid); 1287 1288 inst_it--; 1289 } 1290 1291 // If the ROB was empty, then we actually need to remove the first 1292 // instruction as well. 1293 if (rob_empty) { 1294 squashInstIt(inst_it, tid); 1295 } 1296} 1297 1298template <class Impl> 1299void 1300FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 1301 unsigned tid) 1302{ 1303 assert(!instList.empty()); 1304 1305 removeInstsThisCycle = true; 1306 1307 ListIt inst_iter = instList.end(); 1308 1309 inst_iter--; 1310 1311 DPRINTF(O3CPU, "Deleting instructions from instruction " 1312 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 1313 tid, seq_num, (*inst_iter)->seqNum); 1314 1315 while ((*inst_iter)->seqNum > seq_num) { 1316 1317 bool break_loop = (inst_iter == instList.begin()); 1318 1319 squashInstIt(inst_iter, tid); 1320 1321 inst_iter--; 1322 1323 if (break_loop) 1324 break; 1325 } 1326} 1327 1328template <class Impl> 1329inline void 1330FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 1331{ 1332 if ((*instIt)->threadNumber == tid) { 1333 DPRINTF(O3CPU, "Squashing instruction, " 1334 "[tid:%i] [sn:%lli] PC %#x\n", 1335 (*instIt)->threadNumber, 1336 (*instIt)->seqNum, 1337 (*instIt)->readPC()); 1338 1339 // Mark it as squashed. 1340 (*instIt)->setSquashed(); 1341 1342 // @todo: Formulate a consistent method for deleting 1343 // instructions from the instruction list 1344 // Remove the instruction from the list. 1345 removeList.push(instIt); 1346 } 1347} 1348 1349template <class Impl> 1350void 1351FullO3CPU<Impl>::cleanUpRemovedInsts() 1352{ 1353 while (!removeList.empty()) { 1354 DPRINTF(O3CPU, "Removing instruction, " 1355 "[tid:%i] [sn:%lli] PC %#x\n", 1356 (*removeList.front())->threadNumber, 1357 (*removeList.front())->seqNum, 1358 (*removeList.front())->readPC()); 1359 1360 instList.erase(removeList.front()); 1361 1362 removeList.pop(); 1363 } 1364 1365 removeInstsThisCycle = false; 1366} 1367/* 1368template <class Impl> 1369void 1370FullO3CPU<Impl>::removeAllInsts() 1371{ 1372 instList.clear(); 1373} 1374*/ 1375template <class Impl> 1376void 1377FullO3CPU<Impl>::dumpInsts() 1378{ 1379 int num = 0; 1380 1381 ListIt inst_list_it = instList.begin(); 1382 1383 cprintf("Dumping Instruction List\n"); 1384 1385 while (inst_list_it != instList.end()) { 1386 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 1387 "Squashed:%i\n\n", 1388 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 1389 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 1390 (*inst_list_it)->isSquashed()); 1391 inst_list_it++; 1392 ++num; 1393 } 1394} 1395/* 1396template <class Impl> 1397void 1398FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 1399{ 1400 iew.wakeDependents(inst); 1401} 1402*/ 1403template <class Impl> 1404void 1405FullO3CPU<Impl>::wakeCPU() 1406{ 1407 if (activityRec.active() || tickEvent.scheduled()) { 1408 DPRINTF(Activity, "CPU already running.\n"); 1409 return; 1410 } 1411 1412 DPRINTF(Activity, "Waking up CPU\n"); 1413 1414 idleCycles += (curTick - 1) - lastRunningCycle; 1415 1416 tickEvent.schedule(nextCycle()); 1417} 1418 1419template <class Impl> 1420int 1421FullO3CPU<Impl>::getFreeTid() 1422{ 1423 for (int i=0; i < numThreads; i++) { 1424 if (!tids[i]) { 1425 tids[i] = true; 1426 return i; 1427 } 1428 } 1429 1430 return -1; 1431} 1432 1433template <class Impl> 1434void 1435FullO3CPU<Impl>::doContextSwitch() 1436{ 1437 if (contextSwitch) { 1438 1439 //ADD CODE TO DEACTIVE THREAD HERE (???) 1440 1441 for (int tid=0; tid < cpuWaitList.size(); tid++) { 1442 activateWhenReady(tid); 1443 } 1444 1445 if (cpuWaitList.size() == 0) 1446 contextSwitch = true; 1447 } 1448} 1449 1450template <class Impl> 1451void 1452FullO3CPU<Impl>::updateThreadPriority() 1453{ 1454 if (activeThreads.size() > 1) 1455 { 1456 //DEFAULT TO ROUND ROBIN SCHEME 1457 //e.g. Move highest priority to end of thread list 1458 list<unsigned>::iterator list_begin = activeThreads.begin(); 1459 list<unsigned>::iterator list_end = activeThreads.end(); 1460 1461 unsigned high_thread = *list_begin; 1462 1463 activeThreads.erase(list_begin); 1464 1465 activeThreads.push_back(high_thread); 1466 } 1467} 1468 1469// Forward declaration of FullO3CPU. 1470template class FullO3CPU<O3CPUImpl>; 1471