cpu.cc revision 3781:b00795985f07 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#if FULL_SYSTEM
36#include "cpu/quiesce_event.hh"
37#include "sim/system.hh"
38#else
39#include "sim/process.hh"
40#endif
41
42#include "cpu/activity.hh"
43#include "cpu/simple_thread.hh"
44#include "cpu/thread_context.hh"
45#include "cpu/o3/isa_specific.hh"
46#include "cpu/o3/cpu.hh"
47
48#include "sim/root.hh"
49#include "sim/stat_control.hh"
50
51#if USE_CHECKER
52#include "cpu/checker/cpu.hh"
53#endif
54
55using namespace std;
56using namespace TheISA;
57
58BaseO3CPU::BaseO3CPU(Params *params)
59    : BaseCPU(params), cpu_id(0)
60{
61}
62
63void
64BaseO3CPU::regStats()
65{
66    BaseCPU::regStats();
67}
68
69template <class Impl>
70FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
71    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
72{
73}
74
75template <class Impl>
76void
77FullO3CPU<Impl>::TickEvent::process()
78{
79    cpu->tick();
80}
81
82template <class Impl>
83const char *
84FullO3CPU<Impl>::TickEvent::description()
85{
86    return "FullO3CPU tick event";
87}
88
89template <class Impl>
90FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
91    : Event(&mainEventQueue, CPU_Switch_Pri)
92{
93}
94
95template <class Impl>
96void
97FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
98                                           FullO3CPU<Impl> *thread_cpu)
99{
100    tid = thread_num;
101    cpu = thread_cpu;
102}
103
104template <class Impl>
105void
106FullO3CPU<Impl>::ActivateThreadEvent::process()
107{
108    cpu->activateThread(tid);
109}
110
111template <class Impl>
112const char *
113FullO3CPU<Impl>::ActivateThreadEvent::description()
114{
115    return "FullO3CPU \"Activate Thread\" event";
116}
117
118template <class Impl>
119FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
120    : Event(&mainEventQueue, CPU_Tick_Pri)
121{
122}
123
124template <class Impl>
125void
126FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
127                                           FullO3CPU<Impl> *thread_cpu)
128{
129    tid = thread_num;
130    cpu = thread_cpu;
131}
132
133template <class Impl>
134void
135FullO3CPU<Impl>::DeallocateContextEvent::process()
136{
137    cpu->deactivateThread(tid);
138    if (remove)
139        cpu->removeThread(tid);
140}
141
142template <class Impl>
143const char *
144FullO3CPU<Impl>::DeallocateContextEvent::description()
145{
146    return "FullO3CPU \"Deallocate Context\" event";
147}
148
149template <class Impl>
150FullO3CPU<Impl>::FullO3CPU(Params *params)
151    : BaseO3CPU(params),
152#if FULL_SYSTEM
153      itb(params->itb),
154      dtb(params->dtb),
155#endif
156      tickEvent(this),
157      removeInstsThisCycle(false),
158      fetch(params),
159      decode(params),
160      rename(params),
161      iew(params),
162      commit(params),
163
164      regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
165
166      freeList(params->numberOfThreads,
167               TheISA::NumIntRegs, params->numPhysIntRegs,
168               TheISA::NumFloatRegs, params->numPhysFloatRegs),
169
170      rob(params->numROBEntries, params->squashWidth,
171          params->smtROBPolicy, params->smtROBThreshold,
172          params->numberOfThreads),
173
174      scoreboard(params->numberOfThreads,
175                 TheISA::NumIntRegs, params->numPhysIntRegs,
176                 TheISA::NumFloatRegs, params->numPhysFloatRegs,
177                 TheISA::NumMiscRegs * number_of_threads,
178                 TheISA::ZeroReg),
179
180      timeBuffer(params->backComSize, params->forwardComSize),
181      fetchQueue(params->backComSize, params->forwardComSize),
182      decodeQueue(params->backComSize, params->forwardComSize),
183      renameQueue(params->backComSize, params->forwardComSize),
184      iewQueue(params->backComSize, params->forwardComSize),
185      activityRec(NumStages,
186                  params->backComSize + params->forwardComSize,
187                  params->activity),
188
189      globalSeqNum(1),
190#if FULL_SYSTEM
191      system(params->system),
192      physmem(system->physmem),
193#endif // FULL_SYSTEM
194      drainCount(0),
195      deferRegistration(params->deferRegistration),
196      numThreads(number_of_threads)
197{
198    if (!deferRegistration) {
199        _status = Running;
200    } else {
201        _status = Idle;
202    }
203
204    checker = NULL;
205
206    if (params->checker) {
207#if USE_CHECKER
208        BaseCPU *temp_checker = params->checker;
209        checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
210#if FULL_SYSTEM
211        checker->setSystem(params->system);
212#endif
213#else
214        panic("Checker enabled but not compiled in!");
215#endif // USE_CHECKER
216    }
217
218#if !FULL_SYSTEM
219    thread.resize(number_of_threads);
220    tids.resize(number_of_threads);
221#endif
222
223    // The stages also need their CPU pointer setup.  However this
224    // must be done at the upper level CPU because they have pointers
225    // to the upper level CPU, and not this FullO3CPU.
226
227    // Set up Pointers to the activeThreads list for each stage
228    fetch.setActiveThreads(&activeThreads);
229    decode.setActiveThreads(&activeThreads);
230    rename.setActiveThreads(&activeThreads);
231    iew.setActiveThreads(&activeThreads);
232    commit.setActiveThreads(&activeThreads);
233
234    // Give each of the stages the time buffer they will use.
235    fetch.setTimeBuffer(&timeBuffer);
236    decode.setTimeBuffer(&timeBuffer);
237    rename.setTimeBuffer(&timeBuffer);
238    iew.setTimeBuffer(&timeBuffer);
239    commit.setTimeBuffer(&timeBuffer);
240
241    // Also setup each of the stages' queues.
242    fetch.setFetchQueue(&fetchQueue);
243    decode.setFetchQueue(&fetchQueue);
244    commit.setFetchQueue(&fetchQueue);
245    decode.setDecodeQueue(&decodeQueue);
246    rename.setDecodeQueue(&decodeQueue);
247    rename.setRenameQueue(&renameQueue);
248    iew.setRenameQueue(&renameQueue);
249    iew.setIEWQueue(&iewQueue);
250    commit.setIEWQueue(&iewQueue);
251    commit.setRenameQueue(&renameQueue);
252
253    commit.setIEWStage(&iew);
254    rename.setIEWStage(&iew);
255    rename.setCommitStage(&commit);
256
257#if !FULL_SYSTEM
258    int active_threads = params->workload.size();
259
260    if (active_threads > Impl::MaxThreads) {
261        panic("Workload Size too large. Increase the 'MaxThreads'"
262              "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
263              "edit your workload size.");
264    }
265#else
266    int active_threads = 1;
267#endif
268
269    //Make Sure That this a Valid Architeture
270    assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
271    assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
272
273    rename.setScoreboard(&scoreboard);
274    iew.setScoreboard(&scoreboard);
275
276    // Setup the rename map for whichever stages need it.
277    PhysRegIndex lreg_idx = 0;
278    PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
279
280    for (int tid=0; tid < numThreads; tid++) {
281        bool bindRegs = (tid <= active_threads - 1);
282
283        commitRenameMap[tid].init(TheISA::NumIntRegs,
284                                  params->numPhysIntRegs,
285                                  lreg_idx,            //Index for Logical. Regs
286
287                                  TheISA::NumFloatRegs,
288                                  params->numPhysFloatRegs,
289                                  freg_idx,            //Index for Float Regs
290
291                                  TheISA::NumMiscRegs,
292
293                                  TheISA::ZeroReg,
294                                  TheISA::ZeroReg,
295
296                                  tid,
297                                  false);
298
299        renameMap[tid].init(TheISA::NumIntRegs,
300                            params->numPhysIntRegs,
301                            lreg_idx,                  //Index for Logical. Regs
302
303                            TheISA::NumFloatRegs,
304                            params->numPhysFloatRegs,
305                            freg_idx,                  //Index for Float Regs
306
307                            TheISA::NumMiscRegs,
308
309                            TheISA::ZeroReg,
310                            TheISA::ZeroReg,
311
312                            tid,
313                            bindRegs);
314
315        activateThreadEvent[tid].init(tid, this);
316        deallocateContextEvent[tid].init(tid, this);
317    }
318
319    rename.setRenameMap(renameMap);
320    commit.setRenameMap(commitRenameMap);
321
322    // Give renameMap & rename stage access to the freeList;
323    for (int i=0; i < numThreads; i++) {
324        renameMap[i].setFreeList(&freeList);
325    }
326    rename.setFreeList(&freeList);
327
328    // Setup the ROB for whichever stages need it.
329    commit.setROB(&rob);
330
331    lastRunningCycle = curTick;
332
333    lastActivatedCycle = -1;
334
335    // Give renameMap & rename stage access to the freeList;
336    //for (int i=0; i < numThreads; i++) {
337        //globalSeqNum[i] = 1;
338        //}
339
340    contextSwitch = false;
341}
342
343template <class Impl>
344FullO3CPU<Impl>::~FullO3CPU()
345{
346}
347
348template <class Impl>
349void
350FullO3CPU<Impl>::fullCPURegStats()
351{
352    BaseO3CPU::regStats();
353
354    // Register any of the O3CPU's stats here.
355    timesIdled
356        .name(name() + ".timesIdled")
357        .desc("Number of times that the entire CPU went into an idle state and"
358              " unscheduled itself")
359        .prereq(timesIdled);
360
361    idleCycles
362        .name(name() + ".idleCycles")
363        .desc("Total number of cycles that the CPU has spent unscheduled due "
364              "to idling")
365        .prereq(idleCycles);
366
367    // Number of Instructions simulated
368    // --------------------------------
369    // Should probably be in Base CPU but need templated
370    // MaxThreads so put in here instead
371    committedInsts
372        .init(numThreads)
373        .name(name() + ".committedInsts")
374        .desc("Number of Instructions Simulated");
375
376    totalCommittedInsts
377        .name(name() + ".committedInsts_total")
378        .desc("Number of Instructions Simulated");
379
380    cpi
381        .name(name() + ".cpi")
382        .desc("CPI: Cycles Per Instruction")
383        .precision(6);
384    cpi = simTicks / committedInsts;
385
386    totalCpi
387        .name(name() + ".cpi_total")
388        .desc("CPI: Total CPI of All Threads")
389        .precision(6);
390    totalCpi = simTicks / totalCommittedInsts;
391
392    ipc
393        .name(name() + ".ipc")
394        .desc("IPC: Instructions Per Cycle")
395        .precision(6);
396    ipc =  committedInsts / simTicks;
397
398    totalIpc
399        .name(name() + ".ipc_total")
400        .desc("IPC: Total IPC of All Threads")
401        .precision(6);
402    totalIpc =  totalCommittedInsts / simTicks;
403
404}
405
406template <class Impl>
407Port *
408FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
409{
410    if (if_name == "dcache_port")
411        return iew.getDcachePort();
412    else if (if_name == "icache_port")
413        return fetch.getIcachePort();
414    else
415        panic("No Such Port\n");
416}
417
418template <class Impl>
419void
420FullO3CPU<Impl>::tick()
421{
422    DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
423
424    ++numCycles;
425
426//    activity = false;
427
428    //Tick each of the stages
429    fetch.tick();
430
431    decode.tick();
432
433    rename.tick();
434
435    iew.tick();
436
437    commit.tick();
438
439#if !FULL_SYSTEM
440    doContextSwitch();
441#endif
442
443    // Now advance the time buffers
444    timeBuffer.advance();
445
446    fetchQueue.advance();
447    decodeQueue.advance();
448    renameQueue.advance();
449    iewQueue.advance();
450
451    activityRec.advance();
452
453    if (removeInstsThisCycle) {
454        cleanUpRemovedInsts();
455    }
456
457    if (!tickEvent.scheduled()) {
458        if (_status == SwitchedOut ||
459            getState() == SimObject::Drained) {
460            DPRINTF(O3CPU, "Switched out!\n");
461            // increment stat
462            lastRunningCycle = curTick;
463        } else if (!activityRec.active() || _status == Idle) {
464            DPRINTF(O3CPU, "Idle!\n");
465            lastRunningCycle = curTick;
466            timesIdled++;
467        } else {
468            tickEvent.schedule(curTick + cycles(1));
469            DPRINTF(O3CPU, "Scheduling next tick!\n");
470        }
471    }
472
473#if !FULL_SYSTEM
474    updateThreadPriority();
475#endif
476
477}
478
479template <class Impl>
480void
481FullO3CPU<Impl>::init()
482{
483    if (!deferRegistration) {
484        registerThreadContexts();
485    }
486
487    // Set inSyscall so that the CPU doesn't squash when initially
488    // setting up registers.
489    for (int i = 0; i < number_of_threads; ++i)
490        thread[i]->inSyscall = true;
491
492    for (int tid=0; tid < number_of_threads; tid++) {
493#if FULL_SYSTEM
494        ThreadContext *src_tc = threadContexts[tid];
495#else
496        ThreadContext *src_tc = thread[tid]->getTC();
497#endif
498        // Threads start in the Suspended State
499        if (src_tc->status() != ThreadContext::Suspended) {
500            continue;
501        }
502
503#if FULL_SYSTEM
504        TheISA::initCPU(src_tc, src_tc->readCpuId());
505#endif
506    }
507
508    // Clear inSyscall.
509    for (int i = 0; i < number_of_threads; ++i)
510        thread[i]->inSyscall = false;
511
512    // Initialize stages.
513    fetch.initStage();
514    iew.initStage();
515    rename.initStage();
516    commit.initStage();
517
518    commit.setThreads(thread);
519}
520
521template <class Impl>
522void
523FullO3CPU<Impl>::activateThread(unsigned tid)
524{
525    list<unsigned>::iterator isActive = find(
526        activeThreads.begin(), activeThreads.end(), tid);
527
528    DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
529
530    if (isActive == activeThreads.end()) {
531        DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
532                tid);
533
534        activeThreads.push_back(tid);
535    }
536}
537
538template <class Impl>
539void
540FullO3CPU<Impl>::deactivateThread(unsigned tid)
541{
542    //Remove From Active List, if Active
543    list<unsigned>::iterator thread_it =
544        find(activeThreads.begin(), activeThreads.end(), tid);
545
546    DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
547
548    if (thread_it != activeThreads.end()) {
549        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
550                tid);
551        activeThreads.erase(thread_it);
552    }
553}
554
555template <class Impl>
556void
557FullO3CPU<Impl>::activateContext(int tid, int delay)
558{
559#if FULL_SYSTEM
560    // Connect the ThreadContext's memory ports (Functional/Virtual
561    // Ports)
562    threadContexts[tid]->connectMemPorts();
563#endif
564
565    // Needs to set each stage to running as well.
566    if (delay){
567        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
568                "on cycle %d\n", tid, curTick + cycles(delay));
569        scheduleActivateThreadEvent(tid, delay);
570    } else {
571        activateThread(tid);
572    }
573
574    if (lastActivatedCycle < curTick) {
575        scheduleTickEvent(delay);
576
577        // Be sure to signal that there's some activity so the CPU doesn't
578        // deschedule itself.
579        activityRec.activity();
580        fetch.wakeFromQuiesce();
581
582        lastActivatedCycle = curTick;
583
584        _status = Running;
585    }
586}
587
588template <class Impl>
589bool
590FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay)
591{
592    // Schedule removal of thread data from CPU
593    if (delay){
594        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
595                "on cycle %d\n", tid, curTick + cycles(delay));
596        scheduleDeallocateContextEvent(tid, remove, delay);
597        return false;
598    } else {
599        deactivateThread(tid);
600        if (remove)
601            removeThread(tid);
602        return true;
603    }
604}
605
606template <class Impl>
607void
608FullO3CPU<Impl>::suspendContext(int tid)
609{
610    DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
611    bool deallocated = deallocateContext(tid, false, 1);
612    // If this was the last thread then unschedule the tick event.
613    if ((activeThreads.size() == 1 && !deallocated) || activeThreads.size() == 0)
614        unscheduleTickEvent();
615    _status = Idle;
616}
617
618template <class Impl>
619void
620FullO3CPU<Impl>::haltContext(int tid)
621{
622    //For now, this is the same as deallocate
623    DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
624    deallocateContext(tid, true, 1);
625}
626
627template <class Impl>
628void
629FullO3CPU<Impl>::insertThread(unsigned tid)
630{
631    DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
632    // Will change now that the PC and thread state is internal to the CPU
633    // and not in the ThreadContext.
634#if FULL_SYSTEM
635    ThreadContext *src_tc = system->threadContexts[tid];
636#else
637    ThreadContext *src_tc = tcBase(tid);
638#endif
639
640    //Bind Int Regs to Rename Map
641    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
642        PhysRegIndex phys_reg = freeList.getIntReg();
643
644        renameMap[tid].setEntry(ireg,phys_reg);
645        scoreboard.setReg(phys_reg);
646    }
647
648    //Bind Float Regs to Rename Map
649    for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
650        PhysRegIndex phys_reg = freeList.getFloatReg();
651
652        renameMap[tid].setEntry(freg,phys_reg);
653        scoreboard.setReg(phys_reg);
654    }
655
656    //Copy Thread Data Into RegFile
657    //this->copyFromTC(tid);
658
659    //Set PC/NPC/NNPC
660    setPC(src_tc->readPC(), tid);
661    setNextPC(src_tc->readNextPC(), tid);
662#if ISA_HAS_DELAY_SLOT
663    setNextNPC(src_tc->readNextNPC(), tid);
664#endif
665
666    src_tc->setStatus(ThreadContext::Active);
667
668    activateContext(tid,1);
669
670    //Reset ROB/IQ/LSQ Entries
671    commit.rob->resetEntries();
672    iew.resetEntries();
673}
674
675template <class Impl>
676void
677FullO3CPU<Impl>::removeThread(unsigned tid)
678{
679    DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
680
681    // Copy Thread Data From RegFile
682    // If thread is suspended, it might be re-allocated
683    //this->copyToTC(tid);
684
685    // Unbind Int Regs from Rename Map
686    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
687        PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
688
689        scoreboard.unsetReg(phys_reg);
690        freeList.addReg(phys_reg);
691    }
692
693    // Unbind Float Regs from Rename Map
694    for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
695        PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
696
697        scoreboard.unsetReg(phys_reg);
698        freeList.addReg(phys_reg);
699    }
700
701    // Squash Throughout Pipeline
702    InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
703    fetch.squash(0, squash_seq_num, true, tid);
704    decode.squash(tid);
705    rename.squash(squash_seq_num, tid);
706    iew.squash(tid);
707    commit.rob->squash(squash_seq_num, tid);
708
709    assert(iew.ldstQueue.getCount(tid) == 0);
710
711    // Reset ROB/IQ/LSQ Entries
712
713    // Commented out for now.  This should be possible to do by
714    // telling all the pipeline stages to drain first, and then
715    // checking until the drain completes.  Once the pipeline is
716    // drained, call resetEntries(). - 10-09-06 ktlim
717/*
718    if (activeThreads.size() >= 1) {
719        commit.rob->resetEntries();
720        iew.resetEntries();
721    }
722*/
723}
724
725
726template <class Impl>
727void
728FullO3CPU<Impl>::activateWhenReady(int tid)
729{
730    DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
731            "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
732            tid);
733
734    bool ready = true;
735
736    if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
737        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
738                "Phys. Int. Regs.\n",
739                tid);
740        ready = false;
741    } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
742        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
743                "Phys. Float. Regs.\n",
744                tid);
745        ready = false;
746    } else if (commit.rob->numFreeEntries() >=
747               commit.rob->entryAmount(activeThreads.size() + 1)) {
748        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
749                "ROB entries.\n",
750                tid);
751        ready = false;
752    } else if (iew.instQueue.numFreeEntries() >=
753               iew.instQueue.entryAmount(activeThreads.size() + 1)) {
754        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
755                "IQ entries.\n",
756                tid);
757        ready = false;
758    } else if (iew.ldstQueue.numFreeEntries() >=
759               iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
760        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
761                "LSQ entries.\n",
762                tid);
763        ready = false;
764    }
765
766    if (ready) {
767        insertThread(tid);
768
769        contextSwitch = false;
770
771        cpuWaitList.remove(tid);
772    } else {
773        suspendContext(tid);
774
775        //blocks fetch
776        contextSwitch = true;
777
778        //@todo: dont always add to waitlist
779        //do waitlist
780        cpuWaitList.push_back(tid);
781    }
782}
783
784template <class Impl>
785void
786FullO3CPU<Impl>::serialize(std::ostream &os)
787{
788    SimObject::State so_state = SimObject::getState();
789    SERIALIZE_ENUM(so_state);
790    BaseCPU::serialize(os);
791    nameOut(os, csprintf("%s.tickEvent", name()));
792    tickEvent.serialize(os);
793
794    // Use SimpleThread's ability to checkpoint to make it easier to
795    // write out the registers.  Also make this static so it doesn't
796    // get instantiated multiple times (causes a panic in statistics).
797    static SimpleThread temp;
798
799    for (int i = 0; i < thread.size(); i++) {
800        nameOut(os, csprintf("%s.xc.%i", name(), i));
801        temp.copyTC(thread[i]->getTC());
802        temp.serialize(os);
803    }
804}
805
806template <class Impl>
807void
808FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
809{
810    SimObject::State so_state;
811    UNSERIALIZE_ENUM(so_state);
812    BaseCPU::unserialize(cp, section);
813    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
814
815    // Use SimpleThread's ability to checkpoint to make it easier to
816    // read in the registers.  Also make this static so it doesn't
817    // get instantiated multiple times (causes a panic in statistics).
818    static SimpleThread temp;
819
820    for (int i = 0; i < thread.size(); i++) {
821        temp.copyTC(thread[i]->getTC());
822        temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
823        thread[i]->getTC()->copyArchRegs(temp.getTC());
824    }
825}
826
827template <class Impl>
828unsigned int
829FullO3CPU<Impl>::drain(Event *drain_event)
830{
831    DPRINTF(O3CPU, "Switching out\n");
832
833    // If the CPU isn't doing anything, then return immediately.
834    if (_status == Idle || _status == SwitchedOut) {
835        return 0;
836    }
837
838    drainCount = 0;
839    fetch.drain();
840    decode.drain();
841    rename.drain();
842    iew.drain();
843    commit.drain();
844
845    // Wake the CPU and record activity so everything can drain out if
846    // the CPU was not able to immediately drain.
847    if (getState() != SimObject::Drained) {
848        // A bit of a hack...set the drainEvent after all the drain()
849        // calls have been made, that way if all of the stages drain
850        // immediately, the signalDrained() function knows not to call
851        // process on the drain event.
852        drainEvent = drain_event;
853
854        wakeCPU();
855        activityRec.activity();
856
857        return 1;
858    } else {
859        return 0;
860    }
861}
862
863template <class Impl>
864void
865FullO3CPU<Impl>::resume()
866{
867    fetch.resume();
868    decode.resume();
869    rename.resume();
870    iew.resume();
871    commit.resume();
872
873    changeState(SimObject::Running);
874
875    if (_status == SwitchedOut || _status == Idle)
876        return;
877
878#if FULL_SYSTEM
879    assert(system->getMemoryMode() == System::Timing);
880#endif
881
882    if (!tickEvent.scheduled())
883        tickEvent.schedule(curTick);
884    _status = Running;
885}
886
887template <class Impl>
888void
889FullO3CPU<Impl>::signalDrained()
890{
891    if (++drainCount == NumStages) {
892        if (tickEvent.scheduled())
893            tickEvent.squash();
894
895        changeState(SimObject::Drained);
896
897        BaseCPU::switchOut();
898
899        if (drainEvent) {
900            drainEvent->process();
901            drainEvent = NULL;
902        }
903    }
904    assert(drainCount <= 5);
905}
906
907template <class Impl>
908void
909FullO3CPU<Impl>::switchOut()
910{
911    fetch.switchOut();
912    rename.switchOut();
913    iew.switchOut();
914    commit.switchOut();
915    instList.clear();
916    while (!removeList.empty()) {
917        removeList.pop();
918    }
919
920    _status = SwitchedOut;
921#if USE_CHECKER
922    if (checker)
923        checker->switchOut();
924#endif
925    if (tickEvent.scheduled())
926        tickEvent.squash();
927}
928
929template <class Impl>
930void
931FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
932{
933    // Flush out any old data from the time buffers.
934    for (int i = 0; i < timeBuffer.getSize(); ++i) {
935        timeBuffer.advance();
936        fetchQueue.advance();
937        decodeQueue.advance();
938        renameQueue.advance();
939        iewQueue.advance();
940    }
941
942    activityRec.reset();
943
944    BaseCPU::takeOverFrom(oldCPU);
945
946    fetch.takeOverFrom();
947    decode.takeOverFrom();
948    rename.takeOverFrom();
949    iew.takeOverFrom();
950    commit.takeOverFrom();
951
952    assert(!tickEvent.scheduled());
953
954    // @todo: Figure out how to properly select the tid to put onto
955    // the active threads list.
956    int tid = 0;
957
958    list<unsigned>::iterator isActive = find(
959        activeThreads.begin(), activeThreads.end(), tid);
960
961    if (isActive == activeThreads.end()) {
962        //May Need to Re-code this if the delay variable is the delay
963        //needed for thread to activate
964        DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
965                tid);
966
967        activeThreads.push_back(tid);
968    }
969
970    // Set all statuses to active, schedule the CPU's tick event.
971    // @todo: Fix up statuses so this is handled properly
972    for (int i = 0; i < threadContexts.size(); ++i) {
973        ThreadContext *tc = threadContexts[i];
974        if (tc->status() == ThreadContext::Active && _status != Running) {
975            _status = Running;
976            tickEvent.schedule(curTick);
977        }
978    }
979    if (!tickEvent.scheduled())
980        tickEvent.schedule(curTick);
981
982    Port *peer;
983    Port *icachePort = fetch.getIcachePort();
984    if (icachePort->getPeer() == NULL) {
985        peer = oldCPU->getPort("icache_port")->getPeer();
986        icachePort->setPeer(peer);
987    } else {
988        peer = icachePort->getPeer();
989    }
990    peer->setPeer(icachePort);
991
992    Port *dcachePort = iew.getDcachePort();
993    if (dcachePort->getPeer() == NULL) {
994        peer = oldCPU->getPort("dcache_port")->getPeer();
995        dcachePort->setPeer(peer);
996    } else {
997        peer = dcachePort->getPeer();
998    }
999    peer->setPeer(dcachePort);
1000}
1001
1002template <class Impl>
1003uint64_t
1004FullO3CPU<Impl>::readIntReg(int reg_idx)
1005{
1006    return regFile.readIntReg(reg_idx);
1007}
1008
1009template <class Impl>
1010FloatReg
1011FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
1012{
1013    return regFile.readFloatReg(reg_idx, width);
1014}
1015
1016template <class Impl>
1017FloatReg
1018FullO3CPU<Impl>::readFloatReg(int reg_idx)
1019{
1020    return regFile.readFloatReg(reg_idx);
1021}
1022
1023template <class Impl>
1024FloatRegBits
1025FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
1026{
1027    return regFile.readFloatRegBits(reg_idx, width);
1028}
1029
1030template <class Impl>
1031FloatRegBits
1032FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1033{
1034    return regFile.readFloatRegBits(reg_idx);
1035}
1036
1037template <class Impl>
1038void
1039FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1040{
1041    regFile.setIntReg(reg_idx, val);
1042}
1043
1044template <class Impl>
1045void
1046FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
1047{
1048    regFile.setFloatReg(reg_idx, val, width);
1049}
1050
1051template <class Impl>
1052void
1053FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1054{
1055    regFile.setFloatReg(reg_idx, val);
1056}
1057
1058template <class Impl>
1059void
1060FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
1061{
1062    regFile.setFloatRegBits(reg_idx, val, width);
1063}
1064
1065template <class Impl>
1066void
1067FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1068{
1069    regFile.setFloatRegBits(reg_idx, val);
1070}
1071
1072template <class Impl>
1073uint64_t
1074FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid)
1075{
1076    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1077
1078    return regFile.readIntReg(phys_reg);
1079}
1080
1081template <class Impl>
1082float
1083FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid)
1084{
1085    int idx = reg_idx + TheISA::FP_Base_DepTag;
1086    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1087
1088    return regFile.readFloatReg(phys_reg);
1089}
1090
1091template <class Impl>
1092double
1093FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid)
1094{
1095    int idx = reg_idx + TheISA::FP_Base_DepTag;
1096    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1097
1098    return regFile.readFloatReg(phys_reg, 64);
1099}
1100
1101template <class Impl>
1102uint64_t
1103FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid)
1104{
1105    int idx = reg_idx + TheISA::FP_Base_DepTag;
1106    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1107
1108    return regFile.readFloatRegBits(phys_reg);
1109}
1110
1111template <class Impl>
1112void
1113FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid)
1114{
1115    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1116
1117    regFile.setIntReg(phys_reg, val);
1118}
1119
1120template <class Impl>
1121void
1122FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
1123{
1124    int idx = reg_idx + TheISA::FP_Base_DepTag;
1125    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1126
1127    regFile.setFloatReg(phys_reg, val);
1128}
1129
1130template <class Impl>
1131void
1132FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
1133{
1134    int idx = reg_idx + TheISA::FP_Base_DepTag;
1135    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1136
1137    regFile.setFloatReg(phys_reg, val, 64);
1138}
1139
1140template <class Impl>
1141void
1142FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
1143{
1144    int idx = reg_idx + TheISA::FP_Base_DepTag;
1145    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1146
1147    regFile.setFloatRegBits(phys_reg, val);
1148}
1149
1150template <class Impl>
1151uint64_t
1152FullO3CPU<Impl>::readPC(unsigned tid)
1153{
1154    return commit.readPC(tid);
1155}
1156
1157template <class Impl>
1158void
1159FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid)
1160{
1161    commit.setPC(new_PC, tid);
1162}
1163
1164template <class Impl>
1165uint64_t
1166FullO3CPU<Impl>::readNextPC(unsigned tid)
1167{
1168    return commit.readNextPC(tid);
1169}
1170
1171template <class Impl>
1172void
1173FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
1174{
1175    commit.setNextPC(val, tid);
1176}
1177
1178template <class Impl>
1179uint64_t
1180FullO3CPU<Impl>::readNextNPC(unsigned tid)
1181{
1182    return commit.readNextNPC(tid);
1183}
1184
1185template <class Impl>
1186void
1187FullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid)
1188{
1189    commit.setNextNPC(val, tid);
1190}
1191
1192template <class Impl>
1193typename FullO3CPU<Impl>::ListIt
1194FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1195{
1196    instList.push_back(inst);
1197
1198    return --(instList.end());
1199}
1200
1201template <class Impl>
1202void
1203FullO3CPU<Impl>::instDone(unsigned tid)
1204{
1205    // Keep an instruction count.
1206    thread[tid]->numInst++;
1207    thread[tid]->numInsts++;
1208    committedInsts[tid]++;
1209    totalCommittedInsts++;
1210
1211    // Check for instruction-count-based events.
1212    comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1213}
1214
1215template <class Impl>
1216void
1217FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst)
1218{
1219    removeInstsThisCycle = true;
1220
1221    removeList.push(inst->getInstListIt());
1222}
1223
1224template <class Impl>
1225void
1226FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1227{
1228    DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
1229            "[sn:%lli]\n",
1230            inst->threadNumber, inst->readPC(), inst->seqNum);
1231
1232    removeInstsThisCycle = true;
1233
1234    // Remove the front instruction.
1235    removeList.push(inst->getInstListIt());
1236}
1237
1238template <class Impl>
1239void
1240FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid,
1241                                     bool squash_delay_slot,
1242                                     const InstSeqNum &delay_slot_seq_num)
1243{
1244    DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1245            " list.\n", tid);
1246
1247    ListIt end_it;
1248
1249    bool rob_empty = false;
1250
1251    if (instList.empty()) {
1252        return;
1253    } else if (rob.isEmpty(/*tid*/)) {
1254        DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1255        end_it = instList.begin();
1256        rob_empty = true;
1257    } else {
1258        end_it = (rob.readTailInst(tid))->getInstListIt();
1259        DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1260    }
1261
1262    removeInstsThisCycle = true;
1263
1264    ListIt inst_it = instList.end();
1265
1266    inst_it--;
1267
1268    // Walk through the instruction list, removing any instructions
1269    // that were inserted after the given instruction iterator, end_it.
1270    while (inst_it != end_it) {
1271        assert(!instList.empty());
1272
1273#if ISA_HAS_DELAY_SLOT
1274        if(!squash_delay_slot &&
1275           delay_slot_seq_num >= (*inst_it)->seqNum) {
1276            break;
1277        }
1278#endif
1279        squashInstIt(inst_it, tid);
1280
1281        inst_it--;
1282    }
1283
1284    // If the ROB was empty, then we actually need to remove the first
1285    // instruction as well.
1286    if (rob_empty) {
1287        squashInstIt(inst_it, tid);
1288    }
1289}
1290
1291template <class Impl>
1292void
1293FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
1294                                  unsigned tid)
1295{
1296    assert(!instList.empty());
1297
1298    removeInstsThisCycle = true;
1299
1300    ListIt inst_iter = instList.end();
1301
1302    inst_iter--;
1303
1304    DPRINTF(O3CPU, "Deleting instructions from instruction "
1305            "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1306            tid, seq_num, (*inst_iter)->seqNum);
1307
1308    while ((*inst_iter)->seqNum > seq_num) {
1309
1310        bool break_loop = (inst_iter == instList.begin());
1311
1312        squashInstIt(inst_iter, tid);
1313
1314        inst_iter--;
1315
1316        if (break_loop)
1317            break;
1318    }
1319}
1320
1321template <class Impl>
1322inline void
1323FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
1324{
1325    if ((*instIt)->threadNumber == tid) {
1326        DPRINTF(O3CPU, "Squashing instruction, "
1327                "[tid:%i] [sn:%lli] PC %#x\n",
1328                (*instIt)->threadNumber,
1329                (*instIt)->seqNum,
1330                (*instIt)->readPC());
1331
1332        // Mark it as squashed.
1333        (*instIt)->setSquashed();
1334
1335        // @todo: Formulate a consistent method for deleting
1336        // instructions from the instruction list
1337        // Remove the instruction from the list.
1338        removeList.push(instIt);
1339    }
1340}
1341
1342template <class Impl>
1343void
1344FullO3CPU<Impl>::cleanUpRemovedInsts()
1345{
1346    while (!removeList.empty()) {
1347        DPRINTF(O3CPU, "Removing instruction, "
1348                "[tid:%i] [sn:%lli] PC %#x\n",
1349                (*removeList.front())->threadNumber,
1350                (*removeList.front())->seqNum,
1351                (*removeList.front())->readPC());
1352
1353        instList.erase(removeList.front());
1354
1355        removeList.pop();
1356    }
1357
1358    removeInstsThisCycle = false;
1359}
1360/*
1361template <class Impl>
1362void
1363FullO3CPU<Impl>::removeAllInsts()
1364{
1365    instList.clear();
1366}
1367*/
1368template <class Impl>
1369void
1370FullO3CPU<Impl>::dumpInsts()
1371{
1372    int num = 0;
1373
1374    ListIt inst_list_it = instList.begin();
1375
1376    cprintf("Dumping Instruction List\n");
1377
1378    while (inst_list_it != instList.end()) {
1379        cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1380                "Squashed:%i\n\n",
1381                num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
1382                (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1383                (*inst_list_it)->isSquashed());
1384        inst_list_it++;
1385        ++num;
1386    }
1387}
1388/*
1389template <class Impl>
1390void
1391FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1392{
1393    iew.wakeDependents(inst);
1394}
1395*/
1396template <class Impl>
1397void
1398FullO3CPU<Impl>::wakeCPU()
1399{
1400    if (activityRec.active() || tickEvent.scheduled()) {
1401        DPRINTF(Activity, "CPU already running.\n");
1402        return;
1403    }
1404
1405    DPRINTF(Activity, "Waking up CPU\n");
1406
1407    idleCycles += (curTick - 1) - lastRunningCycle;
1408
1409    tickEvent.schedule(curTick);
1410}
1411
1412template <class Impl>
1413int
1414FullO3CPU<Impl>::getFreeTid()
1415{
1416    for (int i=0; i < numThreads; i++) {
1417        if (!tids[i]) {
1418            tids[i] = true;
1419            return i;
1420        }
1421    }
1422
1423    return -1;
1424}
1425
1426template <class Impl>
1427void
1428FullO3CPU<Impl>::doContextSwitch()
1429{
1430    if (contextSwitch) {
1431
1432        //ADD CODE TO DEACTIVE THREAD HERE (???)
1433
1434        for (int tid=0; tid < cpuWaitList.size(); tid++) {
1435            activateWhenReady(tid);
1436        }
1437
1438        if (cpuWaitList.size() == 0)
1439            contextSwitch = true;
1440    }
1441}
1442
1443template <class Impl>
1444void
1445FullO3CPU<Impl>::updateThreadPriority()
1446{
1447    if (activeThreads.size() > 1)
1448    {
1449        //DEFAULT TO ROUND ROBIN SCHEME
1450        //e.g. Move highest priority to end of thread list
1451        list<unsigned>::iterator list_begin = activeThreads.begin();
1452        list<unsigned>::iterator list_end   = activeThreads.end();
1453
1454        unsigned high_thread = *list_begin;
1455
1456        activeThreads.erase(list_begin);
1457
1458        activeThreads.push_back(high_thread);
1459    }
1460}
1461
1462// Forward declaration of FullO3CPU.
1463template class FullO3CPU<O3CPUImpl>;
1464