cpu.cc revision 2794:0dd6cb8820e1 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#if FULL_SYSTEM
36#include "sim/system.hh"
37#else
38#include "sim/process.hh"
39#endif
40
41#include "cpu/activity.hh"
42#include "cpu/simple_thread.hh"
43#include "cpu/thread_context.hh"
44#include "cpu/o3/alpha_dyn_inst.hh"
45#include "cpu/o3/alpha_impl.hh"
46#include "cpu/o3/cpu.hh"
47
48#include "sim/root.hh"
49#include "sim/stat_control.hh"
50
51#if USE_CHECKER
52#include "cpu/checker/cpu.hh"
53#endif
54
55using namespace std;
56using namespace TheISA;
57
58BaseO3CPU::BaseO3CPU(Params *params)
59    : BaseCPU(params), cpu_id(0)
60{
61}
62
63void
64BaseO3CPU::regStats()
65{
66    BaseCPU::regStats();
67}
68
69template <class Impl>
70FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
71    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
72{
73}
74
75template <class Impl>
76void
77FullO3CPU<Impl>::TickEvent::process()
78{
79    cpu->tick();
80}
81
82template <class Impl>
83const char *
84FullO3CPU<Impl>::TickEvent::description()
85{
86    return "FullO3CPU tick event";
87}
88
89template <class Impl>
90FullO3CPU<Impl>::FullO3CPU(Params *params)
91    : BaseO3CPU(params),
92      tickEvent(this),
93      removeInstsThisCycle(false),
94      fetch(params),
95      decode(params),
96      rename(params),
97      iew(params),
98      commit(params),
99
100      regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
101
102      freeList(params->numberOfThreads,//number of activeThreads
103               TheISA::NumIntRegs, params->numPhysIntRegs,
104               TheISA::NumFloatRegs, params->numPhysFloatRegs),
105
106      rob(params->numROBEntries, params->squashWidth,
107          params->smtROBPolicy, params->smtROBThreshold,
108          params->numberOfThreads),
109
110      scoreboard(params->numberOfThreads,//number of activeThreads
111                 TheISA::NumIntRegs, params->numPhysIntRegs,
112                 TheISA::NumFloatRegs, params->numPhysFloatRegs,
113                 TheISA::NumMiscRegs * number_of_threads,
114                 TheISA::ZeroReg),
115
116      // For now just have these time buffers be pretty big.
117      // @todo: Make these time buffer sizes parameters or derived
118      // from latencies
119      timeBuffer(5, 5),
120      fetchQueue(5, 5),
121      decodeQueue(5, 5),
122      renameQueue(5, 5),
123      iewQueue(5, 5),
124      activityRec(NumStages, 10, params->activity),
125
126      globalSeqNum(1),
127
128#if FULL_SYSTEM
129      system(params->system),
130      physmem(system->physmem),
131#endif // FULL_SYSTEM
132      mem(params->mem),
133      switchCount(0),
134      deferRegistration(params->deferRegistration),
135      numThreads(number_of_threads)
136{
137    _status = Idle;
138
139    checker = NULL;
140
141    if (params->checker) {
142#if USE_CHECKER
143        BaseCPU *temp_checker = params->checker;
144        checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
145        checker->setMemory(mem);
146#if FULL_SYSTEM
147        checker->setSystem(params->system);
148#endif
149#else
150        panic("Checker enabled but not compiled in!");
151#endif // USE_CHECKER
152    }
153
154#if !FULL_SYSTEM
155    thread.resize(number_of_threads);
156    tids.resize(number_of_threads);
157#endif
158
159    // The stages also need their CPU pointer setup.  However this
160    // must be done at the upper level CPU because they have pointers
161    // to the upper level CPU, and not this FullO3CPU.
162
163    // Set up Pointers to the activeThreads list for each stage
164    fetch.setActiveThreads(&activeThreads);
165    decode.setActiveThreads(&activeThreads);
166    rename.setActiveThreads(&activeThreads);
167    iew.setActiveThreads(&activeThreads);
168    commit.setActiveThreads(&activeThreads);
169
170    // Give each of the stages the time buffer they will use.
171    fetch.setTimeBuffer(&timeBuffer);
172    decode.setTimeBuffer(&timeBuffer);
173    rename.setTimeBuffer(&timeBuffer);
174    iew.setTimeBuffer(&timeBuffer);
175    commit.setTimeBuffer(&timeBuffer);
176
177    // Also setup each of the stages' queues.
178    fetch.setFetchQueue(&fetchQueue);
179    decode.setFetchQueue(&fetchQueue);
180    commit.setFetchQueue(&fetchQueue);
181    decode.setDecodeQueue(&decodeQueue);
182    rename.setDecodeQueue(&decodeQueue);
183    rename.setRenameQueue(&renameQueue);
184    iew.setRenameQueue(&renameQueue);
185    iew.setIEWQueue(&iewQueue);
186    commit.setIEWQueue(&iewQueue);
187    commit.setRenameQueue(&renameQueue);
188
189    commit.setFetchStage(&fetch);
190    commit.setIEWStage(&iew);
191    rename.setIEWStage(&iew);
192    rename.setCommitStage(&commit);
193
194#if !FULL_SYSTEM
195    int active_threads = params->workload.size();
196#else
197    int active_threads = 1;
198#endif
199
200    //Make Sure That this a Valid Architeture
201    assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
202    assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
203
204    rename.setScoreboard(&scoreboard);
205    iew.setScoreboard(&scoreboard);
206
207    // Setup the rename map for whichever stages need it.
208    PhysRegIndex lreg_idx = 0;
209    PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
210
211    for (int tid=0; tid < numThreads; tid++) {
212        bool bindRegs = (tid <= active_threads - 1);
213
214        commitRenameMap[tid].init(TheISA::NumIntRegs,
215                                  params->numPhysIntRegs,
216                                  lreg_idx,            //Index for Logical. Regs
217
218                                  TheISA::NumFloatRegs,
219                                  params->numPhysFloatRegs,
220                                  freg_idx,            //Index for Float Regs
221
222                                  TheISA::NumMiscRegs,
223
224                                  TheISA::ZeroReg,
225                                  TheISA::ZeroReg,
226
227                                  tid,
228                                  false);
229
230        renameMap[tid].init(TheISA::NumIntRegs,
231                            params->numPhysIntRegs,
232                            lreg_idx,                  //Index for Logical. Regs
233
234                            TheISA::NumFloatRegs,
235                            params->numPhysFloatRegs,
236                            freg_idx,                  //Index for Float Regs
237
238                            TheISA::NumMiscRegs,
239
240                            TheISA::ZeroReg,
241                            TheISA::ZeroReg,
242
243                            tid,
244                            bindRegs);
245    }
246
247    rename.setRenameMap(renameMap);
248    commit.setRenameMap(commitRenameMap);
249
250    // Give renameMap & rename stage access to the freeList;
251    for (int i=0; i < numThreads; i++) {
252        renameMap[i].setFreeList(&freeList);
253    }
254    rename.setFreeList(&freeList);
255
256    // Setup the ROB for whichever stages need it.
257    commit.setROB(&rob);
258
259    lastRunningCycle = curTick;
260
261    contextSwitch = false;
262}
263
264template <class Impl>
265FullO3CPU<Impl>::~FullO3CPU()
266{
267}
268
269template <class Impl>
270void
271FullO3CPU<Impl>::fullCPURegStats()
272{
273    BaseO3CPU::regStats();
274
275    // Register any of the O3CPU's stats here.
276    timesIdled
277        .name(name() + ".timesIdled")
278        .desc("Number of times that the entire CPU went into an idle state and"
279              " unscheduled itself")
280        .prereq(timesIdled);
281
282    idleCycles
283        .name(name() + ".idleCycles")
284        .desc("Total number of cycles that the CPU has spent unscheduled due "
285              "to idling")
286        .prereq(idleCycles);
287
288    // Number of Instructions simulated
289    // --------------------------------
290    // Should probably be in Base CPU but need templated
291    // MaxThreads so put in here instead
292    committedInsts
293        .init(numThreads)
294        .name(name() + ".committedInsts")
295        .desc("Number of Instructions Simulated");
296
297    totalCommittedInsts
298        .name(name() + ".committedInsts_total")
299        .desc("Number of Instructions Simulated");
300
301    cpi
302        .name(name() + ".cpi")
303        .desc("CPI: Cycles Per Instruction")
304        .precision(6);
305    cpi = simTicks / committedInsts;
306
307    totalCpi
308        .name(name() + ".cpi_total")
309        .desc("CPI: Total CPI of All Threads")
310        .precision(6);
311    totalCpi = simTicks / totalCommittedInsts;
312
313    ipc
314        .name(name() + ".ipc")
315        .desc("IPC: Instructions Per Cycle")
316        .precision(6);
317    ipc =  committedInsts / simTicks;
318
319    totalIpc
320        .name(name() + ".ipc_total")
321        .desc("IPC: Total IPC of All Threads")
322        .precision(6);
323    totalIpc =  totalCommittedInsts / simTicks;
324
325}
326
327template <class Impl>
328void
329FullO3CPU<Impl>::tick()
330{
331    DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
332
333    ++numCycles;
334
335//    activity = false;
336
337    //Tick each of the stages
338    fetch.tick();
339
340    decode.tick();
341
342    rename.tick();
343
344    iew.tick();
345
346    commit.tick();
347
348#if !FULL_SYSTEM
349    doContextSwitch();
350#endif
351
352    // Now advance the time buffers
353    timeBuffer.advance();
354
355    fetchQueue.advance();
356    decodeQueue.advance();
357    renameQueue.advance();
358    iewQueue.advance();
359
360    activityRec.advance();
361
362    if (removeInstsThisCycle) {
363        cleanUpRemovedInsts();
364    }
365
366    if (!tickEvent.scheduled()) {
367        if (_status == SwitchedOut) {
368            // increment stat
369            lastRunningCycle = curTick;
370        } else if (!activityRec.active()) {
371            lastRunningCycle = curTick;
372            timesIdled++;
373        } else {
374            tickEvent.schedule(curTick + cycles(1));
375        }
376    }
377
378#if !FULL_SYSTEM
379    updateThreadPriority();
380#endif
381
382}
383
384template <class Impl>
385void
386FullO3CPU<Impl>::init()
387{
388    if (!deferRegistration) {
389        registerThreadContexts();
390    }
391
392    // Set inSyscall so that the CPU doesn't squash when initially
393    // setting up registers.
394    for (int i = 0; i < number_of_threads; ++i)
395        thread[i]->inSyscall = true;
396
397    for (int tid=0; tid < number_of_threads; tid++) {
398#if FULL_SYSTEM
399        ThreadContext *src_tc = threadContexts[tid];
400#else
401        ThreadContext *src_tc = thread[tid]->getTC();
402#endif
403        // Threads start in the Suspended State
404        if (src_tc->status() != ThreadContext::Suspended) {
405            continue;
406        }
407
408#if FULL_SYSTEM
409        TheISA::initCPU(src_tc, src_tc->readCpuId());
410#endif
411    }
412
413    // Clear inSyscall.
414    for (int i = 0; i < number_of_threads; ++i)
415        thread[i]->inSyscall = false;
416
417    // Initialize stages.
418    fetch.initStage();
419    iew.initStage();
420    rename.initStage();
421    commit.initStage();
422
423    commit.setThreads(thread);
424}
425
426template <class Impl>
427void
428FullO3CPU<Impl>::insertThread(unsigned tid)
429{
430    DPRINTF(O3CPU,"[tid:%i] Initializing thread data");
431    // Will change now that the PC and thread state is internal to the CPU
432    // and not in the ThreadContext.
433#if 0
434#if FULL_SYSTEM
435    ThreadContext *src_tc = system->threadContexts[tid];
436#else
437    ThreadContext *src_tc = thread[tid];
438#endif
439
440    //Bind Int Regs to Rename Map
441    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
442        PhysRegIndex phys_reg = freeList.getIntReg();
443
444        renameMap[tid].setEntry(ireg,phys_reg);
445        scoreboard.setReg(phys_reg);
446    }
447
448    //Bind Float Regs to Rename Map
449    for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
450        PhysRegIndex phys_reg = freeList.getFloatReg();
451
452        renameMap[tid].setEntry(freg,phys_reg);
453        scoreboard.setReg(phys_reg);
454    }
455
456    //Copy Thread Data Into RegFile
457    this->copyFromTC(tid);
458
459    //Set PC/NPC
460    regFile.pc[tid]  = src_tc->readPC();
461    regFile.npc[tid] = src_tc->readNextPC();
462
463    src_tc->setStatus(ThreadContext::Active);
464
465    activateContext(tid,1);
466
467    //Reset ROB/IQ/LSQ Entries
468    commit.rob->resetEntries();
469    iew.resetEntries();
470#endif
471}
472
473template <class Impl>
474void
475FullO3CPU<Impl>::removeThread(unsigned tid)
476{
477    DPRINTF(O3CPU,"[tid:%i] Removing thread data");
478#if 0
479    //Unbind Int Regs from Rename Map
480    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
481        PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
482
483        scoreboard.unsetReg(phys_reg);
484        freeList.addReg(phys_reg);
485    }
486
487    //Unbind Float Regs from Rename Map
488    for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
489        PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
490
491        scoreboard.unsetReg(phys_reg);
492        freeList.addReg(phys_reg);
493    }
494
495    //Copy Thread Data From RegFile
496    /* Fix Me:
497     * Do we really need to do this if we are removing a thread
498     * in the sense that it's finished (exiting)? If the thread is just
499     * being suspended we might...
500     */
501//    this->copyToTC(tid);
502
503    //Squash Throughout Pipeline
504    fetch.squash(0,tid);
505    decode.squash(tid);
506    rename.squash(tid);
507
508    assert(iew.ldstQueue.getCount(tid) == 0);
509
510    //Reset ROB/IQ/LSQ Entries
511    if (activeThreads.size() >= 1) {
512        commit.rob->resetEntries();
513        iew.resetEntries();
514    }
515#endif
516}
517
518
519template <class Impl>
520void
521FullO3CPU<Impl>::activateWhenReady(int tid)
522{
523    DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
524            "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
525            tid);
526
527    bool ready = true;
528
529    if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
530        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
531                "Phys. Int. Regs.\n",
532                tid);
533        ready = false;
534    } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
535        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
536                "Phys. Float. Regs.\n",
537                tid);
538        ready = false;
539    } else if (commit.rob->numFreeEntries() >=
540               commit.rob->entryAmount(activeThreads.size() + 1)) {
541        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
542                "ROB entries.\n",
543                tid);
544        ready = false;
545    } else if (iew.instQueue.numFreeEntries() >=
546               iew.instQueue.entryAmount(activeThreads.size() + 1)) {
547        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
548                "IQ entries.\n",
549                tid);
550        ready = false;
551    } else if (iew.ldstQueue.numFreeEntries() >=
552               iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
553        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
554                "LSQ entries.\n",
555                tid);
556        ready = false;
557    }
558
559    if (ready) {
560        insertThread(tid);
561
562        contextSwitch = false;
563
564        cpuWaitList.remove(tid);
565    } else {
566        suspendContext(tid);
567
568        //blocks fetch
569        contextSwitch = true;
570
571        //do waitlist
572        cpuWaitList.push_back(tid);
573    }
574}
575
576template <class Impl>
577void
578FullO3CPU<Impl>::activateContext(int tid, int delay)
579{
580    // Needs to set each stage to running as well.
581    list<unsigned>::iterator isActive = find(
582        activeThreads.begin(), activeThreads.end(), tid);
583
584    if (isActive == activeThreads.end()) {
585        //May Need to Re-code this if the delay variable is the
586        //delay needed for thread to activate
587        DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
588                tid);
589
590        activeThreads.push_back(tid);
591    }
592
593    assert(_status == Idle || _status == SwitchedOut);
594
595    scheduleTickEvent(delay);
596
597    // Be sure to signal that there's some activity so the CPU doesn't
598    // deschedule itself.
599    activityRec.activity();
600    fetch.wakeFromQuiesce();
601
602    _status = Running;
603}
604
605template <class Impl>
606void
607FullO3CPU<Impl>::suspendContext(int tid)
608{
609    DPRINTF(O3CPU,"[tid: %i]: Suspended ...\n", tid);
610    unscheduleTickEvent();
611    _status = Idle;
612/*
613    //Remove From Active List, if Active
614    list<unsigned>::iterator isActive = find(
615        activeThreads.begin(), activeThreads.end(), tid);
616
617    if (isActive != activeThreads.end()) {
618        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
619                tid);
620        activeThreads.erase(isActive);
621    }
622*/
623}
624
625template <class Impl>
626void
627FullO3CPU<Impl>::deallocateContext(int tid)
628{
629    DPRINTF(O3CPU,"[tid:%i]: Deallocating ...", tid);
630/*
631    //Remove From Active List, if Active
632    list<unsigned>::iterator isActive = find(
633        activeThreads.begin(), activeThreads.end(), tid);
634
635    if (isActive != activeThreads.end()) {
636        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
637                tid);
638        activeThreads.erase(isActive);
639
640        removeThread(tid);
641    }
642*/
643}
644
645template <class Impl>
646void
647FullO3CPU<Impl>::haltContext(int tid)
648{
649    DPRINTF(O3CPU,"[tid:%i]: Halted ...", tid);
650/*
651    //Remove From Active List, if Active
652    list<unsigned>::iterator isActive = find(
653        activeThreads.begin(), activeThreads.end(), tid);
654
655    if (isActive != activeThreads.end()) {
656        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
657                tid);
658        activeThreads.erase(isActive);
659
660        removeThread(tid);
661    }
662*/
663}
664
665template <class Impl>
666void
667FullO3CPU<Impl>::switchOut(Sampler *_sampler)
668{
669    sampler = _sampler;
670    switchCount = 0;
671    fetch.switchOut();
672    decode.switchOut();
673    rename.switchOut();
674    iew.switchOut();
675    commit.switchOut();
676
677    // Wake the CPU and record activity so everything can drain out if
678    // the CPU is currently idle.
679    wakeCPU();
680    activityRec.activity();
681}
682
683template <class Impl>
684void
685FullO3CPU<Impl>::signalSwitched()
686{
687    if (++switchCount == NumStages) {
688        fetch.doSwitchOut();
689        rename.doSwitchOut();
690        commit.doSwitchOut();
691        instList.clear();
692        while (!removeList.empty()) {
693            removeList.pop();
694        }
695
696#if USE_CHECKER
697        if (checker)
698            checker->switchOut(sampler);
699#endif
700
701        if (tickEvent.scheduled())
702            tickEvent.squash();
703        sampler->signalSwitched();
704        _status = SwitchedOut;
705    }
706    assert(switchCount <= 5);
707}
708
709template <class Impl>
710void
711FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
712{
713    // Flush out any old data from the time buffers.
714    for (int i = 0; i < 10; ++i) {
715        timeBuffer.advance();
716        fetchQueue.advance();
717        decodeQueue.advance();
718        renameQueue.advance();
719        iewQueue.advance();
720    }
721
722    activityRec.reset();
723
724    BaseCPU::takeOverFrom(oldCPU);
725
726    fetch.takeOverFrom();
727    decode.takeOverFrom();
728    rename.takeOverFrom();
729    iew.takeOverFrom();
730    commit.takeOverFrom();
731
732    assert(!tickEvent.scheduled());
733
734    // @todo: Figure out how to properly select the tid to put onto
735    // the active threads list.
736    int tid = 0;
737
738    list<unsigned>::iterator isActive = find(
739        activeThreads.begin(), activeThreads.end(), tid);
740
741    if (isActive == activeThreads.end()) {
742        //May Need to Re-code this if the delay variable is the delay
743        //needed for thread to activate
744        DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
745                tid);
746
747        activeThreads.push_back(tid);
748    }
749
750    // Set all statuses to active, schedule the CPU's tick event.
751    // @todo: Fix up statuses so this is handled properly
752    for (int i = 0; i < threadContexts.size(); ++i) {
753        ThreadContext *tc = threadContexts[i];
754        if (tc->status() == ThreadContext::Active && _status != Running) {
755            _status = Running;
756            tickEvent.schedule(curTick);
757        }
758    }
759    if (!tickEvent.scheduled())
760        tickEvent.schedule(curTick);
761}
762
763template <class Impl>
764uint64_t
765FullO3CPU<Impl>::readIntReg(int reg_idx)
766{
767    return regFile.readIntReg(reg_idx);
768}
769
770template <class Impl>
771FloatReg
772FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
773{
774    return regFile.readFloatReg(reg_idx, width);
775}
776
777template <class Impl>
778FloatReg
779FullO3CPU<Impl>::readFloatReg(int reg_idx)
780{
781    return regFile.readFloatReg(reg_idx);
782}
783
784template <class Impl>
785FloatRegBits
786FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
787{
788    return regFile.readFloatRegBits(reg_idx, width);
789}
790
791template <class Impl>
792FloatRegBits
793FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
794{
795    return regFile.readFloatRegBits(reg_idx);
796}
797
798template <class Impl>
799void
800FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
801{
802    regFile.setIntReg(reg_idx, val);
803}
804
805template <class Impl>
806void
807FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
808{
809    regFile.setFloatReg(reg_idx, val, width);
810}
811
812template <class Impl>
813void
814FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
815{
816    regFile.setFloatReg(reg_idx, val);
817}
818
819template <class Impl>
820void
821FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
822{
823    regFile.setFloatRegBits(reg_idx, val, width);
824}
825
826template <class Impl>
827void
828FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
829{
830    regFile.setFloatRegBits(reg_idx, val);
831}
832
833template <class Impl>
834uint64_t
835FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid)
836{
837    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
838
839    return regFile.readIntReg(phys_reg);
840}
841
842template <class Impl>
843float
844FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid)
845{
846    int idx = reg_idx + TheISA::FP_Base_DepTag;
847    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
848
849    return regFile.readFloatReg(phys_reg);
850}
851
852template <class Impl>
853double
854FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid)
855{
856    int idx = reg_idx + TheISA::FP_Base_DepTag;
857    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
858
859    return regFile.readFloatReg(phys_reg, 64);
860}
861
862template <class Impl>
863uint64_t
864FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid)
865{
866    int idx = reg_idx + TheISA::FP_Base_DepTag;
867    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
868
869    return regFile.readFloatRegBits(phys_reg);
870}
871
872template <class Impl>
873void
874FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid)
875{
876    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
877
878    regFile.setIntReg(phys_reg, val);
879}
880
881template <class Impl>
882void
883FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
884{
885    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
886
887    regFile.setFloatReg(phys_reg, val);
888}
889
890template <class Impl>
891void
892FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
893{
894    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
895
896    regFile.setFloatReg(phys_reg, val, 64);
897}
898
899template <class Impl>
900void
901FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
902{
903    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
904
905    regFile.setFloatRegBits(phys_reg, val);
906}
907
908template <class Impl>
909uint64_t
910FullO3CPU<Impl>::readPC(unsigned tid)
911{
912    return commit.readPC(tid);
913}
914
915template <class Impl>
916void
917FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid)
918{
919    commit.setPC(new_PC, tid);
920}
921
922template <class Impl>
923uint64_t
924FullO3CPU<Impl>::readNextPC(unsigned tid)
925{
926    return commit.readNextPC(tid);
927}
928
929template <class Impl>
930void
931FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
932{
933    commit.setNextPC(val, tid);
934}
935
936#if THE_ISA != ALPHA_ISA
937template <class Impl>
938uint64_t
939FullO3CPU<Impl>::readNextNPC(unsigned tid)
940{
941    return commit.readNextNPC(tid);
942}
943
944template <class Impl>
945void
946FullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid)
947{
948    commit.setNextNPC(val, tid);
949}
950#endif
951
952template <class Impl>
953typename FullO3CPU<Impl>::ListIt
954FullO3CPU<Impl>::addInst(DynInstPtr &inst)
955{
956    instList.push_back(inst);
957
958    return --(instList.end());
959}
960
961template <class Impl>
962void
963FullO3CPU<Impl>::instDone(unsigned tid)
964{
965    // Keep an instruction count.
966    thread[tid]->numInst++;
967    thread[tid]->numInsts++;
968    committedInsts[tid]++;
969    totalCommittedInsts++;
970
971    // Check for instruction-count-based events.
972    comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
973}
974
975template <class Impl>
976void
977FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst)
978{
979    removeInstsThisCycle = true;
980
981    removeList.push(inst->getInstListIt());
982}
983
984template <class Impl>
985void
986FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
987{
988    DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
989            "[sn:%lli]\n",
990            inst->threadNumber, inst->readPC(), inst->seqNum);
991
992    removeInstsThisCycle = true;
993
994    // Remove the front instruction.
995    removeList.push(inst->getInstListIt());
996}
997
998template <class Impl>
999void
1000FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
1001{
1002    DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1003            " list.\n", tid);
1004
1005    ListIt end_it;
1006
1007    bool rob_empty = false;
1008
1009    if (instList.empty()) {
1010        return;
1011    } else if (rob.isEmpty(/*tid*/)) {
1012        DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1013        end_it = instList.begin();
1014        rob_empty = true;
1015    } else {
1016        end_it = (rob.readTailInst(tid))->getInstListIt();
1017        DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1018    }
1019
1020    removeInstsThisCycle = true;
1021
1022    ListIt inst_it = instList.end();
1023
1024    inst_it--;
1025
1026    // Walk through the instruction list, removing any instructions
1027    // that were inserted after the given instruction iterator, end_it.
1028    while (inst_it != end_it) {
1029        assert(!instList.empty());
1030
1031        squashInstIt(inst_it, tid);
1032
1033        inst_it--;
1034    }
1035
1036    // If the ROB was empty, then we actually need to remove the first
1037    // instruction as well.
1038    if (rob_empty) {
1039        squashInstIt(inst_it, tid);
1040    }
1041}
1042
1043template <class Impl>
1044void
1045FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
1046                                  unsigned tid)
1047{
1048    assert(!instList.empty());
1049
1050    removeInstsThisCycle = true;
1051
1052    ListIt inst_iter = instList.end();
1053
1054    inst_iter--;
1055
1056    DPRINTF(O3CPU, "Deleting instructions from instruction "
1057            "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1058            tid, seq_num, (*inst_iter)->seqNum);
1059
1060    while ((*inst_iter)->seqNum > seq_num) {
1061
1062        bool break_loop = (inst_iter == instList.begin());
1063
1064        squashInstIt(inst_iter, tid);
1065
1066        inst_iter--;
1067
1068        if (break_loop)
1069            break;
1070    }
1071}
1072
1073template <class Impl>
1074inline void
1075FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
1076{
1077    if ((*instIt)->threadNumber == tid) {
1078        DPRINTF(O3CPU, "Squashing instruction, "
1079                "[tid:%i] [sn:%lli] PC %#x\n",
1080                (*instIt)->threadNumber,
1081                (*instIt)->seqNum,
1082                (*instIt)->readPC());
1083
1084        // Mark it as squashed.
1085        (*instIt)->setSquashed();
1086
1087        // @todo: Formulate a consistent method for deleting
1088        // instructions from the instruction list
1089        // Remove the instruction from the list.
1090        removeList.push(instIt);
1091    }
1092}
1093
1094template <class Impl>
1095void
1096FullO3CPU<Impl>::cleanUpRemovedInsts()
1097{
1098    while (!removeList.empty()) {
1099        DPRINTF(O3CPU, "Removing instruction, "
1100                "[tid:%i] [sn:%lli] PC %#x\n",
1101                (*removeList.front())->threadNumber,
1102                (*removeList.front())->seqNum,
1103                (*removeList.front())->readPC());
1104
1105        instList.erase(removeList.front());
1106
1107        removeList.pop();
1108    }
1109
1110    removeInstsThisCycle = false;
1111}
1112/*
1113template <class Impl>
1114void
1115FullO3CPU<Impl>::removeAllInsts()
1116{
1117    instList.clear();
1118}
1119*/
1120template <class Impl>
1121void
1122FullO3CPU<Impl>::dumpInsts()
1123{
1124    int num = 0;
1125
1126    ListIt inst_list_it = instList.begin();
1127
1128    cprintf("Dumping Instruction List\n");
1129
1130    while (inst_list_it != instList.end()) {
1131        cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1132                "Squashed:%i\n\n",
1133                num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
1134                (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1135                (*inst_list_it)->isSquashed());
1136        inst_list_it++;
1137        ++num;
1138    }
1139}
1140/*
1141template <class Impl>
1142void
1143FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1144{
1145    iew.wakeDependents(inst);
1146}
1147*/
1148template <class Impl>
1149void
1150FullO3CPU<Impl>::wakeCPU()
1151{
1152    if (activityRec.active() || tickEvent.scheduled()) {
1153        DPRINTF(Activity, "CPU already running.\n");
1154        return;
1155    }
1156
1157    DPRINTF(Activity, "Waking up CPU\n");
1158
1159    idleCycles += (curTick - 1) - lastRunningCycle;
1160
1161    tickEvent.schedule(curTick);
1162}
1163
1164template <class Impl>
1165int
1166FullO3CPU<Impl>::getFreeTid()
1167{
1168    for (int i=0; i < numThreads; i++) {
1169        if (!tids[i]) {
1170            tids[i] = true;
1171            return i;
1172        }
1173    }
1174
1175    return -1;
1176}
1177
1178template <class Impl>
1179void
1180FullO3CPU<Impl>::doContextSwitch()
1181{
1182    if (contextSwitch) {
1183
1184        //ADD CODE TO DEACTIVE THREAD HERE (???)
1185
1186        for (int tid=0; tid < cpuWaitList.size(); tid++) {
1187            activateWhenReady(tid);
1188        }
1189
1190        if (cpuWaitList.size() == 0)
1191            contextSwitch = true;
1192    }
1193}
1194
1195template <class Impl>
1196void
1197FullO3CPU<Impl>::updateThreadPriority()
1198{
1199    if (activeThreads.size() > 1)
1200    {
1201        //DEFAULT TO ROUND ROBIN SCHEME
1202        //e.g. Move highest priority to end of thread list
1203        list<unsigned>::iterator list_begin = activeThreads.begin();
1204        list<unsigned>::iterator list_end   = activeThreads.end();
1205
1206        unsigned high_thread = *list_begin;
1207
1208        activeThreads.erase(list_begin);
1209
1210        activeThreads.push_back(high_thread);
1211    }
1212}
1213
1214// Forward declaration of FullO3CPU.
1215template class FullO3CPU<AlphaSimpleImpl>;
1216