cpu.cc revision 12143:e48005f585f2
1/* 2 * Copyright (c) 2011-2012, 2014, 2016, 2017 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * Copyright (c) 2011 Regents of the University of California 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Kevin Lim 43 * Korey Sewell 44 * Rick Strong 45 */ 46 47#include "cpu/o3/cpu.hh" 48 49#include "arch/generic/traits.hh" 50#include "arch/kernel_stats.hh" 51#include "config/the_isa.hh" 52#include "cpu/activity.hh" 53#include "cpu/checker/cpu.hh" 54#include "cpu/checker/thread_context.hh" 55#include "cpu/o3/isa_specific.hh" 56#include "cpu/o3/thread_context.hh" 57#include "cpu/quiesce_event.hh" 58#include "cpu/simple_thread.hh" 59#include "cpu/thread_context.hh" 60#include "debug/Activity.hh" 61#include "debug/Drain.hh" 62#include "debug/O3CPU.hh" 63#include "debug/Quiesce.hh" 64#include "enums/MemoryMode.hh" 65#include "sim/core.hh" 66#include "sim/full_system.hh" 67#include "sim/process.hh" 68#include "sim/stat_control.hh" 69#include "sim/system.hh" 70 71#if THE_ISA == ALPHA_ISA 72#include "arch/alpha/osfpal.hh" 73#include "debug/Activity.hh" 74 75#endif 76 77struct BaseCPUParams; 78 79using namespace TheISA; 80using namespace std; 81 82BaseO3CPU::BaseO3CPU(BaseCPUParams *params) 83 : BaseCPU(params) 84{ 85} 86 87void 88BaseO3CPU::regStats() 89{ 90 BaseCPU::regStats(); 91} 92 93template<class Impl> 94bool 95FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 96{ 97 DPRINTF(O3CPU, "Fetch unit received timing\n"); 98 // We shouldn't ever get a cacheable block in Modified state 99 assert(pkt->req->isUncacheable() || 100 !(pkt->cacheResponding() && !pkt->hasSharers())); 101 fetch->processCacheCompletion(pkt); 102 103 return true; 104} 105 106template<class Impl> 107void 108FullO3CPU<Impl>::IcachePort::recvReqRetry() 109{ 110 fetch->recvReqRetry(); 111} 112 113template <class Impl> 114bool 115FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 116{ 117 return lsq->recvTimingResp(pkt); 118} 119 120template <class Impl> 121void 122FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 123{ 124 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 125 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 126 cpu->wakeup(tid); 127 } 128 } 129 lsq->recvTimingSnoopReq(pkt); 130} 131 132template <class Impl> 133void 134FullO3CPU<Impl>::DcachePort::recvReqRetry() 135{ 136 lsq->recvReqRetry(); 137} 138 139template <class Impl> 140FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 141 : BaseO3CPU(params), 142 itb(params->itb), 143 dtb(params->dtb), 144 tickEvent([this]{ tick(); }, "FullO3CPU tick", 145 false, Event::CPU_Tick_Pri), 146#ifndef NDEBUG 147 instcount(0), 148#endif 149 removeInstsThisCycle(false), 150 fetch(this, params), 151 decode(this, params), 152 rename(this, params), 153 iew(this, params), 154 commit(this, params), 155 156 /* It is mandatory that all SMT threads use the same renaming mode as 157 * they are sharing registers and rename */ 158 vecMode(initRenameMode<TheISA::ISA>::mode(params->isa[0])), 159 regFile(params->numPhysIntRegs, 160 params->numPhysFloatRegs, 161 params->numPhysVecRegs, 162 params->numPhysCCRegs, 163 vecMode), 164 165 freeList(name() + ".freelist", ®File), 166 167 rob(this, params), 168 169 scoreboard(name() + ".scoreboard", 170 regFile.totalNumPhysRegs()), 171 172 isa(numThreads, NULL), 173 174 icachePort(&fetch, this), 175 dcachePort(&iew.ldstQueue, this), 176 177 timeBuffer(params->backComSize, params->forwardComSize), 178 fetchQueue(params->backComSize, params->forwardComSize), 179 decodeQueue(params->backComSize, params->forwardComSize), 180 renameQueue(params->backComSize, params->forwardComSize), 181 iewQueue(params->backComSize, params->forwardComSize), 182 activityRec(name(), NumStages, 183 params->backComSize + params->forwardComSize, 184 params->activity), 185 186 globalSeqNum(1), 187 system(params->system), 188 lastRunningCycle(curCycle()) 189{ 190 if (!params->switched_out) { 191 _status = Running; 192 } else { 193 _status = SwitchedOut; 194 } 195 196 if (params->checker) { 197 BaseCPU *temp_checker = params->checker; 198 checker = dynamic_cast<Checker<Impl> *>(temp_checker); 199 checker->setIcachePort(&icachePort); 200 checker->setSystem(params->system); 201 } else { 202 checker = NULL; 203 } 204 205 if (!FullSystem) { 206 thread.resize(numThreads); 207 tids.resize(numThreads); 208 } 209 210 // The stages also need their CPU pointer setup. However this 211 // must be done at the upper level CPU because they have pointers 212 // to the upper level CPU, and not this FullO3CPU. 213 214 // Set up Pointers to the activeThreads list for each stage 215 fetch.setActiveThreads(&activeThreads); 216 decode.setActiveThreads(&activeThreads); 217 rename.setActiveThreads(&activeThreads); 218 iew.setActiveThreads(&activeThreads); 219 commit.setActiveThreads(&activeThreads); 220 221 // Give each of the stages the time buffer they will use. 222 fetch.setTimeBuffer(&timeBuffer); 223 decode.setTimeBuffer(&timeBuffer); 224 rename.setTimeBuffer(&timeBuffer); 225 iew.setTimeBuffer(&timeBuffer); 226 commit.setTimeBuffer(&timeBuffer); 227 228 // Also setup each of the stages' queues. 229 fetch.setFetchQueue(&fetchQueue); 230 decode.setFetchQueue(&fetchQueue); 231 commit.setFetchQueue(&fetchQueue); 232 decode.setDecodeQueue(&decodeQueue); 233 rename.setDecodeQueue(&decodeQueue); 234 rename.setRenameQueue(&renameQueue); 235 iew.setRenameQueue(&renameQueue); 236 iew.setIEWQueue(&iewQueue); 237 commit.setIEWQueue(&iewQueue); 238 commit.setRenameQueue(&renameQueue); 239 240 commit.setIEWStage(&iew); 241 rename.setIEWStage(&iew); 242 rename.setCommitStage(&commit); 243 244 ThreadID active_threads; 245 if (FullSystem) { 246 active_threads = 1; 247 } else { 248 active_threads = params->workload.size(); 249 250 if (active_threads > Impl::MaxThreads) { 251 panic("Workload Size too large. Increase the 'MaxThreads' " 252 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 253 "or edit your workload size."); 254 } 255 } 256 257 //Make Sure That this a Valid Architeture 258 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 259 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 260 assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs); 261 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs); 262 263 rename.setScoreboard(&scoreboard); 264 iew.setScoreboard(&scoreboard); 265 266 // Setup the rename map for whichever stages need it. 267 for (ThreadID tid = 0; tid < numThreads; tid++) { 268 isa[tid] = params->isa[tid]; 269 assert(initRenameMode<TheISA::ISA>::equals(isa[tid], isa[0])); 270 271 // Only Alpha has an FP zero register, so for other ISAs we 272 // use an invalid FP register index to avoid special treatment 273 // of any valid FP reg. 274 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1; 275 RegIndex fpZeroReg = 276 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg; 277 278 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 279 &freeList, 280 vecMode); 281 282 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 283 &freeList, vecMode); 284 } 285 286 // Initialize rename map to assign physical registers to the 287 // architectural registers for active threads only. 288 for (ThreadID tid = 0; tid < active_threads; tid++) { 289 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) { 290 // Note that we can't use the rename() method because we don't 291 // want special treatment for the zero register at this point 292 PhysRegIdPtr phys_reg = freeList.getIntReg(); 293 renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg); 294 commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg); 295 } 296 297 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) { 298 PhysRegIdPtr phys_reg = freeList.getFloatReg(); 299 renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg); 300 commitRenameMap[tid].setEntry( 301 RegId(FloatRegClass, ridx), phys_reg); 302 } 303 304 /* Here we need two 'interfaces' the 'whole register' and the 305 * 'register element'. At any point only one of them will be 306 * active. */ 307 if (vecMode == Enums::Full) { 308 /* Initialize the full-vector interface */ 309 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) { 310 RegId rid = RegId(VecRegClass, ridx); 311 PhysRegIdPtr phys_reg = freeList.getVecReg(); 312 renameMap[tid].setEntry(rid, phys_reg); 313 commitRenameMap[tid].setEntry(rid, phys_reg); 314 } 315 } else { 316 /* Initialize the vector-element interface */ 317 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) { 318 for (ElemIndex ldx = 0; ldx < TheISA::NumVecElemPerVecReg; 319 ++ldx) { 320 RegId lrid = RegId(VecElemClass, ridx, ldx); 321 PhysRegIdPtr phys_elem = freeList.getVecElem(); 322 renameMap[tid].setEntry(lrid, phys_elem); 323 commitRenameMap[tid].setEntry(lrid, phys_elem); 324 } 325 } 326 } 327 328 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) { 329 PhysRegIdPtr phys_reg = freeList.getCCReg(); 330 renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg); 331 commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg); 332 } 333 } 334 335 rename.setRenameMap(renameMap); 336 commit.setRenameMap(commitRenameMap); 337 rename.setFreeList(&freeList); 338 339 // Setup the ROB for whichever stages need it. 340 commit.setROB(&rob); 341 342 lastActivatedCycle = 0; 343#if 0 344 // Give renameMap & rename stage access to the freeList; 345 for (ThreadID tid = 0; tid < numThreads; tid++) 346 globalSeqNum[tid] = 1; 347#endif 348 349 DPRINTF(O3CPU, "Creating O3CPU object.\n"); 350 351 // Setup any thread state. 352 this->thread.resize(this->numThreads); 353 354 for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 355 if (FullSystem) { 356 // SMT is not supported in FS mode yet. 357 assert(this->numThreads == 1); 358 this->thread[tid] = new Thread(this, 0, NULL); 359 } else { 360 if (tid < params->workload.size()) { 361 DPRINTF(O3CPU, "Workload[%i] process is %#x", 362 tid, this->thread[tid]); 363 this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 364 (typename Impl::O3CPU *)(this), 365 tid, params->workload[tid]); 366 367 //usedTids[tid] = true; 368 //threadMap[tid] = tid; 369 } else { 370 //Allocate Empty thread so M5 can use later 371 //when scheduling threads to CPU 372 Process* dummy_proc = NULL; 373 374 this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 375 (typename Impl::O3CPU *)(this), 376 tid, dummy_proc); 377 //usedTids[tid] = false; 378 } 379 } 380 381 ThreadContext *tc; 382 383 // Setup the TC that will serve as the interface to the threads/CPU. 384 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 385 386 tc = o3_tc; 387 388 // If we're using a checker, then the TC should be the 389 // CheckerThreadContext. 390 if (params->checker) { 391 tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 392 o3_tc, this->checker); 393 } 394 395 o3_tc->cpu = (typename Impl::O3CPU *)(this); 396 assert(o3_tc->cpu); 397 o3_tc->thread = this->thread[tid]; 398 399 // Setup quiesce event. 400 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 401 402 // Give the thread the TC. 403 this->thread[tid]->tc = tc; 404 405 // Add the TC to the CPU's list of TC's. 406 this->threadContexts.push_back(tc); 407 } 408 409 // FullO3CPU always requires an interrupt controller. 410 if (!params->switched_out && interrupts.empty()) { 411 fatal("FullO3CPU %s has no interrupt controller.\n" 412 "Ensure createInterruptController() is called.\n", name()); 413 } 414 415 for (ThreadID tid = 0; tid < this->numThreads; tid++) 416 this->thread[tid]->setFuncExeInst(0); 417} 418 419template <class Impl> 420FullO3CPU<Impl>::~FullO3CPU() 421{ 422} 423 424template <class Impl> 425void 426FullO3CPU<Impl>::regProbePoints() 427{ 428 BaseCPU::regProbePoints(); 429 430 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete"); 431 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete"); 432 433 fetch.regProbePoints(); 434 rename.regProbePoints(); 435 iew.regProbePoints(); 436 commit.regProbePoints(); 437} 438 439template <class Impl> 440void 441FullO3CPU<Impl>::regStats() 442{ 443 BaseO3CPU::regStats(); 444 445 // Register any of the O3CPU's stats here. 446 timesIdled 447 .name(name() + ".timesIdled") 448 .desc("Number of times that the entire CPU went into an idle state and" 449 " unscheduled itself") 450 .prereq(timesIdled); 451 452 idleCycles 453 .name(name() + ".idleCycles") 454 .desc("Total number of cycles that the CPU has spent unscheduled due " 455 "to idling") 456 .prereq(idleCycles); 457 458 quiesceCycles 459 .name(name() + ".quiesceCycles") 460 .desc("Total number of cycles that CPU has spent quiesced or waiting " 461 "for an interrupt") 462 .prereq(quiesceCycles); 463 464 // Number of Instructions simulated 465 // -------------------------------- 466 // Should probably be in Base CPU but need templated 467 // MaxThreads so put in here instead 468 committedInsts 469 .init(numThreads) 470 .name(name() + ".committedInsts") 471 .desc("Number of Instructions Simulated") 472 .flags(Stats::total); 473 474 committedOps 475 .init(numThreads) 476 .name(name() + ".committedOps") 477 .desc("Number of Ops (including micro ops) Simulated") 478 .flags(Stats::total); 479 480 cpi 481 .name(name() + ".cpi") 482 .desc("CPI: Cycles Per Instruction") 483 .precision(6); 484 cpi = numCycles / committedInsts; 485 486 totalCpi 487 .name(name() + ".cpi_total") 488 .desc("CPI: Total CPI of All Threads") 489 .precision(6); 490 totalCpi = numCycles / sum(committedInsts); 491 492 ipc 493 .name(name() + ".ipc") 494 .desc("IPC: Instructions Per Cycle") 495 .precision(6); 496 ipc = committedInsts / numCycles; 497 498 totalIpc 499 .name(name() + ".ipc_total") 500 .desc("IPC: Total IPC of All Threads") 501 .precision(6); 502 totalIpc = sum(committedInsts) / numCycles; 503 504 this->fetch.regStats(); 505 this->decode.regStats(); 506 this->rename.regStats(); 507 this->iew.regStats(); 508 this->commit.regStats(); 509 this->rob.regStats(); 510 511 intRegfileReads 512 .name(name() + ".int_regfile_reads") 513 .desc("number of integer regfile reads") 514 .prereq(intRegfileReads); 515 516 intRegfileWrites 517 .name(name() + ".int_regfile_writes") 518 .desc("number of integer regfile writes") 519 .prereq(intRegfileWrites); 520 521 fpRegfileReads 522 .name(name() + ".fp_regfile_reads") 523 .desc("number of floating regfile reads") 524 .prereq(fpRegfileReads); 525 526 fpRegfileWrites 527 .name(name() + ".fp_regfile_writes") 528 .desc("number of floating regfile writes") 529 .prereq(fpRegfileWrites); 530 531 vecRegfileReads 532 .name(name() + ".vec_regfile_reads") 533 .desc("number of vector regfile reads") 534 .prereq(vecRegfileReads); 535 536 vecRegfileWrites 537 .name(name() + ".vec_regfile_writes") 538 .desc("number of vector regfile writes") 539 .prereq(vecRegfileWrites); 540 541 ccRegfileReads 542 .name(name() + ".cc_regfile_reads") 543 .desc("number of cc regfile reads") 544 .prereq(ccRegfileReads); 545 546 ccRegfileWrites 547 .name(name() + ".cc_regfile_writes") 548 .desc("number of cc regfile writes") 549 .prereq(ccRegfileWrites); 550 551 miscRegfileReads 552 .name(name() + ".misc_regfile_reads") 553 .desc("number of misc regfile reads") 554 .prereq(miscRegfileReads); 555 556 miscRegfileWrites 557 .name(name() + ".misc_regfile_writes") 558 .desc("number of misc regfile writes") 559 .prereq(miscRegfileWrites); 560} 561 562template <class Impl> 563void 564FullO3CPU<Impl>::tick() 565{ 566 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 567 assert(!switchedOut()); 568 assert(drainState() != DrainState::Drained); 569 570 ++numCycles; 571 ppCycles->notify(1); 572 573// activity = false; 574 575 //Tick each of the stages 576 fetch.tick(); 577 578 decode.tick(); 579 580 rename.tick(); 581 582 iew.tick(); 583 584 commit.tick(); 585 586 // Now advance the time buffers 587 timeBuffer.advance(); 588 589 fetchQueue.advance(); 590 decodeQueue.advance(); 591 renameQueue.advance(); 592 iewQueue.advance(); 593 594 activityRec.advance(); 595 596 if (removeInstsThisCycle) { 597 cleanUpRemovedInsts(); 598 } 599 600 if (!tickEvent.scheduled()) { 601 if (_status == SwitchedOut) { 602 DPRINTF(O3CPU, "Switched out!\n"); 603 // increment stat 604 lastRunningCycle = curCycle(); 605 } else if (!activityRec.active() || _status == Idle) { 606 DPRINTF(O3CPU, "Idle!\n"); 607 lastRunningCycle = curCycle(); 608 timesIdled++; 609 } else { 610 schedule(tickEvent, clockEdge(Cycles(1))); 611 DPRINTF(O3CPU, "Scheduling next tick!\n"); 612 } 613 } 614 615 if (!FullSystem) 616 updateThreadPriority(); 617 618 tryDrain(); 619} 620 621template <class Impl> 622void 623FullO3CPU<Impl>::init() 624{ 625 BaseCPU::init(); 626 627 for (ThreadID tid = 0; tid < numThreads; ++tid) { 628 // Set noSquashFromTC so that the CPU doesn't squash when initially 629 // setting up registers. 630 thread[tid]->noSquashFromTC = true; 631 // Initialise the ThreadContext's memory proxies 632 thread[tid]->initMemProxies(thread[tid]->getTC()); 633 } 634 635 if (FullSystem && !params()->switched_out) { 636 for (ThreadID tid = 0; tid < numThreads; tid++) { 637 ThreadContext *src_tc = threadContexts[tid]; 638 TheISA::initCPU(src_tc, src_tc->contextId()); 639 } 640 } 641 642 // Clear noSquashFromTC. 643 for (int tid = 0; tid < numThreads; ++tid) 644 thread[tid]->noSquashFromTC = false; 645 646 commit.setThreads(thread); 647} 648 649template <class Impl> 650void 651FullO3CPU<Impl>::startup() 652{ 653 BaseCPU::startup(); 654 for (int tid = 0; tid < numThreads; ++tid) 655 isa[tid]->startup(threadContexts[tid]); 656 657 fetch.startupStage(); 658 decode.startupStage(); 659 iew.startupStage(); 660 rename.startupStage(); 661 commit.startupStage(); 662} 663 664template <class Impl> 665void 666FullO3CPU<Impl>::activateThread(ThreadID tid) 667{ 668 list<ThreadID>::iterator isActive = 669 std::find(activeThreads.begin(), activeThreads.end(), tid); 670 671 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 672 assert(!switchedOut()); 673 674 if (isActive == activeThreads.end()) { 675 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 676 tid); 677 678 activeThreads.push_back(tid); 679 } 680} 681 682template <class Impl> 683void 684FullO3CPU<Impl>::deactivateThread(ThreadID tid) 685{ 686 //Remove From Active List, if Active 687 list<ThreadID>::iterator thread_it = 688 std::find(activeThreads.begin(), activeThreads.end(), tid); 689 690 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 691 assert(!switchedOut()); 692 693 if (thread_it != activeThreads.end()) { 694 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 695 tid); 696 activeThreads.erase(thread_it); 697 } 698 699 fetch.deactivateThread(tid); 700 commit.deactivateThread(tid); 701} 702 703template <class Impl> 704Counter 705FullO3CPU<Impl>::totalInsts() const 706{ 707 Counter total(0); 708 709 ThreadID size = thread.size(); 710 for (ThreadID i = 0; i < size; i++) 711 total += thread[i]->numInst; 712 713 return total; 714} 715 716template <class Impl> 717Counter 718FullO3CPU<Impl>::totalOps() const 719{ 720 Counter total(0); 721 722 ThreadID size = thread.size(); 723 for (ThreadID i = 0; i < size; i++) 724 total += thread[i]->numOp; 725 726 return total; 727} 728 729template <class Impl> 730void 731FullO3CPU<Impl>::activateContext(ThreadID tid) 732{ 733 assert(!switchedOut()); 734 735 // Needs to set each stage to running as well. 736 activateThread(tid); 737 738 // We don't want to wake the CPU if it is drained. In that case, 739 // we just want to flag the thread as active and schedule the tick 740 // event from drainResume() instead. 741 if (drainState() == DrainState::Drained) 742 return; 743 744 // If we are time 0 or if the last activation time is in the past, 745 // schedule the next tick and wake up the fetch unit 746 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 747 scheduleTickEvent(Cycles(0)); 748 749 // Be sure to signal that there's some activity so the CPU doesn't 750 // deschedule itself. 751 activityRec.activity(); 752 fetch.wakeFromQuiesce(); 753 754 Cycles cycles(curCycle() - lastRunningCycle); 755 // @todo: This is an oddity that is only here to match the stats 756 if (cycles != 0) 757 --cycles; 758 quiesceCycles += cycles; 759 760 lastActivatedCycle = curTick(); 761 762 _status = Running; 763 764 BaseCPU::activateContext(tid); 765 } 766} 767 768template <class Impl> 769void 770FullO3CPU<Impl>::suspendContext(ThreadID tid) 771{ 772 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 773 assert(!switchedOut()); 774 775 deactivateThread(tid); 776 777 // If this was the last thread then unschedule the tick event. 778 if (activeThreads.size() == 0) { 779 unscheduleTickEvent(); 780 lastRunningCycle = curCycle(); 781 _status = Idle; 782 } 783 784 DPRINTF(Quiesce, "Suspending Context\n"); 785 786 BaseCPU::suspendContext(tid); 787} 788 789template <class Impl> 790void 791FullO3CPU<Impl>::haltContext(ThreadID tid) 792{ 793 //For now, this is the same as deallocate 794 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 795 assert(!switchedOut()); 796 797 deactivateThread(tid); 798 removeThread(tid); 799} 800 801template <class Impl> 802void 803FullO3CPU<Impl>::insertThread(ThreadID tid) 804{ 805 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 806 // Will change now that the PC and thread state is internal to the CPU 807 // and not in the ThreadContext. 808 ThreadContext *src_tc; 809 if (FullSystem) 810 src_tc = system->threadContexts[tid]; 811 else 812 src_tc = tcBase(tid); 813 814 //Bind Int Regs to Rename Map 815 816 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs; 817 reg_id.index()++) { 818 PhysRegIdPtr phys_reg = freeList.getIntReg(); 819 renameMap[tid].setEntry(reg_id, phys_reg); 820 scoreboard.setReg(phys_reg); 821 } 822 823 //Bind Float Regs to Rename Map 824 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs; 825 reg_id.index()++) { 826 PhysRegIdPtr phys_reg = freeList.getFloatReg(); 827 renameMap[tid].setEntry(reg_id, phys_reg); 828 scoreboard.setReg(phys_reg); 829 } 830 831 //Bind condition-code Regs to Rename Map 832 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs; 833 reg_id.index()++) { 834 PhysRegIdPtr phys_reg = freeList.getCCReg(); 835 renameMap[tid].setEntry(reg_id, phys_reg); 836 scoreboard.setReg(phys_reg); 837 } 838 839 //Copy Thread Data Into RegFile 840 //this->copyFromTC(tid); 841 842 //Set PC/NPC/NNPC 843 pcState(src_tc->pcState(), tid); 844 845 src_tc->setStatus(ThreadContext::Active); 846 847 activateContext(tid); 848 849 //Reset ROB/IQ/LSQ Entries 850 commit.rob->resetEntries(); 851 iew.resetEntries(); 852} 853 854template <class Impl> 855void 856FullO3CPU<Impl>::removeThread(ThreadID tid) 857{ 858 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 859 860 // Copy Thread Data From RegFile 861 // If thread is suspended, it might be re-allocated 862 // this->copyToTC(tid); 863 864 865 // @todo: 2-27-2008: Fix how we free up rename mappings 866 // here to alleviate the case for double-freeing registers 867 // in SMT workloads. 868 869 // Unbind Int Regs from Rename Map 870 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs; 871 reg_id.index()++) { 872 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id); 873 scoreboard.unsetReg(phys_reg); 874 freeList.addReg(phys_reg); 875 } 876 877 // Unbind Float Regs from Rename Map 878 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs; 879 reg_id.index()++) { 880 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id); 881 scoreboard.unsetReg(phys_reg); 882 freeList.addReg(phys_reg); 883 } 884 885 // Unbind condition-code Regs from Rename Map 886 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs; 887 reg_id.index()++) { 888 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id); 889 scoreboard.unsetReg(phys_reg); 890 freeList.addReg(phys_reg); 891 } 892 893 // Squash Throughout Pipeline 894 DynInstPtr inst = commit.rob->readHeadInst(tid); 895 InstSeqNum squash_seq_num = inst->seqNum; 896 fetch.squash(0, squash_seq_num, inst, tid); 897 decode.squash(tid); 898 rename.squash(squash_seq_num, tid); 899 iew.squash(tid); 900 iew.ldstQueue.squash(squash_seq_num, tid); 901 commit.rob->squash(squash_seq_num, tid); 902 903 904 assert(iew.instQueue.getCount(tid) == 0); 905 assert(iew.ldstQueue.getCount(tid) == 0); 906 907 // Reset ROB/IQ/LSQ Entries 908 909 // Commented out for now. This should be possible to do by 910 // telling all the pipeline stages to drain first, and then 911 // checking until the drain completes. Once the pipeline is 912 // drained, call resetEntries(). - 10-09-06 ktlim 913/* 914 if (activeThreads.size() >= 1) { 915 commit.rob->resetEntries(); 916 iew.resetEntries(); 917 } 918*/ 919} 920 921template <class Impl> 922Fault 923FullO3CPU<Impl>::hwrei(ThreadID tid) 924{ 925#if THE_ISA == ALPHA_ISA 926 // Need to clear the lock flag upon returning from an interrupt. 927 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 928 929 this->thread[tid]->kernelStats->hwrei(); 930 931 // FIXME: XXX check for interrupts? XXX 932#endif 933 return NoFault; 934} 935 936template <class Impl> 937bool 938FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 939{ 940#if THE_ISA == ALPHA_ISA 941 if (this->thread[tid]->kernelStats) 942 this->thread[tid]->kernelStats->callpal(palFunc, 943 this->threadContexts[tid]); 944 945 switch (palFunc) { 946 case PAL::halt: 947 halt(); 948 if (--System::numSystemsRunning == 0) 949 exitSimLoop("all cpus halted"); 950 break; 951 952 case PAL::bpt: 953 case PAL::bugchk: 954 if (this->system->breakpoint()) 955 return false; 956 break; 957 } 958#endif 959 return true; 960} 961 962template <class Impl> 963Fault 964FullO3CPU<Impl>::getInterrupts() 965{ 966 // Check if there are any outstanding interrupts 967 return this->interrupts[0]->getInterrupt(this->threadContexts[0]); 968} 969 970template <class Impl> 971void 972FullO3CPU<Impl>::processInterrupts(const Fault &interrupt) 973{ 974 // Check for interrupts here. For now can copy the code that 975 // exists within isa_fullsys_traits.hh. Also assume that thread 0 976 // is the one that handles the interrupts. 977 // @todo: Possibly consolidate the interrupt checking code. 978 // @todo: Allow other threads to handle interrupts. 979 980 assert(interrupt != NoFault); 981 this->interrupts[0]->updateIntrInfo(this->threadContexts[0]); 982 983 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 984 this->trap(interrupt, 0, nullptr); 985} 986 987template <class Impl> 988void 989FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid, 990 const StaticInstPtr &inst) 991{ 992 // Pass the thread's TC into the invoke method. 993 fault->invoke(this->threadContexts[tid], inst); 994} 995 996template <class Impl> 997void 998FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault) 999{ 1000 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 1001 1002 DPRINTF(Activity,"Activity: syscall() called.\n"); 1003 1004 // Temporarily increase this by one to account for the syscall 1005 // instruction. 1006 ++(this->thread[tid]->funcExeInst); 1007 1008 // Execute the actual syscall. 1009 this->thread[tid]->syscall(callnum, fault); 1010 1011 // Decrease funcExeInst by one as the normal commit will handle 1012 // incrementing it. 1013 --(this->thread[tid]->funcExeInst); 1014} 1015 1016template <class Impl> 1017void 1018FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const 1019{ 1020 thread[tid]->serialize(cp); 1021} 1022 1023template <class Impl> 1024void 1025FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid) 1026{ 1027 thread[tid]->unserialize(cp); 1028} 1029 1030template <class Impl> 1031DrainState 1032FullO3CPU<Impl>::drain() 1033{ 1034 // If the CPU isn't doing anything, then return immediately. 1035 if (switchedOut()) 1036 return DrainState::Drained; 1037 1038 DPRINTF(Drain, "Draining...\n"); 1039 1040 // We only need to signal a drain to the commit stage as this 1041 // initiates squashing controls the draining. Once the commit 1042 // stage commits an instruction where it is safe to stop, it'll 1043 // squash the rest of the instructions in the pipeline and force 1044 // the fetch stage to stall. The pipeline will be drained once all 1045 // in-flight instructions have retired. 1046 commit.drain(); 1047 1048 // Wake the CPU and record activity so everything can drain out if 1049 // the CPU was not able to immediately drain. 1050 if (!isDrained()) { 1051 // If a thread is suspended, wake it up so it can be drained 1052 for (auto t : threadContexts) { 1053 if (t->status() == ThreadContext::Suspended){ 1054 DPRINTF(Drain, "Currently suspended so activate %i \n", 1055 t->threadId()); 1056 t->activate(); 1057 // As the thread is now active, change the power state as well 1058 activateContext(t->threadId()); 1059 } 1060 } 1061 1062 wakeCPU(); 1063 activityRec.activity(); 1064 1065 DPRINTF(Drain, "CPU not drained\n"); 1066 1067 return DrainState::Draining; 1068 } else { 1069 DPRINTF(Drain, "CPU is already drained\n"); 1070 if (tickEvent.scheduled()) 1071 deschedule(tickEvent); 1072 1073 // Flush out any old data from the time buffers. In 1074 // particular, there might be some data in flight from the 1075 // fetch stage that isn't visible in any of the CPU buffers we 1076 // test in isDrained(). 1077 for (int i = 0; i < timeBuffer.getSize(); ++i) { 1078 timeBuffer.advance(); 1079 fetchQueue.advance(); 1080 decodeQueue.advance(); 1081 renameQueue.advance(); 1082 iewQueue.advance(); 1083 } 1084 1085 drainSanityCheck(); 1086 return DrainState::Drained; 1087 } 1088} 1089 1090template <class Impl> 1091bool 1092FullO3CPU<Impl>::tryDrain() 1093{ 1094 if (drainState() != DrainState::Draining || !isDrained()) 1095 return false; 1096 1097 if (tickEvent.scheduled()) 1098 deschedule(tickEvent); 1099 1100 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 1101 signalDrainDone(); 1102 1103 return true; 1104} 1105 1106template <class Impl> 1107void 1108FullO3CPU<Impl>::drainSanityCheck() const 1109{ 1110 assert(isDrained()); 1111 fetch.drainSanityCheck(); 1112 decode.drainSanityCheck(); 1113 rename.drainSanityCheck(); 1114 iew.drainSanityCheck(); 1115 commit.drainSanityCheck(); 1116} 1117 1118template <class Impl> 1119bool 1120FullO3CPU<Impl>::isDrained() const 1121{ 1122 bool drained(true); 1123 1124 if (!instList.empty() || !removeList.empty()) { 1125 DPRINTF(Drain, "Main CPU structures not drained.\n"); 1126 drained = false; 1127 } 1128 1129 if (!fetch.isDrained()) { 1130 DPRINTF(Drain, "Fetch not drained.\n"); 1131 drained = false; 1132 } 1133 1134 if (!decode.isDrained()) { 1135 DPRINTF(Drain, "Decode not drained.\n"); 1136 drained = false; 1137 } 1138 1139 if (!rename.isDrained()) { 1140 DPRINTF(Drain, "Rename not drained.\n"); 1141 drained = false; 1142 } 1143 1144 if (!iew.isDrained()) { 1145 DPRINTF(Drain, "IEW not drained.\n"); 1146 drained = false; 1147 } 1148 1149 if (!commit.isDrained()) { 1150 DPRINTF(Drain, "Commit not drained.\n"); 1151 drained = false; 1152 } 1153 1154 return drained; 1155} 1156 1157template <class Impl> 1158void 1159FullO3CPU<Impl>::commitDrained(ThreadID tid) 1160{ 1161 fetch.drainStall(tid); 1162} 1163 1164template <class Impl> 1165void 1166FullO3CPU<Impl>::drainResume() 1167{ 1168 if (switchedOut()) 1169 return; 1170 1171 DPRINTF(Drain, "Resuming...\n"); 1172 verifyMemoryMode(); 1173 1174 fetch.drainResume(); 1175 commit.drainResume(); 1176 1177 _status = Idle; 1178 for (ThreadID i = 0; i < thread.size(); i++) { 1179 if (thread[i]->status() == ThreadContext::Active) { 1180 DPRINTF(Drain, "Activating thread: %i\n", i); 1181 activateThread(i); 1182 _status = Running; 1183 } 1184 } 1185 1186 assert(!tickEvent.scheduled()); 1187 if (_status == Running) 1188 schedule(tickEvent, nextCycle()); 1189} 1190 1191template <class Impl> 1192void 1193FullO3CPU<Impl>::switchOut() 1194{ 1195 DPRINTF(O3CPU, "Switching out\n"); 1196 BaseCPU::switchOut(); 1197 1198 activityRec.reset(); 1199 1200 _status = SwitchedOut; 1201 1202 if (checker) 1203 checker->switchOut(); 1204} 1205 1206template <class Impl> 1207void 1208FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 1209{ 1210 BaseCPU::takeOverFrom(oldCPU); 1211 1212 fetch.takeOverFrom(); 1213 decode.takeOverFrom(); 1214 rename.takeOverFrom(); 1215 iew.takeOverFrom(); 1216 commit.takeOverFrom(); 1217 1218 assert(!tickEvent.scheduled()); 1219 1220 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 1221 if (oldO3CPU) 1222 globalSeqNum = oldO3CPU->globalSeqNum; 1223 1224 lastRunningCycle = curCycle(); 1225 _status = Idle; 1226} 1227 1228template <class Impl> 1229void 1230FullO3CPU<Impl>::verifyMemoryMode() const 1231{ 1232 if (!system->isTimingMode()) { 1233 fatal("The O3 CPU requires the memory system to be in " 1234 "'timing' mode.\n"); 1235 } 1236} 1237 1238template <class Impl> 1239TheISA::MiscReg 1240FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const 1241{ 1242 return this->isa[tid]->readMiscRegNoEffect(misc_reg); 1243} 1244 1245template <class Impl> 1246TheISA::MiscReg 1247FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 1248{ 1249 miscRegfileReads++; 1250 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 1251} 1252 1253template <class Impl> 1254void 1255FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 1256 const TheISA::MiscReg &val, ThreadID tid) 1257{ 1258 this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 1259} 1260 1261template <class Impl> 1262void 1263FullO3CPU<Impl>::setMiscReg(int misc_reg, 1264 const TheISA::MiscReg &val, ThreadID tid) 1265{ 1266 miscRegfileWrites++; 1267 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 1268} 1269 1270template <class Impl> 1271uint64_t 1272FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg) 1273{ 1274 intRegfileReads++; 1275 return regFile.readIntReg(phys_reg); 1276} 1277 1278template <class Impl> 1279FloatReg 1280FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg) 1281{ 1282 fpRegfileReads++; 1283 return regFile.readFloatReg(phys_reg); 1284} 1285 1286template <class Impl> 1287FloatRegBits 1288FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg) 1289{ 1290 fpRegfileReads++; 1291 return regFile.readFloatRegBits(phys_reg); 1292} 1293 1294template <class Impl> 1295auto 1296FullO3CPU<Impl>::readVecReg(PhysRegIdPtr phys_reg) const 1297 -> const VecRegContainer& 1298{ 1299 vecRegfileReads++; 1300 return regFile.readVecReg(phys_reg); 1301} 1302 1303template <class Impl> 1304auto 1305FullO3CPU<Impl>::getWritableVecReg(PhysRegIdPtr phys_reg) 1306 -> VecRegContainer& 1307{ 1308 vecRegfileWrites++; 1309 return regFile.getWritableVecReg(phys_reg); 1310} 1311 1312template <class Impl> 1313auto 1314FullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem& 1315{ 1316 vecRegfileReads++; 1317 return regFile.readVecElem(phys_reg); 1318} 1319 1320template <class Impl> 1321CCReg 1322FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg) 1323{ 1324 ccRegfileReads++; 1325 return regFile.readCCReg(phys_reg); 1326} 1327 1328template <class Impl> 1329void 1330FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val) 1331{ 1332 intRegfileWrites++; 1333 regFile.setIntReg(phys_reg, val); 1334} 1335 1336template <class Impl> 1337void 1338FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, FloatReg val) 1339{ 1340 fpRegfileWrites++; 1341 regFile.setFloatReg(phys_reg, val); 1342} 1343 1344template <class Impl> 1345void 1346FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val) 1347{ 1348 fpRegfileWrites++; 1349 regFile.setFloatRegBits(phys_reg, val); 1350} 1351 1352template <class Impl> 1353void 1354FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) 1355{ 1356 vecRegfileWrites++; 1357 regFile.setVecReg(phys_reg, val); 1358} 1359 1360template <class Impl> 1361void 1362FullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val) 1363{ 1364 vecRegfileWrites++; 1365 regFile.setVecElem(phys_reg, val); 1366} 1367 1368template <class Impl> 1369void 1370FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val) 1371{ 1372 ccRegfileWrites++; 1373 regFile.setCCReg(phys_reg, val); 1374} 1375 1376template <class Impl> 1377uint64_t 1378FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 1379{ 1380 intRegfileReads++; 1381 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1382 RegId(IntRegClass, reg_idx)); 1383 1384 return regFile.readIntReg(phys_reg); 1385} 1386 1387template <class Impl> 1388float 1389FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 1390{ 1391 fpRegfileReads++; 1392 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1393 RegId(FloatRegClass, reg_idx)); 1394 1395 return regFile.readFloatReg(phys_reg); 1396} 1397 1398template <class Impl> 1399uint64_t 1400FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 1401{ 1402 fpRegfileReads++; 1403 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1404 RegId(FloatRegClass, reg_idx)); 1405 1406 return regFile.readFloatRegBits(phys_reg); 1407} 1408 1409template <class Impl> 1410auto 1411FullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const 1412 -> const VecRegContainer& 1413{ 1414 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1415 RegId(VecRegClass, reg_idx)); 1416 return readVecReg(phys_reg); 1417} 1418 1419template <class Impl> 1420auto 1421FullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid) 1422 -> VecRegContainer& 1423{ 1424 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1425 RegId(VecRegClass, reg_idx)); 1426 return getWritableVecReg(phys_reg); 1427} 1428 1429template <class Impl> 1430auto 1431FullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 1432 ThreadID tid) const -> const VecElem& 1433{ 1434 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1435 RegId(VecRegClass, reg_idx, ldx)); 1436 return readVecElem(phys_reg); 1437} 1438 1439template <class Impl> 1440CCReg 1441FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid) 1442{ 1443 ccRegfileReads++; 1444 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1445 RegId(CCRegClass, reg_idx)); 1446 1447 return regFile.readCCReg(phys_reg); 1448} 1449 1450template <class Impl> 1451void 1452FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 1453{ 1454 intRegfileWrites++; 1455 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1456 RegId(IntRegClass, reg_idx)); 1457 1458 regFile.setIntReg(phys_reg, val); 1459} 1460 1461template <class Impl> 1462void 1463FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 1464{ 1465 fpRegfileWrites++; 1466 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1467 RegId(FloatRegClass, reg_idx)); 1468 1469 regFile.setFloatReg(phys_reg, val); 1470} 1471 1472template <class Impl> 1473void 1474FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 1475{ 1476 fpRegfileWrites++; 1477 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1478 RegId(FloatRegClass, reg_idx)); 1479 1480 regFile.setFloatRegBits(phys_reg, val); 1481} 1482 1483template <class Impl> 1484void 1485FullO3CPU<Impl>::setArchVecReg(int reg_idx, const VecRegContainer& val, 1486 ThreadID tid) 1487{ 1488 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1489 RegId(VecRegClass, reg_idx)); 1490 setVecReg(phys_reg, val); 1491} 1492 1493template <class Impl> 1494void 1495FullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 1496 const VecElem& val, ThreadID tid) 1497{ 1498 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1499 RegId(VecRegClass, reg_idx, ldx)); 1500 setVecElem(phys_reg, val); 1501} 1502 1503template <class Impl> 1504void 1505FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid) 1506{ 1507 ccRegfileWrites++; 1508 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1509 RegId(CCRegClass, reg_idx)); 1510 1511 regFile.setCCReg(phys_reg, val); 1512} 1513 1514template <class Impl> 1515TheISA::PCState 1516FullO3CPU<Impl>::pcState(ThreadID tid) 1517{ 1518 return commit.pcState(tid); 1519} 1520 1521template <class Impl> 1522void 1523FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 1524{ 1525 commit.pcState(val, tid); 1526} 1527 1528template <class Impl> 1529Addr 1530FullO3CPU<Impl>::instAddr(ThreadID tid) 1531{ 1532 return commit.instAddr(tid); 1533} 1534 1535template <class Impl> 1536Addr 1537FullO3CPU<Impl>::nextInstAddr(ThreadID tid) 1538{ 1539 return commit.nextInstAddr(tid); 1540} 1541 1542template <class Impl> 1543MicroPC 1544FullO3CPU<Impl>::microPC(ThreadID tid) 1545{ 1546 return commit.microPC(tid); 1547} 1548 1549template <class Impl> 1550void 1551FullO3CPU<Impl>::squashFromTC(ThreadID tid) 1552{ 1553 this->thread[tid]->noSquashFromTC = true; 1554 this->commit.generateTCEvent(tid); 1555} 1556 1557template <class Impl> 1558typename FullO3CPU<Impl>::ListIt 1559FullO3CPU<Impl>::addInst(DynInstPtr &inst) 1560{ 1561 instList.push_back(inst); 1562 1563 return --(instList.end()); 1564} 1565 1566template <class Impl> 1567void 1568FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 1569{ 1570 // Keep an instruction count. 1571 if (!inst->isMicroop() || inst->isLastMicroop()) { 1572 thread[tid]->numInst++; 1573 thread[tid]->numInsts++; 1574 committedInsts[tid]++; 1575 system->totalNumInsts++; 1576 1577 // Check for instruction-count-based events. 1578 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 1579 system->instEventQueue.serviceEvents(system->totalNumInsts); 1580 } 1581 thread[tid]->numOp++; 1582 thread[tid]->numOps++; 1583 committedOps[tid]++; 1584 1585 probeInstCommit(inst->staticInst); 1586} 1587 1588template <class Impl> 1589void 1590FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 1591{ 1592 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 1593 "[sn:%lli]\n", 1594 inst->threadNumber, inst->pcState(), inst->seqNum); 1595 1596 removeInstsThisCycle = true; 1597 1598 // Remove the front instruction. 1599 removeList.push(inst->getInstListIt()); 1600} 1601 1602template <class Impl> 1603void 1604FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 1605{ 1606 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 1607 " list.\n", tid); 1608 1609 ListIt end_it; 1610 1611 bool rob_empty = false; 1612 1613 if (instList.empty()) { 1614 return; 1615 } else if (rob.isEmpty(tid)) { 1616 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 1617 end_it = instList.begin(); 1618 rob_empty = true; 1619 } else { 1620 end_it = (rob.readTailInst(tid))->getInstListIt(); 1621 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 1622 } 1623 1624 removeInstsThisCycle = true; 1625 1626 ListIt inst_it = instList.end(); 1627 1628 inst_it--; 1629 1630 // Walk through the instruction list, removing any instructions 1631 // that were inserted after the given instruction iterator, end_it. 1632 while (inst_it != end_it) { 1633 assert(!instList.empty()); 1634 1635 squashInstIt(inst_it, tid); 1636 1637 inst_it--; 1638 } 1639 1640 // If the ROB was empty, then we actually need to remove the first 1641 // instruction as well. 1642 if (rob_empty) { 1643 squashInstIt(inst_it, tid); 1644 } 1645} 1646 1647template <class Impl> 1648void 1649FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 1650{ 1651 assert(!instList.empty()); 1652 1653 removeInstsThisCycle = true; 1654 1655 ListIt inst_iter = instList.end(); 1656 1657 inst_iter--; 1658 1659 DPRINTF(O3CPU, "Deleting instructions from instruction " 1660 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 1661 tid, seq_num, (*inst_iter)->seqNum); 1662 1663 while ((*inst_iter)->seqNum > seq_num) { 1664 1665 bool break_loop = (inst_iter == instList.begin()); 1666 1667 squashInstIt(inst_iter, tid); 1668 1669 inst_iter--; 1670 1671 if (break_loop) 1672 break; 1673 } 1674} 1675 1676template <class Impl> 1677inline void 1678FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 1679{ 1680 if ((*instIt)->threadNumber == tid) { 1681 DPRINTF(O3CPU, "Squashing instruction, " 1682 "[tid:%i] [sn:%lli] PC %s\n", 1683 (*instIt)->threadNumber, 1684 (*instIt)->seqNum, 1685 (*instIt)->pcState()); 1686 1687 // Mark it as squashed. 1688 (*instIt)->setSquashed(); 1689 1690 // @todo: Formulate a consistent method for deleting 1691 // instructions from the instruction list 1692 // Remove the instruction from the list. 1693 removeList.push(instIt); 1694 } 1695} 1696 1697template <class Impl> 1698void 1699FullO3CPU<Impl>::cleanUpRemovedInsts() 1700{ 1701 while (!removeList.empty()) { 1702 DPRINTF(O3CPU, "Removing instruction, " 1703 "[tid:%i] [sn:%lli] PC %s\n", 1704 (*removeList.front())->threadNumber, 1705 (*removeList.front())->seqNum, 1706 (*removeList.front())->pcState()); 1707 1708 instList.erase(removeList.front()); 1709 1710 removeList.pop(); 1711 } 1712 1713 removeInstsThisCycle = false; 1714} 1715/* 1716template <class Impl> 1717void 1718FullO3CPU<Impl>::removeAllInsts() 1719{ 1720 instList.clear(); 1721} 1722*/ 1723template <class Impl> 1724void 1725FullO3CPU<Impl>::dumpInsts() 1726{ 1727 int num = 0; 1728 1729 ListIt inst_list_it = instList.begin(); 1730 1731 cprintf("Dumping Instruction List\n"); 1732 1733 while (inst_list_it != instList.end()) { 1734 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 1735 "Squashed:%i\n\n", 1736 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 1737 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 1738 (*inst_list_it)->isSquashed()); 1739 inst_list_it++; 1740 ++num; 1741 } 1742} 1743/* 1744template <class Impl> 1745void 1746FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 1747{ 1748 iew.wakeDependents(inst); 1749} 1750*/ 1751template <class Impl> 1752void 1753FullO3CPU<Impl>::wakeCPU() 1754{ 1755 if (activityRec.active() || tickEvent.scheduled()) { 1756 DPRINTF(Activity, "CPU already running.\n"); 1757 return; 1758 } 1759 1760 DPRINTF(Activity, "Waking up CPU\n"); 1761 1762 Cycles cycles(curCycle() - lastRunningCycle); 1763 // @todo: This is an oddity that is only here to match the stats 1764 if (cycles > 1) { 1765 --cycles; 1766 idleCycles += cycles; 1767 numCycles += cycles; 1768 ppCycles->notify(cycles); 1769 } 1770 1771 schedule(tickEvent, clockEdge()); 1772} 1773 1774template <class Impl> 1775void 1776FullO3CPU<Impl>::wakeup(ThreadID tid) 1777{ 1778 if (this->thread[tid]->status() != ThreadContext::Suspended) 1779 return; 1780 1781 this->wakeCPU(); 1782 1783 DPRINTF(Quiesce, "Suspended Processor woken\n"); 1784 this->threadContexts[tid]->activate(); 1785} 1786 1787template <class Impl> 1788ThreadID 1789FullO3CPU<Impl>::getFreeTid() 1790{ 1791 for (ThreadID tid = 0; tid < numThreads; tid++) { 1792 if (!tids[tid]) { 1793 tids[tid] = true; 1794 return tid; 1795 } 1796 } 1797 1798 return InvalidThreadID; 1799} 1800 1801template <class Impl> 1802void 1803FullO3CPU<Impl>::updateThreadPriority() 1804{ 1805 if (activeThreads.size() > 1) { 1806 //DEFAULT TO ROUND ROBIN SCHEME 1807 //e.g. Move highest priority to end of thread list 1808 list<ThreadID>::iterator list_begin = activeThreads.begin(); 1809 1810 unsigned high_thread = *list_begin; 1811 1812 activeThreads.erase(list_begin); 1813 1814 activeThreads.push_back(high_thread); 1815 } 1816} 1817 1818// Forward declaration of FullO3CPU. 1819template class FullO3CPU<O3CPUImpl>; 1820