cpu.cc revision 10821 
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 *          Korey Sewell
44 *          Rick Strong
45 */
46
47#include "arch/kernel_stats.hh"
48#include "config/the_isa.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/checker/thread_context.hh"
51#include "cpu/o3/cpu.hh"
52#include "cpu/o3/isa_specific.hh"
53#include "cpu/o3/thread_context.hh"
54#include "cpu/activity.hh"
55#include "cpu/quiesce_event.hh"
56#include "cpu/simple_thread.hh"
57#include "cpu/thread_context.hh"
58#include "debug/Activity.hh"
59#include "debug/Drain.hh"
60#include "debug/O3CPU.hh"
61#include "debug/Quiesce.hh"
62#include "enums/MemoryMode.hh"
63#include "sim/core.hh"
64#include "sim/full_system.hh"
65#include "sim/process.hh"
66#include "sim/stat_control.hh"
67#include "sim/system.hh"
68
69#if THE_ISA == ALPHA_ISA
70#include "arch/alpha/osfpal.hh"
71#include "debug/Activity.hh"
72#endif
73
74struct BaseCPUParams;
75
76using namespace TheISA;
77using namespace std;
78
79BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
80    : BaseCPU(params)
81{
82}
83
84void
85BaseO3CPU::regStats()
86{
87    BaseCPU::regStats();
88}
89
90template<class Impl>
91bool
92FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
93{
94    DPRINTF(O3CPU, "Fetch unit received timing\n");
95    // We shouldn't ever get a cacheable block in ownership state
96    assert(pkt->req->isUncacheable() ||
97           !(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
98    fetch->processCacheCompletion(pkt);
99
100    return true;
101}
102
103template<class Impl>
104void
105FullO3CPU<Impl>::IcachePort::recvReqRetry()
106{
107    fetch->recvReqRetry();
108}
109
110template <class Impl>
111bool
112FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
113{
114    return lsq->recvTimingResp(pkt);
115}
116
117template <class Impl>
118void
119FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
120{
121    // X86 ISA: Snooping an invalidation for monitor/mwait
122    if(cpu->getCpuAddrMonitor()->doMonitor(pkt)) {
123        cpu->wakeup();
124    }
125    lsq->recvTimingSnoopReq(pkt);
126}
127
128template <class Impl>
129void
130FullO3CPU<Impl>::DcachePort::recvReqRetry()
131{
132    lsq->recvReqRetry();
133}
134
135template <class Impl>
136FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
137    : Event(CPU_Tick_Pri), cpu(c)
138{
139}
140
141template <class Impl>
142void
143FullO3CPU<Impl>::TickEvent::process()
144{
145    cpu->tick();
146}
147
148template <class Impl>
149const char *
150FullO3CPU<Impl>::TickEvent::description() const
151{
152    return "FullO3CPU tick";
153}
154
155template <class Impl>
156FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
157    : BaseO3CPU(params),
158      itb(params->itb),
159      dtb(params->dtb),
160      tickEvent(this),
161#ifndef NDEBUG
162      instcount(0),
163#endif
164      removeInstsThisCycle(false),
165      fetch(this, params),
166      decode(this, params),
167      rename(this, params),
168      iew(this, params),
169      commit(this, params),
170
171      regFile(params->numPhysIntRegs,
172              params->numPhysFloatRegs,
173              params->numPhysCCRegs),
174
175      freeList(name() + ".freelist", &regFile),
176
177      rob(this, params),
178
179      scoreboard(name() + ".scoreboard",
180                 regFile.totalNumPhysRegs(), TheISA::NumMiscRegs,
181                 TheISA::ZeroReg, TheISA::ZeroReg),
182
183      isa(numThreads, NULL),
184
185      icachePort(&fetch, this),
186      dcachePort(&iew.ldstQueue, this),
187
188      timeBuffer(params->backComSize, params->forwardComSize),
189      fetchQueue(params->backComSize, params->forwardComSize),
190      decodeQueue(params->backComSize, params->forwardComSize),
191      renameQueue(params->backComSize, params->forwardComSize),
192      iewQueue(params->backComSize, params->forwardComSize),
193      activityRec(name(), NumStages,
194                  params->backComSize + params->forwardComSize,
195                  params->activity),
196
197      globalSeqNum(1),
198      system(params->system),
199      drainManager(NULL),
200      lastRunningCycle(curCycle())
201{
202    if (!params->switched_out) {
203        _status = Running;
204    } else {
205        _status = SwitchedOut;
206    }
207
208    if (params->checker) {
209        BaseCPU *temp_checker = params->checker;
210        checker = dynamic_cast<Checker<Impl> *>(temp_checker);
211        checker->setIcachePort(&icachePort);
212        checker->setSystem(params->system);
213    } else {
214        checker = NULL;
215    }
216
217    if (!FullSystem) {
218        thread.resize(numThreads);
219        tids.resize(numThreads);
220    }
221
222    // The stages also need their CPU pointer setup.  However this
223    // must be done at the upper level CPU because they have pointers
224    // to the upper level CPU, and not this FullO3CPU.
225
226    // Set up Pointers to the activeThreads list for each stage
227    fetch.setActiveThreads(&activeThreads);
228    decode.setActiveThreads(&activeThreads);
229    rename.setActiveThreads(&activeThreads);
230    iew.setActiveThreads(&activeThreads);
231    commit.setActiveThreads(&activeThreads);
232
233    // Give each of the stages the time buffer they will use.
234    fetch.setTimeBuffer(&timeBuffer);
235    decode.setTimeBuffer(&timeBuffer);
236    rename.setTimeBuffer(&timeBuffer);
237    iew.setTimeBuffer(&timeBuffer);
238    commit.setTimeBuffer(&timeBuffer);
239
240    // Also setup each of the stages' queues.
241    fetch.setFetchQueue(&fetchQueue);
242    decode.setFetchQueue(&fetchQueue);
243    commit.setFetchQueue(&fetchQueue);
244    decode.setDecodeQueue(&decodeQueue);
245    rename.setDecodeQueue(&decodeQueue);
246    rename.setRenameQueue(&renameQueue);
247    iew.setRenameQueue(&renameQueue);
248    iew.setIEWQueue(&iewQueue);
249    commit.setIEWQueue(&iewQueue);
250    commit.setRenameQueue(&renameQueue);
251
252    commit.setIEWStage(&iew);
253    rename.setIEWStage(&iew);
254    rename.setCommitStage(&commit);
255
256    ThreadID active_threads;
257    if (FullSystem) {
258        active_threads = 1;
259    } else {
260        active_threads = params->workload.size();
261
262        if (active_threads > Impl::MaxThreads) {
263            panic("Workload Size too large. Increase the 'MaxThreads' "
264                  "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
265                  "or edit your workload size.");
266        }
267    }
268
269    //Make Sure That this a Valid Architeture
270    assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
271    assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
272    assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
273
274    rename.setScoreboard(&scoreboard);
275    iew.setScoreboard(&scoreboard);
276
277    // Setup the rename map for whichever stages need it.
278    for (ThreadID tid = 0; tid < numThreads; tid++) {
279        isa[tid] = params->isa[tid];
280
281        // Only Alpha has an FP zero register, so for other ISAs we
282        // use an invalid FP register index to avoid special treatment
283        // of any valid FP reg.
284        RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
285        RegIndex fpZeroReg =
286            (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
287
288        commitRenameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
289                                  &freeList);
290
291        renameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
292                            &freeList);
293    }
294
295    // Initialize rename map to assign physical registers to the
296    // architectural registers for active threads only.
297    for (ThreadID tid = 0; tid < active_threads; tid++) {
298        for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
299            // Note that we can't use the rename() method because we don't
300            // want special treatment for the zero register at this point
301            PhysRegIndex phys_reg = freeList.getIntReg();
302            renameMap[tid].setIntEntry(ridx, phys_reg);
303            commitRenameMap[tid].setIntEntry(ridx, phys_reg);
304        }
305
306        for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
307            PhysRegIndex phys_reg = freeList.getFloatReg();
308            renameMap[tid].setFloatEntry(ridx, phys_reg);
309            commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
310        }
311
312        for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
313            PhysRegIndex phys_reg = freeList.getCCReg();
314            renameMap[tid].setCCEntry(ridx, phys_reg);
315            commitRenameMap[tid].setCCEntry(ridx, phys_reg);
316        }
317    }
318
319    rename.setRenameMap(renameMap);
320    commit.setRenameMap(commitRenameMap);
321    rename.setFreeList(&freeList);
322
323    // Setup the ROB for whichever stages need it.
324    commit.setROB(&rob);
325
326    lastActivatedCycle = 0;
327#if 0
328    // Give renameMap & rename stage access to the freeList;
329    for (ThreadID tid = 0; tid < numThreads; tid++)
330        globalSeqNum[tid] = 1;
331#endif
332
333    DPRINTF(O3CPU, "Creating O3CPU object.\n");
334
335    // Setup any thread state.
336    this->thread.resize(this->numThreads);
337
338    for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
339        if (FullSystem) {
340            // SMT is not supported in FS mode yet.
341            assert(this->numThreads == 1);
342            this->thread[tid] = new Thread(this, 0, NULL);
343        } else {
344            if (tid < params->workload.size()) {
345                DPRINTF(O3CPU, "Workload[%i] process is %#x",
346                        tid, this->thread[tid]);
347                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
348                        (typename Impl::O3CPU *)(this),
349                        tid, params->workload[tid]);
350
351                //usedTids[tid] = true;
352                //threadMap[tid] = tid;
353            } else {
354                //Allocate Empty thread so M5 can use later
355                //when scheduling threads to CPU
356                Process* dummy_proc = NULL;
357
358                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
359                        (typename Impl::O3CPU *)(this),
360                        tid, dummy_proc);
361                //usedTids[tid] = false;
362            }
363        }
364
365        ThreadContext *tc;
366
367        // Setup the TC that will serve as the interface to the threads/CPU.
368        O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
369
370        tc = o3_tc;
371
372        // If we're using a checker, then the TC should be the
373        // CheckerThreadContext.
374        if (params->checker) {
375            tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
376                o3_tc, this->checker);
377        }
378
379        o3_tc->cpu = (typename Impl::O3CPU *)(this);
380        assert(o3_tc->cpu);
381        o3_tc->thread = this->thread[tid];
382
383        if (FullSystem) {
384            // Setup quiesce event.
385            this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
386        }
387        // Give the thread the TC.
388        this->thread[tid]->tc = tc;
389
390        // Add the TC to the CPU's list of TC's.
391        this->threadContexts.push_back(tc);
392    }
393
394    // FullO3CPU always requires an interrupt controller.
395    if (!params->switched_out && !interrupts) {
396        fatal("FullO3CPU %s has no interrupt controller.\n"
397              "Ensure createInterruptController() is called.\n", name());
398    }
399
400    for (ThreadID tid = 0; tid < this->numThreads; tid++)
401        this->thread[tid]->setFuncExeInst(0);
402}
403
404template <class Impl>
405FullO3CPU<Impl>::~FullO3CPU()
406{
407}
408
409template <class Impl>
410void
411FullO3CPU<Impl>::regProbePoints()
412{
413    BaseCPU::regProbePoints();
414
415    ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
416    ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
417
418    fetch.regProbePoints();
419    iew.regProbePoints();
420    commit.regProbePoints();
421}
422
423template <class Impl>
424void
425FullO3CPU<Impl>::regStats()
426{
427    BaseO3CPU::regStats();
428
429    // Register any of the O3CPU's stats here.
430    timesIdled
431        .name(name() + ".timesIdled")
432        .desc("Number of times that the entire CPU went into an idle state and"
433              " unscheduled itself")
434        .prereq(timesIdled);
435
436    idleCycles
437        .name(name() + ".idleCycles")
438        .desc("Total number of cycles that the CPU has spent unscheduled due "
439              "to idling")
440        .prereq(idleCycles);
441
442    quiesceCycles
443        .name(name() + ".quiesceCycles")
444        .desc("Total number of cycles that CPU has spent quiesced or waiting "
445              "for an interrupt")
446        .prereq(quiesceCycles);
447
448    // Number of Instructions simulated
449    // --------------------------------
450    // Should probably be in Base CPU but need templated
451    // MaxThreads so put in here instead
452    committedInsts
453        .init(numThreads)
454        .name(name() + ".committedInsts")
455        .desc("Number of Instructions Simulated")
456        .flags(Stats::total);
457
458    committedOps
459        .init(numThreads)
460        .name(name() + ".committedOps")
461        .desc("Number of Ops (including micro ops) Simulated")
462        .flags(Stats::total);
463
464    cpi
465        .name(name() + ".cpi")
466        .desc("CPI: Cycles Per Instruction")
467        .precision(6);
468    cpi = numCycles / committedInsts;
469
470    totalCpi
471        .name(name() + ".cpi_total")
472        .desc("CPI: Total CPI of All Threads")
473        .precision(6);
474    totalCpi = numCycles / sum(committedInsts);
475
476    ipc
477        .name(name() + ".ipc")
478        .desc("IPC: Instructions Per Cycle")
479        .precision(6);
480    ipc =  committedInsts / numCycles;
481
482    totalIpc
483        .name(name() + ".ipc_total")
484        .desc("IPC: Total IPC of All Threads")
485        .precision(6);
486    totalIpc =  sum(committedInsts) / numCycles;
487
488    this->fetch.regStats();
489    this->decode.regStats();
490    this->rename.regStats();
491    this->iew.regStats();
492    this->commit.regStats();
493    this->rob.regStats();
494
495    intRegfileReads
496        .name(name() + ".int_regfile_reads")
497        .desc("number of integer regfile reads")
498        .prereq(intRegfileReads);
499
500    intRegfileWrites
501        .name(name() + ".int_regfile_writes")
502        .desc("number of integer regfile writes")
503        .prereq(intRegfileWrites);
504
505    fpRegfileReads
506        .name(name() + ".fp_regfile_reads")
507        .desc("number of floating regfile reads")
508        .prereq(fpRegfileReads);
509
510    fpRegfileWrites
511        .name(name() + ".fp_regfile_writes")
512        .desc("number of floating regfile writes")
513        .prereq(fpRegfileWrites);
514
515    ccRegfileReads
516        .name(name() + ".cc_regfile_reads")
517        .desc("number of cc regfile reads")
518        .prereq(ccRegfileReads);
519
520    ccRegfileWrites
521        .name(name() + ".cc_regfile_writes")
522        .desc("number of cc regfile writes")
523        .prereq(ccRegfileWrites);
524
525    miscRegfileReads
526        .name(name() + ".misc_regfile_reads")
527        .desc("number of misc regfile reads")
528        .prereq(miscRegfileReads);
529
530    miscRegfileWrites
531        .name(name() + ".misc_regfile_writes")
532        .desc("number of misc regfile writes")
533        .prereq(miscRegfileWrites);
534}
535
536template <class Impl>
537void
538FullO3CPU<Impl>::tick()
539{
540    DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
541    assert(!switchedOut());
542    assert(getDrainState() != Drainable::Drained);
543
544    ++numCycles;
545    ppCycles->notify(1);
546
547//    activity = false;
548
549    //Tick each of the stages
550    fetch.tick();
551
552    decode.tick();
553
554    rename.tick();
555
556    iew.tick();
557
558    commit.tick();
559
560    // Now advance the time buffers
561    timeBuffer.advance();
562
563    fetchQueue.advance();
564    decodeQueue.advance();
565    renameQueue.advance();
566    iewQueue.advance();
567
568    activityRec.advance();
569
570    if (removeInstsThisCycle) {
571        cleanUpRemovedInsts();
572    }
573
574    if (!tickEvent.scheduled()) {
575        if (_status == SwitchedOut) {
576            DPRINTF(O3CPU, "Switched out!\n");
577            // increment stat
578            lastRunningCycle = curCycle();
579        } else if (!activityRec.active() || _status == Idle) {
580            DPRINTF(O3CPU, "Idle!\n");
581            lastRunningCycle = curCycle();
582            timesIdled++;
583        } else {
584            schedule(tickEvent, clockEdge(Cycles(1)));
585            DPRINTF(O3CPU, "Scheduling next tick!\n");
586        }
587    }
588
589    if (!FullSystem)
590        updateThreadPriority();
591
592    tryDrain();
593}
594
595template <class Impl>
596void
597FullO3CPU<Impl>::init()
598{
599    BaseCPU::init();
600
601    for (ThreadID tid = 0; tid < numThreads; ++tid) {
602        // Set noSquashFromTC so that the CPU doesn't squash when initially
603        // setting up registers.
604        thread[tid]->noSquashFromTC = true;
605        // Initialise the ThreadContext's memory proxies
606        thread[tid]->initMemProxies(thread[tid]->getTC());
607    }
608
609    if (FullSystem && !params()->switched_out) {
610        for (ThreadID tid = 0; tid < numThreads; tid++) {
611            ThreadContext *src_tc = threadContexts[tid];
612            TheISA::initCPU(src_tc, src_tc->contextId());
613        }
614    }
615
616    // Clear noSquashFromTC.
617    for (int tid = 0; tid < numThreads; ++tid)
618        thread[tid]->noSquashFromTC = false;
619
620    commit.setThreads(thread);
621}
622
623template <class Impl>
624void
625FullO3CPU<Impl>::startup()
626{
627    BaseCPU::startup();
628    for (int tid = 0; tid < numThreads; ++tid)
629        isa[tid]->startup(threadContexts[tid]);
630
631    fetch.startupStage();
632    decode.startupStage();
633    iew.startupStage();
634    rename.startupStage();
635    commit.startupStage();
636}
637
638template <class Impl>
639void
640FullO3CPU<Impl>::activateThread(ThreadID tid)
641{
642    list<ThreadID>::iterator isActive =
643        std::find(activeThreads.begin(), activeThreads.end(), tid);
644
645    DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
646    assert(!switchedOut());
647
648    if (isActive == activeThreads.end()) {
649        DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
650                tid);
651
652        activeThreads.push_back(tid);
653    }
654}
655
656template <class Impl>
657void
658FullO3CPU<Impl>::deactivateThread(ThreadID tid)
659{
660    //Remove From Active List, if Active
661    list<ThreadID>::iterator thread_it =
662        std::find(activeThreads.begin(), activeThreads.end(), tid);
663
664    DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
665    assert(!switchedOut());
666
667    if (thread_it != activeThreads.end()) {
668        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
669                tid);
670        activeThreads.erase(thread_it);
671    }
672
673    fetch.deactivateThread(tid);
674    commit.deactivateThread(tid);
675}
676
677template <class Impl>
678Counter
679FullO3CPU<Impl>::totalInsts() const
680{
681    Counter total(0);
682
683    ThreadID size = thread.size();
684    for (ThreadID i = 0; i < size; i++)
685        total += thread[i]->numInst;
686
687    return total;
688}
689
690template <class Impl>
691Counter
692FullO3CPU<Impl>::totalOps() const
693{
694    Counter total(0);
695
696    ThreadID size = thread.size();
697    for (ThreadID i = 0; i < size; i++)
698        total += thread[i]->numOp;
699
700    return total;
701}
702
703template <class Impl>
704void
705FullO3CPU<Impl>::activateContext(ThreadID tid)
706{
707    assert(!switchedOut());
708
709    // Needs to set each stage to running as well.
710    activateThread(tid);
711
712    // We don't want to wake the CPU if it is drained. In that case,
713    // we just want to flag the thread as active and schedule the tick
714    // event from drainResume() instead.
715    if (getDrainState() == Drainable::Drained)
716        return;
717
718    // If we are time 0 or if the last activation time is in the past,
719    // schedule the next tick and wake up the fetch unit
720    if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
721        scheduleTickEvent(Cycles(0));
722
723        // Be sure to signal that there's some activity so the CPU doesn't
724        // deschedule itself.
725        activityRec.activity();
726        fetch.wakeFromQuiesce();
727
728        Cycles cycles(curCycle() - lastRunningCycle);
729        // @todo: This is an oddity that is only here to match the stats
730        if (cycles != 0)
731            --cycles;
732        quiesceCycles += cycles;
733
734        lastActivatedCycle = curTick();
735
736        _status = Running;
737    }
738}
739
740template <class Impl>
741void
742FullO3CPU<Impl>::suspendContext(ThreadID tid)
743{
744    DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
745    assert(!switchedOut());
746
747    deactivateThread(tid);
748
749    // If this was the last thread then unschedule the tick event.
750    if (activeThreads.size() == 0) {
751        unscheduleTickEvent();
752        lastRunningCycle = curCycle();
753        _status = Idle;
754    }
755
756    DPRINTF(Quiesce, "Suspending Context\n");
757}
758
759template <class Impl>
760void
761FullO3CPU<Impl>::haltContext(ThreadID tid)
762{
763    //For now, this is the same as deallocate
764    DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
765    assert(!switchedOut());
766
767    deactivateThread(tid);
768    removeThread(tid);
769}
770
771template <class Impl>
772void
773FullO3CPU<Impl>::insertThread(ThreadID tid)
774{
775    DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
776    // Will change now that the PC and thread state is internal to the CPU
777    // and not in the ThreadContext.
778    ThreadContext *src_tc;
779    if (FullSystem)
780        src_tc = system->threadContexts[tid];
781    else
782        src_tc = tcBase(tid);
783
784    //Bind Int Regs to Rename Map
785    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
786        PhysRegIndex phys_reg = freeList.getIntReg();
787
788        renameMap[tid].setEntry(ireg,phys_reg);
789        scoreboard.setReg(phys_reg);
790    }
791
792    //Bind Float Regs to Rename Map
793    int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
794    for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
795        PhysRegIndex phys_reg = freeList.getFloatReg();
796
797        renameMap[tid].setEntry(freg,phys_reg);
798        scoreboard.setReg(phys_reg);
799    }
800
801    //Bind condition-code Regs to Rename Map
802    max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
803    for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
804         creg < max_reg; creg++) {
805        PhysRegIndex phys_reg = freeList.getCCReg();
806
807        renameMap[tid].setEntry(creg,phys_reg);
808        scoreboard.setReg(phys_reg);
809    }
810
811    //Copy Thread Data Into RegFile
812    //this->copyFromTC(tid);
813
814    //Set PC/NPC/NNPC
815    pcState(src_tc->pcState(), tid);
816
817    src_tc->setStatus(ThreadContext::Active);
818
819    activateContext(tid);
820
821    //Reset ROB/IQ/LSQ Entries
822    commit.rob->resetEntries();
823    iew.resetEntries();
824}
825
826template <class Impl>
827void
828FullO3CPU<Impl>::removeThread(ThreadID tid)
829{
830    DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
831
832    // Copy Thread Data From RegFile
833    // If thread is suspended, it might be re-allocated
834    // this->copyToTC(tid);
835
836
837    // @todo: 2-27-2008: Fix how we free up rename mappings
838    // here to alleviate the case for double-freeing registers
839    // in SMT workloads.
840
841    // Unbind Int Regs from Rename Map
842    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
843        PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
844        scoreboard.unsetReg(phys_reg);
845        freeList.addReg(phys_reg);
846    }
847
848    // Unbind Float Regs from Rename Map
849    int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
850    for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
851        PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
852        scoreboard.unsetReg(phys_reg);
853        freeList.addReg(phys_reg);
854    }
855
856    // Unbind condition-code Regs from Rename Map
857    max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
858    for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) {
859        PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
860        scoreboard.unsetReg(phys_reg);
861        freeList.addReg(phys_reg);
862    }
863
864    // Squash Throughout Pipeline
865    DynInstPtr inst = commit.rob->readHeadInst(tid);
866    InstSeqNum squash_seq_num = inst->seqNum;
867    fetch.squash(0, squash_seq_num, inst, tid);
868    decode.squash(tid);
869    rename.squash(squash_seq_num, tid);
870    iew.squash(tid);
871    iew.ldstQueue.squash(squash_seq_num, tid);
872    commit.rob->squash(squash_seq_num, tid);
873
874
875    assert(iew.instQueue.getCount(tid) == 0);
876    assert(iew.ldstQueue.getCount(tid) == 0);
877
878    // Reset ROB/IQ/LSQ Entries
879
880    // Commented out for now.  This should be possible to do by
881    // telling all the pipeline stages to drain first, and then
882    // checking until the drain completes.  Once the pipeline is
883    // drained, call resetEntries(). - 10-09-06 ktlim
884/*
885    if (activeThreads.size() >= 1) {
886        commit.rob->resetEntries();
887        iew.resetEntries();
888    }
889*/
890}
891
892template <class Impl>
893Fault
894FullO3CPU<Impl>::hwrei(ThreadID tid)
895{
896#if THE_ISA == ALPHA_ISA
897    // Need to clear the lock flag upon returning from an interrupt.
898    this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
899
900    this->thread[tid]->kernelStats->hwrei();
901
902    // FIXME: XXX check for interrupts? XXX
903#endif
904    return NoFault;
905}
906
907template <class Impl>
908bool
909FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
910{
911#if THE_ISA == ALPHA_ISA
912    if (this->thread[tid]->kernelStats)
913        this->thread[tid]->kernelStats->callpal(palFunc,
914                                                this->threadContexts[tid]);
915
916    switch (palFunc) {
917      case PAL::halt:
918        halt();
919        if (--System::numSystemsRunning == 0)
920            exitSimLoop("all cpus halted");
921        break;
922
923      case PAL::bpt:
924      case PAL::bugchk:
925        if (this->system->breakpoint())
926            return false;
927        break;
928    }
929#endif
930    return true;
931}
932
933template <class Impl>
934Fault
935FullO3CPU<Impl>::getInterrupts()
936{
937    // Check if there are any outstanding interrupts
938    return this->interrupts->getInterrupt(this->threadContexts[0]);
939}
940
941template <class Impl>
942void
943FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
944{
945    // Check for interrupts here.  For now can copy the code that
946    // exists within isa_fullsys_traits.hh.  Also assume that thread 0
947    // is the one that handles the interrupts.
948    // @todo: Possibly consolidate the interrupt checking code.
949    // @todo: Allow other threads to handle interrupts.
950
951    assert(interrupt != NoFault);
952    this->interrupts->updateIntrInfo(this->threadContexts[0]);
953
954    DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
955    this->trap(interrupt, 0, nullptr);
956}
957
958template <class Impl>
959void
960FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
961                      const StaticInstPtr &inst)
962{
963    // Pass the thread's TC into the invoke method.
964    fault->invoke(this->threadContexts[tid], inst);
965}
966
967template <class Impl>
968void
969FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
970{
971    DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
972
973    DPRINTF(Activity,"Activity: syscall() called.\n");
974
975    // Temporarily increase this by one to account for the syscall
976    // instruction.
977    ++(this->thread[tid]->funcExeInst);
978
979    // Execute the actual syscall.
980    this->thread[tid]->syscall(callnum);
981
982    // Decrease funcExeInst by one as the normal commit will handle
983    // incrementing it.
984    --(this->thread[tid]->funcExeInst);
985}
986
987template <class Impl>
988void
989FullO3CPU<Impl>::serializeThread(std::ostream &os, ThreadID tid)
990{
991    thread[tid]->serialize(os);
992}
993
994template <class Impl>
995void
996FullO3CPU<Impl>::unserializeThread(Checkpoint *cp, const std::string &section,
997                                   ThreadID tid)
998{
999    thread[tid]->unserialize(cp, section);
1000}
1001
1002template <class Impl>
1003unsigned int
1004FullO3CPU<Impl>::drain(DrainManager *drain_manager)
1005{
1006    // If the CPU isn't doing anything, then return immediately.
1007    if (switchedOut()) {
1008        setDrainState(Drainable::Drained);
1009        return 0;
1010    }
1011
1012    DPRINTF(Drain, "Draining...\n");
1013    setDrainState(Drainable::Draining);
1014
1015    // We only need to signal a drain to the commit stage as this
1016    // initiates squashing controls the draining. Once the commit
1017    // stage commits an instruction where it is safe to stop, it'll
1018    // squash the rest of the instructions in the pipeline and force
1019    // the fetch stage to stall. The pipeline will be drained once all
1020    // in-flight instructions have retired.
1021    commit.drain();
1022
1023    // Wake the CPU and record activity so everything can drain out if
1024    // the CPU was not able to immediately drain.
1025    if (!isDrained())  {
1026        drainManager = drain_manager;
1027
1028        wakeCPU();
1029        activityRec.activity();
1030
1031        DPRINTF(Drain, "CPU not drained\n");
1032
1033        return 1;
1034    } else {
1035        setDrainState(Drainable::Drained);
1036        DPRINTF(Drain, "CPU is already drained\n");
1037        if (tickEvent.scheduled())
1038            deschedule(tickEvent);
1039
1040        // Flush out any old data from the time buffers.  In
1041        // particular, there might be some data in flight from the
1042        // fetch stage that isn't visible in any of the CPU buffers we
1043        // test in isDrained().
1044        for (int i = 0; i < timeBuffer.getSize(); ++i) {
1045            timeBuffer.advance();
1046            fetchQueue.advance();
1047            decodeQueue.advance();
1048            renameQueue.advance();
1049            iewQueue.advance();
1050        }
1051
1052        drainSanityCheck();
1053        return 0;
1054    }
1055}
1056
1057template <class Impl>
1058bool
1059FullO3CPU<Impl>::tryDrain()
1060{
1061    if (!drainManager || !isDrained())
1062        return false;
1063
1064    if (tickEvent.scheduled())
1065        deschedule(tickEvent);
1066
1067    DPRINTF(Drain, "CPU done draining, processing drain event\n");
1068    drainManager->signalDrainDone();
1069    drainManager = NULL;
1070
1071    return true;
1072}
1073
1074template <class Impl>
1075void
1076FullO3CPU<Impl>::drainSanityCheck() const
1077{
1078    assert(isDrained());
1079    fetch.drainSanityCheck();
1080    decode.drainSanityCheck();
1081    rename.drainSanityCheck();
1082    iew.drainSanityCheck();
1083    commit.drainSanityCheck();
1084}
1085
1086template <class Impl>
1087bool
1088FullO3CPU<Impl>::isDrained() const
1089{
1090    bool drained(true);
1091
1092    if (!instList.empty() || !removeList.empty()) {
1093        DPRINTF(Drain, "Main CPU structures not drained.\n");
1094        drained = false;
1095    }
1096
1097    if (!fetch.isDrained()) {
1098        DPRINTF(Drain, "Fetch not drained.\n");
1099        drained = false;
1100    }
1101
1102    if (!decode.isDrained()) {
1103        DPRINTF(Drain, "Decode not drained.\n");
1104        drained = false;
1105    }
1106
1107    if (!rename.isDrained()) {
1108        DPRINTF(Drain, "Rename not drained.\n");
1109        drained = false;
1110    }
1111
1112    if (!iew.isDrained()) {
1113        DPRINTF(Drain, "IEW not drained.\n");
1114        drained = false;
1115    }
1116
1117    if (!commit.isDrained()) {
1118        DPRINTF(Drain, "Commit not drained.\n");
1119        drained = false;
1120    }
1121
1122    return drained;
1123}
1124
1125template <class Impl>
1126void
1127FullO3CPU<Impl>::commitDrained(ThreadID tid)
1128{
1129    fetch.drainStall(tid);
1130}
1131
1132template <class Impl>
1133void
1134FullO3CPU<Impl>::drainResume()
1135{
1136    setDrainState(Drainable::Running);
1137    if (switchedOut())
1138        return;
1139
1140    DPRINTF(Drain, "Resuming...\n");
1141    verifyMemoryMode();
1142
1143    fetch.drainResume();
1144    commit.drainResume();
1145
1146    _status = Idle;
1147    for (ThreadID i = 0; i < thread.size(); i++) {
1148        if (thread[i]->status() == ThreadContext::Active) {
1149            DPRINTF(Drain, "Activating thread: %i\n", i);
1150            activateThread(i);
1151            _status = Running;
1152        }
1153    }
1154
1155    assert(!tickEvent.scheduled());
1156    if (_status == Running)
1157        schedule(tickEvent, nextCycle());
1158}
1159
1160template <class Impl>
1161void
1162FullO3CPU<Impl>::switchOut()
1163{
1164    DPRINTF(O3CPU, "Switching out\n");
1165    BaseCPU::switchOut();
1166
1167    activityRec.reset();
1168
1169    _status = SwitchedOut;
1170
1171    if (checker)
1172        checker->switchOut();
1173}
1174
1175template <class Impl>
1176void
1177FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1178{
1179    BaseCPU::takeOverFrom(oldCPU);
1180
1181    fetch.takeOverFrom();
1182    decode.takeOverFrom();
1183    rename.takeOverFrom();
1184    iew.takeOverFrom();
1185    commit.takeOverFrom();
1186
1187    assert(!tickEvent.scheduled());
1188
1189    FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1190    if (oldO3CPU)
1191        globalSeqNum = oldO3CPU->globalSeqNum;
1192
1193    lastRunningCycle = curCycle();
1194    _status = Idle;
1195}
1196
1197template <class Impl>
1198void
1199FullO3CPU<Impl>::verifyMemoryMode() const
1200{
1201    if (!system->isTimingMode()) {
1202        fatal("The O3 CPU requires the memory system to be in "
1203              "'timing' mode.\n");
1204    }
1205}
1206
1207template <class Impl>
1208TheISA::MiscReg
1209FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1210{
1211    return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1212}
1213
1214template <class Impl>
1215TheISA::MiscReg
1216FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1217{
1218    miscRegfileReads++;
1219    return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1220}
1221
1222template <class Impl>
1223void
1224FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1225        const TheISA::MiscReg &val, ThreadID tid)
1226{
1227    this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1228}
1229
1230template <class Impl>
1231void
1232FullO3CPU<Impl>::setMiscReg(int misc_reg,
1233        const TheISA::MiscReg &val, ThreadID tid)
1234{
1235    miscRegfileWrites++;
1236    this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1237}
1238
1239template <class Impl>
1240uint64_t
1241FullO3CPU<Impl>::readIntReg(int reg_idx)
1242{
1243    intRegfileReads++;
1244    return regFile.readIntReg(reg_idx);
1245}
1246
1247template <class Impl>
1248FloatReg
1249FullO3CPU<Impl>::readFloatReg(int reg_idx)
1250{
1251    fpRegfileReads++;
1252    return regFile.readFloatReg(reg_idx);
1253}
1254
1255template <class Impl>
1256FloatRegBits
1257FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1258{
1259    fpRegfileReads++;
1260    return regFile.readFloatRegBits(reg_idx);
1261}
1262
1263template <class Impl>
1264CCReg
1265FullO3CPU<Impl>::readCCReg(int reg_idx)
1266{
1267    ccRegfileReads++;
1268    return regFile.readCCReg(reg_idx);
1269}
1270
1271template <class Impl>
1272void
1273FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1274{
1275    intRegfileWrites++;
1276    regFile.setIntReg(reg_idx, val);
1277}
1278
1279template <class Impl>
1280void
1281FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1282{
1283    fpRegfileWrites++;
1284    regFile.setFloatReg(reg_idx, val);
1285}
1286
1287template <class Impl>
1288void
1289FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1290{
1291    fpRegfileWrites++;
1292    regFile.setFloatRegBits(reg_idx, val);
1293}
1294
1295template <class Impl>
1296void
1297FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val)
1298{
1299    ccRegfileWrites++;
1300    regFile.setCCReg(reg_idx, val);
1301}
1302
1303template <class Impl>
1304uint64_t
1305FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1306{
1307    intRegfileReads++;
1308    PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1309
1310    return regFile.readIntReg(phys_reg);
1311}
1312
1313template <class Impl>
1314float
1315FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1316{
1317    fpRegfileReads++;
1318    PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1319
1320    return regFile.readFloatReg(phys_reg);
1321}
1322
1323template <class Impl>
1324uint64_t
1325FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1326{
1327    fpRegfileReads++;
1328    PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1329
1330    return regFile.readFloatRegBits(phys_reg);
1331}
1332
1333template <class Impl>
1334CCReg
1335FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1336{
1337    ccRegfileReads++;
1338    PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1339
1340    return regFile.readCCReg(phys_reg);
1341}
1342
1343template <class Impl>
1344void
1345FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1346{
1347    intRegfileWrites++;
1348    PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1349
1350    regFile.setIntReg(phys_reg, val);
1351}
1352
1353template <class Impl>
1354void
1355FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1356{
1357    fpRegfileWrites++;
1358    PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1359
1360    regFile.setFloatReg(phys_reg, val);
1361}
1362
1363template <class Impl>
1364void
1365FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1366{
1367    fpRegfileWrites++;
1368    PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1369
1370    regFile.setFloatRegBits(phys_reg, val);
1371}
1372
1373template <class Impl>
1374void
1375FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1376{
1377    ccRegfileWrites++;
1378    PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1379
1380    regFile.setCCReg(phys_reg, val);
1381}
1382
1383template <class Impl>
1384TheISA::PCState
1385FullO3CPU<Impl>::pcState(ThreadID tid)
1386{
1387    return commit.pcState(tid);
1388}
1389
1390template <class Impl>
1391void
1392FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1393{
1394    commit.pcState(val, tid);
1395}
1396
1397template <class Impl>
1398Addr
1399FullO3CPU<Impl>::instAddr(ThreadID tid)
1400{
1401    return commit.instAddr(tid);
1402}
1403
1404template <class Impl>
1405Addr
1406FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1407{
1408    return commit.nextInstAddr(tid);
1409}
1410
1411template <class Impl>
1412MicroPC
1413FullO3CPU<Impl>::microPC(ThreadID tid)
1414{
1415    return commit.microPC(tid);
1416}
1417
1418template <class Impl>
1419void
1420FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1421{
1422    this->thread[tid]->noSquashFromTC = true;
1423    this->commit.generateTCEvent(tid);
1424}
1425
1426template <class Impl>
1427typename FullO3CPU<Impl>::ListIt
1428FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1429{
1430    instList.push_back(inst);
1431
1432    return --(instList.end());
1433}
1434
1435template <class Impl>
1436void
1437FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1438{
1439    // Keep an instruction count.
1440    if (!inst->isMicroop() || inst->isLastMicroop()) {
1441        thread[tid]->numInst++;
1442        thread[tid]->numInsts++;
1443        committedInsts[tid]++;
1444        system->totalNumInsts++;
1445
1446        // Check for instruction-count-based events.
1447        comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1448        system->instEventQueue.serviceEvents(system->totalNumInsts);
1449    }
1450    thread[tid]->numOp++;
1451    thread[tid]->numOps++;
1452    committedOps[tid]++;
1453
1454    probeInstCommit(inst->staticInst);
1455}
1456
1457template <class Impl>
1458void
1459FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1460{
1461    DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1462            "[sn:%lli]\n",
1463            inst->threadNumber, inst->pcState(), inst->seqNum);
1464
1465    removeInstsThisCycle = true;
1466
1467    // Remove the front instruction.
1468    removeList.push(inst->getInstListIt());
1469}
1470
1471template <class Impl>
1472void
1473FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1474{
1475    DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1476            " list.\n", tid);
1477
1478    ListIt end_it;
1479
1480    bool rob_empty = false;
1481
1482    if (instList.empty()) {
1483        return;
1484    } else if (rob.isEmpty(tid)) {
1485        DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1486        end_it = instList.begin();
1487        rob_empty = true;
1488    } else {
1489        end_it = (rob.readTailInst(tid))->getInstListIt();
1490        DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1491    }
1492
1493    removeInstsThisCycle = true;
1494
1495    ListIt inst_it = instList.end();
1496
1497    inst_it--;
1498
1499    // Walk through the instruction list, removing any instructions
1500    // that were inserted after the given instruction iterator, end_it.
1501    while (inst_it != end_it) {
1502        assert(!instList.empty());
1503
1504        squashInstIt(inst_it, tid);
1505
1506        inst_it--;
1507    }
1508
1509    // If the ROB was empty, then we actually need to remove the first
1510    // instruction as well.
1511    if (rob_empty) {
1512        squashInstIt(inst_it, tid);
1513    }
1514}
1515
1516template <class Impl>
1517void
1518FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1519{
1520    assert(!instList.empty());
1521
1522    removeInstsThisCycle = true;
1523
1524    ListIt inst_iter = instList.end();
1525
1526    inst_iter--;
1527
1528    DPRINTF(O3CPU, "Deleting instructions from instruction "
1529            "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1530            tid, seq_num, (*inst_iter)->seqNum);
1531
1532    while ((*inst_iter)->seqNum > seq_num) {
1533
1534        bool break_loop = (inst_iter == instList.begin());
1535
1536        squashInstIt(inst_iter, tid);
1537
1538        inst_iter--;
1539
1540        if (break_loop)
1541            break;
1542    }
1543}
1544
1545template <class Impl>
1546inline void
1547FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1548{
1549    if ((*instIt)->threadNumber == tid) {
1550        DPRINTF(O3CPU, "Squashing instruction, "
1551                "[tid:%i] [sn:%lli] PC %s\n",
1552                (*instIt)->threadNumber,
1553                (*instIt)->seqNum,
1554                (*instIt)->pcState());
1555
1556        // Mark it as squashed.
1557        (*instIt)->setSquashed();
1558
1559        // @todo: Formulate a consistent method for deleting
1560        // instructions from the instruction list
1561        // Remove the instruction from the list.
1562        removeList.push(instIt);
1563    }
1564}
1565
1566template <class Impl>
1567void
1568FullO3CPU<Impl>::cleanUpRemovedInsts()
1569{
1570    while (!removeList.empty()) {
1571        DPRINTF(O3CPU, "Removing instruction, "
1572                "[tid:%i] [sn:%lli] PC %s\n",
1573                (*removeList.front())->threadNumber,
1574                (*removeList.front())->seqNum,
1575                (*removeList.front())->pcState());
1576
1577        instList.erase(removeList.front());
1578
1579        removeList.pop();
1580    }
1581
1582    removeInstsThisCycle = false;
1583}
1584/*
1585template <class Impl>
1586void
1587FullO3CPU<Impl>::removeAllInsts()
1588{
1589    instList.clear();
1590}
1591*/
1592template <class Impl>
1593void
1594FullO3CPU<Impl>::dumpInsts()
1595{
1596    int num = 0;
1597
1598    ListIt inst_list_it = instList.begin();
1599
1600    cprintf("Dumping Instruction List\n");
1601
1602    while (inst_list_it != instList.end()) {
1603        cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1604                "Squashed:%i\n\n",
1605                num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1606                (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1607                (*inst_list_it)->isSquashed());
1608        inst_list_it++;
1609        ++num;
1610    }
1611}
1612/*
1613template <class Impl>
1614void
1615FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1616{
1617    iew.wakeDependents(inst);
1618}
1619*/
1620template <class Impl>
1621void
1622FullO3CPU<Impl>::wakeCPU()
1623{
1624    if (activityRec.active() || tickEvent.scheduled()) {
1625        DPRINTF(Activity, "CPU already running.\n");
1626        return;
1627    }
1628
1629    DPRINTF(Activity, "Waking up CPU\n");
1630
1631    Cycles cycles(curCycle() - lastRunningCycle);
1632    // @todo: This is an oddity that is only here to match the stats
1633    if (cycles > 1) {
1634        --cycles;
1635        idleCycles += cycles;
1636        numCycles += cycles;
1637        ppCycles->notify(cycles);
1638    }
1639
1640    schedule(tickEvent, clockEdge());
1641}
1642
1643template <class Impl>
1644void
1645FullO3CPU<Impl>::wakeup()
1646{
1647    if (this->thread[0]->status() != ThreadContext::Suspended)
1648        return;
1649
1650    this->wakeCPU();
1651
1652    DPRINTF(Quiesce, "Suspended Processor woken\n");
1653    this->threadContexts[0]->activate();
1654}
1655
1656template <class Impl>
1657ThreadID
1658FullO3CPU<Impl>::getFreeTid()
1659{
1660    for (ThreadID tid = 0; tid < numThreads; tid++) {
1661        if (!tids[tid]) {
1662            tids[tid] = true;
1663            return tid;
1664        }
1665    }
1666
1667    return InvalidThreadID;
1668}
1669
1670template <class Impl>
1671void
1672FullO3CPU<Impl>::updateThreadPriority()
1673{
1674    if (activeThreads.size() > 1) {
1675        //DEFAULT TO ROUND ROBIN SCHEME
1676        //e.g. Move highest priority to end of thread list
1677        list<ThreadID>::iterator list_begin = activeThreads.begin();
1678
1679        unsigned high_thread = *list_begin;
1680
1681        activeThreads.erase(list_begin);
1682
1683        activeThreads.push_back(high_thread);
1684    }
1685}
1686
1687// Forward declaration of FullO3CPU.
1688template class FullO3CPU<O3CPUImpl>;
1689