cpu.cc revision 9920
11689SN/A/* 28948Sandreas.hansson@arm.com * Copyright (c) 2011-2012 ARM Limited 39916Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 152325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 167897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432756Sksewell@umich.edu * Korey Sewell 447897Shestness@cs.utexas.edu * Rick Strong 451689SN/A */ 461689SN/A 478779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 498887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 508887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 518229Snate@binkert.org#include "cpu/o3/cpu.hh" 528229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 538229Snate@binkert.org#include "cpu/o3/thread_context.hh" 544762Snate@binkert.org#include "cpu/activity.hh" 558779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 564762Snate@binkert.org#include "cpu/simple_thread.hh" 574762Snate@binkert.org#include "cpu/thread_context.hh" 588232Snate@binkert.org#include "debug/Activity.hh" 599152Satgutier@umich.edu#include "debug/Drain.hh" 608232Snate@binkert.org#include "debug/O3CPU.hh" 618232Snate@binkert.org#include "debug/Quiesce.hh" 624762Snate@binkert.org#include "enums/MemoryMode.hh" 634762Snate@binkert.org#include "sim/core.hh" 648793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 658779Sgblack@eecs.umich.edu#include "sim/process.hh" 664762Snate@binkert.org#include "sim/stat_control.hh" 678460SAli.Saidi@ARM.com#include "sim/system.hh" 684762Snate@binkert.org 695702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 705702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 718232Snate@binkert.org#include "debug/Activity.hh" 725702Ssaidi@eecs.umich.edu#endif 735702Ssaidi@eecs.umich.edu 748737Skoansin.tan@gmail.comstruct BaseCPUParams; 755529Snate@binkert.org 762669Sktlim@umich.eduusing namespace TheISA; 776221Snate@binkert.orgusing namespace std; 781060SN/A 795529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 805712Shsul@eecs.umich.edu : BaseCPU(params) 811060SN/A{ 821060SN/A} 831060SN/A 842292SN/Avoid 852733Sktlim@umich.eduBaseO3CPU::regStats() 862292SN/A{ 872292SN/A BaseCPU::regStats(); 882292SN/A} 892292SN/A 908707Sandreas.hansson@arm.comtemplate<class Impl> 918707Sandreas.hansson@arm.combool 928975Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 938707Sandreas.hansson@arm.com{ 948707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 958948Sandreas.hansson@arm.com // We shouldn't ever get a block in ownership state 968948Sandreas.hansson@arm.com assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 978948Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 988707Sandreas.hansson@arm.com 998707Sandreas.hansson@arm.com return true; 1008707Sandreas.hansson@arm.com} 1018707Sandreas.hansson@arm.com 1028707Sandreas.hansson@arm.comtemplate<class Impl> 1038707Sandreas.hansson@arm.comvoid 1048707Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvRetry() 1058707Sandreas.hansson@arm.com{ 1068707Sandreas.hansson@arm.com fetch->recvRetry(); 1078707Sandreas.hansson@arm.com} 1088707Sandreas.hansson@arm.com 1098707Sandreas.hansson@arm.comtemplate <class Impl> 1108707Sandreas.hansson@arm.combool 1118975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 1128707Sandreas.hansson@arm.com{ 1138975Sandreas.hansson@arm.com return lsq->recvTimingResp(pkt); 1148707Sandreas.hansson@arm.com} 1158707Sandreas.hansson@arm.com 1168707Sandreas.hansson@arm.comtemplate <class Impl> 1178975Sandreas.hansson@arm.comvoid 1188975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 1198948Sandreas.hansson@arm.com{ 1208975Sandreas.hansson@arm.com lsq->recvTimingSnoopReq(pkt); 1218948Sandreas.hansson@arm.com} 1228948Sandreas.hansson@arm.com 1238948Sandreas.hansson@arm.comtemplate <class Impl> 1248707Sandreas.hansson@arm.comvoid 1258707Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvRetry() 1268707Sandreas.hansson@arm.com{ 1278707Sandreas.hansson@arm.com lsq->recvRetry(); 1288707Sandreas.hansson@arm.com} 1298707Sandreas.hansson@arm.com 1301060SN/Atemplate <class Impl> 1311755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 1325606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 1331060SN/A{ 1341060SN/A} 1351060SN/A 1361060SN/Atemplate <class Impl> 1371060SN/Avoid 1381755SN/AFullO3CPU<Impl>::TickEvent::process() 1391060SN/A{ 1401060SN/A cpu->tick(); 1411060SN/A} 1421060SN/A 1431060SN/Atemplate <class Impl> 1441060SN/Aconst char * 1455336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 1461060SN/A{ 1474873Sstever@eecs.umich.edu return "FullO3CPU tick"; 1481060SN/A} 1491060SN/A 1501060SN/Atemplate <class Impl> 1512829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 1525606Snate@binkert.org : Event(CPU_Switch_Pri) 1532829Sksewell@umich.edu{ 1542829Sksewell@umich.edu} 1552829Sksewell@umich.edu 1562829Sksewell@umich.edutemplate <class Impl> 1572829Sksewell@umich.eduvoid 1582829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1592829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1602829Sksewell@umich.edu{ 1612829Sksewell@umich.edu tid = thread_num; 1622829Sksewell@umich.edu cpu = thread_cpu; 1632829Sksewell@umich.edu} 1642829Sksewell@umich.edu 1652829Sksewell@umich.edutemplate <class Impl> 1662829Sksewell@umich.eduvoid 1672829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1682829Sksewell@umich.edu{ 1692829Sksewell@umich.edu cpu->activateThread(tid); 1702829Sksewell@umich.edu} 1712829Sksewell@umich.edu 1722829Sksewell@umich.edutemplate <class Impl> 1732829Sksewell@umich.educonst char * 1745336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1752829Sksewell@umich.edu{ 1764873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1772829Sksewell@umich.edu} 1782829Sksewell@umich.edu 1792829Sksewell@umich.edutemplate <class Impl> 1802875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1815606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1822875Sksewell@umich.edu{ 1832875Sksewell@umich.edu} 1842875Sksewell@umich.edu 1852875Sksewell@umich.edutemplate <class Impl> 1862875Sksewell@umich.eduvoid 1872875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1883859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1892875Sksewell@umich.edu{ 1902875Sksewell@umich.edu tid = thread_num; 1912875Sksewell@umich.edu cpu = thread_cpu; 1923859Sbinkertn@umich.edu remove = false; 1932875Sksewell@umich.edu} 1942875Sksewell@umich.edu 1952875Sksewell@umich.edutemplate <class Impl> 1962875Sksewell@umich.eduvoid 1972875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1982875Sksewell@umich.edu{ 1992875Sksewell@umich.edu cpu->deactivateThread(tid); 2003221Sktlim@umich.edu if (remove) 2013221Sktlim@umich.edu cpu->removeThread(tid); 2022875Sksewell@umich.edu} 2032875Sksewell@umich.edu 2042875Sksewell@umich.edutemplate <class Impl> 2052875Sksewell@umich.educonst char * 2065336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 2072875Sksewell@umich.edu{ 2084873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 2092875Sksewell@umich.edu} 2102875Sksewell@umich.edu 2112875Sksewell@umich.edutemplate <class Impl> 2125595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 2132733Sktlim@umich.edu : BaseO3CPU(params), 2143781Sgblack@eecs.umich.edu itb(params->itb), 2153781Sgblack@eecs.umich.edu dtb(params->dtb), 2161060SN/A tickEvent(this), 2175737Scws3k@cs.virginia.edu#ifndef NDEBUG 2185737Scws3k@cs.virginia.edu instcount(0), 2195737Scws3k@cs.virginia.edu#endif 2202292SN/A removeInstsThisCycle(false), 2215595Sgblack@eecs.umich.edu fetch(this, params), 2225595Sgblack@eecs.umich.edu decode(this, params), 2235595Sgblack@eecs.umich.edu rename(this, params), 2245595Sgblack@eecs.umich.edu iew(this, params), 2255595Sgblack@eecs.umich.edu commit(this, params), 2261060SN/A 2279915Ssteve.reinhardt@amd.com regFile(params->numPhysIntRegs, 2289920Syasuko.eckert@amd.com params->numPhysFloatRegs, 2299920Syasuko.eckert@amd.com params->numPhysCCRegs), 2301060SN/A 2319919Ssteve.reinhardt@amd.com freeList(name() + ".freelist", ®File), 2321060SN/A 2335595Sgblack@eecs.umich.edu rob(this, 2344329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 2352292SN/A params->smtROBPolicy, params->smtROBThreshold, 2365529Snate@binkert.org params->numThreads), 2371060SN/A 2389916Ssteve.reinhardt@amd.com scoreboard(name() + ".scoreboard", 2399916Ssteve.reinhardt@amd.com regFile.totalNumPhysRegs(), TheISA::NumMiscRegs, 2409916Ssteve.reinhardt@amd.com TheISA::ZeroReg, TheISA::ZeroReg), 2411060SN/A 2429384SAndreas.Sandberg@arm.com isa(numThreads, NULL), 2439384SAndreas.Sandberg@arm.com 2448707Sandreas.hansson@arm.com icachePort(&fetch, this), 2458707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 2468707Sandreas.hansson@arm.com 2472873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 2482873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 2492873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 2502873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 2512873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 2525804Snate@binkert.org activityRec(name(), NumStages, 2532873Sktlim@umich.edu params->backComSize + params->forwardComSize, 2542873Sktlim@umich.edu params->activity), 2551060SN/A 2561060SN/A globalSeqNum(1), 2572292SN/A system(params->system), 2589444SAndreas.Sandberg@ARM.com drainManager(NULL), 2599180Sandreas.hansson@arm.com lastRunningCycle(curCycle()) 2601060SN/A{ 2619433SAndreas.Sandberg@ARM.com if (!params->switched_out) { 2623221Sktlim@umich.edu _status = Running; 2633221Sktlim@umich.edu } else { 2649152Satgutier@umich.edu _status = SwitchedOut; 2653221Sktlim@umich.edu } 2661681SN/A 2672794Sktlim@umich.edu if (params->checker) { 2682316SN/A BaseCPU *temp_checker = params->checker; 2698733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 2708707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2712316SN/A checker->setSystem(params->system); 2724598Sbinkertn@umich.edu } else { 2734598Sbinkertn@umich.edu checker = NULL; 2744598Sbinkertn@umich.edu } 2752316SN/A 2768793Sgblack@eecs.umich.edu if (!FullSystem) { 2778793Sgblack@eecs.umich.edu thread.resize(numThreads); 2788793Sgblack@eecs.umich.edu tids.resize(numThreads); 2798793Sgblack@eecs.umich.edu } 2801681SN/A 2812325SN/A // The stages also need their CPU pointer setup. However this 2822325SN/A // must be done at the upper level CPU because they have pointers 2832325SN/A // to the upper level CPU, and not this FullO3CPU. 2841060SN/A 2852292SN/A // Set up Pointers to the activeThreads list for each stage 2862292SN/A fetch.setActiveThreads(&activeThreads); 2872292SN/A decode.setActiveThreads(&activeThreads); 2882292SN/A rename.setActiveThreads(&activeThreads); 2892292SN/A iew.setActiveThreads(&activeThreads); 2902292SN/A commit.setActiveThreads(&activeThreads); 2911060SN/A 2921060SN/A // Give each of the stages the time buffer they will use. 2931060SN/A fetch.setTimeBuffer(&timeBuffer); 2941060SN/A decode.setTimeBuffer(&timeBuffer); 2951060SN/A rename.setTimeBuffer(&timeBuffer); 2961060SN/A iew.setTimeBuffer(&timeBuffer); 2971060SN/A commit.setTimeBuffer(&timeBuffer); 2981060SN/A 2991060SN/A // Also setup each of the stages' queues. 3001060SN/A fetch.setFetchQueue(&fetchQueue); 3011060SN/A decode.setFetchQueue(&fetchQueue); 3022292SN/A commit.setFetchQueue(&fetchQueue); 3031060SN/A decode.setDecodeQueue(&decodeQueue); 3041060SN/A rename.setDecodeQueue(&decodeQueue); 3051060SN/A rename.setRenameQueue(&renameQueue); 3061060SN/A iew.setRenameQueue(&renameQueue); 3071060SN/A iew.setIEWQueue(&iewQueue); 3081060SN/A commit.setIEWQueue(&iewQueue); 3091060SN/A commit.setRenameQueue(&renameQueue); 3101060SN/A 3112292SN/A commit.setIEWStage(&iew); 3122292SN/A rename.setIEWStage(&iew); 3132292SN/A rename.setCommitStage(&commit); 3142292SN/A 3158793Sgblack@eecs.umich.edu ThreadID active_threads; 3168793Sgblack@eecs.umich.edu if (FullSystem) { 3178793Sgblack@eecs.umich.edu active_threads = 1; 3188793Sgblack@eecs.umich.edu } else { 3198793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 3202831Sksewell@umich.edu 3218793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 3228793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 3238793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 3248793Sgblack@eecs.umich.edu "or edit your workload size."); 3258793Sgblack@eecs.umich.edu } 3262831Sksewell@umich.edu } 3272292SN/A 3282316SN/A //Make Sure That this a Valid Architeture 3292292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 3302292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 3319920Syasuko.eckert@amd.com assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs); 3322292SN/A 3332292SN/A rename.setScoreboard(&scoreboard); 3342292SN/A iew.setScoreboard(&scoreboard); 3352292SN/A 3361060SN/A // Setup the rename map for whichever stages need it. 3376221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3389384SAndreas.Sandberg@arm.com isa[tid] = params->isa[tid]; 3399384SAndreas.Sandberg@arm.com 3409919Ssteve.reinhardt@amd.com // Only Alpha has an FP zero register, so for other ISAs we 3419919Ssteve.reinhardt@amd.com // use an invalid FP register index to avoid special treatment 3429919Ssteve.reinhardt@amd.com // of any valid FP reg. 3439919Ssteve.reinhardt@amd.com RegIndex invalidFPReg = TheISA::NumFloatRegs + 1; 3449919Ssteve.reinhardt@amd.com RegIndex fpZeroReg = 3459919Ssteve.reinhardt@amd.com (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg; 3462292SN/A 3479919Ssteve.reinhardt@amd.com commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 3489919Ssteve.reinhardt@amd.com &freeList); 3492292SN/A 3509919Ssteve.reinhardt@amd.com renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 3519919Ssteve.reinhardt@amd.com &freeList); 3523221Sktlim@umich.edu 3533221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3543221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3552292SN/A } 3562292SN/A 3579919Ssteve.reinhardt@amd.com // Initialize rename map to assign physical registers to the 3589919Ssteve.reinhardt@amd.com // architectural registers for active threads only. 3599919Ssteve.reinhardt@amd.com for (ThreadID tid = 0; tid < active_threads; tid++) { 3609919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) { 3619919Ssteve.reinhardt@amd.com // Note that we can't use the rename() method because we don't 3629919Ssteve.reinhardt@amd.com // want special treatment for the zero register at this point 3639919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = freeList.getIntReg(); 3649919Ssteve.reinhardt@amd.com renameMap[tid].setIntEntry(ridx, phys_reg); 3659919Ssteve.reinhardt@amd.com commitRenameMap[tid].setIntEntry(ridx, phys_reg); 3669919Ssteve.reinhardt@amd.com } 3679919Ssteve.reinhardt@amd.com 3689919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) { 3699919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = freeList.getFloatReg(); 3709919Ssteve.reinhardt@amd.com renameMap[tid].setFloatEntry(ridx, phys_reg); 3719919Ssteve.reinhardt@amd.com commitRenameMap[tid].setFloatEntry(ridx, phys_reg); 3729919Ssteve.reinhardt@amd.com } 3739920Syasuko.eckert@amd.com 3749920Syasuko.eckert@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) { 3759920Syasuko.eckert@amd.com PhysRegIndex phys_reg = freeList.getCCReg(); 3769920Syasuko.eckert@amd.com renameMap[tid].setCCEntry(ridx, phys_reg); 3779920Syasuko.eckert@amd.com commitRenameMap[tid].setCCEntry(ridx, phys_reg); 3789920Syasuko.eckert@amd.com } 3799919Ssteve.reinhardt@amd.com } 3809919Ssteve.reinhardt@amd.com 3812292SN/A rename.setRenameMap(renameMap); 3822292SN/A commit.setRenameMap(commitRenameMap); 3831060SN/A rename.setFreeList(&freeList); 3842292SN/A 3851060SN/A // Setup the ROB for whichever stages need it. 3861060SN/A commit.setROB(&rob); 3872292SN/A 3889158Sandreas.hansson@arm.com lastActivatedCycle = 0; 3896221Snate@binkert.org#if 0 3903093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3916221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3926221Snate@binkert.org globalSeqNum[tid] = 1; 3936221Snate@binkert.org#endif 3943093Sksewell@umich.edu 3952292SN/A contextSwitch = false; 3965595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3975595Sgblack@eecs.umich.edu 3985595Sgblack@eecs.umich.edu // Setup any thread state. 3995595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 4005595Sgblack@eecs.umich.edu 4016221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 4028793Sgblack@eecs.umich.edu if (FullSystem) { 4038793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 4048793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 4058793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 4068793Sgblack@eecs.umich.edu } else { 4078793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 4088793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 4098793Sgblack@eecs.umich.edu tid, this->thread[tid]); 4108793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4118793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4128793Sgblack@eecs.umich.edu tid, params->workload[tid]); 4135595Sgblack@eecs.umich.edu 4148793Sgblack@eecs.umich.edu //usedTids[tid] = true; 4158793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 4168793Sgblack@eecs.umich.edu } else { 4178793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 4188793Sgblack@eecs.umich.edu //when scheduling threads to CPU 4198793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 4205595Sgblack@eecs.umich.edu 4218793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4228793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4238793Sgblack@eecs.umich.edu tid, dummy_proc); 4248793Sgblack@eecs.umich.edu //usedTids[tid] = false; 4258793Sgblack@eecs.umich.edu } 4265595Sgblack@eecs.umich.edu } 4275595Sgblack@eecs.umich.edu 4285595Sgblack@eecs.umich.edu ThreadContext *tc; 4295595Sgblack@eecs.umich.edu 4305595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 4315595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 4325595Sgblack@eecs.umich.edu 4335595Sgblack@eecs.umich.edu tc = o3_tc; 4345595Sgblack@eecs.umich.edu 4355595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 4365595Sgblack@eecs.umich.edu // CheckerThreadContext. 4375595Sgblack@eecs.umich.edu if (params->checker) { 4385595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 4395595Sgblack@eecs.umich.edu o3_tc, this->checker); 4405595Sgblack@eecs.umich.edu } 4415595Sgblack@eecs.umich.edu 4425595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 4435595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 4446221Snate@binkert.org o3_tc->thread = this->thread[tid]; 4455595Sgblack@eecs.umich.edu 4468793Sgblack@eecs.umich.edu if (FullSystem) { 4478793Sgblack@eecs.umich.edu // Setup quiesce event. 4488793Sgblack@eecs.umich.edu this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 4498793Sgblack@eecs.umich.edu } 4505595Sgblack@eecs.umich.edu // Give the thread the TC. 4516221Snate@binkert.org this->thread[tid]->tc = tc; 4525595Sgblack@eecs.umich.edu 4535595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4545595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4555595Sgblack@eecs.umich.edu } 4565595Sgblack@eecs.umich.edu 4578876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 4589433SAndreas.Sandberg@ARM.com if (!params->switched_out && !interrupts) { 4598876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 4608876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 4618876Sandreas.hansson@arm.com } 4628876Sandreas.hansson@arm.com 4636221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4646221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4651060SN/A} 4661060SN/A 4671060SN/Atemplate <class Impl> 4681755SN/AFullO3CPU<Impl>::~FullO3CPU() 4691060SN/A{ 4701060SN/A} 4711060SN/A 4721060SN/Atemplate <class Impl> 4731060SN/Avoid 4745595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4751062SN/A{ 4762733Sktlim@umich.edu BaseO3CPU::regStats(); 4772292SN/A 4782733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4792292SN/A timesIdled 4802292SN/A .name(name() + ".timesIdled") 4812292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4822292SN/A " unscheduled itself") 4832292SN/A .prereq(timesIdled); 4842292SN/A 4852292SN/A idleCycles 4862292SN/A .name(name() + ".idleCycles") 4872292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4882292SN/A "to idling") 4892292SN/A .prereq(idleCycles); 4902292SN/A 4918627SAli.Saidi@ARM.com quiesceCycles 4928627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 4938627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 4948627SAli.Saidi@ARM.com "for an interrupt") 4958627SAli.Saidi@ARM.com .prereq(quiesceCycles); 4968627SAli.Saidi@ARM.com 4972292SN/A // Number of Instructions simulated 4982292SN/A // -------------------------------- 4992292SN/A // Should probably be in Base CPU but need templated 5002292SN/A // MaxThreads so put in here instead 5012292SN/A committedInsts 5022292SN/A .init(numThreads) 5032292SN/A .name(name() + ".committedInsts") 5042292SN/A .desc("Number of Instructions Simulated"); 5052292SN/A 5068834Satgutier@umich.edu committedOps 5078834Satgutier@umich.edu .init(numThreads) 5088834Satgutier@umich.edu .name(name() + ".committedOps") 5098834Satgutier@umich.edu .desc("Number of Ops (including micro ops) Simulated"); 5108834Satgutier@umich.edu 5112292SN/A totalCommittedInsts 5122292SN/A .name(name() + ".committedInsts_total") 5132292SN/A .desc("Number of Instructions Simulated"); 5142292SN/A 5152292SN/A cpi 5162292SN/A .name(name() + ".cpi") 5172292SN/A .desc("CPI: Cycles Per Instruction") 5182292SN/A .precision(6); 5194392Sktlim@umich.edu cpi = numCycles / committedInsts; 5202292SN/A 5212292SN/A totalCpi 5222292SN/A .name(name() + ".cpi_total") 5232292SN/A .desc("CPI: Total CPI of All Threads") 5242292SN/A .precision(6); 5254392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 5262292SN/A 5272292SN/A ipc 5282292SN/A .name(name() + ".ipc") 5292292SN/A .desc("IPC: Instructions Per Cycle") 5302292SN/A .precision(6); 5314392Sktlim@umich.edu ipc = committedInsts / numCycles; 5322292SN/A 5332292SN/A totalIpc 5342292SN/A .name(name() + ".ipc_total") 5352292SN/A .desc("IPC: Total IPC of All Threads") 5362292SN/A .precision(6); 5374392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 5382292SN/A 5395595Sgblack@eecs.umich.edu this->fetch.regStats(); 5405595Sgblack@eecs.umich.edu this->decode.regStats(); 5415595Sgblack@eecs.umich.edu this->rename.regStats(); 5425595Sgblack@eecs.umich.edu this->iew.regStats(); 5435595Sgblack@eecs.umich.edu this->commit.regStats(); 5447897Shestness@cs.utexas.edu this->rob.regStats(); 5457897Shestness@cs.utexas.edu 5467897Shestness@cs.utexas.edu intRegfileReads 5477897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 5487897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 5497897Shestness@cs.utexas.edu .prereq(intRegfileReads); 5507897Shestness@cs.utexas.edu 5517897Shestness@cs.utexas.edu intRegfileWrites 5527897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 5537897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 5547897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 5557897Shestness@cs.utexas.edu 5567897Shestness@cs.utexas.edu fpRegfileReads 5577897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 5587897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5597897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5607897Shestness@cs.utexas.edu 5617897Shestness@cs.utexas.edu fpRegfileWrites 5627897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5637897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5647897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5657897Shestness@cs.utexas.edu 5669920Syasuko.eckert@amd.com ccRegfileReads 5679920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_reads") 5689920Syasuko.eckert@amd.com .desc("number of cc regfile reads") 5699920Syasuko.eckert@amd.com .prereq(ccRegfileReads); 5709920Syasuko.eckert@amd.com 5719920Syasuko.eckert@amd.com ccRegfileWrites 5729920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_writes") 5739920Syasuko.eckert@amd.com .desc("number of cc regfile writes") 5749920Syasuko.eckert@amd.com .prereq(ccRegfileWrites); 5759920Syasuko.eckert@amd.com 5767897Shestness@cs.utexas.edu miscRegfileReads 5777897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5787897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5797897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5807897Shestness@cs.utexas.edu 5817897Shestness@cs.utexas.edu miscRegfileWrites 5827897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5837897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5847897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5851062SN/A} 5861062SN/A 5871062SN/Atemplate <class Impl> 5881062SN/Avoid 5891755SN/AFullO3CPU<Impl>::tick() 5901060SN/A{ 5912733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5929444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 5939444SAndreas.Sandberg@ARM.com assert(getDrainState() != Drainable::Drained); 5941060SN/A 5952292SN/A ++numCycles; 5962292SN/A 5972325SN/A// activity = false; 5982292SN/A 5992292SN/A //Tick each of the stages 6001060SN/A fetch.tick(); 6011060SN/A 6021060SN/A decode.tick(); 6031060SN/A 6041060SN/A rename.tick(); 6051060SN/A 6061060SN/A iew.tick(); 6071060SN/A 6081060SN/A commit.tick(); 6091060SN/A 6108793Sgblack@eecs.umich.edu if (!FullSystem) 6118793Sgblack@eecs.umich.edu doContextSwitch(); 6122292SN/A 6132292SN/A // Now advance the time buffers 6141060SN/A timeBuffer.advance(); 6151060SN/A 6161060SN/A fetchQueue.advance(); 6171060SN/A decodeQueue.advance(); 6181060SN/A renameQueue.advance(); 6191060SN/A iewQueue.advance(); 6201060SN/A 6212325SN/A activityRec.advance(); 6222292SN/A 6232292SN/A if (removeInstsThisCycle) { 6242292SN/A cleanUpRemovedInsts(); 6252292SN/A } 6262292SN/A 6272325SN/A if (!tickEvent.scheduled()) { 6289444SAndreas.Sandberg@ARM.com if (_status == SwitchedOut) { 6293226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 6302325SN/A // increment stat 6319179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6323221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 6333226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 6349179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6352325SN/A timesIdled++; 6362325SN/A } else { 6379180Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(Cycles(1))); 6383226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 6392325SN/A } 6402292SN/A } 6412292SN/A 6428793Sgblack@eecs.umich.edu if (!FullSystem) 6438793Sgblack@eecs.umich.edu updateThreadPriority(); 6449444SAndreas.Sandberg@ARM.com 6459444SAndreas.Sandberg@ARM.com tryDrain(); 6461060SN/A} 6471060SN/A 6481060SN/Atemplate <class Impl> 6491060SN/Avoid 6501755SN/AFullO3CPU<Impl>::init() 6511060SN/A{ 6525714Shsul@eecs.umich.edu BaseCPU::init(); 6531060SN/A 6548921Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 6559382SAli.Saidi@ARM.com // Set noSquashFromTC so that the CPU doesn't squash when initially 6568921Sandreas.hansson@arm.com // setting up registers. 6579382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 6588921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 6598921Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 6608921Sandreas.hansson@arm.com } 6612292SN/A 6629433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 6638793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6648793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6658793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6668793Sgblack@eecs.umich.edu } 6676034Ssteve.reinhardt@amd.com } 6682292SN/A 6699382SAli.Saidi@ARM.com // Clear noSquashFromTC. 6706221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6719382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6722292SN/A 6739427SAndreas.Sandberg@ARM.com commit.setThreads(thread); 6749427SAndreas.Sandberg@ARM.com} 6752292SN/A 6769427SAndreas.Sandberg@ARM.comtemplate <class Impl> 6779427SAndreas.Sandberg@ARM.comvoid 6789427SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::startup() 6799427SAndreas.Sandberg@ARM.com{ 6809461Snilay@cs.wisc.edu for (int tid = 0; tid < numThreads; ++tid) 6819461Snilay@cs.wisc.edu isa[tid]->startup(threadContexts[tid]); 6829461Snilay@cs.wisc.edu 6839427SAndreas.Sandberg@ARM.com fetch.startupStage(); 6849444SAndreas.Sandberg@ARM.com decode.startupStage(); 6859427SAndreas.Sandberg@ARM.com iew.startupStage(); 6869427SAndreas.Sandberg@ARM.com rename.startupStage(); 6879427SAndreas.Sandberg@ARM.com commit.startupStage(); 6882292SN/A} 6892292SN/A 6902292SN/Atemplate <class Impl> 6912292SN/Avoid 6926221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6932875Sksewell@umich.edu{ 6946221Snate@binkert.org list<ThreadID>::iterator isActive = 6955314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6962875Sksewell@umich.edu 6973226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6989444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6993226Sktlim@umich.edu 7002875Sksewell@umich.edu if (isActive == activeThreads.end()) { 7012875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 7022875Sksewell@umich.edu tid); 7032875Sksewell@umich.edu 7042875Sksewell@umich.edu activeThreads.push_back(tid); 7052875Sksewell@umich.edu } 7062875Sksewell@umich.edu} 7072875Sksewell@umich.edu 7082875Sksewell@umich.edutemplate <class Impl> 7092875Sksewell@umich.eduvoid 7106221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 7112875Sksewell@umich.edu{ 7122875Sksewell@umich.edu //Remove From Active List, if Active 7136221Snate@binkert.org list<ThreadID>::iterator thread_it = 7145314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 7152875Sksewell@umich.edu 7163226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 7179444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7183226Sktlim@umich.edu 7192875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 7202875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 7212875Sksewell@umich.edu tid); 7222875Sksewell@umich.edu activeThreads.erase(thread_it); 7232875Sksewell@umich.edu } 7242875Sksewell@umich.edu} 7252875Sksewell@umich.edu 7262875Sksewell@umich.edutemplate <class Impl> 7276221Snate@binkert.orgCounter 7288834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 7296221Snate@binkert.org{ 7306221Snate@binkert.org Counter total(0); 7316221Snate@binkert.org 7326221Snate@binkert.org ThreadID size = thread.size(); 7336221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 7346221Snate@binkert.org total += thread[i]->numInst; 7356221Snate@binkert.org 7366221Snate@binkert.org return total; 7376221Snate@binkert.org} 7386221Snate@binkert.org 7396221Snate@binkert.orgtemplate <class Impl> 7408834Satgutier@umich.eduCounter 7418834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 7428834Satgutier@umich.edu{ 7438834Satgutier@umich.edu Counter total(0); 7448834Satgutier@umich.edu 7458834Satgutier@umich.edu ThreadID size = thread.size(); 7468834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 7478834Satgutier@umich.edu total += thread[i]->numOp; 7488834Satgutier@umich.edu 7498834Satgutier@umich.edu return total; 7508834Satgutier@umich.edu} 7518834Satgutier@umich.edu 7528834Satgutier@umich.edutemplate <class Impl> 7532875Sksewell@umich.eduvoid 7549180Sandreas.hansson@arm.comFullO3CPU<Impl>::activateContext(ThreadID tid, Cycles delay) 7552875Sksewell@umich.edu{ 7569444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7579444SAndreas.Sandberg@ARM.com 7582875Sksewell@umich.edu // Needs to set each stage to running as well. 7592875Sksewell@umich.edu if (delay){ 7602875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 7619180Sandreas.hansson@arm.com "on cycle %d\n", tid, clockEdge(delay)); 7622875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 7632875Sksewell@umich.edu } else { 7642875Sksewell@umich.edu activateThread(tid); 7652875Sksewell@umich.edu } 7662875Sksewell@umich.edu 7679444SAndreas.Sandberg@ARM.com // We don't want to wake the CPU if it is drained. In that case, 7689444SAndreas.Sandberg@ARM.com // we just want to flag the thread as active and schedule the tick 7699444SAndreas.Sandberg@ARM.com // event from drainResume() instead. 7709444SAndreas.Sandberg@ARM.com if (getDrainState() == Drainable::Drained) 7719444SAndreas.Sandberg@ARM.com return; 7729444SAndreas.Sandberg@ARM.com 7739158Sandreas.hansson@arm.com // If we are time 0 or if the last activation time is in the past, 7749158Sandreas.hansson@arm.com // schedule the next tick and wake up the fetch unit 7759158Sandreas.hansson@arm.com if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 7762875Sksewell@umich.edu scheduleTickEvent(delay); 7772875Sksewell@umich.edu 7782875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7792875Sksewell@umich.edu // deschedule itself. 7802875Sksewell@umich.edu activityRec.activity(); 7812875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7822875Sksewell@umich.edu 7839180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 7849180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 7859179Sandreas.hansson@arm.com if (cycles != 0) 7869179Sandreas.hansson@arm.com --cycles; 7879179Sandreas.hansson@arm.com quiesceCycles += cycles; 7888627SAli.Saidi@ARM.com 7897823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7902875Sksewell@umich.edu 7912875Sksewell@umich.edu _status = Running; 7922875Sksewell@umich.edu } 7932875Sksewell@umich.edu} 7942875Sksewell@umich.edu 7952875Sksewell@umich.edutemplate <class Impl> 7963221Sktlim@umich.edubool 7978737Skoansin.tan@gmail.comFullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove, 7989180Sandreas.hansson@arm.com Cycles delay) 7992875Sksewell@umich.edu{ 8002875Sksewell@umich.edu // Schedule removal of thread data from CPU 8012875Sksewell@umich.edu if (delay){ 8022875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 8039180Sandreas.hansson@arm.com "on tick %d\n", tid, clockEdge(delay)); 8043221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 8053221Sktlim@umich.edu return false; 8062875Sksewell@umich.edu } else { 8072875Sksewell@umich.edu deactivateThread(tid); 8083221Sktlim@umich.edu if (remove) 8093221Sktlim@umich.edu removeThread(tid); 8103221Sktlim@umich.edu return true; 8112875Sksewell@umich.edu } 8122875Sksewell@umich.edu} 8132875Sksewell@umich.edu 8142875Sksewell@umich.edutemplate <class Impl> 8152875Sksewell@umich.eduvoid 8166221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 8172875Sksewell@umich.edu{ 8182875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 8199444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 8209180Sandreas.hansson@arm.com bool deallocated = scheduleDeallocateContext(tid, false, Cycles(1)); 8213221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 8225570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 8233859Sbinkertn@umich.edu activeThreads.size() == 0) 8242910Sksewell@umich.edu unscheduleTickEvent(); 8258627SAli.Saidi@ARM.com 8268627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 8279179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 8282875Sksewell@umich.edu _status = Idle; 8292875Sksewell@umich.edu} 8302875Sksewell@umich.edu 8312875Sksewell@umich.edutemplate <class Impl> 8322875Sksewell@umich.eduvoid 8336221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 8342875Sksewell@umich.edu{ 8352910Sksewell@umich.edu //For now, this is the same as deallocate 8362910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 8379444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 8389180Sandreas.hansson@arm.com scheduleDeallocateContext(tid, true, Cycles(1)); 8392875Sksewell@umich.edu} 8402875Sksewell@umich.edu 8412875Sksewell@umich.edutemplate <class Impl> 8422875Sksewell@umich.eduvoid 8436221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 8442292SN/A{ 8452847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 8462292SN/A // Will change now that the PC and thread state is internal to the CPU 8472683Sktlim@umich.edu // and not in the ThreadContext. 8488793Sgblack@eecs.umich.edu ThreadContext *src_tc; 8498793Sgblack@eecs.umich.edu if (FullSystem) 8508793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 8518793Sgblack@eecs.umich.edu else 8528793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 8532292SN/A 8542292SN/A //Bind Int Regs to Rename Map 8552292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8562292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 8572292SN/A 8582292SN/A renameMap[tid].setEntry(ireg,phys_reg); 8592292SN/A scoreboard.setReg(phys_reg); 8602292SN/A } 8612292SN/A 8622292SN/A //Bind Float Regs to Rename Map 8639920Syasuko.eckert@amd.com int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 8649920Syasuko.eckert@amd.com for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) { 8652292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 8662292SN/A 8672292SN/A renameMap[tid].setEntry(freg,phys_reg); 8682292SN/A scoreboard.setReg(phys_reg); 8692292SN/A } 8702292SN/A 8719920Syasuko.eckert@amd.com //Bind condition-code Regs to Rename Map 8729920Syasuko.eckert@amd.com max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs; 8739920Syasuko.eckert@amd.com for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 8749920Syasuko.eckert@amd.com creg < max_reg; creg++) { 8759920Syasuko.eckert@amd.com PhysRegIndex phys_reg = freeList.getCCReg(); 8769920Syasuko.eckert@amd.com 8779920Syasuko.eckert@amd.com renameMap[tid].setEntry(creg,phys_reg); 8789920Syasuko.eckert@amd.com scoreboard.setReg(phys_reg); 8799920Syasuko.eckert@amd.com } 8809920Syasuko.eckert@amd.com 8812292SN/A //Copy Thread Data Into RegFile 8822847Sksewell@umich.edu //this->copyFromTC(tid); 8832292SN/A 8842847Sksewell@umich.edu //Set PC/NPC/NNPC 8857720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8862292SN/A 8872680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8882292SN/A 8899180Sandreas.hansson@arm.com activateContext(tid, Cycles(1)); 8902292SN/A 8912292SN/A //Reset ROB/IQ/LSQ Entries 8922292SN/A commit.rob->resetEntries(); 8932292SN/A iew.resetEntries(); 8942292SN/A} 8952292SN/A 8962292SN/Atemplate <class Impl> 8972292SN/Avoid 8986221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8992292SN/A{ 9002877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 9012847Sksewell@umich.edu 9022847Sksewell@umich.edu // Copy Thread Data From RegFile 9032847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 9045364Sksewell@umich.edu // this->copyToTC(tid); 9055364Sksewell@umich.edu 9065364Sksewell@umich.edu 9075364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 9085364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 9095364Sksewell@umich.edu // in SMT workloads. 9102847Sksewell@umich.edu 9112847Sksewell@umich.edu // Unbind Int Regs from Rename Map 9122292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 9132292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 9142292SN/A 9152292SN/A scoreboard.unsetReg(phys_reg); 9162292SN/A freeList.addReg(phys_reg); 9172292SN/A } 9182292SN/A 9192847Sksewell@umich.edu // Unbind Float Regs from Rename Map 9209920Syasuko.eckert@amd.com int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 9219920Syasuko.eckert@amd.com for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) { 9222292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 9232292SN/A 9242292SN/A scoreboard.unsetReg(phys_reg); 9252292SN/A freeList.addReg(phys_reg); 9262292SN/A } 9272292SN/A 9289920Syasuko.eckert@amd.com // Unbind condition-code Regs from Rename Map 9299920Syasuko.eckert@amd.com max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs; 9309920Syasuko.eckert@amd.com for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 9319920Syasuko.eckert@amd.com creg < max_reg; creg++) { 9329920Syasuko.eckert@amd.com PhysRegIndex phys_reg = renameMap[tid].lookup(creg); 9339920Syasuko.eckert@amd.com 9349920Syasuko.eckert@amd.com scoreboard.unsetReg(phys_reg); 9359920Syasuko.eckert@amd.com freeList.addReg(phys_reg); 9369920Syasuko.eckert@amd.com } 9379920Syasuko.eckert@amd.com 9382847Sksewell@umich.edu // Squash Throughout Pipeline 9398138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 9408138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 9418138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 9422292SN/A decode.squash(tid); 9432935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 9442875Sksewell@umich.edu iew.squash(tid); 9455363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 9462935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 9472292SN/A 9485362Sksewell@umich.edu 9495362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 9502292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 9512292SN/A 9522847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 9533229Sktlim@umich.edu 9543229Sktlim@umich.edu // Commented out for now. This should be possible to do by 9553229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 9563229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 9573229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 9583229Sktlim@umich.edu/* 9592292SN/A if (activeThreads.size() >= 1) { 9602292SN/A commit.rob->resetEntries(); 9612292SN/A iew.resetEntries(); 9622292SN/A } 9633229Sktlim@umich.edu*/ 9642292SN/A} 9652292SN/A 9662292SN/A 9672292SN/Atemplate <class Impl> 9682292SN/Avoid 9696221Snate@binkert.orgFullO3CPU<Impl>::activateWhenReady(ThreadID tid) 9702292SN/A{ 9712733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 9722292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 9732292SN/A tid); 9742292SN/A 9752292SN/A bool ready = true; 9762292SN/A 9779920Syasuko.eckert@amd.com // Should these all be '<' not '>='? This seems backwards... 9782292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 9792733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9802292SN/A "Phys. Int. Regs.\n", 9812292SN/A tid); 9822292SN/A ready = false; 9832292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 9842733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9852292SN/A "Phys. Float. Regs.\n", 9862292SN/A tid); 9872292SN/A ready = false; 9889920Syasuko.eckert@amd.com } else if (freeList.numFreeCCRegs() >= TheISA::NumCCRegs) { 9899920Syasuko.eckert@amd.com DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9909920Syasuko.eckert@amd.com "Phys. CC. Regs.\n", 9919920Syasuko.eckert@amd.com tid); 9929920Syasuko.eckert@amd.com ready = false; 9932292SN/A } else if (commit.rob->numFreeEntries() >= 9942292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 9952733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9962292SN/A "ROB entries.\n", 9972292SN/A tid); 9982292SN/A ready = false; 9992292SN/A } else if (iew.instQueue.numFreeEntries() >= 10002292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 10012733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 10022292SN/A "IQ entries.\n", 10032292SN/A tid); 10042292SN/A ready = false; 10052292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 10062292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 10072733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 10082292SN/A "LSQ entries.\n", 10092292SN/A tid); 10102292SN/A ready = false; 10112292SN/A } 10122292SN/A 10132292SN/A if (ready) { 10142292SN/A insertThread(tid); 10152292SN/A 10162292SN/A contextSwitch = false; 10172292SN/A 10182292SN/A cpuWaitList.remove(tid); 10192292SN/A } else { 10202292SN/A suspendContext(tid); 10212292SN/A 10222292SN/A //blocks fetch 10232292SN/A contextSwitch = true; 10242292SN/A 10252875Sksewell@umich.edu //@todo: dont always add to waitlist 10262292SN/A //do waitlist 10272292SN/A cpuWaitList.push_back(tid); 10281060SN/A } 10291060SN/A} 10301060SN/A 10314192Sktlim@umich.edutemplate <class Impl> 10325595Sgblack@eecs.umich.eduFault 10336221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 10345702Ssaidi@eecs.umich.edu{ 10355702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 10365702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 10375702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 10385702Ssaidi@eecs.umich.edu 10395702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 10405702Ssaidi@eecs.umich.edu 10415702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 10425702Ssaidi@eecs.umich.edu#endif 10435702Ssaidi@eecs.umich.edu return NoFault; 10445702Ssaidi@eecs.umich.edu} 10455702Ssaidi@eecs.umich.edu 10465702Ssaidi@eecs.umich.edutemplate <class Impl> 10475702Ssaidi@eecs.umich.edubool 10486221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 10495702Ssaidi@eecs.umich.edu{ 10505702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 10515702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 10525702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 10535702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 10545702Ssaidi@eecs.umich.edu 10555702Ssaidi@eecs.umich.edu switch (palFunc) { 10565702Ssaidi@eecs.umich.edu case PAL::halt: 10575702Ssaidi@eecs.umich.edu halt(); 10585702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 10595702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 10605702Ssaidi@eecs.umich.edu break; 10615702Ssaidi@eecs.umich.edu 10625702Ssaidi@eecs.umich.edu case PAL::bpt: 10635702Ssaidi@eecs.umich.edu case PAL::bugchk: 10645702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 10655702Ssaidi@eecs.umich.edu return false; 10665702Ssaidi@eecs.umich.edu break; 10675702Ssaidi@eecs.umich.edu } 10685702Ssaidi@eecs.umich.edu#endif 10695702Ssaidi@eecs.umich.edu return true; 10705702Ssaidi@eecs.umich.edu} 10715702Ssaidi@eecs.umich.edu 10725702Ssaidi@eecs.umich.edutemplate <class Impl> 10735702Ssaidi@eecs.umich.eduFault 10745595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 10755595Sgblack@eecs.umich.edu{ 10765595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 10775647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 10785595Sgblack@eecs.umich.edu} 10795595Sgblack@eecs.umich.edu 10805595Sgblack@eecs.umich.edutemplate <class Impl> 10815595Sgblack@eecs.umich.eduvoid 10825595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 10835595Sgblack@eecs.umich.edu{ 10845595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 10855595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 10865595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 10875595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 10885595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 10895595Sgblack@eecs.umich.edu 10905595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 10915647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 10925595Sgblack@eecs.umich.edu 10935595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 10947684Sgblack@eecs.umich.edu this->trap(interrupt, 0, NULL); 10955595Sgblack@eecs.umich.edu} 10965595Sgblack@eecs.umich.edu 10971060SN/Atemplate <class Impl> 10982852Sktlim@umich.eduvoid 10997684Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) 11005595Sgblack@eecs.umich.edu{ 11015595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 11027684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 11035595Sgblack@eecs.umich.edu} 11045595Sgblack@eecs.umich.edu 11055595Sgblack@eecs.umich.edutemplate <class Impl> 11065595Sgblack@eecs.umich.eduvoid 11076221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 11085595Sgblack@eecs.umich.edu{ 11095595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 11105595Sgblack@eecs.umich.edu 11115595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 11125595Sgblack@eecs.umich.edu 11135595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 11145595Sgblack@eecs.umich.edu // instruction. 11155595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 11165595Sgblack@eecs.umich.edu 11175595Sgblack@eecs.umich.edu // Execute the actual syscall. 11185595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 11195595Sgblack@eecs.umich.edu 11205595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 11215595Sgblack@eecs.umich.edu // incrementing it. 11225595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 11235595Sgblack@eecs.umich.edu} 11245595Sgblack@eecs.umich.edu 11255595Sgblack@eecs.umich.edutemplate <class Impl> 11265595Sgblack@eecs.umich.eduvoid 11279448SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::serializeThread(std::ostream &os, ThreadID tid) 11282864Sktlim@umich.edu{ 11299448SAndreas.Sandberg@ARM.com thread[tid]->serialize(os); 11302864Sktlim@umich.edu} 11312864Sktlim@umich.edu 11322864Sktlim@umich.edutemplate <class Impl> 11332864Sktlim@umich.eduvoid 11349448SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::unserializeThread(Checkpoint *cp, const std::string §ion, 11359448SAndreas.Sandberg@ARM.com ThreadID tid) 11362864Sktlim@umich.edu{ 11379448SAndreas.Sandberg@ARM.com thread[tid]->unserialize(cp, section); 11382864Sktlim@umich.edu} 11392864Sktlim@umich.edu 11402864Sktlim@umich.edutemplate <class Impl> 11412905Sktlim@umich.eduunsigned int 11429342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drain(DrainManager *drain_manager) 11431060SN/A{ 11449444SAndreas.Sandberg@ARM.com // If the CPU isn't doing anything, then return immediately. 11459444SAndreas.Sandberg@ARM.com if (switchedOut()) { 11469444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Drained); 11479444SAndreas.Sandberg@ARM.com return 0; 11489444SAndreas.Sandberg@ARM.com } 11493512Sktlim@umich.edu 11509444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Draining...\n"); 11519444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Draining); 11523512Sktlim@umich.edu 11539444SAndreas.Sandberg@ARM.com // We only need to signal a drain to the commit stage as this 11549444SAndreas.Sandberg@ARM.com // initiates squashing controls the draining. Once the commit 11559444SAndreas.Sandberg@ARM.com // stage commits an instruction where it is safe to stop, it'll 11569444SAndreas.Sandberg@ARM.com // squash the rest of the instructions in the pipeline and force 11579444SAndreas.Sandberg@ARM.com // the fetch stage to stall. The pipeline will be drained once all 11589444SAndreas.Sandberg@ARM.com // in-flight instructions have retired. 11592843Sktlim@umich.edu commit.drain(); 11602325SN/A 11612325SN/A // Wake the CPU and record activity so everything can drain out if 11622863Sktlim@umich.edu // the CPU was not able to immediately drain. 11639444SAndreas.Sandberg@ARM.com if (!isDrained()) { 11649342SAndreas.Sandberg@arm.com drainManager = drain_manager; 11652843Sktlim@umich.edu 11662863Sktlim@umich.edu wakeCPU(); 11672863Sktlim@umich.edu activityRec.activity(); 11682852Sktlim@umich.edu 11699152Satgutier@umich.edu DPRINTF(Drain, "CPU not drained\n"); 11709152Satgutier@umich.edu 11712905Sktlim@umich.edu return 1; 11722863Sktlim@umich.edu } else { 11739444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Drained); 11749444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU is already drained\n"); 11759444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 11769444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 11779444SAndreas.Sandberg@ARM.com 11789444SAndreas.Sandberg@ARM.com // Flush out any old data from the time buffers. In 11799444SAndreas.Sandberg@ARM.com // particular, there might be some data in flight from the 11809444SAndreas.Sandberg@ARM.com // fetch stage that isn't visible in any of the CPU buffers we 11819444SAndreas.Sandberg@ARM.com // test in isDrained(). 11829444SAndreas.Sandberg@ARM.com for (int i = 0; i < timeBuffer.getSize(); ++i) { 11839444SAndreas.Sandberg@ARM.com timeBuffer.advance(); 11849444SAndreas.Sandberg@ARM.com fetchQueue.advance(); 11859444SAndreas.Sandberg@ARM.com decodeQueue.advance(); 11869444SAndreas.Sandberg@ARM.com renameQueue.advance(); 11879444SAndreas.Sandberg@ARM.com iewQueue.advance(); 11889444SAndreas.Sandberg@ARM.com } 11899444SAndreas.Sandberg@ARM.com 11909444SAndreas.Sandberg@ARM.com drainSanityCheck(); 11912905Sktlim@umich.edu return 0; 11922863Sktlim@umich.edu } 11932316SN/A} 11942310SN/A 11952316SN/Atemplate <class Impl> 11969444SAndreas.Sandberg@ARM.combool 11979444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::tryDrain() 11989444SAndreas.Sandberg@ARM.com{ 11999444SAndreas.Sandberg@ARM.com if (!drainManager || !isDrained()) 12009444SAndreas.Sandberg@ARM.com return false; 12019444SAndreas.Sandberg@ARM.com 12029444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 12039444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 12049444SAndreas.Sandberg@ARM.com 12059444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 12069444SAndreas.Sandberg@ARM.com drainManager->signalDrainDone(); 12079444SAndreas.Sandberg@ARM.com drainManager = NULL; 12089444SAndreas.Sandberg@ARM.com 12099444SAndreas.Sandberg@ARM.com return true; 12109444SAndreas.Sandberg@ARM.com} 12119444SAndreas.Sandberg@ARM.com 12129444SAndreas.Sandberg@ARM.comtemplate <class Impl> 12139444SAndreas.Sandberg@ARM.comvoid 12149444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::drainSanityCheck() const 12159444SAndreas.Sandberg@ARM.com{ 12169444SAndreas.Sandberg@ARM.com assert(isDrained()); 12179444SAndreas.Sandberg@ARM.com fetch.drainSanityCheck(); 12189444SAndreas.Sandberg@ARM.com decode.drainSanityCheck(); 12199444SAndreas.Sandberg@ARM.com rename.drainSanityCheck(); 12209444SAndreas.Sandberg@ARM.com iew.drainSanityCheck(); 12219444SAndreas.Sandberg@ARM.com commit.drainSanityCheck(); 12229444SAndreas.Sandberg@ARM.com} 12239444SAndreas.Sandberg@ARM.com 12249444SAndreas.Sandberg@ARM.comtemplate <class Impl> 12259444SAndreas.Sandberg@ARM.combool 12269444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::isDrained() const 12279444SAndreas.Sandberg@ARM.com{ 12289444SAndreas.Sandberg@ARM.com bool drained(true); 12299444SAndreas.Sandberg@ARM.com 12309444SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); ++i) { 12319444SAndreas.Sandberg@ARM.com if (activateThreadEvent[i].scheduled()) { 12329444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU not drained, tread %i has a " 12339444SAndreas.Sandberg@ARM.com "pending activate event\n", i); 12349444SAndreas.Sandberg@ARM.com drained = false; 12359444SAndreas.Sandberg@ARM.com } 12369444SAndreas.Sandberg@ARM.com if (deallocateContextEvent[i].scheduled()) { 12379444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU not drained, tread %i has a " 12389444SAndreas.Sandberg@ARM.com "pending deallocate context event\n", i); 12399444SAndreas.Sandberg@ARM.com drained = false; 12409444SAndreas.Sandberg@ARM.com } 12419444SAndreas.Sandberg@ARM.com } 12429444SAndreas.Sandberg@ARM.com 12439444SAndreas.Sandberg@ARM.com if (!instList.empty() || !removeList.empty()) { 12449444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Main CPU structures not drained.\n"); 12459444SAndreas.Sandberg@ARM.com drained = false; 12469444SAndreas.Sandberg@ARM.com } 12479444SAndreas.Sandberg@ARM.com 12489444SAndreas.Sandberg@ARM.com if (!fetch.isDrained()) { 12499444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Fetch not drained.\n"); 12509444SAndreas.Sandberg@ARM.com drained = false; 12519444SAndreas.Sandberg@ARM.com } 12529444SAndreas.Sandberg@ARM.com 12539444SAndreas.Sandberg@ARM.com if (!decode.isDrained()) { 12549444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Decode not drained.\n"); 12559444SAndreas.Sandberg@ARM.com drained = false; 12569444SAndreas.Sandberg@ARM.com } 12579444SAndreas.Sandberg@ARM.com 12589444SAndreas.Sandberg@ARM.com if (!rename.isDrained()) { 12599444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Rename not drained.\n"); 12609444SAndreas.Sandberg@ARM.com drained = false; 12619444SAndreas.Sandberg@ARM.com } 12629444SAndreas.Sandberg@ARM.com 12639444SAndreas.Sandberg@ARM.com if (!iew.isDrained()) { 12649444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "IEW not drained.\n"); 12659444SAndreas.Sandberg@ARM.com drained = false; 12669444SAndreas.Sandberg@ARM.com } 12679444SAndreas.Sandberg@ARM.com 12689444SAndreas.Sandberg@ARM.com if (!commit.isDrained()) { 12699444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Commit not drained.\n"); 12709444SAndreas.Sandberg@ARM.com drained = false; 12719444SAndreas.Sandberg@ARM.com } 12729444SAndreas.Sandberg@ARM.com 12739444SAndreas.Sandberg@ARM.com return drained; 12749444SAndreas.Sandberg@ARM.com} 12759444SAndreas.Sandberg@ARM.com 12769444SAndreas.Sandberg@ARM.comtemplate <class Impl> 12779444SAndreas.Sandberg@ARM.comvoid 12789444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::commitDrained(ThreadID tid) 12799444SAndreas.Sandberg@ARM.com{ 12809444SAndreas.Sandberg@ARM.com fetch.drainStall(tid); 12819444SAndreas.Sandberg@ARM.com} 12829444SAndreas.Sandberg@ARM.com 12839444SAndreas.Sandberg@ARM.comtemplate <class Impl> 12842316SN/Avoid 12859342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drainResume() 12862316SN/A{ 12879444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Running); 12889444SAndreas.Sandberg@ARM.com if (switchedOut()) 12899444SAndreas.Sandberg@ARM.com return; 12902316SN/A 12919444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Resuming...\n"); 12929523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 12933319Shsul@eecs.umich.edu 12949444SAndreas.Sandberg@ARM.com fetch.drainResume(); 12959444SAndreas.Sandberg@ARM.com commit.drainResume(); 12962316SN/A 12979444SAndreas.Sandberg@ARM.com _status = Idle; 12989444SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); i++) { 12999444SAndreas.Sandberg@ARM.com if (thread[i]->status() == ThreadContext::Active) { 13009444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Activating thread: %i\n", i); 13019444SAndreas.Sandberg@ARM.com activateThread(i); 13029444SAndreas.Sandberg@ARM.com _status = Running; 13032863Sktlim@umich.edu } 13042310SN/A } 13059444SAndreas.Sandberg@ARM.com 13069444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 13079444SAndreas.Sandberg@ARM.com if (_status == Running) 13089444SAndreas.Sandberg@ARM.com schedule(tickEvent, nextCycle()); 13092843Sktlim@umich.edu} 13102843Sktlim@umich.edu 13112843Sktlim@umich.edutemplate <class Impl> 13122843Sktlim@umich.eduvoid 13132843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 13142843Sktlim@umich.edu{ 13159444SAndreas.Sandberg@ARM.com DPRINTF(O3CPU, "Switching out\n"); 13169429SAndreas.Sandberg@ARM.com BaseCPU::switchOut(); 13179429SAndreas.Sandberg@ARM.com 13189444SAndreas.Sandberg@ARM.com activityRec.reset(); 13192843Sktlim@umich.edu 13202843Sktlim@umich.edu _status = SwitchedOut; 13218887Sgeoffrey.blake@arm.com 13222843Sktlim@umich.edu if (checker) 13232843Sktlim@umich.edu checker->switchOut(); 13241060SN/A} 13251060SN/A 13261060SN/Atemplate <class Impl> 13271060SN/Avoid 13281755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 13291060SN/A{ 13308737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 13311060SN/A 13322307SN/A fetch.takeOverFrom(); 13332307SN/A decode.takeOverFrom(); 13342307SN/A rename.takeOverFrom(); 13352307SN/A iew.takeOverFrom(); 13362307SN/A commit.takeOverFrom(); 13372307SN/A 13389444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 13391060SN/A 13409152Satgutier@umich.edu FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 13419152Satgutier@umich.edu if (oldO3CPU) 13429152Satgutier@umich.edu globalSeqNum = oldO3CPU->globalSeqNum; 13439152Satgutier@umich.edu 13449179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 13459444SAndreas.Sandberg@ARM.com _status = Idle; 13461060SN/A} 13471060SN/A 13481060SN/Atemplate <class Impl> 13499523SAndreas.Sandberg@ARM.comvoid 13509523SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::verifyMemoryMode() const 13519523SAndreas.Sandberg@ARM.com{ 13529524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 13539523SAndreas.Sandberg@ARM.com fatal("The O3 CPU requires the memory system to be in " 13549523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 13559523SAndreas.Sandberg@ARM.com } 13569523SAndreas.Sandberg@ARM.com} 13579523SAndreas.Sandberg@ARM.com 13589523SAndreas.Sandberg@ARM.comtemplate <class Impl> 13595595Sgblack@eecs.umich.eduTheISA::MiscReg 13606221Snate@binkert.orgFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 13615595Sgblack@eecs.umich.edu{ 13629384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscRegNoEffect(misc_reg); 13635595Sgblack@eecs.umich.edu} 13645595Sgblack@eecs.umich.edu 13655595Sgblack@eecs.umich.edutemplate <class Impl> 13665595Sgblack@eecs.umich.eduTheISA::MiscReg 13676221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 13685595Sgblack@eecs.umich.edu{ 13697897Shestness@cs.utexas.edu miscRegfileReads++; 13709384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 13715595Sgblack@eecs.umich.edu} 13725595Sgblack@eecs.umich.edu 13735595Sgblack@eecs.umich.edutemplate <class Impl> 13745595Sgblack@eecs.umich.eduvoid 13755595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 13766221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 13775595Sgblack@eecs.umich.edu{ 13789384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 13795595Sgblack@eecs.umich.edu} 13805595Sgblack@eecs.umich.edu 13815595Sgblack@eecs.umich.edutemplate <class Impl> 13825595Sgblack@eecs.umich.eduvoid 13835595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 13846221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 13855595Sgblack@eecs.umich.edu{ 13867897Shestness@cs.utexas.edu miscRegfileWrites++; 13879384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 13885595Sgblack@eecs.umich.edu} 13895595Sgblack@eecs.umich.edu 13905595Sgblack@eecs.umich.edutemplate <class Impl> 13911060SN/Auint64_t 13921755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 13931060SN/A{ 13947897Shestness@cs.utexas.edu intRegfileReads++; 13951060SN/A return regFile.readIntReg(reg_idx); 13961060SN/A} 13971060SN/A 13981060SN/Atemplate <class Impl> 13992455SN/AFloatReg 14002455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 14011060SN/A{ 14027897Shestness@cs.utexas.edu fpRegfileReads++; 14032455SN/A return regFile.readFloatReg(reg_idx); 14041060SN/A} 14051060SN/A 14061060SN/Atemplate <class Impl> 14072455SN/AFloatRegBits 14082455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 14092455SN/A{ 14107897Shestness@cs.utexas.edu fpRegfileReads++; 14112455SN/A return regFile.readFloatRegBits(reg_idx); 14121060SN/A} 14131060SN/A 14141060SN/Atemplate <class Impl> 14159920Syasuko.eckert@amd.comCCReg 14169920Syasuko.eckert@amd.comFullO3CPU<Impl>::readCCReg(int reg_idx) 14179920Syasuko.eckert@amd.com{ 14189920Syasuko.eckert@amd.com ccRegfileReads++; 14199920Syasuko.eckert@amd.com return regFile.readCCReg(reg_idx); 14209920Syasuko.eckert@amd.com} 14219920Syasuko.eckert@amd.com 14229920Syasuko.eckert@amd.comtemplate <class Impl> 14231060SN/Avoid 14241755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 14251060SN/A{ 14267897Shestness@cs.utexas.edu intRegfileWrites++; 14271060SN/A regFile.setIntReg(reg_idx, val); 14281060SN/A} 14291060SN/A 14301060SN/Atemplate <class Impl> 14311060SN/Avoid 14322455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 14331060SN/A{ 14347897Shestness@cs.utexas.edu fpRegfileWrites++; 14352455SN/A regFile.setFloatReg(reg_idx, val); 14361060SN/A} 14371060SN/A 14381060SN/Atemplate <class Impl> 14391060SN/Avoid 14402455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 14412455SN/A{ 14427897Shestness@cs.utexas.edu fpRegfileWrites++; 14432455SN/A regFile.setFloatRegBits(reg_idx, val); 14441060SN/A} 14451060SN/A 14461060SN/Atemplate <class Impl> 14479920Syasuko.eckert@amd.comvoid 14489920Syasuko.eckert@amd.comFullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val) 14499920Syasuko.eckert@amd.com{ 14509920Syasuko.eckert@amd.com ccRegfileWrites++; 14519920Syasuko.eckert@amd.com regFile.setCCReg(reg_idx, val); 14529920Syasuko.eckert@amd.com} 14539920Syasuko.eckert@amd.com 14549920Syasuko.eckert@amd.comtemplate <class Impl> 14551060SN/Auint64_t 14566221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 14571060SN/A{ 14587897Shestness@cs.utexas.edu intRegfileReads++; 14599919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 14602292SN/A 14612292SN/A return regFile.readIntReg(phys_reg); 14622292SN/A} 14632292SN/A 14642292SN/Atemplate <class Impl> 14652292SN/Afloat 14666314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 14672292SN/A{ 14687897Shestness@cs.utexas.edu fpRegfileReads++; 14699919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 14702292SN/A 14712669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 14722292SN/A} 14732292SN/A 14742292SN/Atemplate <class Impl> 14752292SN/Auint64_t 14766221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 14772292SN/A{ 14787897Shestness@cs.utexas.edu fpRegfileReads++; 14799919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 14802292SN/A 14812669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 14821060SN/A} 14831060SN/A 14841060SN/Atemplate <class Impl> 14859920Syasuko.eckert@amd.comCCReg 14869920Syasuko.eckert@amd.comFullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid) 14879920Syasuko.eckert@amd.com{ 14889920Syasuko.eckert@amd.com ccRegfileReads++; 14899920Syasuko.eckert@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 14909920Syasuko.eckert@amd.com 14919920Syasuko.eckert@amd.com return regFile.readCCReg(phys_reg); 14929920Syasuko.eckert@amd.com} 14939920Syasuko.eckert@amd.com 14949920Syasuko.eckert@amd.comtemplate <class Impl> 14951060SN/Avoid 14966221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 14971060SN/A{ 14987897Shestness@cs.utexas.edu intRegfileWrites++; 14999919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 15002292SN/A 15012292SN/A regFile.setIntReg(phys_reg, val); 15021060SN/A} 15031060SN/A 15041060SN/Atemplate <class Impl> 15051060SN/Avoid 15066314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 15071060SN/A{ 15087897Shestness@cs.utexas.edu fpRegfileWrites++; 15099919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 15102292SN/A 15112669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 15121060SN/A} 15131060SN/A 15141060SN/Atemplate <class Impl> 15151060SN/Avoid 15166221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 15171060SN/A{ 15187897Shestness@cs.utexas.edu fpRegfileWrites++; 15199919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 15201060SN/A 15212669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 15222292SN/A} 15232292SN/A 15242292SN/Atemplate <class Impl> 15259920Syasuko.eckert@amd.comvoid 15269920Syasuko.eckert@amd.comFullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid) 15279920Syasuko.eckert@amd.com{ 15289920Syasuko.eckert@amd.com ccRegfileWrites++; 15299920Syasuko.eckert@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 15309920Syasuko.eckert@amd.com 15319920Syasuko.eckert@amd.com regFile.setCCReg(phys_reg, val); 15329920Syasuko.eckert@amd.com} 15339920Syasuko.eckert@amd.com 15349920Syasuko.eckert@amd.comtemplate <class Impl> 15357720Sgblack@eecs.umich.eduTheISA::PCState 15367720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 15372292SN/A{ 15387720Sgblack@eecs.umich.edu return commit.pcState(tid); 15391060SN/A} 15401060SN/A 15411060SN/Atemplate <class Impl> 15421060SN/Avoid 15437720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 15441060SN/A{ 15457720Sgblack@eecs.umich.edu commit.pcState(val, tid); 15462292SN/A} 15471060SN/A 15482292SN/Atemplate <class Impl> 15497720Sgblack@eecs.umich.eduAddr 15507720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 15514636Sgblack@eecs.umich.edu{ 15527720Sgblack@eecs.umich.edu return commit.instAddr(tid); 15534636Sgblack@eecs.umich.edu} 15544636Sgblack@eecs.umich.edu 15554636Sgblack@eecs.umich.edutemplate <class Impl> 15567720Sgblack@eecs.umich.eduAddr 15577720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 15584636Sgblack@eecs.umich.edu{ 15597720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 15604636Sgblack@eecs.umich.edu} 15614636Sgblack@eecs.umich.edu 15624636Sgblack@eecs.umich.edutemplate <class Impl> 15637720Sgblack@eecs.umich.eduMicroPC 15647720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 15652292SN/A{ 15667720Sgblack@eecs.umich.edu return commit.microPC(tid); 15674636Sgblack@eecs.umich.edu} 15684636Sgblack@eecs.umich.edu 15694636Sgblack@eecs.umich.edutemplate <class Impl> 15705595Sgblack@eecs.umich.eduvoid 15716221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 15725595Sgblack@eecs.umich.edu{ 15739382SAli.Saidi@ARM.com this->thread[tid]->noSquashFromTC = true; 15745595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 15755595Sgblack@eecs.umich.edu} 15765595Sgblack@eecs.umich.edu 15775595Sgblack@eecs.umich.edutemplate <class Impl> 15782292SN/Atypename FullO3CPU<Impl>::ListIt 15792292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 15802292SN/A{ 15812292SN/A instList.push_back(inst); 15821060SN/A 15832292SN/A return --(instList.end()); 15842292SN/A} 15851060SN/A 15862292SN/Atemplate <class Impl> 15872292SN/Avoid 15888834Satgutier@umich.eduFullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 15892292SN/A{ 15902292SN/A // Keep an instruction count. 15918834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 15928834Satgutier@umich.edu thread[tid]->numInst++; 15938834Satgutier@umich.edu thread[tid]->numInsts++; 15948834Satgutier@umich.edu committedInsts[tid]++; 15958834Satgutier@umich.edu totalCommittedInsts++; 15968834Satgutier@umich.edu } 15978834Satgutier@umich.edu thread[tid]->numOp++; 15988834Satgutier@umich.edu thread[tid]->numOps++; 15998834Satgutier@umich.edu committedOps[tid]++; 16008834Satgutier@umich.edu 16017897Shestness@cs.utexas.edu system->totalNumInsts++; 16022292SN/A // Check for instruction-count-based events. 16032292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 16047897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 16052292SN/A} 16062292SN/A 16072292SN/Atemplate <class Impl> 16082292SN/Avoid 16091755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 16101060SN/A{ 16117720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 16122292SN/A "[sn:%lli]\n", 16137720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 16141060SN/A 16152292SN/A removeInstsThisCycle = true; 16161060SN/A 16171060SN/A // Remove the front instruction. 16182292SN/A removeList.push(inst->getInstListIt()); 16191060SN/A} 16201060SN/A 16211060SN/Atemplate <class Impl> 16221060SN/Avoid 16236221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 16241060SN/A{ 16252733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 16262292SN/A " list.\n", tid); 16271060SN/A 16282292SN/A ListIt end_it; 16291060SN/A 16302292SN/A bool rob_empty = false; 16312292SN/A 16322292SN/A if (instList.empty()) { 16332292SN/A return; 16342292SN/A } else if (rob.isEmpty(/*tid*/)) { 16352733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 16362292SN/A end_it = instList.begin(); 16372292SN/A rob_empty = true; 16382292SN/A } else { 16392292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 16402733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 16412292SN/A } 16422292SN/A 16432292SN/A removeInstsThisCycle = true; 16442292SN/A 16452292SN/A ListIt inst_it = instList.end(); 16462292SN/A 16472292SN/A inst_it--; 16482292SN/A 16492292SN/A // Walk through the instruction list, removing any instructions 16502292SN/A // that were inserted after the given instruction iterator, end_it. 16512292SN/A while (inst_it != end_it) { 16522292SN/A assert(!instList.empty()); 16532292SN/A 16542292SN/A squashInstIt(inst_it, tid); 16552292SN/A 16562292SN/A inst_it--; 16572292SN/A } 16582292SN/A 16592292SN/A // If the ROB was empty, then we actually need to remove the first 16602292SN/A // instruction as well. 16612292SN/A if (rob_empty) { 16622292SN/A squashInstIt(inst_it, tid); 16632292SN/A } 16641060SN/A} 16651060SN/A 16661060SN/Atemplate <class Impl> 16671060SN/Avoid 16686221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 16691062SN/A{ 16702292SN/A assert(!instList.empty()); 16712292SN/A 16722292SN/A removeInstsThisCycle = true; 16732292SN/A 16742292SN/A ListIt inst_iter = instList.end(); 16752292SN/A 16762292SN/A inst_iter--; 16772292SN/A 16782733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 16792292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 16802292SN/A tid, seq_num, (*inst_iter)->seqNum); 16811062SN/A 16822292SN/A while ((*inst_iter)->seqNum > seq_num) { 16831062SN/A 16842292SN/A bool break_loop = (inst_iter == instList.begin()); 16851062SN/A 16862292SN/A squashInstIt(inst_iter, tid); 16871062SN/A 16882292SN/A inst_iter--; 16891062SN/A 16902292SN/A if (break_loop) 16912292SN/A break; 16922292SN/A } 16932292SN/A} 16942292SN/A 16952292SN/Atemplate <class Impl> 16962292SN/Ainline void 16976221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 16982292SN/A{ 16992292SN/A if ((*instIt)->threadNumber == tid) { 17002733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 17017720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 17022292SN/A (*instIt)->threadNumber, 17032292SN/A (*instIt)->seqNum, 17047720Sgblack@eecs.umich.edu (*instIt)->pcState()); 17051062SN/A 17061062SN/A // Mark it as squashed. 17072292SN/A (*instIt)->setSquashed(); 17082292SN/A 17092325SN/A // @todo: Formulate a consistent method for deleting 17102325SN/A // instructions from the instruction list 17112292SN/A // Remove the instruction from the list. 17122292SN/A removeList.push(instIt); 17132292SN/A } 17142292SN/A} 17152292SN/A 17162292SN/Atemplate <class Impl> 17172292SN/Avoid 17182292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 17192292SN/A{ 17202292SN/A while (!removeList.empty()) { 17212733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 17227720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 17232292SN/A (*removeList.front())->threadNumber, 17242292SN/A (*removeList.front())->seqNum, 17257720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 17262292SN/A 17272292SN/A instList.erase(removeList.front()); 17282292SN/A 17292292SN/A removeList.pop(); 17301062SN/A } 17311062SN/A 17322292SN/A removeInstsThisCycle = false; 17331062SN/A} 17342325SN/A/* 17351062SN/Atemplate <class Impl> 17361062SN/Avoid 17371755SN/AFullO3CPU<Impl>::removeAllInsts() 17381060SN/A{ 17391060SN/A instList.clear(); 17401060SN/A} 17412325SN/A*/ 17421060SN/Atemplate <class Impl> 17431060SN/Avoid 17441755SN/AFullO3CPU<Impl>::dumpInsts() 17451060SN/A{ 17461060SN/A int num = 0; 17471060SN/A 17482292SN/A ListIt inst_list_it = instList.begin(); 17492292SN/A 17502292SN/A cprintf("Dumping Instruction List\n"); 17512292SN/A 17522292SN/A while (inst_list_it != instList.end()) { 17532292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 17542292SN/A "Squashed:%i\n\n", 17557720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 17562292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 17572292SN/A (*inst_list_it)->isSquashed()); 17581060SN/A inst_list_it++; 17591060SN/A ++num; 17601060SN/A } 17611060SN/A} 17622325SN/A/* 17631060SN/Atemplate <class Impl> 17641060SN/Avoid 17651755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 17661060SN/A{ 17671060SN/A iew.wakeDependents(inst); 17681060SN/A} 17692325SN/A*/ 17702292SN/Atemplate <class Impl> 17712292SN/Avoid 17722292SN/AFullO3CPU<Impl>::wakeCPU() 17732292SN/A{ 17742325SN/A if (activityRec.active() || tickEvent.scheduled()) { 17752325SN/A DPRINTF(Activity, "CPU already running.\n"); 17762292SN/A return; 17772292SN/A } 17782292SN/A 17792325SN/A DPRINTF(Activity, "Waking up CPU\n"); 17802325SN/A 17819180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 17829180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 17839179Sandreas.hansson@arm.com if (cycles != 0) 17849179Sandreas.hansson@arm.com --cycles; 17859179Sandreas.hansson@arm.com idleCycles += cycles; 17869179Sandreas.hansson@arm.com numCycles += cycles; 17872292SN/A 17889648Sdam.sunwoo@arm.com schedule(tickEvent, clockEdge()); 17892292SN/A} 17902292SN/A 17915807Snate@binkert.orgtemplate <class Impl> 17925807Snate@binkert.orgvoid 17935807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 17945807Snate@binkert.org{ 17955807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 17965807Snate@binkert.org return; 17975807Snate@binkert.org 17985807Snate@binkert.org this->wakeCPU(); 17995807Snate@binkert.org 18005807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 18015807Snate@binkert.org this->threadContexts[0]->activate(); 18025807Snate@binkert.org} 18035807Snate@binkert.org 18042292SN/Atemplate <class Impl> 18056221Snate@binkert.orgThreadID 18062292SN/AFullO3CPU<Impl>::getFreeTid() 18072292SN/A{ 18086221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 18096221Snate@binkert.org if (!tids[tid]) { 18106221Snate@binkert.org tids[tid] = true; 18116221Snate@binkert.org return tid; 18122292SN/A } 18132292SN/A } 18142292SN/A 18156221Snate@binkert.org return InvalidThreadID; 18162292SN/A} 18172292SN/A 18182292SN/Atemplate <class Impl> 18192292SN/Avoid 18202292SN/AFullO3CPU<Impl>::doContextSwitch() 18212292SN/A{ 18222292SN/A if (contextSwitch) { 18232292SN/A 18242292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 18252292SN/A 18266221Snate@binkert.org ThreadID size = cpuWaitList.size(); 18276221Snate@binkert.org for (ThreadID tid = 0; tid < size; tid++) { 18282292SN/A activateWhenReady(tid); 18292292SN/A } 18302292SN/A 18312292SN/A if (cpuWaitList.size() == 0) 18322292SN/A contextSwitch = true; 18332292SN/A } 18342292SN/A} 18352292SN/A 18362292SN/Atemplate <class Impl> 18372292SN/Avoid 18382292SN/AFullO3CPU<Impl>::updateThreadPriority() 18392292SN/A{ 18406221Snate@binkert.org if (activeThreads.size() > 1) { 18412292SN/A //DEFAULT TO ROUND ROBIN SCHEME 18422292SN/A //e.g. Move highest priority to end of thread list 18436221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 18442292SN/A 18452292SN/A unsigned high_thread = *list_begin; 18462292SN/A 18472292SN/A activeThreads.erase(list_begin); 18482292SN/A 18492292SN/A activeThreads.push_back(high_thread); 18502292SN/A } 18512292SN/A} 18521060SN/A 18531755SN/A// Forward declaration of FullO3CPU. 18542818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1855