cpu.cc revision 9433
11689SN/A/* 28948Sandreas.hansson@arm.com * Copyright (c) 2011-2012 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 142325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422756Sksewell@umich.edu * Korey Sewell 437897Shestness@cs.utexas.edu * Rick Strong 441689SN/A */ 451689SN/A 468779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 498887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 508229Snate@binkert.org#include "cpu/o3/cpu.hh" 518229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 528229Snate@binkert.org#include "cpu/o3/thread_context.hh" 534762Snate@binkert.org#include "cpu/activity.hh" 548779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 554762Snate@binkert.org#include "cpu/simple_thread.hh" 564762Snate@binkert.org#include "cpu/thread_context.hh" 578232Snate@binkert.org#include "debug/Activity.hh" 589152Satgutier@umich.edu#include "debug/Drain.hh" 598232Snate@binkert.org#include "debug/O3CPU.hh" 608232Snate@binkert.org#include "debug/Quiesce.hh" 614762Snate@binkert.org#include "enums/MemoryMode.hh" 624762Snate@binkert.org#include "sim/core.hh" 638793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 648779Sgblack@eecs.umich.edu#include "sim/process.hh" 654762Snate@binkert.org#include "sim/stat_control.hh" 668460SAli.Saidi@ARM.com#include "sim/system.hh" 674762Snate@binkert.org 685702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 695702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 708232Snate@binkert.org#include "debug/Activity.hh" 715702Ssaidi@eecs.umich.edu#endif 725702Ssaidi@eecs.umich.edu 738737Skoansin.tan@gmail.comstruct BaseCPUParams; 745529Snate@binkert.org 752669Sktlim@umich.eduusing namespace TheISA; 766221Snate@binkert.orgusing namespace std; 771060SN/A 785529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 795712Shsul@eecs.umich.edu : BaseCPU(params) 801060SN/A{ 811060SN/A} 821060SN/A 832292SN/Avoid 842733Sktlim@umich.eduBaseO3CPU::regStats() 852292SN/A{ 862292SN/A BaseCPU::regStats(); 872292SN/A} 882292SN/A 898707Sandreas.hansson@arm.comtemplate<class Impl> 908707Sandreas.hansson@arm.combool 918975Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 928707Sandreas.hansson@arm.com{ 938707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 948948Sandreas.hansson@arm.com // We shouldn't ever get a block in ownership state 958948Sandreas.hansson@arm.com assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 968948Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 978707Sandreas.hansson@arm.com 988707Sandreas.hansson@arm.com return true; 998707Sandreas.hansson@arm.com} 1008707Sandreas.hansson@arm.com 1018707Sandreas.hansson@arm.comtemplate<class Impl> 1028707Sandreas.hansson@arm.comvoid 1038707Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvRetry() 1048707Sandreas.hansson@arm.com{ 1058707Sandreas.hansson@arm.com fetch->recvRetry(); 1068707Sandreas.hansson@arm.com} 1078707Sandreas.hansson@arm.com 1088707Sandreas.hansson@arm.comtemplate <class Impl> 1098707Sandreas.hansson@arm.combool 1108975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 1118707Sandreas.hansson@arm.com{ 1128975Sandreas.hansson@arm.com return lsq->recvTimingResp(pkt); 1138707Sandreas.hansson@arm.com} 1148707Sandreas.hansson@arm.com 1158707Sandreas.hansson@arm.comtemplate <class Impl> 1168975Sandreas.hansson@arm.comvoid 1178975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 1188948Sandreas.hansson@arm.com{ 1198975Sandreas.hansson@arm.com lsq->recvTimingSnoopReq(pkt); 1208948Sandreas.hansson@arm.com} 1218948Sandreas.hansson@arm.com 1228948Sandreas.hansson@arm.comtemplate <class Impl> 1238707Sandreas.hansson@arm.comvoid 1248707Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvRetry() 1258707Sandreas.hansson@arm.com{ 1268707Sandreas.hansson@arm.com lsq->recvRetry(); 1278707Sandreas.hansson@arm.com} 1288707Sandreas.hansson@arm.com 1291060SN/Atemplate <class Impl> 1301755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 1315606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 1321060SN/A{ 1331060SN/A} 1341060SN/A 1351060SN/Atemplate <class Impl> 1361060SN/Avoid 1371755SN/AFullO3CPU<Impl>::TickEvent::process() 1381060SN/A{ 1391060SN/A cpu->tick(); 1401060SN/A} 1411060SN/A 1421060SN/Atemplate <class Impl> 1431060SN/Aconst char * 1445336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 1451060SN/A{ 1464873Sstever@eecs.umich.edu return "FullO3CPU tick"; 1471060SN/A} 1481060SN/A 1491060SN/Atemplate <class Impl> 1502829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 1515606Snate@binkert.org : Event(CPU_Switch_Pri) 1522829Sksewell@umich.edu{ 1532829Sksewell@umich.edu} 1542829Sksewell@umich.edu 1552829Sksewell@umich.edutemplate <class Impl> 1562829Sksewell@umich.eduvoid 1572829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1582829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1592829Sksewell@umich.edu{ 1602829Sksewell@umich.edu tid = thread_num; 1612829Sksewell@umich.edu cpu = thread_cpu; 1622829Sksewell@umich.edu} 1632829Sksewell@umich.edu 1642829Sksewell@umich.edutemplate <class Impl> 1652829Sksewell@umich.eduvoid 1662829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1672829Sksewell@umich.edu{ 1682829Sksewell@umich.edu cpu->activateThread(tid); 1692829Sksewell@umich.edu} 1702829Sksewell@umich.edu 1712829Sksewell@umich.edutemplate <class Impl> 1722829Sksewell@umich.educonst char * 1735336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1742829Sksewell@umich.edu{ 1754873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1762829Sksewell@umich.edu} 1772829Sksewell@umich.edu 1782829Sksewell@umich.edutemplate <class Impl> 1792875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1805606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1812875Sksewell@umich.edu{ 1822875Sksewell@umich.edu} 1832875Sksewell@umich.edu 1842875Sksewell@umich.edutemplate <class Impl> 1852875Sksewell@umich.eduvoid 1862875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1873859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1882875Sksewell@umich.edu{ 1892875Sksewell@umich.edu tid = thread_num; 1902875Sksewell@umich.edu cpu = thread_cpu; 1913859Sbinkertn@umich.edu remove = false; 1922875Sksewell@umich.edu} 1932875Sksewell@umich.edu 1942875Sksewell@umich.edutemplate <class Impl> 1952875Sksewell@umich.eduvoid 1962875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1972875Sksewell@umich.edu{ 1982875Sksewell@umich.edu cpu->deactivateThread(tid); 1993221Sktlim@umich.edu if (remove) 2003221Sktlim@umich.edu cpu->removeThread(tid); 2012875Sksewell@umich.edu} 2022875Sksewell@umich.edu 2032875Sksewell@umich.edutemplate <class Impl> 2042875Sksewell@umich.educonst char * 2055336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 2062875Sksewell@umich.edu{ 2074873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 2082875Sksewell@umich.edu} 2092875Sksewell@umich.edu 2102875Sksewell@umich.edutemplate <class Impl> 2115595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 2122733Sktlim@umich.edu : BaseO3CPU(params), 2133781Sgblack@eecs.umich.edu itb(params->itb), 2143781Sgblack@eecs.umich.edu dtb(params->dtb), 2151060SN/A tickEvent(this), 2165737Scws3k@cs.virginia.edu#ifndef NDEBUG 2175737Scws3k@cs.virginia.edu instcount(0), 2185737Scws3k@cs.virginia.edu#endif 2192292SN/A removeInstsThisCycle(false), 2205595Sgblack@eecs.umich.edu fetch(this, params), 2215595Sgblack@eecs.umich.edu decode(this, params), 2225595Sgblack@eecs.umich.edu rename(this, params), 2235595Sgblack@eecs.umich.edu iew(this, params), 2245595Sgblack@eecs.umich.edu commit(this, params), 2251060SN/A 2265595Sgblack@eecs.umich.edu regFile(this, params->numPhysIntRegs, 2274329Sktlim@umich.edu params->numPhysFloatRegs), 2281060SN/A 2295529Snate@binkert.org freeList(params->numThreads, 2302292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 2312292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 2321060SN/A 2335595Sgblack@eecs.umich.edu rob(this, 2344329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 2352292SN/A params->smtROBPolicy, params->smtROBThreshold, 2365529Snate@binkert.org params->numThreads), 2371060SN/A 2385529Snate@binkert.org scoreboard(params->numThreads, 2392292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 2402292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 2416221Snate@binkert.org TheISA::NumMiscRegs * numThreads, 2422292SN/A TheISA::ZeroReg), 2431060SN/A 2449384SAndreas.Sandberg@arm.com isa(numThreads, NULL), 2459384SAndreas.Sandberg@arm.com 2468707Sandreas.hansson@arm.com icachePort(&fetch, this), 2478707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 2488707Sandreas.hansson@arm.com 2492873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 2502873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 2512873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 2522873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 2532873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 2545804Snate@binkert.org activityRec(name(), NumStages, 2552873Sktlim@umich.edu params->backComSize + params->forwardComSize, 2562873Sktlim@umich.edu params->activity), 2571060SN/A 2581060SN/A globalSeqNum(1), 2592292SN/A system(params->system), 2602843Sktlim@umich.edu drainCount(0), 2619180Sandreas.hansson@arm.com lastRunningCycle(curCycle()) 2621060SN/A{ 2639433SAndreas.Sandberg@ARM.com if (!params->switched_out) { 2643221Sktlim@umich.edu _status = Running; 2653221Sktlim@umich.edu } else { 2669152Satgutier@umich.edu _status = SwitchedOut; 2673221Sktlim@umich.edu } 2681681SN/A 2692794Sktlim@umich.edu if (params->checker) { 2702316SN/A BaseCPU *temp_checker = params->checker; 2718733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 2728707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2732316SN/A checker->setSystem(params->system); 2744598Sbinkertn@umich.edu } else { 2754598Sbinkertn@umich.edu checker = NULL; 2764598Sbinkertn@umich.edu } 2772316SN/A 2788793Sgblack@eecs.umich.edu if (!FullSystem) { 2798793Sgblack@eecs.umich.edu thread.resize(numThreads); 2808793Sgblack@eecs.umich.edu tids.resize(numThreads); 2818793Sgblack@eecs.umich.edu } 2821681SN/A 2832325SN/A // The stages also need their CPU pointer setup. However this 2842325SN/A // must be done at the upper level CPU because they have pointers 2852325SN/A // to the upper level CPU, and not this FullO3CPU. 2861060SN/A 2872292SN/A // Set up Pointers to the activeThreads list for each stage 2882292SN/A fetch.setActiveThreads(&activeThreads); 2892292SN/A decode.setActiveThreads(&activeThreads); 2902292SN/A rename.setActiveThreads(&activeThreads); 2912292SN/A iew.setActiveThreads(&activeThreads); 2922292SN/A commit.setActiveThreads(&activeThreads); 2931060SN/A 2941060SN/A // Give each of the stages the time buffer they will use. 2951060SN/A fetch.setTimeBuffer(&timeBuffer); 2961060SN/A decode.setTimeBuffer(&timeBuffer); 2971060SN/A rename.setTimeBuffer(&timeBuffer); 2981060SN/A iew.setTimeBuffer(&timeBuffer); 2991060SN/A commit.setTimeBuffer(&timeBuffer); 3001060SN/A 3011060SN/A // Also setup each of the stages' queues. 3021060SN/A fetch.setFetchQueue(&fetchQueue); 3031060SN/A decode.setFetchQueue(&fetchQueue); 3042292SN/A commit.setFetchQueue(&fetchQueue); 3051060SN/A decode.setDecodeQueue(&decodeQueue); 3061060SN/A rename.setDecodeQueue(&decodeQueue); 3071060SN/A rename.setRenameQueue(&renameQueue); 3081060SN/A iew.setRenameQueue(&renameQueue); 3091060SN/A iew.setIEWQueue(&iewQueue); 3101060SN/A commit.setIEWQueue(&iewQueue); 3111060SN/A commit.setRenameQueue(&renameQueue); 3121060SN/A 3132292SN/A commit.setIEWStage(&iew); 3142292SN/A rename.setIEWStage(&iew); 3152292SN/A rename.setCommitStage(&commit); 3162292SN/A 3178793Sgblack@eecs.umich.edu ThreadID active_threads; 3188793Sgblack@eecs.umich.edu if (FullSystem) { 3198793Sgblack@eecs.umich.edu active_threads = 1; 3208793Sgblack@eecs.umich.edu } else { 3218793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 3222831Sksewell@umich.edu 3238793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 3248793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 3258793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 3268793Sgblack@eecs.umich.edu "or edit your workload size."); 3278793Sgblack@eecs.umich.edu } 3282831Sksewell@umich.edu } 3292292SN/A 3302316SN/A //Make Sure That this a Valid Architeture 3312292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 3322292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 3332292SN/A 3342292SN/A rename.setScoreboard(&scoreboard); 3352292SN/A iew.setScoreboard(&scoreboard); 3362292SN/A 3371060SN/A // Setup the rename map for whichever stages need it. 3382292SN/A PhysRegIndex lreg_idx = 0; 3392292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 3401060SN/A 3416221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3422307SN/A bool bindRegs = (tid <= active_threads - 1); 3432292SN/A 3449384SAndreas.Sandberg@arm.com isa[tid] = params->isa[tid]; 3459384SAndreas.Sandberg@arm.com 3462292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 3472292SN/A params->numPhysIntRegs, 3482325SN/A lreg_idx, //Index for Logical. Regs 3492292SN/A 3502292SN/A TheISA::NumFloatRegs, 3512292SN/A params->numPhysFloatRegs, 3522325SN/A freg_idx, //Index for Float Regs 3532292SN/A 3542292SN/A TheISA::NumMiscRegs, 3552292SN/A 3562292SN/A TheISA::ZeroReg, 3572292SN/A TheISA::ZeroReg, 3582292SN/A 3592292SN/A tid, 3602292SN/A false); 3612292SN/A 3622292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3632292SN/A params->numPhysIntRegs, 3642325SN/A lreg_idx, //Index for Logical. Regs 3652292SN/A 3662292SN/A TheISA::NumFloatRegs, 3672292SN/A params->numPhysFloatRegs, 3682325SN/A freg_idx, //Index for Float Regs 3692292SN/A 3702292SN/A TheISA::NumMiscRegs, 3712292SN/A 3722292SN/A TheISA::ZeroReg, 3732292SN/A TheISA::ZeroReg, 3742292SN/A 3752292SN/A tid, 3762292SN/A bindRegs); 3773221Sktlim@umich.edu 3783221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3793221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3802292SN/A } 3812292SN/A 3822292SN/A rename.setRenameMap(renameMap); 3832292SN/A commit.setRenameMap(commitRenameMap); 3842292SN/A 3852292SN/A // Give renameMap & rename stage access to the freeList; 3866221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3876221Snate@binkert.org renameMap[tid].setFreeList(&freeList); 3881060SN/A rename.setFreeList(&freeList); 3892292SN/A 3901060SN/A // Setup the ROB for whichever stages need it. 3911060SN/A commit.setROB(&rob); 3922292SN/A 3939158Sandreas.hansson@arm.com lastActivatedCycle = 0; 3946221Snate@binkert.org#if 0 3953093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3966221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3976221Snate@binkert.org globalSeqNum[tid] = 1; 3986221Snate@binkert.org#endif 3993093Sksewell@umich.edu 4002292SN/A contextSwitch = false; 4015595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 4025595Sgblack@eecs.umich.edu 4035595Sgblack@eecs.umich.edu // Setup any thread state. 4045595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 4055595Sgblack@eecs.umich.edu 4066221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 4078793Sgblack@eecs.umich.edu if (FullSystem) { 4088793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 4098793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 4108793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 4118793Sgblack@eecs.umich.edu } else { 4128793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 4138793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 4148793Sgblack@eecs.umich.edu tid, this->thread[tid]); 4158793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4168793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4178793Sgblack@eecs.umich.edu tid, params->workload[tid]); 4185595Sgblack@eecs.umich.edu 4198793Sgblack@eecs.umich.edu //usedTids[tid] = true; 4208793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 4218793Sgblack@eecs.umich.edu } else { 4228793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 4238793Sgblack@eecs.umich.edu //when scheduling threads to CPU 4248793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 4255595Sgblack@eecs.umich.edu 4268793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4278793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4288793Sgblack@eecs.umich.edu tid, dummy_proc); 4298793Sgblack@eecs.umich.edu //usedTids[tid] = false; 4308793Sgblack@eecs.umich.edu } 4315595Sgblack@eecs.umich.edu } 4325595Sgblack@eecs.umich.edu 4335595Sgblack@eecs.umich.edu ThreadContext *tc; 4345595Sgblack@eecs.umich.edu 4355595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 4365595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 4375595Sgblack@eecs.umich.edu 4385595Sgblack@eecs.umich.edu tc = o3_tc; 4395595Sgblack@eecs.umich.edu 4405595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 4415595Sgblack@eecs.umich.edu // CheckerThreadContext. 4425595Sgblack@eecs.umich.edu if (params->checker) { 4435595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 4445595Sgblack@eecs.umich.edu o3_tc, this->checker); 4455595Sgblack@eecs.umich.edu } 4465595Sgblack@eecs.umich.edu 4475595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 4485595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 4496221Snate@binkert.org o3_tc->thread = this->thread[tid]; 4505595Sgblack@eecs.umich.edu 4518793Sgblack@eecs.umich.edu if (FullSystem) { 4528793Sgblack@eecs.umich.edu // Setup quiesce event. 4538793Sgblack@eecs.umich.edu this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 4548793Sgblack@eecs.umich.edu } 4555595Sgblack@eecs.umich.edu // Give the thread the TC. 4566221Snate@binkert.org this->thread[tid]->tc = tc; 4575595Sgblack@eecs.umich.edu 4585595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4595595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4605595Sgblack@eecs.umich.edu } 4615595Sgblack@eecs.umich.edu 4628876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 4639433SAndreas.Sandberg@ARM.com if (!params->switched_out && !interrupts) { 4648876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 4658876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 4668876Sandreas.hansson@arm.com } 4678876Sandreas.hansson@arm.com 4686221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4696221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4705595Sgblack@eecs.umich.edu 4715595Sgblack@eecs.umich.edu lockAddr = 0; 4725595Sgblack@eecs.umich.edu lockFlag = false; 4731060SN/A} 4741060SN/A 4751060SN/Atemplate <class Impl> 4761755SN/AFullO3CPU<Impl>::~FullO3CPU() 4771060SN/A{ 4781060SN/A} 4791060SN/A 4801060SN/Atemplate <class Impl> 4811060SN/Avoid 4825595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4831062SN/A{ 4842733Sktlim@umich.edu BaseO3CPU::regStats(); 4852292SN/A 4862733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4872292SN/A timesIdled 4882292SN/A .name(name() + ".timesIdled") 4892292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4902292SN/A " unscheduled itself") 4912292SN/A .prereq(timesIdled); 4922292SN/A 4932292SN/A idleCycles 4942292SN/A .name(name() + ".idleCycles") 4952292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4962292SN/A "to idling") 4972292SN/A .prereq(idleCycles); 4982292SN/A 4998627SAli.Saidi@ARM.com quiesceCycles 5008627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 5018627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 5028627SAli.Saidi@ARM.com "for an interrupt") 5038627SAli.Saidi@ARM.com .prereq(quiesceCycles); 5048627SAli.Saidi@ARM.com 5052292SN/A // Number of Instructions simulated 5062292SN/A // -------------------------------- 5072292SN/A // Should probably be in Base CPU but need templated 5082292SN/A // MaxThreads so put in here instead 5092292SN/A committedInsts 5102292SN/A .init(numThreads) 5112292SN/A .name(name() + ".committedInsts") 5122292SN/A .desc("Number of Instructions Simulated"); 5132292SN/A 5148834Satgutier@umich.edu committedOps 5158834Satgutier@umich.edu .init(numThreads) 5168834Satgutier@umich.edu .name(name() + ".committedOps") 5178834Satgutier@umich.edu .desc("Number of Ops (including micro ops) Simulated"); 5188834Satgutier@umich.edu 5192292SN/A totalCommittedInsts 5202292SN/A .name(name() + ".committedInsts_total") 5212292SN/A .desc("Number of Instructions Simulated"); 5222292SN/A 5232292SN/A cpi 5242292SN/A .name(name() + ".cpi") 5252292SN/A .desc("CPI: Cycles Per Instruction") 5262292SN/A .precision(6); 5274392Sktlim@umich.edu cpi = numCycles / committedInsts; 5282292SN/A 5292292SN/A totalCpi 5302292SN/A .name(name() + ".cpi_total") 5312292SN/A .desc("CPI: Total CPI of All Threads") 5322292SN/A .precision(6); 5334392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 5342292SN/A 5352292SN/A ipc 5362292SN/A .name(name() + ".ipc") 5372292SN/A .desc("IPC: Instructions Per Cycle") 5382292SN/A .precision(6); 5394392Sktlim@umich.edu ipc = committedInsts / numCycles; 5402292SN/A 5412292SN/A totalIpc 5422292SN/A .name(name() + ".ipc_total") 5432292SN/A .desc("IPC: Total IPC of All Threads") 5442292SN/A .precision(6); 5454392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 5462292SN/A 5475595Sgblack@eecs.umich.edu this->fetch.regStats(); 5485595Sgblack@eecs.umich.edu this->decode.regStats(); 5495595Sgblack@eecs.umich.edu this->rename.regStats(); 5505595Sgblack@eecs.umich.edu this->iew.regStats(); 5515595Sgblack@eecs.umich.edu this->commit.regStats(); 5527897Shestness@cs.utexas.edu this->rob.regStats(); 5537897Shestness@cs.utexas.edu 5547897Shestness@cs.utexas.edu intRegfileReads 5557897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 5567897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 5577897Shestness@cs.utexas.edu .prereq(intRegfileReads); 5587897Shestness@cs.utexas.edu 5597897Shestness@cs.utexas.edu intRegfileWrites 5607897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 5617897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 5627897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 5637897Shestness@cs.utexas.edu 5647897Shestness@cs.utexas.edu fpRegfileReads 5657897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 5667897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5677897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5687897Shestness@cs.utexas.edu 5697897Shestness@cs.utexas.edu fpRegfileWrites 5707897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5717897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5727897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5737897Shestness@cs.utexas.edu 5747897Shestness@cs.utexas.edu miscRegfileReads 5757897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5767897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5777897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5787897Shestness@cs.utexas.edu 5797897Shestness@cs.utexas.edu miscRegfileWrites 5807897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5817897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5827897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5831062SN/A} 5841062SN/A 5851062SN/Atemplate <class Impl> 5861062SN/Avoid 5871755SN/AFullO3CPU<Impl>::tick() 5881060SN/A{ 5892733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5901060SN/A 5912292SN/A ++numCycles; 5922292SN/A 5932325SN/A// activity = false; 5942292SN/A 5952292SN/A //Tick each of the stages 5961060SN/A fetch.tick(); 5971060SN/A 5981060SN/A decode.tick(); 5991060SN/A 6001060SN/A rename.tick(); 6011060SN/A 6021060SN/A iew.tick(); 6031060SN/A 6041060SN/A commit.tick(); 6051060SN/A 6068793Sgblack@eecs.umich.edu if (!FullSystem) 6078793Sgblack@eecs.umich.edu doContextSwitch(); 6082292SN/A 6092292SN/A // Now advance the time buffers 6101060SN/A timeBuffer.advance(); 6111060SN/A 6121060SN/A fetchQueue.advance(); 6131060SN/A decodeQueue.advance(); 6141060SN/A renameQueue.advance(); 6151060SN/A iewQueue.advance(); 6161060SN/A 6172325SN/A activityRec.advance(); 6182292SN/A 6192292SN/A if (removeInstsThisCycle) { 6202292SN/A cleanUpRemovedInsts(); 6212292SN/A } 6222292SN/A 6232325SN/A if (!tickEvent.scheduled()) { 6242867Sktlim@umich.edu if (_status == SwitchedOut || 6259342SAndreas.Sandberg@arm.com getDrainState() == Drainable::Drained) { 6263226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 6272325SN/A // increment stat 6289179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6293221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 6303226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 6319179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6322325SN/A timesIdled++; 6332325SN/A } else { 6349180Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(Cycles(1))); 6353226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 6362325SN/A } 6372292SN/A } 6382292SN/A 6398793Sgblack@eecs.umich.edu if (!FullSystem) 6408793Sgblack@eecs.umich.edu updateThreadPriority(); 6411060SN/A} 6421060SN/A 6431060SN/Atemplate <class Impl> 6441060SN/Avoid 6451755SN/AFullO3CPU<Impl>::init() 6461060SN/A{ 6475714Shsul@eecs.umich.edu BaseCPU::init(); 6481060SN/A 6499433SAndreas.Sandberg@ARM.com if (!params()->switched_out && 6509424SAndreas.Sandberg@ARM.com system->getMemoryMode() != Enums::timing) { 6519424SAndreas.Sandberg@ARM.com fatal("The O3 CPU requires the memory system to be in " 6529424SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 6539424SAndreas.Sandberg@ARM.com } 6549424SAndreas.Sandberg@ARM.com 6558921Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 6569382SAli.Saidi@ARM.com // Set noSquashFromTC so that the CPU doesn't squash when initially 6578921Sandreas.hansson@arm.com // setting up registers. 6589382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 6598921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 6608921Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 6618921Sandreas.hansson@arm.com } 6622292SN/A 6638707Sandreas.hansson@arm.com // this CPU could still be unconnected if we are restoring from a 6648707Sandreas.hansson@arm.com // checkpoint and this CPU is to be switched in, thus we can only 6658707Sandreas.hansson@arm.com // do this here if the instruction port is actually connected, if 6668707Sandreas.hansson@arm.com // not we have to do it as part of takeOverFrom 6678707Sandreas.hansson@arm.com if (icachePort.isConnected()) 6688707Sandreas.hansson@arm.com fetch.setIcache(); 6698707Sandreas.hansson@arm.com 6709433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 6718793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6728793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6738793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6748793Sgblack@eecs.umich.edu } 6756034Ssteve.reinhardt@amd.com } 6762292SN/A 6779382SAli.Saidi@ARM.com // Clear noSquashFromTC. 6786221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6799382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6802292SN/A 6819427SAndreas.Sandberg@ARM.com commit.setThreads(thread); 6829427SAndreas.Sandberg@ARM.com} 6832292SN/A 6849427SAndreas.Sandberg@ARM.comtemplate <class Impl> 6859427SAndreas.Sandberg@ARM.comvoid 6869427SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::startup() 6879427SAndreas.Sandberg@ARM.com{ 6889427SAndreas.Sandberg@ARM.com fetch.startupStage(); 6899427SAndreas.Sandberg@ARM.com iew.startupStage(); 6909427SAndreas.Sandberg@ARM.com rename.startupStage(); 6919427SAndreas.Sandberg@ARM.com commit.startupStage(); 6922292SN/A} 6932292SN/A 6942292SN/Atemplate <class Impl> 6952292SN/Avoid 6966221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6972875Sksewell@umich.edu{ 6986221Snate@binkert.org list<ThreadID>::iterator isActive = 6995314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 7002875Sksewell@umich.edu 7013226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 7023226Sktlim@umich.edu 7032875Sksewell@umich.edu if (isActive == activeThreads.end()) { 7042875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 7052875Sksewell@umich.edu tid); 7062875Sksewell@umich.edu 7072875Sksewell@umich.edu activeThreads.push_back(tid); 7082875Sksewell@umich.edu } 7092875Sksewell@umich.edu} 7102875Sksewell@umich.edu 7112875Sksewell@umich.edutemplate <class Impl> 7122875Sksewell@umich.eduvoid 7136221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 7142875Sksewell@umich.edu{ 7152875Sksewell@umich.edu //Remove From Active List, if Active 7166221Snate@binkert.org list<ThreadID>::iterator thread_it = 7175314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 7182875Sksewell@umich.edu 7193226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 7203226Sktlim@umich.edu 7212875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 7222875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 7232875Sksewell@umich.edu tid); 7242875Sksewell@umich.edu activeThreads.erase(thread_it); 7252875Sksewell@umich.edu } 7262875Sksewell@umich.edu} 7272875Sksewell@umich.edu 7282875Sksewell@umich.edutemplate <class Impl> 7296221Snate@binkert.orgCounter 7308834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 7316221Snate@binkert.org{ 7326221Snate@binkert.org Counter total(0); 7336221Snate@binkert.org 7346221Snate@binkert.org ThreadID size = thread.size(); 7356221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 7366221Snate@binkert.org total += thread[i]->numInst; 7376221Snate@binkert.org 7386221Snate@binkert.org return total; 7396221Snate@binkert.org} 7406221Snate@binkert.org 7416221Snate@binkert.orgtemplate <class Impl> 7428834Satgutier@umich.eduCounter 7438834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 7448834Satgutier@umich.edu{ 7458834Satgutier@umich.edu Counter total(0); 7468834Satgutier@umich.edu 7478834Satgutier@umich.edu ThreadID size = thread.size(); 7488834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 7498834Satgutier@umich.edu total += thread[i]->numOp; 7508834Satgutier@umich.edu 7518834Satgutier@umich.edu return total; 7528834Satgutier@umich.edu} 7538834Satgutier@umich.edu 7548834Satgutier@umich.edutemplate <class Impl> 7552875Sksewell@umich.eduvoid 7569180Sandreas.hansson@arm.comFullO3CPU<Impl>::activateContext(ThreadID tid, Cycles delay) 7572875Sksewell@umich.edu{ 7582875Sksewell@umich.edu // Needs to set each stage to running as well. 7592875Sksewell@umich.edu if (delay){ 7602875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 7619180Sandreas.hansson@arm.com "on cycle %d\n", tid, clockEdge(delay)); 7622875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 7632875Sksewell@umich.edu } else { 7642875Sksewell@umich.edu activateThread(tid); 7652875Sksewell@umich.edu } 7662875Sksewell@umich.edu 7679158Sandreas.hansson@arm.com // If we are time 0 or if the last activation time is in the past, 7689158Sandreas.hansson@arm.com // schedule the next tick and wake up the fetch unit 7699158Sandreas.hansson@arm.com if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 7702875Sksewell@umich.edu scheduleTickEvent(delay); 7712875Sksewell@umich.edu 7722875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7732875Sksewell@umich.edu // deschedule itself. 7742875Sksewell@umich.edu activityRec.activity(); 7752875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7762875Sksewell@umich.edu 7779180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 7789180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 7799179Sandreas.hansson@arm.com if (cycles != 0) 7809179Sandreas.hansson@arm.com --cycles; 7819179Sandreas.hansson@arm.com quiesceCycles += cycles; 7828627SAli.Saidi@ARM.com 7837823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7842875Sksewell@umich.edu 7852875Sksewell@umich.edu _status = Running; 7862875Sksewell@umich.edu } 7872875Sksewell@umich.edu} 7882875Sksewell@umich.edu 7892875Sksewell@umich.edutemplate <class Impl> 7903221Sktlim@umich.edubool 7918737Skoansin.tan@gmail.comFullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove, 7929180Sandreas.hansson@arm.com Cycles delay) 7932875Sksewell@umich.edu{ 7942875Sksewell@umich.edu // Schedule removal of thread data from CPU 7952875Sksewell@umich.edu if (delay){ 7962875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 7979180Sandreas.hansson@arm.com "on tick %d\n", tid, clockEdge(delay)); 7983221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 7993221Sktlim@umich.edu return false; 8002875Sksewell@umich.edu } else { 8012875Sksewell@umich.edu deactivateThread(tid); 8023221Sktlim@umich.edu if (remove) 8033221Sktlim@umich.edu removeThread(tid); 8043221Sktlim@umich.edu return true; 8052875Sksewell@umich.edu } 8062875Sksewell@umich.edu} 8072875Sksewell@umich.edu 8082875Sksewell@umich.edutemplate <class Impl> 8092875Sksewell@umich.eduvoid 8106221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 8112875Sksewell@umich.edu{ 8122875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 8139180Sandreas.hansson@arm.com bool deallocated = scheduleDeallocateContext(tid, false, Cycles(1)); 8143221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 8155570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 8163859Sbinkertn@umich.edu activeThreads.size() == 0) 8172910Sksewell@umich.edu unscheduleTickEvent(); 8188627SAli.Saidi@ARM.com 8198627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 8209179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 8212875Sksewell@umich.edu _status = Idle; 8222875Sksewell@umich.edu} 8232875Sksewell@umich.edu 8242875Sksewell@umich.edutemplate <class Impl> 8252875Sksewell@umich.eduvoid 8266221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 8272875Sksewell@umich.edu{ 8282910Sksewell@umich.edu //For now, this is the same as deallocate 8292910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 8309180Sandreas.hansson@arm.com scheduleDeallocateContext(tid, true, Cycles(1)); 8312875Sksewell@umich.edu} 8322875Sksewell@umich.edu 8332875Sksewell@umich.edutemplate <class Impl> 8342875Sksewell@umich.eduvoid 8356221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 8362292SN/A{ 8372847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 8382292SN/A // Will change now that the PC and thread state is internal to the CPU 8392683Sktlim@umich.edu // and not in the ThreadContext. 8408793Sgblack@eecs.umich.edu ThreadContext *src_tc; 8418793Sgblack@eecs.umich.edu if (FullSystem) 8428793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 8438793Sgblack@eecs.umich.edu else 8448793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 8452292SN/A 8462292SN/A //Bind Int Regs to Rename Map 8472292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8482292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 8492292SN/A 8502292SN/A renameMap[tid].setEntry(ireg,phys_reg); 8512292SN/A scoreboard.setReg(phys_reg); 8522292SN/A } 8532292SN/A 8542292SN/A //Bind Float Regs to Rename Map 8552292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 8562292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 8572292SN/A 8582292SN/A renameMap[tid].setEntry(freg,phys_reg); 8592292SN/A scoreboard.setReg(phys_reg); 8602292SN/A } 8612292SN/A 8622292SN/A //Copy Thread Data Into RegFile 8632847Sksewell@umich.edu //this->copyFromTC(tid); 8642292SN/A 8652847Sksewell@umich.edu //Set PC/NPC/NNPC 8667720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8672292SN/A 8682680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8692292SN/A 8709180Sandreas.hansson@arm.com activateContext(tid, Cycles(1)); 8712292SN/A 8722292SN/A //Reset ROB/IQ/LSQ Entries 8732292SN/A commit.rob->resetEntries(); 8742292SN/A iew.resetEntries(); 8752292SN/A} 8762292SN/A 8772292SN/Atemplate <class Impl> 8782292SN/Avoid 8796221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8802292SN/A{ 8812877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 8822847Sksewell@umich.edu 8832847Sksewell@umich.edu // Copy Thread Data From RegFile 8842847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 8855364Sksewell@umich.edu // this->copyToTC(tid); 8865364Sksewell@umich.edu 8875364Sksewell@umich.edu 8885364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 8895364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 8905364Sksewell@umich.edu // in SMT workloads. 8912847Sksewell@umich.edu 8922847Sksewell@umich.edu // Unbind Int Regs from Rename Map 8932292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8942292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 8952292SN/A 8962292SN/A scoreboard.unsetReg(phys_reg); 8972292SN/A freeList.addReg(phys_reg); 8982292SN/A } 8992292SN/A 9002847Sksewell@umich.edu // Unbind Float Regs from Rename Map 9015362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 9022292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 9032292SN/A 9042292SN/A scoreboard.unsetReg(phys_reg); 9052292SN/A freeList.addReg(phys_reg); 9062292SN/A } 9072292SN/A 9082847Sksewell@umich.edu // Squash Throughout Pipeline 9098138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 9108138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 9118138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 9122292SN/A decode.squash(tid); 9132935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 9142875Sksewell@umich.edu iew.squash(tid); 9155363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 9162935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 9172292SN/A 9185362Sksewell@umich.edu 9195362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 9202292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 9212292SN/A 9222847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 9233229Sktlim@umich.edu 9243229Sktlim@umich.edu // Commented out for now. This should be possible to do by 9253229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 9263229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 9273229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 9283229Sktlim@umich.edu/* 9292292SN/A if (activeThreads.size() >= 1) { 9302292SN/A commit.rob->resetEntries(); 9312292SN/A iew.resetEntries(); 9322292SN/A } 9333229Sktlim@umich.edu*/ 9342292SN/A} 9352292SN/A 9362292SN/A 9372292SN/Atemplate <class Impl> 9382292SN/Avoid 9396221Snate@binkert.orgFullO3CPU<Impl>::activateWhenReady(ThreadID tid) 9402292SN/A{ 9412733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 9422292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 9432292SN/A tid); 9442292SN/A 9452292SN/A bool ready = true; 9462292SN/A 9472292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 9482733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9492292SN/A "Phys. Int. Regs.\n", 9502292SN/A tid); 9512292SN/A ready = false; 9522292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 9532733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9542292SN/A "Phys. Float. Regs.\n", 9552292SN/A tid); 9562292SN/A ready = false; 9572292SN/A } else if (commit.rob->numFreeEntries() >= 9582292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 9592733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9602292SN/A "ROB entries.\n", 9612292SN/A tid); 9622292SN/A ready = false; 9632292SN/A } else if (iew.instQueue.numFreeEntries() >= 9642292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 9652733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9662292SN/A "IQ entries.\n", 9672292SN/A tid); 9682292SN/A ready = false; 9692292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 9702292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 9712733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9722292SN/A "LSQ entries.\n", 9732292SN/A tid); 9742292SN/A ready = false; 9752292SN/A } 9762292SN/A 9772292SN/A if (ready) { 9782292SN/A insertThread(tid); 9792292SN/A 9802292SN/A contextSwitch = false; 9812292SN/A 9822292SN/A cpuWaitList.remove(tid); 9832292SN/A } else { 9842292SN/A suspendContext(tid); 9852292SN/A 9862292SN/A //blocks fetch 9872292SN/A contextSwitch = true; 9882292SN/A 9892875Sksewell@umich.edu //@todo: dont always add to waitlist 9902292SN/A //do waitlist 9912292SN/A cpuWaitList.push_back(tid); 9921060SN/A } 9931060SN/A} 9941060SN/A 9954192Sktlim@umich.edutemplate <class Impl> 9965595Sgblack@eecs.umich.eduFault 9976221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 9985702Ssaidi@eecs.umich.edu{ 9995702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 10005702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 10015702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 10025702Ssaidi@eecs.umich.edu 10035702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 10045702Ssaidi@eecs.umich.edu 10055702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 10065702Ssaidi@eecs.umich.edu#endif 10075702Ssaidi@eecs.umich.edu return NoFault; 10085702Ssaidi@eecs.umich.edu} 10095702Ssaidi@eecs.umich.edu 10105702Ssaidi@eecs.umich.edutemplate <class Impl> 10115702Ssaidi@eecs.umich.edubool 10126221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 10135702Ssaidi@eecs.umich.edu{ 10145702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 10155702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 10165702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 10175702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 10185702Ssaidi@eecs.umich.edu 10195702Ssaidi@eecs.umich.edu switch (palFunc) { 10205702Ssaidi@eecs.umich.edu case PAL::halt: 10215702Ssaidi@eecs.umich.edu halt(); 10225702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 10235702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 10245702Ssaidi@eecs.umich.edu break; 10255702Ssaidi@eecs.umich.edu 10265702Ssaidi@eecs.umich.edu case PAL::bpt: 10275702Ssaidi@eecs.umich.edu case PAL::bugchk: 10285702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 10295702Ssaidi@eecs.umich.edu return false; 10305702Ssaidi@eecs.umich.edu break; 10315702Ssaidi@eecs.umich.edu } 10325702Ssaidi@eecs.umich.edu#endif 10335702Ssaidi@eecs.umich.edu return true; 10345702Ssaidi@eecs.umich.edu} 10355702Ssaidi@eecs.umich.edu 10365702Ssaidi@eecs.umich.edutemplate <class Impl> 10375702Ssaidi@eecs.umich.eduFault 10385595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 10395595Sgblack@eecs.umich.edu{ 10405595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 10415647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 10425595Sgblack@eecs.umich.edu} 10435595Sgblack@eecs.umich.edu 10445595Sgblack@eecs.umich.edutemplate <class Impl> 10455595Sgblack@eecs.umich.eduvoid 10465595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 10475595Sgblack@eecs.umich.edu{ 10485595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 10495595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 10505595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 10515595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 10525595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 10535595Sgblack@eecs.umich.edu 10545595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 10555647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 10565595Sgblack@eecs.umich.edu 10575595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 10587684Sgblack@eecs.umich.edu this->trap(interrupt, 0, NULL); 10595595Sgblack@eecs.umich.edu} 10605595Sgblack@eecs.umich.edu 10611060SN/Atemplate <class Impl> 10622852Sktlim@umich.eduvoid 10637684Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) 10645595Sgblack@eecs.umich.edu{ 10655595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 10667684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 10675595Sgblack@eecs.umich.edu} 10685595Sgblack@eecs.umich.edu 10695595Sgblack@eecs.umich.edutemplate <class Impl> 10705595Sgblack@eecs.umich.eduvoid 10716221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 10725595Sgblack@eecs.umich.edu{ 10735595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 10745595Sgblack@eecs.umich.edu 10755595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 10765595Sgblack@eecs.umich.edu 10775595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 10785595Sgblack@eecs.umich.edu // instruction. 10795595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 10805595Sgblack@eecs.umich.edu 10815595Sgblack@eecs.umich.edu // Execute the actual syscall. 10825595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 10835595Sgblack@eecs.umich.edu 10845595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 10855595Sgblack@eecs.umich.edu // incrementing it. 10865595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 10875595Sgblack@eecs.umich.edu} 10885595Sgblack@eecs.umich.edu 10895595Sgblack@eecs.umich.edutemplate <class Impl> 10905595Sgblack@eecs.umich.eduvoid 10912864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 10922864Sktlim@umich.edu{ 10939342SAndreas.Sandberg@arm.com Drainable::State so_state(getDrainState()); 10942918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 10952864Sktlim@umich.edu BaseCPU::serialize(os); 10962864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 10972864Sktlim@umich.edu tickEvent.serialize(os); 10982864Sktlim@umich.edu 10999428SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); i++) { 11002864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 11019428SAndreas.Sandberg@ARM.com thread[i]->serialize(os); 11022864Sktlim@umich.edu } 11032864Sktlim@umich.edu} 11042864Sktlim@umich.edu 11052864Sktlim@umich.edutemplate <class Impl> 11062864Sktlim@umich.eduvoid 11072864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 11082864Sktlim@umich.edu{ 11099342SAndreas.Sandberg@arm.com Drainable::State so_state; 11102918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 11112864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 11122864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 11132864Sktlim@umich.edu 11149428SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); i++) { 11159428SAndreas.Sandberg@ARM.com thread[i]->unserialize(cp, 11169428SAndreas.Sandberg@ARM.com csprintf("%s.xc.%i", section, i)); 11179428SAndreas.Sandberg@ARM.com if (thread[i]->status() == ThreadContext::Active) 11189428SAndreas.Sandberg@ARM.com activateThread(i); 11192864Sktlim@umich.edu } 11202864Sktlim@umich.edu} 11212864Sktlim@umich.edu 11222864Sktlim@umich.edutemplate <class Impl> 11232905Sktlim@umich.eduunsigned int 11249342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drain(DrainManager *drain_manager) 11251060SN/A{ 11263125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 11273512Sktlim@umich.edu 11283512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 11299152Satgutier@umich.edu if (_status == SwitchedOut) 11303512Sktlim@umich.edu return 0; 11313512Sktlim@umich.edu 11322843Sktlim@umich.edu drainCount = 0; 11332843Sktlim@umich.edu fetch.drain(); 11342843Sktlim@umich.edu decode.drain(); 11352843Sktlim@umich.edu rename.drain(); 11362843Sktlim@umich.edu iew.drain(); 11372843Sktlim@umich.edu commit.drain(); 11382325SN/A 11392325SN/A // Wake the CPU and record activity so everything can drain out if 11402863Sktlim@umich.edu // the CPU was not able to immediately drain. 11419342SAndreas.Sandberg@arm.com if (getDrainState() != Drainable::Drained) { 11429342SAndreas.Sandberg@arm.com // A bit of a hack...set the drainManager after all the drain() 11432864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 11442864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 11452864Sktlim@umich.edu // process on the drain event. 11469342SAndreas.Sandberg@arm.com drainManager = drain_manager; 11472843Sktlim@umich.edu 11482863Sktlim@umich.edu wakeCPU(); 11492863Sktlim@umich.edu activityRec.activity(); 11502852Sktlim@umich.edu 11519152Satgutier@umich.edu DPRINTF(Drain, "CPU not drained\n"); 11529152Satgutier@umich.edu 11532905Sktlim@umich.edu return 1; 11542863Sktlim@umich.edu } else { 11552905Sktlim@umich.edu return 0; 11562863Sktlim@umich.edu } 11572316SN/A} 11582310SN/A 11592316SN/Atemplate <class Impl> 11602316SN/Avoid 11619342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drainResume() 11622316SN/A{ 11632843Sktlim@umich.edu fetch.resume(); 11642843Sktlim@umich.edu decode.resume(); 11652843Sktlim@umich.edu rename.resume(); 11662843Sktlim@umich.edu iew.resume(); 11672843Sktlim@umich.edu commit.resume(); 11682316SN/A 11699342SAndreas.Sandberg@arm.com setDrainState(Drainable::Running); 11702905Sktlim@umich.edu 11719152Satgutier@umich.edu if (_status == SwitchedOut) 11722864Sktlim@umich.edu return; 11732864Sktlim@umich.edu 11749424SAndreas.Sandberg@ARM.com if (system->getMemoryMode() != Enums::timing) { 11759424SAndreas.Sandberg@ARM.com fatal("The O3 CPU requires the memory system to be in " 11769424SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 11779424SAndreas.Sandberg@ARM.com } 11783319Shsul@eecs.umich.edu 11792843Sktlim@umich.edu if (!tickEvent.scheduled()) 11805606Snate@binkert.org schedule(tickEvent, nextCycle()); 11812843Sktlim@umich.edu _status = Running; 11822843Sktlim@umich.edu} 11832316SN/A 11842843Sktlim@umich.edutemplate <class Impl> 11852843Sktlim@umich.eduvoid 11862843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 11872843Sktlim@umich.edu{ 11882843Sktlim@umich.edu if (++drainCount == NumStages) { 11892316SN/A if (tickEvent.scheduled()) 11902316SN/A tickEvent.squash(); 11912863Sktlim@umich.edu 11929342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 11932863Sktlim@umich.edu 11949342SAndreas.Sandberg@arm.com if (drainManager) { 11959152Satgutier@umich.edu DPRINTF(Drain, "CPU done draining, processing drain event\n"); 11969342SAndreas.Sandberg@arm.com drainManager->signalDrainDone(); 11979342SAndreas.Sandberg@arm.com drainManager = NULL; 11982863Sktlim@umich.edu } 11992310SN/A } 12002843Sktlim@umich.edu assert(drainCount <= 5); 12012843Sktlim@umich.edu} 12022843Sktlim@umich.edu 12032843Sktlim@umich.edutemplate <class Impl> 12042843Sktlim@umich.eduvoid 12052843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 12062843Sktlim@umich.edu{ 12079429SAndreas.Sandberg@ARM.com BaseCPU::switchOut(); 12089429SAndreas.Sandberg@ARM.com 12092843Sktlim@umich.edu fetch.switchOut(); 12102843Sktlim@umich.edu rename.switchOut(); 12112325SN/A iew.switchOut(); 12122843Sktlim@umich.edu commit.switchOut(); 12132843Sktlim@umich.edu instList.clear(); 12142843Sktlim@umich.edu while (!removeList.empty()) { 12152843Sktlim@umich.edu removeList.pop(); 12162843Sktlim@umich.edu } 12172843Sktlim@umich.edu 12182843Sktlim@umich.edu _status = SwitchedOut; 12198887Sgeoffrey.blake@arm.com 12202843Sktlim@umich.edu if (checker) 12212843Sktlim@umich.edu checker->switchOut(); 12228887Sgeoffrey.blake@arm.com 12233126Sktlim@umich.edu if (tickEvent.scheduled()) 12243126Sktlim@umich.edu tickEvent.squash(); 12251060SN/A} 12261060SN/A 12271060SN/Atemplate <class Impl> 12281060SN/Avoid 12291755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 12301060SN/A{ 12312325SN/A // Flush out any old data from the time buffers. 12322873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 12332307SN/A timeBuffer.advance(); 12342307SN/A fetchQueue.advance(); 12352307SN/A decodeQueue.advance(); 12362307SN/A renameQueue.advance(); 12372307SN/A iewQueue.advance(); 12382307SN/A } 12392307SN/A 12402325SN/A activityRec.reset(); 12412307SN/A 12428737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 12431060SN/A 12442307SN/A fetch.takeOverFrom(); 12452307SN/A decode.takeOverFrom(); 12462307SN/A rename.takeOverFrom(); 12472307SN/A iew.takeOverFrom(); 12482307SN/A commit.takeOverFrom(); 12492307SN/A 12507507Stjones1@inf.ed.ac.uk assert(!tickEvent.scheduled() || tickEvent.squashed()); 12511060SN/A 12529152Satgutier@umich.edu FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 12539152Satgutier@umich.edu if (oldO3CPU) 12549152Satgutier@umich.edu globalSeqNum = oldO3CPU->globalSeqNum; 12559152Satgutier@umich.edu 12562325SN/A // @todo: Figure out how to properly select the tid to put onto 12572325SN/A // the active threads list. 12586221Snate@binkert.org ThreadID tid = 0; 12592307SN/A 12606221Snate@binkert.org list<ThreadID>::iterator isActive = 12615314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 12622307SN/A 12632307SN/A if (isActive == activeThreads.end()) { 12642325SN/A //May Need to Re-code this if the delay variable is the delay 12652325SN/A //needed for thread to activate 12662733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 12672307SN/A tid); 12682307SN/A 12692307SN/A activeThreads.push_back(tid); 12702307SN/A } 12712307SN/A 12722325SN/A // Set all statuses to active, schedule the CPU's tick event. 12732307SN/A // @todo: Fix up statuses so this is handled properly 12746221Snate@binkert.org ThreadID size = threadContexts.size(); 12756221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 12762680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 12772680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 12781681SN/A _status = Running; 12797507Stjones1@inf.ed.ac.uk reschedule(tickEvent, nextCycle(), true); 12801681SN/A } 12811060SN/A } 12822307SN/A if (!tickEvent.scheduled()) 12835606Snate@binkert.org schedule(tickEvent, nextCycle()); 12848627SAli.Saidi@ARM.com 12859179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 12861060SN/A} 12871060SN/A 12881060SN/Atemplate <class Impl> 12895595Sgblack@eecs.umich.eduTheISA::MiscReg 12906221Snate@binkert.orgFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 12915595Sgblack@eecs.umich.edu{ 12929384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscRegNoEffect(misc_reg); 12935595Sgblack@eecs.umich.edu} 12945595Sgblack@eecs.umich.edu 12955595Sgblack@eecs.umich.edutemplate <class Impl> 12965595Sgblack@eecs.umich.eduTheISA::MiscReg 12976221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 12985595Sgblack@eecs.umich.edu{ 12997897Shestness@cs.utexas.edu miscRegfileReads++; 13009384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 13015595Sgblack@eecs.umich.edu} 13025595Sgblack@eecs.umich.edu 13035595Sgblack@eecs.umich.edutemplate <class Impl> 13045595Sgblack@eecs.umich.eduvoid 13055595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 13066221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 13075595Sgblack@eecs.umich.edu{ 13089384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 13095595Sgblack@eecs.umich.edu} 13105595Sgblack@eecs.umich.edu 13115595Sgblack@eecs.umich.edutemplate <class Impl> 13125595Sgblack@eecs.umich.eduvoid 13135595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 13146221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 13155595Sgblack@eecs.umich.edu{ 13167897Shestness@cs.utexas.edu miscRegfileWrites++; 13179384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 13185595Sgblack@eecs.umich.edu} 13195595Sgblack@eecs.umich.edu 13205595Sgblack@eecs.umich.edutemplate <class Impl> 13211060SN/Auint64_t 13221755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 13231060SN/A{ 13247897Shestness@cs.utexas.edu intRegfileReads++; 13251060SN/A return regFile.readIntReg(reg_idx); 13261060SN/A} 13271060SN/A 13281060SN/Atemplate <class Impl> 13292455SN/AFloatReg 13302455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 13311060SN/A{ 13327897Shestness@cs.utexas.edu fpRegfileReads++; 13332455SN/A return regFile.readFloatReg(reg_idx); 13341060SN/A} 13351060SN/A 13361060SN/Atemplate <class Impl> 13372455SN/AFloatRegBits 13382455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 13392455SN/A{ 13407897Shestness@cs.utexas.edu fpRegfileReads++; 13412455SN/A return regFile.readFloatRegBits(reg_idx); 13421060SN/A} 13431060SN/A 13441060SN/Atemplate <class Impl> 13451060SN/Avoid 13461755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 13471060SN/A{ 13487897Shestness@cs.utexas.edu intRegfileWrites++; 13491060SN/A regFile.setIntReg(reg_idx, val); 13501060SN/A} 13511060SN/A 13521060SN/Atemplate <class Impl> 13531060SN/Avoid 13542455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 13551060SN/A{ 13567897Shestness@cs.utexas.edu fpRegfileWrites++; 13572455SN/A regFile.setFloatReg(reg_idx, val); 13581060SN/A} 13591060SN/A 13601060SN/Atemplate <class Impl> 13611060SN/Avoid 13622455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 13632455SN/A{ 13647897Shestness@cs.utexas.edu fpRegfileWrites++; 13652455SN/A regFile.setFloatRegBits(reg_idx, val); 13661060SN/A} 13671060SN/A 13681060SN/Atemplate <class Impl> 13691060SN/Auint64_t 13706221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 13711060SN/A{ 13727897Shestness@cs.utexas.edu intRegfileReads++; 13732292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13742292SN/A 13752292SN/A return regFile.readIntReg(phys_reg); 13762292SN/A} 13772292SN/A 13782292SN/Atemplate <class Impl> 13792292SN/Afloat 13806314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 13812292SN/A{ 13827897Shestness@cs.utexas.edu fpRegfileReads++; 13836032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13842307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13852292SN/A 13862669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 13872292SN/A} 13882292SN/A 13892292SN/Atemplate <class Impl> 13902292SN/Auint64_t 13916221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 13922292SN/A{ 13937897Shestness@cs.utexas.edu fpRegfileReads++; 13946032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13952307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13962292SN/A 13972669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13981060SN/A} 13991060SN/A 14001060SN/Atemplate <class Impl> 14011060SN/Avoid 14026221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 14031060SN/A{ 14047897Shestness@cs.utexas.edu intRegfileWrites++; 14052292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 14062292SN/A 14072292SN/A regFile.setIntReg(phys_reg, val); 14081060SN/A} 14091060SN/A 14101060SN/Atemplate <class Impl> 14111060SN/Avoid 14126314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 14131060SN/A{ 14147897Shestness@cs.utexas.edu fpRegfileWrites++; 14156032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 14162918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 14172292SN/A 14182669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 14191060SN/A} 14201060SN/A 14211060SN/Atemplate <class Impl> 14221060SN/Avoid 14236221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 14241060SN/A{ 14257897Shestness@cs.utexas.edu fpRegfileWrites++; 14266032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 14272918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 14281060SN/A 14292669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 14302292SN/A} 14312292SN/A 14322292SN/Atemplate <class Impl> 14337720Sgblack@eecs.umich.eduTheISA::PCState 14347720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 14352292SN/A{ 14367720Sgblack@eecs.umich.edu return commit.pcState(tid); 14371060SN/A} 14381060SN/A 14391060SN/Atemplate <class Impl> 14401060SN/Avoid 14417720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 14421060SN/A{ 14437720Sgblack@eecs.umich.edu commit.pcState(val, tid); 14442292SN/A} 14451060SN/A 14462292SN/Atemplate <class Impl> 14477720Sgblack@eecs.umich.eduAddr 14487720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 14494636Sgblack@eecs.umich.edu{ 14507720Sgblack@eecs.umich.edu return commit.instAddr(tid); 14514636Sgblack@eecs.umich.edu} 14524636Sgblack@eecs.umich.edu 14534636Sgblack@eecs.umich.edutemplate <class Impl> 14547720Sgblack@eecs.umich.eduAddr 14557720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 14564636Sgblack@eecs.umich.edu{ 14577720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 14584636Sgblack@eecs.umich.edu} 14594636Sgblack@eecs.umich.edu 14604636Sgblack@eecs.umich.edutemplate <class Impl> 14617720Sgblack@eecs.umich.eduMicroPC 14627720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 14632292SN/A{ 14647720Sgblack@eecs.umich.edu return commit.microPC(tid); 14654636Sgblack@eecs.umich.edu} 14664636Sgblack@eecs.umich.edu 14674636Sgblack@eecs.umich.edutemplate <class Impl> 14685595Sgblack@eecs.umich.eduvoid 14696221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 14705595Sgblack@eecs.umich.edu{ 14719382SAli.Saidi@ARM.com this->thread[tid]->noSquashFromTC = true; 14725595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 14735595Sgblack@eecs.umich.edu} 14745595Sgblack@eecs.umich.edu 14755595Sgblack@eecs.umich.edutemplate <class Impl> 14762292SN/Atypename FullO3CPU<Impl>::ListIt 14772292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14782292SN/A{ 14792292SN/A instList.push_back(inst); 14801060SN/A 14812292SN/A return --(instList.end()); 14822292SN/A} 14831060SN/A 14842292SN/Atemplate <class Impl> 14852292SN/Avoid 14868834Satgutier@umich.eduFullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 14872292SN/A{ 14882292SN/A // Keep an instruction count. 14898834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 14908834Satgutier@umich.edu thread[tid]->numInst++; 14918834Satgutier@umich.edu thread[tid]->numInsts++; 14928834Satgutier@umich.edu committedInsts[tid]++; 14938834Satgutier@umich.edu totalCommittedInsts++; 14948834Satgutier@umich.edu } 14958834Satgutier@umich.edu thread[tid]->numOp++; 14968834Satgutier@umich.edu thread[tid]->numOps++; 14978834Satgutier@umich.edu committedOps[tid]++; 14988834Satgutier@umich.edu 14997897Shestness@cs.utexas.edu system->totalNumInsts++; 15002292SN/A // Check for instruction-count-based events. 15012292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 15027897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 15032292SN/A} 15042292SN/A 15052292SN/Atemplate <class Impl> 15062292SN/Avoid 15071755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 15081060SN/A{ 15097720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 15102292SN/A "[sn:%lli]\n", 15117720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 15121060SN/A 15132292SN/A removeInstsThisCycle = true; 15141060SN/A 15151060SN/A // Remove the front instruction. 15162292SN/A removeList.push(inst->getInstListIt()); 15171060SN/A} 15181060SN/A 15191060SN/Atemplate <class Impl> 15201060SN/Avoid 15216221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 15221060SN/A{ 15232733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 15242292SN/A " list.\n", tid); 15251060SN/A 15262292SN/A ListIt end_it; 15271060SN/A 15282292SN/A bool rob_empty = false; 15292292SN/A 15302292SN/A if (instList.empty()) { 15312292SN/A return; 15322292SN/A } else if (rob.isEmpty(/*tid*/)) { 15332733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 15342292SN/A end_it = instList.begin(); 15352292SN/A rob_empty = true; 15362292SN/A } else { 15372292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 15382733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 15392292SN/A } 15402292SN/A 15412292SN/A removeInstsThisCycle = true; 15422292SN/A 15432292SN/A ListIt inst_it = instList.end(); 15442292SN/A 15452292SN/A inst_it--; 15462292SN/A 15472292SN/A // Walk through the instruction list, removing any instructions 15482292SN/A // that were inserted after the given instruction iterator, end_it. 15492292SN/A while (inst_it != end_it) { 15502292SN/A assert(!instList.empty()); 15512292SN/A 15522292SN/A squashInstIt(inst_it, tid); 15532292SN/A 15542292SN/A inst_it--; 15552292SN/A } 15562292SN/A 15572292SN/A // If the ROB was empty, then we actually need to remove the first 15582292SN/A // instruction as well. 15592292SN/A if (rob_empty) { 15602292SN/A squashInstIt(inst_it, tid); 15612292SN/A } 15621060SN/A} 15631060SN/A 15641060SN/Atemplate <class Impl> 15651060SN/Avoid 15666221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 15671062SN/A{ 15682292SN/A assert(!instList.empty()); 15692292SN/A 15702292SN/A removeInstsThisCycle = true; 15712292SN/A 15722292SN/A ListIt inst_iter = instList.end(); 15732292SN/A 15742292SN/A inst_iter--; 15752292SN/A 15762733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 15772292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15782292SN/A tid, seq_num, (*inst_iter)->seqNum); 15791062SN/A 15802292SN/A while ((*inst_iter)->seqNum > seq_num) { 15811062SN/A 15822292SN/A bool break_loop = (inst_iter == instList.begin()); 15831062SN/A 15842292SN/A squashInstIt(inst_iter, tid); 15851062SN/A 15862292SN/A inst_iter--; 15871062SN/A 15882292SN/A if (break_loop) 15892292SN/A break; 15902292SN/A } 15912292SN/A} 15922292SN/A 15932292SN/Atemplate <class Impl> 15942292SN/Ainline void 15956221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 15962292SN/A{ 15972292SN/A if ((*instIt)->threadNumber == tid) { 15982733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 15997720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 16002292SN/A (*instIt)->threadNumber, 16012292SN/A (*instIt)->seqNum, 16027720Sgblack@eecs.umich.edu (*instIt)->pcState()); 16031062SN/A 16041062SN/A // Mark it as squashed. 16052292SN/A (*instIt)->setSquashed(); 16062292SN/A 16072325SN/A // @todo: Formulate a consistent method for deleting 16082325SN/A // instructions from the instruction list 16092292SN/A // Remove the instruction from the list. 16102292SN/A removeList.push(instIt); 16112292SN/A } 16122292SN/A} 16132292SN/A 16142292SN/Atemplate <class Impl> 16152292SN/Avoid 16162292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 16172292SN/A{ 16182292SN/A while (!removeList.empty()) { 16192733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 16207720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 16212292SN/A (*removeList.front())->threadNumber, 16222292SN/A (*removeList.front())->seqNum, 16237720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 16242292SN/A 16252292SN/A instList.erase(removeList.front()); 16262292SN/A 16272292SN/A removeList.pop(); 16281062SN/A } 16291062SN/A 16302292SN/A removeInstsThisCycle = false; 16311062SN/A} 16322325SN/A/* 16331062SN/Atemplate <class Impl> 16341062SN/Avoid 16351755SN/AFullO3CPU<Impl>::removeAllInsts() 16361060SN/A{ 16371060SN/A instList.clear(); 16381060SN/A} 16392325SN/A*/ 16401060SN/Atemplate <class Impl> 16411060SN/Avoid 16421755SN/AFullO3CPU<Impl>::dumpInsts() 16431060SN/A{ 16441060SN/A int num = 0; 16451060SN/A 16462292SN/A ListIt inst_list_it = instList.begin(); 16472292SN/A 16482292SN/A cprintf("Dumping Instruction List\n"); 16492292SN/A 16502292SN/A while (inst_list_it != instList.end()) { 16512292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 16522292SN/A "Squashed:%i\n\n", 16537720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 16542292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16552292SN/A (*inst_list_it)->isSquashed()); 16561060SN/A inst_list_it++; 16571060SN/A ++num; 16581060SN/A } 16591060SN/A} 16602325SN/A/* 16611060SN/Atemplate <class Impl> 16621060SN/Avoid 16631755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 16641060SN/A{ 16651060SN/A iew.wakeDependents(inst); 16661060SN/A} 16672325SN/A*/ 16682292SN/Atemplate <class Impl> 16692292SN/Avoid 16702292SN/AFullO3CPU<Impl>::wakeCPU() 16712292SN/A{ 16722325SN/A if (activityRec.active() || tickEvent.scheduled()) { 16732325SN/A DPRINTF(Activity, "CPU already running.\n"); 16742292SN/A return; 16752292SN/A } 16762292SN/A 16772325SN/A DPRINTF(Activity, "Waking up CPU\n"); 16782325SN/A 16799180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 16809180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 16819179Sandreas.hansson@arm.com if (cycles != 0) 16829179Sandreas.hansson@arm.com --cycles; 16839179Sandreas.hansson@arm.com idleCycles += cycles; 16849179Sandreas.hansson@arm.com numCycles += cycles; 16852292SN/A 16865606Snate@binkert.org schedule(tickEvent, nextCycle()); 16872292SN/A} 16882292SN/A 16895807Snate@binkert.orgtemplate <class Impl> 16905807Snate@binkert.orgvoid 16915807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 16925807Snate@binkert.org{ 16935807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 16945807Snate@binkert.org return; 16955807Snate@binkert.org 16965807Snate@binkert.org this->wakeCPU(); 16975807Snate@binkert.org 16985807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 16995807Snate@binkert.org this->threadContexts[0]->activate(); 17005807Snate@binkert.org} 17015807Snate@binkert.org 17022292SN/Atemplate <class Impl> 17036221Snate@binkert.orgThreadID 17042292SN/AFullO3CPU<Impl>::getFreeTid() 17052292SN/A{ 17066221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 17076221Snate@binkert.org if (!tids[tid]) { 17086221Snate@binkert.org tids[tid] = true; 17096221Snate@binkert.org return tid; 17102292SN/A } 17112292SN/A } 17122292SN/A 17136221Snate@binkert.org return InvalidThreadID; 17142292SN/A} 17152292SN/A 17162292SN/Atemplate <class Impl> 17172292SN/Avoid 17182292SN/AFullO3CPU<Impl>::doContextSwitch() 17192292SN/A{ 17202292SN/A if (contextSwitch) { 17212292SN/A 17222292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 17232292SN/A 17246221Snate@binkert.org ThreadID size = cpuWaitList.size(); 17256221Snate@binkert.org for (ThreadID tid = 0; tid < size; tid++) { 17262292SN/A activateWhenReady(tid); 17272292SN/A } 17282292SN/A 17292292SN/A if (cpuWaitList.size() == 0) 17302292SN/A contextSwitch = true; 17312292SN/A } 17322292SN/A} 17332292SN/A 17342292SN/Atemplate <class Impl> 17352292SN/Avoid 17362292SN/AFullO3CPU<Impl>::updateThreadPriority() 17372292SN/A{ 17386221Snate@binkert.org if (activeThreads.size() > 1) { 17392292SN/A //DEFAULT TO ROUND ROBIN SCHEME 17402292SN/A //e.g. Move highest priority to end of thread list 17416221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 17422292SN/A 17432292SN/A unsigned high_thread = *list_begin; 17442292SN/A 17452292SN/A activeThreads.erase(list_begin); 17462292SN/A 17472292SN/A activeThreads.push_back(high_thread); 17482292SN/A } 17492292SN/A} 17501060SN/A 17511755SN/A// Forward declaration of FullO3CPU. 17522818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1753