cpu.cc revision 9180
11689SN/A/* 28948Sandreas.hansson@arm.com * Copyright (c) 2011-2012 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 142325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422756Sksewell@umich.edu * Korey Sewell 437897Shestness@cs.utexas.edu * Rick Strong 441689SN/A */ 451689SN/A 468779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 498887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 508229Snate@binkert.org#include "cpu/o3/cpu.hh" 518229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 528229Snate@binkert.org#include "cpu/o3/thread_context.hh" 534762Snate@binkert.org#include "cpu/activity.hh" 548779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 554762Snate@binkert.org#include "cpu/simple_thread.hh" 564762Snate@binkert.org#include "cpu/thread_context.hh" 578232Snate@binkert.org#include "debug/Activity.hh" 589152Satgutier@umich.edu#include "debug/Drain.hh" 598232Snate@binkert.org#include "debug/O3CPU.hh" 608232Snate@binkert.org#include "debug/Quiesce.hh" 614762Snate@binkert.org#include "enums/MemoryMode.hh" 624762Snate@binkert.org#include "sim/core.hh" 638793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 648779Sgblack@eecs.umich.edu#include "sim/process.hh" 654762Snate@binkert.org#include "sim/stat_control.hh" 668460SAli.Saidi@ARM.com#include "sim/system.hh" 674762Snate@binkert.org 685702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 695702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 708232Snate@binkert.org#include "debug/Activity.hh" 715702Ssaidi@eecs.umich.edu#endif 725702Ssaidi@eecs.umich.edu 738737Skoansin.tan@gmail.comstruct BaseCPUParams; 745529Snate@binkert.org 752669Sktlim@umich.eduusing namespace TheISA; 766221Snate@binkert.orgusing namespace std; 771060SN/A 785529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 795712Shsul@eecs.umich.edu : BaseCPU(params) 801060SN/A{ 811060SN/A} 821060SN/A 832292SN/Avoid 842733Sktlim@umich.eduBaseO3CPU::regStats() 852292SN/A{ 862292SN/A BaseCPU::regStats(); 872292SN/A} 882292SN/A 898707Sandreas.hansson@arm.comtemplate<class Impl> 908707Sandreas.hansson@arm.combool 918975Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 928707Sandreas.hansson@arm.com{ 938707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 948948Sandreas.hansson@arm.com // We shouldn't ever get a block in ownership state 958948Sandreas.hansson@arm.com assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 968948Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 978707Sandreas.hansson@arm.com 988707Sandreas.hansson@arm.com return true; 998707Sandreas.hansson@arm.com} 1008707Sandreas.hansson@arm.com 1018707Sandreas.hansson@arm.comtemplate<class Impl> 1028707Sandreas.hansson@arm.comvoid 1038707Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvRetry() 1048707Sandreas.hansson@arm.com{ 1058707Sandreas.hansson@arm.com fetch->recvRetry(); 1068707Sandreas.hansson@arm.com} 1078707Sandreas.hansson@arm.com 1088707Sandreas.hansson@arm.comtemplate <class Impl> 1098707Sandreas.hansson@arm.combool 1108975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 1118707Sandreas.hansson@arm.com{ 1128975Sandreas.hansson@arm.com return lsq->recvTimingResp(pkt); 1138707Sandreas.hansson@arm.com} 1148707Sandreas.hansson@arm.com 1158707Sandreas.hansson@arm.comtemplate <class Impl> 1168975Sandreas.hansson@arm.comvoid 1178975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 1188948Sandreas.hansson@arm.com{ 1198975Sandreas.hansson@arm.com lsq->recvTimingSnoopReq(pkt); 1208948Sandreas.hansson@arm.com} 1218948Sandreas.hansson@arm.com 1228948Sandreas.hansson@arm.comtemplate <class Impl> 1238707Sandreas.hansson@arm.comvoid 1248707Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvRetry() 1258707Sandreas.hansson@arm.com{ 1268707Sandreas.hansson@arm.com lsq->recvRetry(); 1278707Sandreas.hansson@arm.com} 1288707Sandreas.hansson@arm.com 1291060SN/Atemplate <class Impl> 1301755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 1315606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 1321060SN/A{ 1331060SN/A} 1341060SN/A 1351060SN/Atemplate <class Impl> 1361060SN/Avoid 1371755SN/AFullO3CPU<Impl>::TickEvent::process() 1381060SN/A{ 1391060SN/A cpu->tick(); 1401060SN/A} 1411060SN/A 1421060SN/Atemplate <class Impl> 1431060SN/Aconst char * 1445336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 1451060SN/A{ 1464873Sstever@eecs.umich.edu return "FullO3CPU tick"; 1471060SN/A} 1481060SN/A 1491060SN/Atemplate <class Impl> 1502829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 1515606Snate@binkert.org : Event(CPU_Switch_Pri) 1522829Sksewell@umich.edu{ 1532829Sksewell@umich.edu} 1542829Sksewell@umich.edu 1552829Sksewell@umich.edutemplate <class Impl> 1562829Sksewell@umich.eduvoid 1572829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1582829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1592829Sksewell@umich.edu{ 1602829Sksewell@umich.edu tid = thread_num; 1612829Sksewell@umich.edu cpu = thread_cpu; 1622829Sksewell@umich.edu} 1632829Sksewell@umich.edu 1642829Sksewell@umich.edutemplate <class Impl> 1652829Sksewell@umich.eduvoid 1662829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1672829Sksewell@umich.edu{ 1682829Sksewell@umich.edu cpu->activateThread(tid); 1692829Sksewell@umich.edu} 1702829Sksewell@umich.edu 1712829Sksewell@umich.edutemplate <class Impl> 1722829Sksewell@umich.educonst char * 1735336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1742829Sksewell@umich.edu{ 1754873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1762829Sksewell@umich.edu} 1772829Sksewell@umich.edu 1782829Sksewell@umich.edutemplate <class Impl> 1792875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1805606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1812875Sksewell@umich.edu{ 1822875Sksewell@umich.edu} 1832875Sksewell@umich.edu 1842875Sksewell@umich.edutemplate <class Impl> 1852875Sksewell@umich.eduvoid 1862875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1873859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1882875Sksewell@umich.edu{ 1892875Sksewell@umich.edu tid = thread_num; 1902875Sksewell@umich.edu cpu = thread_cpu; 1913859Sbinkertn@umich.edu remove = false; 1922875Sksewell@umich.edu} 1932875Sksewell@umich.edu 1942875Sksewell@umich.edutemplate <class Impl> 1952875Sksewell@umich.eduvoid 1962875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1972875Sksewell@umich.edu{ 1982875Sksewell@umich.edu cpu->deactivateThread(tid); 1993221Sktlim@umich.edu if (remove) 2003221Sktlim@umich.edu cpu->removeThread(tid); 2012875Sksewell@umich.edu} 2022875Sksewell@umich.edu 2032875Sksewell@umich.edutemplate <class Impl> 2042875Sksewell@umich.educonst char * 2055336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 2062875Sksewell@umich.edu{ 2074873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 2082875Sksewell@umich.edu} 2092875Sksewell@umich.edu 2102875Sksewell@umich.edutemplate <class Impl> 2115595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 2122733Sktlim@umich.edu : BaseO3CPU(params), 2133781Sgblack@eecs.umich.edu itb(params->itb), 2143781Sgblack@eecs.umich.edu dtb(params->dtb), 2151060SN/A tickEvent(this), 2165737Scws3k@cs.virginia.edu#ifndef NDEBUG 2175737Scws3k@cs.virginia.edu instcount(0), 2185737Scws3k@cs.virginia.edu#endif 2192292SN/A removeInstsThisCycle(false), 2205595Sgblack@eecs.umich.edu fetch(this, params), 2215595Sgblack@eecs.umich.edu decode(this, params), 2225595Sgblack@eecs.umich.edu rename(this, params), 2235595Sgblack@eecs.umich.edu iew(this, params), 2245595Sgblack@eecs.umich.edu commit(this, params), 2251060SN/A 2265595Sgblack@eecs.umich.edu regFile(this, params->numPhysIntRegs, 2274329Sktlim@umich.edu params->numPhysFloatRegs), 2281060SN/A 2295529Snate@binkert.org freeList(params->numThreads, 2302292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 2312292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 2321060SN/A 2335595Sgblack@eecs.umich.edu rob(this, 2344329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 2352292SN/A params->smtROBPolicy, params->smtROBThreshold, 2365529Snate@binkert.org params->numThreads), 2371060SN/A 2385529Snate@binkert.org scoreboard(params->numThreads, 2392292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 2402292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 2416221Snate@binkert.org TheISA::NumMiscRegs * numThreads, 2422292SN/A TheISA::ZeroReg), 2431060SN/A 2448707Sandreas.hansson@arm.com icachePort(&fetch, this), 2458707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 2468707Sandreas.hansson@arm.com 2472873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 2482873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 2492873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 2502873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 2512873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 2525804Snate@binkert.org activityRec(name(), NumStages, 2532873Sktlim@umich.edu params->backComSize + params->forwardComSize, 2542873Sktlim@umich.edu params->activity), 2551060SN/A 2561060SN/A globalSeqNum(1), 2572292SN/A system(params->system), 2582843Sktlim@umich.edu drainCount(0), 2599180Sandreas.hansson@arm.com deferRegistration(params->defer_registration), 2609180Sandreas.hansson@arm.com lastRunningCycle(curCycle()) 2611060SN/A{ 2623221Sktlim@umich.edu if (!deferRegistration) { 2633221Sktlim@umich.edu _status = Running; 2643221Sktlim@umich.edu } else { 2659152Satgutier@umich.edu _status = SwitchedOut; 2663221Sktlim@umich.edu } 2671681SN/A 2682794Sktlim@umich.edu if (params->checker) { 2692316SN/A BaseCPU *temp_checker = params->checker; 2708733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 2718707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2722316SN/A checker->setSystem(params->system); 2734598Sbinkertn@umich.edu } else { 2744598Sbinkertn@umich.edu checker = NULL; 2754598Sbinkertn@umich.edu } 2762316SN/A 2778793Sgblack@eecs.umich.edu if (!FullSystem) { 2788793Sgblack@eecs.umich.edu thread.resize(numThreads); 2798793Sgblack@eecs.umich.edu tids.resize(numThreads); 2808793Sgblack@eecs.umich.edu } 2811681SN/A 2822325SN/A // The stages also need their CPU pointer setup. However this 2832325SN/A // must be done at the upper level CPU because they have pointers 2842325SN/A // to the upper level CPU, and not this FullO3CPU. 2851060SN/A 2862292SN/A // Set up Pointers to the activeThreads list for each stage 2872292SN/A fetch.setActiveThreads(&activeThreads); 2882292SN/A decode.setActiveThreads(&activeThreads); 2892292SN/A rename.setActiveThreads(&activeThreads); 2902292SN/A iew.setActiveThreads(&activeThreads); 2912292SN/A commit.setActiveThreads(&activeThreads); 2921060SN/A 2931060SN/A // Give each of the stages the time buffer they will use. 2941060SN/A fetch.setTimeBuffer(&timeBuffer); 2951060SN/A decode.setTimeBuffer(&timeBuffer); 2961060SN/A rename.setTimeBuffer(&timeBuffer); 2971060SN/A iew.setTimeBuffer(&timeBuffer); 2981060SN/A commit.setTimeBuffer(&timeBuffer); 2991060SN/A 3001060SN/A // Also setup each of the stages' queues. 3011060SN/A fetch.setFetchQueue(&fetchQueue); 3021060SN/A decode.setFetchQueue(&fetchQueue); 3032292SN/A commit.setFetchQueue(&fetchQueue); 3041060SN/A decode.setDecodeQueue(&decodeQueue); 3051060SN/A rename.setDecodeQueue(&decodeQueue); 3061060SN/A rename.setRenameQueue(&renameQueue); 3071060SN/A iew.setRenameQueue(&renameQueue); 3081060SN/A iew.setIEWQueue(&iewQueue); 3091060SN/A commit.setIEWQueue(&iewQueue); 3101060SN/A commit.setRenameQueue(&renameQueue); 3111060SN/A 3122292SN/A commit.setIEWStage(&iew); 3132292SN/A rename.setIEWStage(&iew); 3142292SN/A rename.setCommitStage(&commit); 3152292SN/A 3168793Sgblack@eecs.umich.edu ThreadID active_threads; 3178793Sgblack@eecs.umich.edu if (FullSystem) { 3188793Sgblack@eecs.umich.edu active_threads = 1; 3198793Sgblack@eecs.umich.edu } else { 3208793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 3212831Sksewell@umich.edu 3228793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 3238793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 3248793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 3258793Sgblack@eecs.umich.edu "or edit your workload size."); 3268793Sgblack@eecs.umich.edu } 3272831Sksewell@umich.edu } 3282292SN/A 3292316SN/A //Make Sure That this a Valid Architeture 3302292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 3312292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 3322292SN/A 3332292SN/A rename.setScoreboard(&scoreboard); 3342292SN/A iew.setScoreboard(&scoreboard); 3352292SN/A 3361060SN/A // Setup the rename map for whichever stages need it. 3372292SN/A PhysRegIndex lreg_idx = 0; 3382292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 3391060SN/A 3406221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3412307SN/A bool bindRegs = (tid <= active_threads - 1); 3422292SN/A 3432292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 3442292SN/A params->numPhysIntRegs, 3452325SN/A lreg_idx, //Index for Logical. Regs 3462292SN/A 3472292SN/A TheISA::NumFloatRegs, 3482292SN/A params->numPhysFloatRegs, 3492325SN/A freg_idx, //Index for Float Regs 3502292SN/A 3512292SN/A TheISA::NumMiscRegs, 3522292SN/A 3532292SN/A TheISA::ZeroReg, 3542292SN/A TheISA::ZeroReg, 3552292SN/A 3562292SN/A tid, 3572292SN/A false); 3582292SN/A 3592292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3602292SN/A params->numPhysIntRegs, 3612325SN/A lreg_idx, //Index for Logical. Regs 3622292SN/A 3632292SN/A TheISA::NumFloatRegs, 3642292SN/A params->numPhysFloatRegs, 3652325SN/A freg_idx, //Index for Float Regs 3662292SN/A 3672292SN/A TheISA::NumMiscRegs, 3682292SN/A 3692292SN/A TheISA::ZeroReg, 3702292SN/A TheISA::ZeroReg, 3712292SN/A 3722292SN/A tid, 3732292SN/A bindRegs); 3743221Sktlim@umich.edu 3753221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3763221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3772292SN/A } 3782292SN/A 3792292SN/A rename.setRenameMap(renameMap); 3802292SN/A commit.setRenameMap(commitRenameMap); 3812292SN/A 3822292SN/A // Give renameMap & rename stage access to the freeList; 3836221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3846221Snate@binkert.org renameMap[tid].setFreeList(&freeList); 3851060SN/A rename.setFreeList(&freeList); 3862292SN/A 3871060SN/A // Setup the ROB for whichever stages need it. 3881060SN/A commit.setROB(&rob); 3892292SN/A 3909158Sandreas.hansson@arm.com lastActivatedCycle = 0; 3916221Snate@binkert.org#if 0 3923093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3936221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3946221Snate@binkert.org globalSeqNum[tid] = 1; 3956221Snate@binkert.org#endif 3963093Sksewell@umich.edu 3972292SN/A contextSwitch = false; 3985595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3995595Sgblack@eecs.umich.edu 4005595Sgblack@eecs.umich.edu // Setup any thread state. 4015595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 4025595Sgblack@eecs.umich.edu 4036221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 4048793Sgblack@eecs.umich.edu if (FullSystem) { 4058793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 4068793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 4078793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 4088793Sgblack@eecs.umich.edu } else { 4098793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 4108793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 4118793Sgblack@eecs.umich.edu tid, this->thread[tid]); 4128793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4138793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4148793Sgblack@eecs.umich.edu tid, params->workload[tid]); 4155595Sgblack@eecs.umich.edu 4168793Sgblack@eecs.umich.edu //usedTids[tid] = true; 4178793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 4188793Sgblack@eecs.umich.edu } else { 4198793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 4208793Sgblack@eecs.umich.edu //when scheduling threads to CPU 4218793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 4225595Sgblack@eecs.umich.edu 4238793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4248793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4258793Sgblack@eecs.umich.edu tid, dummy_proc); 4268793Sgblack@eecs.umich.edu //usedTids[tid] = false; 4278793Sgblack@eecs.umich.edu } 4285595Sgblack@eecs.umich.edu } 4295595Sgblack@eecs.umich.edu 4305595Sgblack@eecs.umich.edu ThreadContext *tc; 4315595Sgblack@eecs.umich.edu 4325595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 4335595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 4345595Sgblack@eecs.umich.edu 4355595Sgblack@eecs.umich.edu tc = o3_tc; 4365595Sgblack@eecs.umich.edu 4375595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 4385595Sgblack@eecs.umich.edu // CheckerThreadContext. 4395595Sgblack@eecs.umich.edu if (params->checker) { 4405595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 4415595Sgblack@eecs.umich.edu o3_tc, this->checker); 4425595Sgblack@eecs.umich.edu } 4435595Sgblack@eecs.umich.edu 4445595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 4455595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 4466221Snate@binkert.org o3_tc->thread = this->thread[tid]; 4475595Sgblack@eecs.umich.edu 4488793Sgblack@eecs.umich.edu if (FullSystem) { 4498793Sgblack@eecs.umich.edu // Setup quiesce event. 4508793Sgblack@eecs.umich.edu this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 4518793Sgblack@eecs.umich.edu } 4525595Sgblack@eecs.umich.edu // Give the thread the TC. 4536221Snate@binkert.org this->thread[tid]->tc = tc; 4545595Sgblack@eecs.umich.edu 4555595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4565595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4575595Sgblack@eecs.umich.edu } 4585595Sgblack@eecs.umich.edu 4598876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 4608876Sandreas.hansson@arm.com if (!params->defer_registration && !interrupts) { 4618876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 4628876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 4638876Sandreas.hansson@arm.com } 4648876Sandreas.hansson@arm.com 4656221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4666221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4675595Sgblack@eecs.umich.edu 4685595Sgblack@eecs.umich.edu lockAddr = 0; 4695595Sgblack@eecs.umich.edu lockFlag = false; 4701060SN/A} 4711060SN/A 4721060SN/Atemplate <class Impl> 4731755SN/AFullO3CPU<Impl>::~FullO3CPU() 4741060SN/A{ 4751060SN/A} 4761060SN/A 4771060SN/Atemplate <class Impl> 4781060SN/Avoid 4795595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4801062SN/A{ 4812733Sktlim@umich.edu BaseO3CPU::regStats(); 4822292SN/A 4832733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4842292SN/A timesIdled 4852292SN/A .name(name() + ".timesIdled") 4862292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4872292SN/A " unscheduled itself") 4882292SN/A .prereq(timesIdled); 4892292SN/A 4902292SN/A idleCycles 4912292SN/A .name(name() + ".idleCycles") 4922292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4932292SN/A "to idling") 4942292SN/A .prereq(idleCycles); 4952292SN/A 4968627SAli.Saidi@ARM.com quiesceCycles 4978627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 4988627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 4998627SAli.Saidi@ARM.com "for an interrupt") 5008627SAli.Saidi@ARM.com .prereq(quiesceCycles); 5018627SAli.Saidi@ARM.com 5022292SN/A // Number of Instructions simulated 5032292SN/A // -------------------------------- 5042292SN/A // Should probably be in Base CPU but need templated 5052292SN/A // MaxThreads so put in here instead 5062292SN/A committedInsts 5072292SN/A .init(numThreads) 5082292SN/A .name(name() + ".committedInsts") 5092292SN/A .desc("Number of Instructions Simulated"); 5102292SN/A 5118834Satgutier@umich.edu committedOps 5128834Satgutier@umich.edu .init(numThreads) 5138834Satgutier@umich.edu .name(name() + ".committedOps") 5148834Satgutier@umich.edu .desc("Number of Ops (including micro ops) Simulated"); 5158834Satgutier@umich.edu 5162292SN/A totalCommittedInsts 5172292SN/A .name(name() + ".committedInsts_total") 5182292SN/A .desc("Number of Instructions Simulated"); 5192292SN/A 5202292SN/A cpi 5212292SN/A .name(name() + ".cpi") 5222292SN/A .desc("CPI: Cycles Per Instruction") 5232292SN/A .precision(6); 5244392Sktlim@umich.edu cpi = numCycles / committedInsts; 5252292SN/A 5262292SN/A totalCpi 5272292SN/A .name(name() + ".cpi_total") 5282292SN/A .desc("CPI: Total CPI of All Threads") 5292292SN/A .precision(6); 5304392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 5312292SN/A 5322292SN/A ipc 5332292SN/A .name(name() + ".ipc") 5342292SN/A .desc("IPC: Instructions Per Cycle") 5352292SN/A .precision(6); 5364392Sktlim@umich.edu ipc = committedInsts / numCycles; 5372292SN/A 5382292SN/A totalIpc 5392292SN/A .name(name() + ".ipc_total") 5402292SN/A .desc("IPC: Total IPC of All Threads") 5412292SN/A .precision(6); 5424392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 5432292SN/A 5445595Sgblack@eecs.umich.edu this->fetch.regStats(); 5455595Sgblack@eecs.umich.edu this->decode.regStats(); 5465595Sgblack@eecs.umich.edu this->rename.regStats(); 5475595Sgblack@eecs.umich.edu this->iew.regStats(); 5485595Sgblack@eecs.umich.edu this->commit.regStats(); 5497897Shestness@cs.utexas.edu this->rob.regStats(); 5507897Shestness@cs.utexas.edu 5517897Shestness@cs.utexas.edu intRegfileReads 5527897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 5537897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 5547897Shestness@cs.utexas.edu .prereq(intRegfileReads); 5557897Shestness@cs.utexas.edu 5567897Shestness@cs.utexas.edu intRegfileWrites 5577897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 5587897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 5597897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 5607897Shestness@cs.utexas.edu 5617897Shestness@cs.utexas.edu fpRegfileReads 5627897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 5637897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5647897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5657897Shestness@cs.utexas.edu 5667897Shestness@cs.utexas.edu fpRegfileWrites 5677897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5687897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5697897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5707897Shestness@cs.utexas.edu 5717897Shestness@cs.utexas.edu miscRegfileReads 5727897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5737897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5747897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5757897Shestness@cs.utexas.edu 5767897Shestness@cs.utexas.edu miscRegfileWrites 5777897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5787897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5797897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5801062SN/A} 5811062SN/A 5821062SN/Atemplate <class Impl> 5831062SN/Avoid 5841755SN/AFullO3CPU<Impl>::tick() 5851060SN/A{ 5862733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5871060SN/A 5882292SN/A ++numCycles; 5892292SN/A 5902325SN/A// activity = false; 5912292SN/A 5922292SN/A //Tick each of the stages 5931060SN/A fetch.tick(); 5941060SN/A 5951060SN/A decode.tick(); 5961060SN/A 5971060SN/A rename.tick(); 5981060SN/A 5991060SN/A iew.tick(); 6001060SN/A 6011060SN/A commit.tick(); 6021060SN/A 6038793Sgblack@eecs.umich.edu if (!FullSystem) 6048793Sgblack@eecs.umich.edu doContextSwitch(); 6052292SN/A 6062292SN/A // Now advance the time buffers 6071060SN/A timeBuffer.advance(); 6081060SN/A 6091060SN/A fetchQueue.advance(); 6101060SN/A decodeQueue.advance(); 6111060SN/A renameQueue.advance(); 6121060SN/A iewQueue.advance(); 6131060SN/A 6142325SN/A activityRec.advance(); 6152292SN/A 6162292SN/A if (removeInstsThisCycle) { 6172292SN/A cleanUpRemovedInsts(); 6182292SN/A } 6192292SN/A 6202325SN/A if (!tickEvent.scheduled()) { 6212867Sktlim@umich.edu if (_status == SwitchedOut || 6222905Sktlim@umich.edu getState() == SimObject::Drained) { 6233226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 6242325SN/A // increment stat 6259179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6263221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 6273226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 6289179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6292325SN/A timesIdled++; 6302325SN/A } else { 6319180Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(Cycles(1))); 6323226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 6332325SN/A } 6342292SN/A } 6352292SN/A 6368793Sgblack@eecs.umich.edu if (!FullSystem) 6378793Sgblack@eecs.umich.edu updateThreadPriority(); 6381060SN/A} 6391060SN/A 6401060SN/Atemplate <class Impl> 6411060SN/Avoid 6421755SN/AFullO3CPU<Impl>::init() 6431060SN/A{ 6445714Shsul@eecs.umich.edu BaseCPU::init(); 6451060SN/A 6468921Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 6478921Sandreas.hansson@arm.com // Set inSyscall so that the CPU doesn't squash when initially 6488921Sandreas.hansson@arm.com // setting up registers. 6496221Snate@binkert.org thread[tid]->inSyscall = true; 6508921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 6518921Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 6528921Sandreas.hansson@arm.com } 6532292SN/A 6548707Sandreas.hansson@arm.com // this CPU could still be unconnected if we are restoring from a 6558707Sandreas.hansson@arm.com // checkpoint and this CPU is to be switched in, thus we can only 6568707Sandreas.hansson@arm.com // do this here if the instruction port is actually connected, if 6578707Sandreas.hansson@arm.com // not we have to do it as part of takeOverFrom 6588707Sandreas.hansson@arm.com if (icachePort.isConnected()) 6598707Sandreas.hansson@arm.com fetch.setIcache(); 6608707Sandreas.hansson@arm.com 6618863Snilay@cs.wisc.edu if (FullSystem && !params()->defer_registration) { 6628793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6638793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6648793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6658793Sgblack@eecs.umich.edu } 6666034Ssteve.reinhardt@amd.com } 6672292SN/A 6682292SN/A // Clear inSyscall. 6696221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6706221Snate@binkert.org thread[tid]->inSyscall = false; 6712292SN/A 6722316SN/A // Initialize stages. 6732292SN/A fetch.initStage(); 6742292SN/A iew.initStage(); 6752292SN/A rename.initStage(); 6762292SN/A commit.initStage(); 6772292SN/A 6782292SN/A commit.setThreads(thread); 6792292SN/A} 6802292SN/A 6812292SN/Atemplate <class Impl> 6822292SN/Avoid 6836221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6842875Sksewell@umich.edu{ 6856221Snate@binkert.org list<ThreadID>::iterator isActive = 6865314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6872875Sksewell@umich.edu 6883226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6893226Sktlim@umich.edu 6902875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6912875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6922875Sksewell@umich.edu tid); 6932875Sksewell@umich.edu 6942875Sksewell@umich.edu activeThreads.push_back(tid); 6952875Sksewell@umich.edu } 6962875Sksewell@umich.edu} 6972875Sksewell@umich.edu 6982875Sksewell@umich.edutemplate <class Impl> 6992875Sksewell@umich.eduvoid 7006221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 7012875Sksewell@umich.edu{ 7022875Sksewell@umich.edu //Remove From Active List, if Active 7036221Snate@binkert.org list<ThreadID>::iterator thread_it = 7045314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 7052875Sksewell@umich.edu 7063226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 7073226Sktlim@umich.edu 7082875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 7092875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 7102875Sksewell@umich.edu tid); 7112875Sksewell@umich.edu activeThreads.erase(thread_it); 7122875Sksewell@umich.edu } 7132875Sksewell@umich.edu} 7142875Sksewell@umich.edu 7152875Sksewell@umich.edutemplate <class Impl> 7166221Snate@binkert.orgCounter 7178834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 7186221Snate@binkert.org{ 7196221Snate@binkert.org Counter total(0); 7206221Snate@binkert.org 7216221Snate@binkert.org ThreadID size = thread.size(); 7226221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 7236221Snate@binkert.org total += thread[i]->numInst; 7246221Snate@binkert.org 7256221Snate@binkert.org return total; 7266221Snate@binkert.org} 7276221Snate@binkert.org 7286221Snate@binkert.orgtemplate <class Impl> 7298834Satgutier@umich.eduCounter 7308834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 7318834Satgutier@umich.edu{ 7328834Satgutier@umich.edu Counter total(0); 7338834Satgutier@umich.edu 7348834Satgutier@umich.edu ThreadID size = thread.size(); 7358834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 7368834Satgutier@umich.edu total += thread[i]->numOp; 7378834Satgutier@umich.edu 7388834Satgutier@umich.edu return total; 7398834Satgutier@umich.edu} 7408834Satgutier@umich.edu 7418834Satgutier@umich.edutemplate <class Impl> 7422875Sksewell@umich.eduvoid 7439180Sandreas.hansson@arm.comFullO3CPU<Impl>::activateContext(ThreadID tid, Cycles delay) 7442875Sksewell@umich.edu{ 7452875Sksewell@umich.edu // Needs to set each stage to running as well. 7462875Sksewell@umich.edu if (delay){ 7472875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 7489180Sandreas.hansson@arm.com "on cycle %d\n", tid, clockEdge(delay)); 7492875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 7502875Sksewell@umich.edu } else { 7512875Sksewell@umich.edu activateThread(tid); 7522875Sksewell@umich.edu } 7532875Sksewell@umich.edu 7549158Sandreas.hansson@arm.com // If we are time 0 or if the last activation time is in the past, 7559158Sandreas.hansson@arm.com // schedule the next tick and wake up the fetch unit 7569158Sandreas.hansson@arm.com if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 7572875Sksewell@umich.edu scheduleTickEvent(delay); 7582875Sksewell@umich.edu 7592875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7602875Sksewell@umich.edu // deschedule itself. 7612875Sksewell@umich.edu activityRec.activity(); 7622875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7632875Sksewell@umich.edu 7649180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 7659180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 7669179Sandreas.hansson@arm.com if (cycles != 0) 7679179Sandreas.hansson@arm.com --cycles; 7689179Sandreas.hansson@arm.com quiesceCycles += cycles; 7698627SAli.Saidi@ARM.com 7707823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7712875Sksewell@umich.edu 7722875Sksewell@umich.edu _status = Running; 7732875Sksewell@umich.edu } 7742875Sksewell@umich.edu} 7752875Sksewell@umich.edu 7762875Sksewell@umich.edutemplate <class Impl> 7773221Sktlim@umich.edubool 7788737Skoansin.tan@gmail.comFullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove, 7799180Sandreas.hansson@arm.com Cycles delay) 7802875Sksewell@umich.edu{ 7812875Sksewell@umich.edu // Schedule removal of thread data from CPU 7822875Sksewell@umich.edu if (delay){ 7832875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 7849180Sandreas.hansson@arm.com "on tick %d\n", tid, clockEdge(delay)); 7853221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 7863221Sktlim@umich.edu return false; 7872875Sksewell@umich.edu } else { 7882875Sksewell@umich.edu deactivateThread(tid); 7893221Sktlim@umich.edu if (remove) 7903221Sktlim@umich.edu removeThread(tid); 7913221Sktlim@umich.edu return true; 7922875Sksewell@umich.edu } 7932875Sksewell@umich.edu} 7942875Sksewell@umich.edu 7952875Sksewell@umich.edutemplate <class Impl> 7962875Sksewell@umich.eduvoid 7976221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 7982875Sksewell@umich.edu{ 7992875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 8009180Sandreas.hansson@arm.com bool deallocated = scheduleDeallocateContext(tid, false, Cycles(1)); 8013221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 8025570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 8033859Sbinkertn@umich.edu activeThreads.size() == 0) 8042910Sksewell@umich.edu unscheduleTickEvent(); 8058627SAli.Saidi@ARM.com 8068627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 8079179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 8082875Sksewell@umich.edu _status = Idle; 8092875Sksewell@umich.edu} 8102875Sksewell@umich.edu 8112875Sksewell@umich.edutemplate <class Impl> 8122875Sksewell@umich.eduvoid 8136221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 8142875Sksewell@umich.edu{ 8152910Sksewell@umich.edu //For now, this is the same as deallocate 8162910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 8179180Sandreas.hansson@arm.com scheduleDeallocateContext(tid, true, Cycles(1)); 8182875Sksewell@umich.edu} 8192875Sksewell@umich.edu 8202875Sksewell@umich.edutemplate <class Impl> 8212875Sksewell@umich.eduvoid 8226221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 8232292SN/A{ 8242847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 8252292SN/A // Will change now that the PC and thread state is internal to the CPU 8262683Sktlim@umich.edu // and not in the ThreadContext. 8278793Sgblack@eecs.umich.edu ThreadContext *src_tc; 8288793Sgblack@eecs.umich.edu if (FullSystem) 8298793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 8308793Sgblack@eecs.umich.edu else 8318793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 8322292SN/A 8332292SN/A //Bind Int Regs to Rename Map 8342292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8352292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 8362292SN/A 8372292SN/A renameMap[tid].setEntry(ireg,phys_reg); 8382292SN/A scoreboard.setReg(phys_reg); 8392292SN/A } 8402292SN/A 8412292SN/A //Bind Float Regs to Rename Map 8422292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 8432292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 8442292SN/A 8452292SN/A renameMap[tid].setEntry(freg,phys_reg); 8462292SN/A scoreboard.setReg(phys_reg); 8472292SN/A } 8482292SN/A 8492292SN/A //Copy Thread Data Into RegFile 8502847Sksewell@umich.edu //this->copyFromTC(tid); 8512292SN/A 8522847Sksewell@umich.edu //Set PC/NPC/NNPC 8537720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8542292SN/A 8552680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8562292SN/A 8579180Sandreas.hansson@arm.com activateContext(tid, Cycles(1)); 8582292SN/A 8592292SN/A //Reset ROB/IQ/LSQ Entries 8602292SN/A commit.rob->resetEntries(); 8612292SN/A iew.resetEntries(); 8622292SN/A} 8632292SN/A 8642292SN/Atemplate <class Impl> 8652292SN/Avoid 8666221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8672292SN/A{ 8682877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 8692847Sksewell@umich.edu 8702847Sksewell@umich.edu // Copy Thread Data From RegFile 8712847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 8725364Sksewell@umich.edu // this->copyToTC(tid); 8735364Sksewell@umich.edu 8745364Sksewell@umich.edu 8755364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 8765364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 8775364Sksewell@umich.edu // in SMT workloads. 8782847Sksewell@umich.edu 8792847Sksewell@umich.edu // Unbind Int Regs from Rename Map 8802292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8812292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 8822292SN/A 8832292SN/A scoreboard.unsetReg(phys_reg); 8842292SN/A freeList.addReg(phys_reg); 8852292SN/A } 8862292SN/A 8872847Sksewell@umich.edu // Unbind Float Regs from Rename Map 8885362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 8892292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 8902292SN/A 8912292SN/A scoreboard.unsetReg(phys_reg); 8922292SN/A freeList.addReg(phys_reg); 8932292SN/A } 8942292SN/A 8952847Sksewell@umich.edu // Squash Throughout Pipeline 8968138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 8978138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 8988138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 8992292SN/A decode.squash(tid); 9002935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 9012875Sksewell@umich.edu iew.squash(tid); 9025363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 9032935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 9042292SN/A 9055362Sksewell@umich.edu 9065362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 9072292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 9082292SN/A 9092847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 9103229Sktlim@umich.edu 9113229Sktlim@umich.edu // Commented out for now. This should be possible to do by 9123229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 9133229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 9143229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 9153229Sktlim@umich.edu/* 9162292SN/A if (activeThreads.size() >= 1) { 9172292SN/A commit.rob->resetEntries(); 9182292SN/A iew.resetEntries(); 9192292SN/A } 9203229Sktlim@umich.edu*/ 9212292SN/A} 9222292SN/A 9232292SN/A 9242292SN/Atemplate <class Impl> 9252292SN/Avoid 9266221Snate@binkert.orgFullO3CPU<Impl>::activateWhenReady(ThreadID tid) 9272292SN/A{ 9282733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 9292292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 9302292SN/A tid); 9312292SN/A 9322292SN/A bool ready = true; 9332292SN/A 9342292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 9352733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9362292SN/A "Phys. Int. Regs.\n", 9372292SN/A tid); 9382292SN/A ready = false; 9392292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 9402733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9412292SN/A "Phys. Float. Regs.\n", 9422292SN/A tid); 9432292SN/A ready = false; 9442292SN/A } else if (commit.rob->numFreeEntries() >= 9452292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 9462733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9472292SN/A "ROB entries.\n", 9482292SN/A tid); 9492292SN/A ready = false; 9502292SN/A } else if (iew.instQueue.numFreeEntries() >= 9512292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 9522733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9532292SN/A "IQ entries.\n", 9542292SN/A tid); 9552292SN/A ready = false; 9562292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 9572292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 9582733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9592292SN/A "LSQ entries.\n", 9602292SN/A tid); 9612292SN/A ready = false; 9622292SN/A } 9632292SN/A 9642292SN/A if (ready) { 9652292SN/A insertThread(tid); 9662292SN/A 9672292SN/A contextSwitch = false; 9682292SN/A 9692292SN/A cpuWaitList.remove(tid); 9702292SN/A } else { 9712292SN/A suspendContext(tid); 9722292SN/A 9732292SN/A //blocks fetch 9742292SN/A contextSwitch = true; 9752292SN/A 9762875Sksewell@umich.edu //@todo: dont always add to waitlist 9772292SN/A //do waitlist 9782292SN/A cpuWaitList.push_back(tid); 9791060SN/A } 9801060SN/A} 9811060SN/A 9824192Sktlim@umich.edutemplate <class Impl> 9835595Sgblack@eecs.umich.eduFault 9846221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 9855702Ssaidi@eecs.umich.edu{ 9865702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9875702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 9885702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 9895702Ssaidi@eecs.umich.edu 9905702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 9915702Ssaidi@eecs.umich.edu 9925702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9935702Ssaidi@eecs.umich.edu#endif 9945702Ssaidi@eecs.umich.edu return NoFault; 9955702Ssaidi@eecs.umich.edu} 9965702Ssaidi@eecs.umich.edu 9975702Ssaidi@eecs.umich.edutemplate <class Impl> 9985702Ssaidi@eecs.umich.edubool 9996221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 10005702Ssaidi@eecs.umich.edu{ 10015702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 10025702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 10035702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 10045702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 10055702Ssaidi@eecs.umich.edu 10065702Ssaidi@eecs.umich.edu switch (palFunc) { 10075702Ssaidi@eecs.umich.edu case PAL::halt: 10085702Ssaidi@eecs.umich.edu halt(); 10095702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 10105702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 10115702Ssaidi@eecs.umich.edu break; 10125702Ssaidi@eecs.umich.edu 10135702Ssaidi@eecs.umich.edu case PAL::bpt: 10145702Ssaidi@eecs.umich.edu case PAL::bugchk: 10155702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 10165702Ssaidi@eecs.umich.edu return false; 10175702Ssaidi@eecs.umich.edu break; 10185702Ssaidi@eecs.umich.edu } 10195702Ssaidi@eecs.umich.edu#endif 10205702Ssaidi@eecs.umich.edu return true; 10215702Ssaidi@eecs.umich.edu} 10225702Ssaidi@eecs.umich.edu 10235702Ssaidi@eecs.umich.edutemplate <class Impl> 10245702Ssaidi@eecs.umich.eduFault 10255595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 10265595Sgblack@eecs.umich.edu{ 10275595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 10285647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 10295595Sgblack@eecs.umich.edu} 10305595Sgblack@eecs.umich.edu 10315595Sgblack@eecs.umich.edutemplate <class Impl> 10325595Sgblack@eecs.umich.eduvoid 10335595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 10345595Sgblack@eecs.umich.edu{ 10355595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 10365595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 10375595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 10385595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 10395595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 10405595Sgblack@eecs.umich.edu 10415595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 10425647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 10435595Sgblack@eecs.umich.edu 10445595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 10457684Sgblack@eecs.umich.edu this->trap(interrupt, 0, NULL); 10465595Sgblack@eecs.umich.edu} 10475595Sgblack@eecs.umich.edu 10481060SN/Atemplate <class Impl> 10492852Sktlim@umich.eduvoid 10507684Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) 10515595Sgblack@eecs.umich.edu{ 10525595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 10537684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 10545595Sgblack@eecs.umich.edu} 10555595Sgblack@eecs.umich.edu 10565595Sgblack@eecs.umich.edutemplate <class Impl> 10575595Sgblack@eecs.umich.eduvoid 10586221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 10595595Sgblack@eecs.umich.edu{ 10605595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 10615595Sgblack@eecs.umich.edu 10625595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 10635595Sgblack@eecs.umich.edu 10645595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 10655595Sgblack@eecs.umich.edu // instruction. 10665595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 10675595Sgblack@eecs.umich.edu 10685595Sgblack@eecs.umich.edu // Execute the actual syscall. 10695595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 10705595Sgblack@eecs.umich.edu 10715595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 10725595Sgblack@eecs.umich.edu // incrementing it. 10735595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 10745595Sgblack@eecs.umich.edu} 10755595Sgblack@eecs.umich.edu 10765595Sgblack@eecs.umich.edutemplate <class Impl> 10775595Sgblack@eecs.umich.eduvoid 10782864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 10792864Sktlim@umich.edu{ 10802918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 10812918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 10822864Sktlim@umich.edu BaseCPU::serialize(os); 10832864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 10842864Sktlim@umich.edu tickEvent.serialize(os); 10852864Sktlim@umich.edu 10862864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10872864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 10882864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10892864Sktlim@umich.edu static SimpleThread temp; 10902864Sktlim@umich.edu 10916221Snate@binkert.org ThreadID size = thread.size(); 10926221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 10932864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 10942864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10952864Sktlim@umich.edu temp.serialize(os); 10962864Sktlim@umich.edu } 10972864Sktlim@umich.edu} 10982864Sktlim@umich.edu 10992864Sktlim@umich.edutemplate <class Impl> 11002864Sktlim@umich.eduvoid 11012864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 11022864Sktlim@umich.edu{ 11032918Sktlim@umich.edu SimObject::State so_state; 11042918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 11052864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 11062864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 11072864Sktlim@umich.edu 11082864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 11092864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 11102864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 11112864Sktlim@umich.edu static SimpleThread temp; 11122864Sktlim@umich.edu 11136221Snate@binkert.org ThreadID size = thread.size(); 11146221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 11152864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 11162864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 11172864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 11182864Sktlim@umich.edu } 11192864Sktlim@umich.edu} 11202864Sktlim@umich.edu 11212864Sktlim@umich.edutemplate <class Impl> 11222905Sktlim@umich.eduunsigned int 11232843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 11241060SN/A{ 11253125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 11263512Sktlim@umich.edu 11273512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 11289152Satgutier@umich.edu if (_status == SwitchedOut) 11293512Sktlim@umich.edu return 0; 11303512Sktlim@umich.edu 11312843Sktlim@umich.edu drainCount = 0; 11322843Sktlim@umich.edu fetch.drain(); 11332843Sktlim@umich.edu decode.drain(); 11342843Sktlim@umich.edu rename.drain(); 11352843Sktlim@umich.edu iew.drain(); 11362843Sktlim@umich.edu commit.drain(); 11372325SN/A 11382325SN/A // Wake the CPU and record activity so everything can drain out if 11392863Sktlim@umich.edu // the CPU was not able to immediately drain. 11402905Sktlim@umich.edu if (getState() != SimObject::Drained) { 11412864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 11422864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 11432864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 11442864Sktlim@umich.edu // process on the drain event. 11452864Sktlim@umich.edu drainEvent = drain_event; 11462843Sktlim@umich.edu 11472863Sktlim@umich.edu wakeCPU(); 11482863Sktlim@umich.edu activityRec.activity(); 11492852Sktlim@umich.edu 11509152Satgutier@umich.edu DPRINTF(Drain, "CPU not drained\n"); 11519152Satgutier@umich.edu 11522905Sktlim@umich.edu return 1; 11532863Sktlim@umich.edu } else { 11542905Sktlim@umich.edu return 0; 11552863Sktlim@umich.edu } 11562316SN/A} 11572310SN/A 11582316SN/Atemplate <class Impl> 11592316SN/Avoid 11602843Sktlim@umich.eduFullO3CPU<Impl>::resume() 11612316SN/A{ 11622843Sktlim@umich.edu fetch.resume(); 11632843Sktlim@umich.edu decode.resume(); 11642843Sktlim@umich.edu rename.resume(); 11652843Sktlim@umich.edu iew.resume(); 11662843Sktlim@umich.edu commit.resume(); 11672316SN/A 11682905Sktlim@umich.edu changeState(SimObject::Running); 11692905Sktlim@umich.edu 11709152Satgutier@umich.edu if (_status == SwitchedOut) 11712864Sktlim@umich.edu return; 11722864Sktlim@umich.edu 11734762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 11743319Shsul@eecs.umich.edu 11752843Sktlim@umich.edu if (!tickEvent.scheduled()) 11765606Snate@binkert.org schedule(tickEvent, nextCycle()); 11772843Sktlim@umich.edu _status = Running; 11782843Sktlim@umich.edu} 11792316SN/A 11802843Sktlim@umich.edutemplate <class Impl> 11812843Sktlim@umich.eduvoid 11822843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 11832843Sktlim@umich.edu{ 11842843Sktlim@umich.edu if (++drainCount == NumStages) { 11852316SN/A if (tickEvent.scheduled()) 11862316SN/A tickEvent.squash(); 11872863Sktlim@umich.edu 11882905Sktlim@umich.edu changeState(SimObject::Drained); 11892863Sktlim@umich.edu 11903126Sktlim@umich.edu BaseCPU::switchOut(); 11913126Sktlim@umich.edu 11922863Sktlim@umich.edu if (drainEvent) { 11939152Satgutier@umich.edu DPRINTF(Drain, "CPU done draining, processing drain event\n"); 11942863Sktlim@umich.edu drainEvent->process(); 11952863Sktlim@umich.edu drainEvent = NULL; 11962863Sktlim@umich.edu } 11972310SN/A } 11982843Sktlim@umich.edu assert(drainCount <= 5); 11992843Sktlim@umich.edu} 12002843Sktlim@umich.edu 12012843Sktlim@umich.edutemplate <class Impl> 12022843Sktlim@umich.eduvoid 12032843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 12042843Sktlim@umich.edu{ 12052843Sktlim@umich.edu fetch.switchOut(); 12062843Sktlim@umich.edu rename.switchOut(); 12072325SN/A iew.switchOut(); 12082843Sktlim@umich.edu commit.switchOut(); 12092843Sktlim@umich.edu instList.clear(); 12102843Sktlim@umich.edu while (!removeList.empty()) { 12112843Sktlim@umich.edu removeList.pop(); 12122843Sktlim@umich.edu } 12132843Sktlim@umich.edu 12142843Sktlim@umich.edu _status = SwitchedOut; 12158887Sgeoffrey.blake@arm.com 12162843Sktlim@umich.edu if (checker) 12172843Sktlim@umich.edu checker->switchOut(); 12188887Sgeoffrey.blake@arm.com 12193126Sktlim@umich.edu if (tickEvent.scheduled()) 12203126Sktlim@umich.edu tickEvent.squash(); 12211060SN/A} 12221060SN/A 12231060SN/Atemplate <class Impl> 12241060SN/Avoid 12251755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 12261060SN/A{ 12272325SN/A // Flush out any old data from the time buffers. 12282873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 12292307SN/A timeBuffer.advance(); 12302307SN/A fetchQueue.advance(); 12312307SN/A decodeQueue.advance(); 12322307SN/A renameQueue.advance(); 12332307SN/A iewQueue.advance(); 12342307SN/A } 12352307SN/A 12362325SN/A activityRec.reset(); 12372307SN/A 12388737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 12391060SN/A 12402307SN/A fetch.takeOverFrom(); 12412307SN/A decode.takeOverFrom(); 12422307SN/A rename.takeOverFrom(); 12432307SN/A iew.takeOverFrom(); 12442307SN/A commit.takeOverFrom(); 12452307SN/A 12467507Stjones1@inf.ed.ac.uk assert(!tickEvent.scheduled() || tickEvent.squashed()); 12471060SN/A 12489152Satgutier@umich.edu FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 12499152Satgutier@umich.edu if (oldO3CPU) 12509152Satgutier@umich.edu globalSeqNum = oldO3CPU->globalSeqNum; 12519152Satgutier@umich.edu 12522325SN/A // @todo: Figure out how to properly select the tid to put onto 12532325SN/A // the active threads list. 12546221Snate@binkert.org ThreadID tid = 0; 12552307SN/A 12566221Snate@binkert.org list<ThreadID>::iterator isActive = 12575314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 12582307SN/A 12592307SN/A if (isActive == activeThreads.end()) { 12602325SN/A //May Need to Re-code this if the delay variable is the delay 12612325SN/A //needed for thread to activate 12622733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 12632307SN/A tid); 12642307SN/A 12652307SN/A activeThreads.push_back(tid); 12662307SN/A } 12672307SN/A 12682325SN/A // Set all statuses to active, schedule the CPU's tick event. 12692307SN/A // @todo: Fix up statuses so this is handled properly 12706221Snate@binkert.org ThreadID size = threadContexts.size(); 12716221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 12722680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 12732680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 12741681SN/A _status = Running; 12757507Stjones1@inf.ed.ac.uk reschedule(tickEvent, nextCycle(), true); 12761681SN/A } 12771060SN/A } 12782307SN/A if (!tickEvent.scheduled()) 12795606Snate@binkert.org schedule(tickEvent, nextCycle()); 12808627SAli.Saidi@ARM.com 12819179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 12821060SN/A} 12831060SN/A 12841060SN/Atemplate <class Impl> 12855595Sgblack@eecs.umich.eduTheISA::MiscReg 12866221Snate@binkert.orgFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 12875595Sgblack@eecs.umich.edu{ 12886313Sgblack@eecs.umich.edu return this->isa[tid].readMiscRegNoEffect(misc_reg); 12895595Sgblack@eecs.umich.edu} 12905595Sgblack@eecs.umich.edu 12915595Sgblack@eecs.umich.edutemplate <class Impl> 12925595Sgblack@eecs.umich.eduTheISA::MiscReg 12936221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 12945595Sgblack@eecs.umich.edu{ 12957897Shestness@cs.utexas.edu miscRegfileReads++; 12966313Sgblack@eecs.umich.edu return this->isa[tid].readMiscReg(misc_reg, tcBase(tid)); 12975595Sgblack@eecs.umich.edu} 12985595Sgblack@eecs.umich.edu 12995595Sgblack@eecs.umich.edutemplate <class Impl> 13005595Sgblack@eecs.umich.eduvoid 13015595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 13026221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 13035595Sgblack@eecs.umich.edu{ 13046313Sgblack@eecs.umich.edu this->isa[tid].setMiscRegNoEffect(misc_reg, val); 13055595Sgblack@eecs.umich.edu} 13065595Sgblack@eecs.umich.edu 13075595Sgblack@eecs.umich.edutemplate <class Impl> 13085595Sgblack@eecs.umich.eduvoid 13095595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 13106221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 13115595Sgblack@eecs.umich.edu{ 13127897Shestness@cs.utexas.edu miscRegfileWrites++; 13136313Sgblack@eecs.umich.edu this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); 13145595Sgblack@eecs.umich.edu} 13155595Sgblack@eecs.umich.edu 13165595Sgblack@eecs.umich.edutemplate <class Impl> 13171060SN/Auint64_t 13181755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 13191060SN/A{ 13207897Shestness@cs.utexas.edu intRegfileReads++; 13211060SN/A return regFile.readIntReg(reg_idx); 13221060SN/A} 13231060SN/A 13241060SN/Atemplate <class Impl> 13252455SN/AFloatReg 13262455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 13271060SN/A{ 13287897Shestness@cs.utexas.edu fpRegfileReads++; 13292455SN/A return regFile.readFloatReg(reg_idx); 13301060SN/A} 13311060SN/A 13321060SN/Atemplate <class Impl> 13332455SN/AFloatRegBits 13342455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 13352455SN/A{ 13367897Shestness@cs.utexas.edu fpRegfileReads++; 13372455SN/A return regFile.readFloatRegBits(reg_idx); 13381060SN/A} 13391060SN/A 13401060SN/Atemplate <class Impl> 13411060SN/Avoid 13421755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 13431060SN/A{ 13447897Shestness@cs.utexas.edu intRegfileWrites++; 13451060SN/A regFile.setIntReg(reg_idx, val); 13461060SN/A} 13471060SN/A 13481060SN/Atemplate <class Impl> 13491060SN/Avoid 13502455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 13511060SN/A{ 13527897Shestness@cs.utexas.edu fpRegfileWrites++; 13532455SN/A regFile.setFloatReg(reg_idx, val); 13541060SN/A} 13551060SN/A 13561060SN/Atemplate <class Impl> 13571060SN/Avoid 13582455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 13592455SN/A{ 13607897Shestness@cs.utexas.edu fpRegfileWrites++; 13612455SN/A regFile.setFloatRegBits(reg_idx, val); 13621060SN/A} 13631060SN/A 13641060SN/Atemplate <class Impl> 13651060SN/Auint64_t 13666221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 13671060SN/A{ 13687897Shestness@cs.utexas.edu intRegfileReads++; 13692292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13702292SN/A 13712292SN/A return regFile.readIntReg(phys_reg); 13722292SN/A} 13732292SN/A 13742292SN/Atemplate <class Impl> 13752292SN/Afloat 13766314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 13772292SN/A{ 13787897Shestness@cs.utexas.edu fpRegfileReads++; 13796032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13802307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13812292SN/A 13822669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 13832292SN/A} 13842292SN/A 13852292SN/Atemplate <class Impl> 13862292SN/Auint64_t 13876221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 13882292SN/A{ 13897897Shestness@cs.utexas.edu fpRegfileReads++; 13906032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13912307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13922292SN/A 13932669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13941060SN/A} 13951060SN/A 13961060SN/Atemplate <class Impl> 13971060SN/Avoid 13986221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 13991060SN/A{ 14007897Shestness@cs.utexas.edu intRegfileWrites++; 14012292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 14022292SN/A 14032292SN/A regFile.setIntReg(phys_reg, val); 14041060SN/A} 14051060SN/A 14061060SN/Atemplate <class Impl> 14071060SN/Avoid 14086314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 14091060SN/A{ 14107897Shestness@cs.utexas.edu fpRegfileWrites++; 14116032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 14122918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 14132292SN/A 14142669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 14151060SN/A} 14161060SN/A 14171060SN/Atemplate <class Impl> 14181060SN/Avoid 14196221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 14201060SN/A{ 14217897Shestness@cs.utexas.edu fpRegfileWrites++; 14226032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 14232918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 14241060SN/A 14252669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 14262292SN/A} 14272292SN/A 14282292SN/Atemplate <class Impl> 14297720Sgblack@eecs.umich.eduTheISA::PCState 14307720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 14312292SN/A{ 14327720Sgblack@eecs.umich.edu return commit.pcState(tid); 14331060SN/A} 14341060SN/A 14351060SN/Atemplate <class Impl> 14361060SN/Avoid 14377720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 14381060SN/A{ 14397720Sgblack@eecs.umich.edu commit.pcState(val, tid); 14402292SN/A} 14411060SN/A 14422292SN/Atemplate <class Impl> 14437720Sgblack@eecs.umich.eduAddr 14447720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 14454636Sgblack@eecs.umich.edu{ 14467720Sgblack@eecs.umich.edu return commit.instAddr(tid); 14474636Sgblack@eecs.umich.edu} 14484636Sgblack@eecs.umich.edu 14494636Sgblack@eecs.umich.edutemplate <class Impl> 14507720Sgblack@eecs.umich.eduAddr 14517720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 14524636Sgblack@eecs.umich.edu{ 14537720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 14544636Sgblack@eecs.umich.edu} 14554636Sgblack@eecs.umich.edu 14564636Sgblack@eecs.umich.edutemplate <class Impl> 14577720Sgblack@eecs.umich.eduMicroPC 14587720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 14592292SN/A{ 14607720Sgblack@eecs.umich.edu return commit.microPC(tid); 14614636Sgblack@eecs.umich.edu} 14624636Sgblack@eecs.umich.edu 14634636Sgblack@eecs.umich.edutemplate <class Impl> 14645595Sgblack@eecs.umich.eduvoid 14656221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 14665595Sgblack@eecs.umich.edu{ 14675595Sgblack@eecs.umich.edu this->thread[tid]->inSyscall = true; 14685595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 14695595Sgblack@eecs.umich.edu} 14705595Sgblack@eecs.umich.edu 14715595Sgblack@eecs.umich.edutemplate <class Impl> 14722292SN/Atypename FullO3CPU<Impl>::ListIt 14732292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14742292SN/A{ 14752292SN/A instList.push_back(inst); 14761060SN/A 14772292SN/A return --(instList.end()); 14782292SN/A} 14791060SN/A 14802292SN/Atemplate <class Impl> 14812292SN/Avoid 14828834Satgutier@umich.eduFullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 14832292SN/A{ 14842292SN/A // Keep an instruction count. 14858834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 14868834Satgutier@umich.edu thread[tid]->numInst++; 14878834Satgutier@umich.edu thread[tid]->numInsts++; 14888834Satgutier@umich.edu committedInsts[tid]++; 14898834Satgutier@umich.edu totalCommittedInsts++; 14908834Satgutier@umich.edu } 14918834Satgutier@umich.edu thread[tid]->numOp++; 14928834Satgutier@umich.edu thread[tid]->numOps++; 14938834Satgutier@umich.edu committedOps[tid]++; 14948834Satgutier@umich.edu 14957897Shestness@cs.utexas.edu system->totalNumInsts++; 14962292SN/A // Check for instruction-count-based events. 14972292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 14987897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 14992292SN/A} 15002292SN/A 15012292SN/Atemplate <class Impl> 15022292SN/Avoid 15031755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 15041060SN/A{ 15057720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 15062292SN/A "[sn:%lli]\n", 15077720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 15081060SN/A 15092292SN/A removeInstsThisCycle = true; 15101060SN/A 15111060SN/A // Remove the front instruction. 15122292SN/A removeList.push(inst->getInstListIt()); 15131060SN/A} 15141060SN/A 15151060SN/Atemplate <class Impl> 15161060SN/Avoid 15176221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 15181060SN/A{ 15192733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 15202292SN/A " list.\n", tid); 15211060SN/A 15222292SN/A ListIt end_it; 15231060SN/A 15242292SN/A bool rob_empty = false; 15252292SN/A 15262292SN/A if (instList.empty()) { 15272292SN/A return; 15282292SN/A } else if (rob.isEmpty(/*tid*/)) { 15292733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 15302292SN/A end_it = instList.begin(); 15312292SN/A rob_empty = true; 15322292SN/A } else { 15332292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 15342733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 15352292SN/A } 15362292SN/A 15372292SN/A removeInstsThisCycle = true; 15382292SN/A 15392292SN/A ListIt inst_it = instList.end(); 15402292SN/A 15412292SN/A inst_it--; 15422292SN/A 15432292SN/A // Walk through the instruction list, removing any instructions 15442292SN/A // that were inserted after the given instruction iterator, end_it. 15452292SN/A while (inst_it != end_it) { 15462292SN/A assert(!instList.empty()); 15472292SN/A 15482292SN/A squashInstIt(inst_it, tid); 15492292SN/A 15502292SN/A inst_it--; 15512292SN/A } 15522292SN/A 15532292SN/A // If the ROB was empty, then we actually need to remove the first 15542292SN/A // instruction as well. 15552292SN/A if (rob_empty) { 15562292SN/A squashInstIt(inst_it, tid); 15572292SN/A } 15581060SN/A} 15591060SN/A 15601060SN/Atemplate <class Impl> 15611060SN/Avoid 15626221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 15631062SN/A{ 15642292SN/A assert(!instList.empty()); 15652292SN/A 15662292SN/A removeInstsThisCycle = true; 15672292SN/A 15682292SN/A ListIt inst_iter = instList.end(); 15692292SN/A 15702292SN/A inst_iter--; 15712292SN/A 15722733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 15732292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15742292SN/A tid, seq_num, (*inst_iter)->seqNum); 15751062SN/A 15762292SN/A while ((*inst_iter)->seqNum > seq_num) { 15771062SN/A 15782292SN/A bool break_loop = (inst_iter == instList.begin()); 15791062SN/A 15802292SN/A squashInstIt(inst_iter, tid); 15811062SN/A 15822292SN/A inst_iter--; 15831062SN/A 15842292SN/A if (break_loop) 15852292SN/A break; 15862292SN/A } 15872292SN/A} 15882292SN/A 15892292SN/Atemplate <class Impl> 15902292SN/Ainline void 15916221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 15922292SN/A{ 15932292SN/A if ((*instIt)->threadNumber == tid) { 15942733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 15957720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15962292SN/A (*instIt)->threadNumber, 15972292SN/A (*instIt)->seqNum, 15987720Sgblack@eecs.umich.edu (*instIt)->pcState()); 15991062SN/A 16001062SN/A // Mark it as squashed. 16012292SN/A (*instIt)->setSquashed(); 16022292SN/A 16032325SN/A // @todo: Formulate a consistent method for deleting 16042325SN/A // instructions from the instruction list 16052292SN/A // Remove the instruction from the list. 16062292SN/A removeList.push(instIt); 16072292SN/A } 16082292SN/A} 16092292SN/A 16102292SN/Atemplate <class Impl> 16112292SN/Avoid 16122292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 16132292SN/A{ 16142292SN/A while (!removeList.empty()) { 16152733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 16167720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 16172292SN/A (*removeList.front())->threadNumber, 16182292SN/A (*removeList.front())->seqNum, 16197720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 16202292SN/A 16212292SN/A instList.erase(removeList.front()); 16222292SN/A 16232292SN/A removeList.pop(); 16241062SN/A } 16251062SN/A 16262292SN/A removeInstsThisCycle = false; 16271062SN/A} 16282325SN/A/* 16291062SN/Atemplate <class Impl> 16301062SN/Avoid 16311755SN/AFullO3CPU<Impl>::removeAllInsts() 16321060SN/A{ 16331060SN/A instList.clear(); 16341060SN/A} 16352325SN/A*/ 16361060SN/Atemplate <class Impl> 16371060SN/Avoid 16381755SN/AFullO3CPU<Impl>::dumpInsts() 16391060SN/A{ 16401060SN/A int num = 0; 16411060SN/A 16422292SN/A ListIt inst_list_it = instList.begin(); 16432292SN/A 16442292SN/A cprintf("Dumping Instruction List\n"); 16452292SN/A 16462292SN/A while (inst_list_it != instList.end()) { 16472292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 16482292SN/A "Squashed:%i\n\n", 16497720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 16502292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16512292SN/A (*inst_list_it)->isSquashed()); 16521060SN/A inst_list_it++; 16531060SN/A ++num; 16541060SN/A } 16551060SN/A} 16562325SN/A/* 16571060SN/Atemplate <class Impl> 16581060SN/Avoid 16591755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 16601060SN/A{ 16611060SN/A iew.wakeDependents(inst); 16621060SN/A} 16632325SN/A*/ 16642292SN/Atemplate <class Impl> 16652292SN/Avoid 16662292SN/AFullO3CPU<Impl>::wakeCPU() 16672292SN/A{ 16682325SN/A if (activityRec.active() || tickEvent.scheduled()) { 16692325SN/A DPRINTF(Activity, "CPU already running.\n"); 16702292SN/A return; 16712292SN/A } 16722292SN/A 16732325SN/A DPRINTF(Activity, "Waking up CPU\n"); 16742325SN/A 16759180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 16769180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 16779179Sandreas.hansson@arm.com if (cycles != 0) 16789179Sandreas.hansson@arm.com --cycles; 16799179Sandreas.hansson@arm.com idleCycles += cycles; 16809179Sandreas.hansson@arm.com numCycles += cycles; 16812292SN/A 16825606Snate@binkert.org schedule(tickEvent, nextCycle()); 16832292SN/A} 16842292SN/A 16855807Snate@binkert.orgtemplate <class Impl> 16865807Snate@binkert.orgvoid 16875807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 16885807Snate@binkert.org{ 16895807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 16905807Snate@binkert.org return; 16915807Snate@binkert.org 16925807Snate@binkert.org this->wakeCPU(); 16935807Snate@binkert.org 16945807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 16955807Snate@binkert.org this->threadContexts[0]->activate(); 16965807Snate@binkert.org} 16975807Snate@binkert.org 16982292SN/Atemplate <class Impl> 16996221Snate@binkert.orgThreadID 17002292SN/AFullO3CPU<Impl>::getFreeTid() 17012292SN/A{ 17026221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 17036221Snate@binkert.org if (!tids[tid]) { 17046221Snate@binkert.org tids[tid] = true; 17056221Snate@binkert.org return tid; 17062292SN/A } 17072292SN/A } 17082292SN/A 17096221Snate@binkert.org return InvalidThreadID; 17102292SN/A} 17112292SN/A 17122292SN/Atemplate <class Impl> 17132292SN/Avoid 17142292SN/AFullO3CPU<Impl>::doContextSwitch() 17152292SN/A{ 17162292SN/A if (contextSwitch) { 17172292SN/A 17182292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 17192292SN/A 17206221Snate@binkert.org ThreadID size = cpuWaitList.size(); 17216221Snate@binkert.org for (ThreadID tid = 0; tid < size; tid++) { 17222292SN/A activateWhenReady(tid); 17232292SN/A } 17242292SN/A 17252292SN/A if (cpuWaitList.size() == 0) 17262292SN/A contextSwitch = true; 17272292SN/A } 17282292SN/A} 17292292SN/A 17302292SN/Atemplate <class Impl> 17312292SN/Avoid 17322292SN/AFullO3CPU<Impl>::updateThreadPriority() 17332292SN/A{ 17346221Snate@binkert.org if (activeThreads.size() > 1) { 17352292SN/A //DEFAULT TO ROUND ROBIN SCHEME 17362292SN/A //e.g. Move highest priority to end of thread list 17376221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 17382292SN/A 17392292SN/A unsigned high_thread = *list_begin; 17402292SN/A 17412292SN/A activeThreads.erase(list_begin); 17422292SN/A 17432292SN/A activeThreads.push_back(high_thread); 17442292SN/A } 17452292SN/A} 17461060SN/A 17471755SN/A// Forward declaration of FullO3CPU. 17482818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1749