cpu.cc revision 8975
11689SN/A/* 28948Sandreas.hansson@arm.com * Copyright (c) 2011-2012 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 142325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422756Sksewell@umich.edu * Korey Sewell 437897Shestness@cs.utexas.edu * Rick Strong 441689SN/A */ 451689SN/A 468779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 498887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 508229Snate@binkert.org#include "cpu/o3/cpu.hh" 518229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 528229Snate@binkert.org#include "cpu/o3/thread_context.hh" 534762Snate@binkert.org#include "cpu/activity.hh" 548779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 554762Snate@binkert.org#include "cpu/simple_thread.hh" 564762Snate@binkert.org#include "cpu/thread_context.hh" 578232Snate@binkert.org#include "debug/Activity.hh" 588232Snate@binkert.org#include "debug/O3CPU.hh" 598232Snate@binkert.org#include "debug/Quiesce.hh" 604762Snate@binkert.org#include "enums/MemoryMode.hh" 614762Snate@binkert.org#include "sim/core.hh" 628793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 638779Sgblack@eecs.umich.edu#include "sim/process.hh" 644762Snate@binkert.org#include "sim/stat_control.hh" 658460SAli.Saidi@ARM.com#include "sim/system.hh" 664762Snate@binkert.org 675702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 685702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 698232Snate@binkert.org#include "debug/Activity.hh" 705702Ssaidi@eecs.umich.edu#endif 715702Ssaidi@eecs.umich.edu 728737Skoansin.tan@gmail.comstruct BaseCPUParams; 735529Snate@binkert.org 742669Sktlim@umich.eduusing namespace TheISA; 756221Snate@binkert.orgusing namespace std; 761060SN/A 775529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 785712Shsul@eecs.umich.edu : BaseCPU(params) 791060SN/A{ 801060SN/A} 811060SN/A 822292SN/Avoid 832733Sktlim@umich.eduBaseO3CPU::regStats() 842292SN/A{ 852292SN/A BaseCPU::regStats(); 862292SN/A} 872292SN/A 888707Sandreas.hansson@arm.comtemplate<class Impl> 898707Sandreas.hansson@arm.combool 908975Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 918707Sandreas.hansson@arm.com{ 928707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 938948Sandreas.hansson@arm.com // We shouldn't ever get a block in ownership state 948948Sandreas.hansson@arm.com assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 958948Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 968707Sandreas.hansson@arm.com 978707Sandreas.hansson@arm.com return true; 988707Sandreas.hansson@arm.com} 998707Sandreas.hansson@arm.com 1008707Sandreas.hansson@arm.comtemplate<class Impl> 1018707Sandreas.hansson@arm.comvoid 1028707Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvRetry() 1038707Sandreas.hansson@arm.com{ 1048707Sandreas.hansson@arm.com fetch->recvRetry(); 1058707Sandreas.hansson@arm.com} 1068707Sandreas.hansson@arm.com 1078707Sandreas.hansson@arm.comtemplate <class Impl> 1088707Sandreas.hansson@arm.combool 1098975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 1108707Sandreas.hansson@arm.com{ 1118975Sandreas.hansson@arm.com return lsq->recvTimingResp(pkt); 1128707Sandreas.hansson@arm.com} 1138707Sandreas.hansson@arm.com 1148707Sandreas.hansson@arm.comtemplate <class Impl> 1158975Sandreas.hansson@arm.comvoid 1168975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 1178948Sandreas.hansson@arm.com{ 1188975Sandreas.hansson@arm.com lsq->recvTimingSnoopReq(pkt); 1198948Sandreas.hansson@arm.com} 1208948Sandreas.hansson@arm.com 1218948Sandreas.hansson@arm.comtemplate <class Impl> 1228707Sandreas.hansson@arm.comvoid 1238707Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvRetry() 1248707Sandreas.hansson@arm.com{ 1258707Sandreas.hansson@arm.com lsq->recvRetry(); 1268707Sandreas.hansson@arm.com} 1278707Sandreas.hansson@arm.com 1281060SN/Atemplate <class Impl> 1291755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 1305606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 1311060SN/A{ 1321060SN/A} 1331060SN/A 1341060SN/Atemplate <class Impl> 1351060SN/Avoid 1361755SN/AFullO3CPU<Impl>::TickEvent::process() 1371060SN/A{ 1381060SN/A cpu->tick(); 1391060SN/A} 1401060SN/A 1411060SN/Atemplate <class Impl> 1421060SN/Aconst char * 1435336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 1441060SN/A{ 1454873Sstever@eecs.umich.edu return "FullO3CPU tick"; 1461060SN/A} 1471060SN/A 1481060SN/Atemplate <class Impl> 1492829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 1505606Snate@binkert.org : Event(CPU_Switch_Pri) 1512829Sksewell@umich.edu{ 1522829Sksewell@umich.edu} 1532829Sksewell@umich.edu 1542829Sksewell@umich.edutemplate <class Impl> 1552829Sksewell@umich.eduvoid 1562829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1572829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1582829Sksewell@umich.edu{ 1592829Sksewell@umich.edu tid = thread_num; 1602829Sksewell@umich.edu cpu = thread_cpu; 1612829Sksewell@umich.edu} 1622829Sksewell@umich.edu 1632829Sksewell@umich.edutemplate <class Impl> 1642829Sksewell@umich.eduvoid 1652829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1662829Sksewell@umich.edu{ 1672829Sksewell@umich.edu cpu->activateThread(tid); 1682829Sksewell@umich.edu} 1692829Sksewell@umich.edu 1702829Sksewell@umich.edutemplate <class Impl> 1712829Sksewell@umich.educonst char * 1725336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1732829Sksewell@umich.edu{ 1744873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1752829Sksewell@umich.edu} 1762829Sksewell@umich.edu 1772829Sksewell@umich.edutemplate <class Impl> 1782875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1795606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1802875Sksewell@umich.edu{ 1812875Sksewell@umich.edu} 1822875Sksewell@umich.edu 1832875Sksewell@umich.edutemplate <class Impl> 1842875Sksewell@umich.eduvoid 1852875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1863859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1872875Sksewell@umich.edu{ 1882875Sksewell@umich.edu tid = thread_num; 1892875Sksewell@umich.edu cpu = thread_cpu; 1903859Sbinkertn@umich.edu remove = false; 1912875Sksewell@umich.edu} 1922875Sksewell@umich.edu 1932875Sksewell@umich.edutemplate <class Impl> 1942875Sksewell@umich.eduvoid 1952875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1962875Sksewell@umich.edu{ 1972875Sksewell@umich.edu cpu->deactivateThread(tid); 1983221Sktlim@umich.edu if (remove) 1993221Sktlim@umich.edu cpu->removeThread(tid); 2002875Sksewell@umich.edu} 2012875Sksewell@umich.edu 2022875Sksewell@umich.edutemplate <class Impl> 2032875Sksewell@umich.educonst char * 2045336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 2052875Sksewell@umich.edu{ 2064873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 2072875Sksewell@umich.edu} 2082875Sksewell@umich.edu 2092875Sksewell@umich.edutemplate <class Impl> 2105595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 2112733Sktlim@umich.edu : BaseO3CPU(params), 2123781Sgblack@eecs.umich.edu itb(params->itb), 2133781Sgblack@eecs.umich.edu dtb(params->dtb), 2141060SN/A tickEvent(this), 2155737Scws3k@cs.virginia.edu#ifndef NDEBUG 2165737Scws3k@cs.virginia.edu instcount(0), 2175737Scws3k@cs.virginia.edu#endif 2182292SN/A removeInstsThisCycle(false), 2195595Sgblack@eecs.umich.edu fetch(this, params), 2205595Sgblack@eecs.umich.edu decode(this, params), 2215595Sgblack@eecs.umich.edu rename(this, params), 2225595Sgblack@eecs.umich.edu iew(this, params), 2235595Sgblack@eecs.umich.edu commit(this, params), 2241060SN/A 2255595Sgblack@eecs.umich.edu regFile(this, params->numPhysIntRegs, 2264329Sktlim@umich.edu params->numPhysFloatRegs), 2271060SN/A 2285529Snate@binkert.org freeList(params->numThreads, 2292292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 2302292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 2311060SN/A 2325595Sgblack@eecs.umich.edu rob(this, 2334329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 2342292SN/A params->smtROBPolicy, params->smtROBThreshold, 2355529Snate@binkert.org params->numThreads), 2361060SN/A 2375529Snate@binkert.org scoreboard(params->numThreads, 2382292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 2392292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 2406221Snate@binkert.org TheISA::NumMiscRegs * numThreads, 2412292SN/A TheISA::ZeroReg), 2421060SN/A 2438707Sandreas.hansson@arm.com icachePort(&fetch, this), 2448707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 2458707Sandreas.hansson@arm.com 2462873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 2472873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 2482873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 2492873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 2502873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 2515804Snate@binkert.org activityRec(name(), NumStages, 2522873Sktlim@umich.edu params->backComSize + params->forwardComSize, 2532873Sktlim@umich.edu params->activity), 2541060SN/A 2551060SN/A globalSeqNum(1), 2562292SN/A system(params->system), 2572843Sktlim@umich.edu drainCount(0), 2586221Snate@binkert.org deferRegistration(params->defer_registration) 2591060SN/A{ 2603221Sktlim@umich.edu if (!deferRegistration) { 2613221Sktlim@umich.edu _status = Running; 2623221Sktlim@umich.edu } else { 2633221Sktlim@umich.edu _status = Idle; 2643221Sktlim@umich.edu } 2651681SN/A 2662794Sktlim@umich.edu if (params->checker) { 2672316SN/A BaseCPU *temp_checker = params->checker; 2688733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 2698707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2702316SN/A checker->setSystem(params->system); 2714598Sbinkertn@umich.edu } else { 2724598Sbinkertn@umich.edu checker = NULL; 2734598Sbinkertn@umich.edu } 2742316SN/A 2758793Sgblack@eecs.umich.edu if (!FullSystem) { 2768793Sgblack@eecs.umich.edu thread.resize(numThreads); 2778793Sgblack@eecs.umich.edu tids.resize(numThreads); 2788793Sgblack@eecs.umich.edu } 2791681SN/A 2802325SN/A // The stages also need their CPU pointer setup. However this 2812325SN/A // must be done at the upper level CPU because they have pointers 2822325SN/A // to the upper level CPU, and not this FullO3CPU. 2831060SN/A 2842292SN/A // Set up Pointers to the activeThreads list for each stage 2852292SN/A fetch.setActiveThreads(&activeThreads); 2862292SN/A decode.setActiveThreads(&activeThreads); 2872292SN/A rename.setActiveThreads(&activeThreads); 2882292SN/A iew.setActiveThreads(&activeThreads); 2892292SN/A commit.setActiveThreads(&activeThreads); 2901060SN/A 2911060SN/A // Give each of the stages the time buffer they will use. 2921060SN/A fetch.setTimeBuffer(&timeBuffer); 2931060SN/A decode.setTimeBuffer(&timeBuffer); 2941060SN/A rename.setTimeBuffer(&timeBuffer); 2951060SN/A iew.setTimeBuffer(&timeBuffer); 2961060SN/A commit.setTimeBuffer(&timeBuffer); 2971060SN/A 2981060SN/A // Also setup each of the stages' queues. 2991060SN/A fetch.setFetchQueue(&fetchQueue); 3001060SN/A decode.setFetchQueue(&fetchQueue); 3012292SN/A commit.setFetchQueue(&fetchQueue); 3021060SN/A decode.setDecodeQueue(&decodeQueue); 3031060SN/A rename.setDecodeQueue(&decodeQueue); 3041060SN/A rename.setRenameQueue(&renameQueue); 3051060SN/A iew.setRenameQueue(&renameQueue); 3061060SN/A iew.setIEWQueue(&iewQueue); 3071060SN/A commit.setIEWQueue(&iewQueue); 3081060SN/A commit.setRenameQueue(&renameQueue); 3091060SN/A 3102292SN/A commit.setIEWStage(&iew); 3112292SN/A rename.setIEWStage(&iew); 3122292SN/A rename.setCommitStage(&commit); 3132292SN/A 3148793Sgblack@eecs.umich.edu ThreadID active_threads; 3158793Sgblack@eecs.umich.edu if (FullSystem) { 3168793Sgblack@eecs.umich.edu active_threads = 1; 3178793Sgblack@eecs.umich.edu } else { 3188793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 3192831Sksewell@umich.edu 3208793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 3218793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 3228793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 3238793Sgblack@eecs.umich.edu "or edit your workload size."); 3248793Sgblack@eecs.umich.edu } 3252831Sksewell@umich.edu } 3262292SN/A 3272316SN/A //Make Sure That this a Valid Architeture 3282292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 3292292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 3302292SN/A 3312292SN/A rename.setScoreboard(&scoreboard); 3322292SN/A iew.setScoreboard(&scoreboard); 3332292SN/A 3341060SN/A // Setup the rename map for whichever stages need it. 3352292SN/A PhysRegIndex lreg_idx = 0; 3362292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 3371060SN/A 3386221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3392307SN/A bool bindRegs = (tid <= active_threads - 1); 3402292SN/A 3412292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 3422292SN/A params->numPhysIntRegs, 3432325SN/A lreg_idx, //Index for Logical. Regs 3442292SN/A 3452292SN/A TheISA::NumFloatRegs, 3462292SN/A params->numPhysFloatRegs, 3472325SN/A freg_idx, //Index for Float Regs 3482292SN/A 3492292SN/A TheISA::NumMiscRegs, 3502292SN/A 3512292SN/A TheISA::ZeroReg, 3522292SN/A TheISA::ZeroReg, 3532292SN/A 3542292SN/A tid, 3552292SN/A false); 3562292SN/A 3572292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3582292SN/A params->numPhysIntRegs, 3592325SN/A lreg_idx, //Index for Logical. Regs 3602292SN/A 3612292SN/A TheISA::NumFloatRegs, 3622292SN/A params->numPhysFloatRegs, 3632325SN/A freg_idx, //Index for Float Regs 3642292SN/A 3652292SN/A TheISA::NumMiscRegs, 3662292SN/A 3672292SN/A TheISA::ZeroReg, 3682292SN/A TheISA::ZeroReg, 3692292SN/A 3702292SN/A tid, 3712292SN/A bindRegs); 3723221Sktlim@umich.edu 3733221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3743221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3752292SN/A } 3762292SN/A 3772292SN/A rename.setRenameMap(renameMap); 3782292SN/A commit.setRenameMap(commitRenameMap); 3792292SN/A 3802292SN/A // Give renameMap & rename stage access to the freeList; 3816221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3826221Snate@binkert.org renameMap[tid].setFreeList(&freeList); 3831060SN/A rename.setFreeList(&freeList); 3842292SN/A 3851060SN/A // Setup the ROB for whichever stages need it. 3861060SN/A commit.setROB(&rob); 3872292SN/A 3887823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 3892292SN/A 3902829Sksewell@umich.edu lastActivatedCycle = -1; 3916221Snate@binkert.org#if 0 3923093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3936221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3946221Snate@binkert.org globalSeqNum[tid] = 1; 3956221Snate@binkert.org#endif 3963093Sksewell@umich.edu 3972292SN/A contextSwitch = false; 3985595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3995595Sgblack@eecs.umich.edu 4005595Sgblack@eecs.umich.edu // Setup any thread state. 4015595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 4025595Sgblack@eecs.umich.edu 4036221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 4048793Sgblack@eecs.umich.edu if (FullSystem) { 4058793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 4068793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 4078793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 4088793Sgblack@eecs.umich.edu } else { 4098793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 4108793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 4118793Sgblack@eecs.umich.edu tid, this->thread[tid]); 4128793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4138793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4148793Sgblack@eecs.umich.edu tid, params->workload[tid]); 4155595Sgblack@eecs.umich.edu 4168793Sgblack@eecs.umich.edu //usedTids[tid] = true; 4178793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 4188793Sgblack@eecs.umich.edu } else { 4198793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 4208793Sgblack@eecs.umich.edu //when scheduling threads to CPU 4218793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 4225595Sgblack@eecs.umich.edu 4238793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4248793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4258793Sgblack@eecs.umich.edu tid, dummy_proc); 4268793Sgblack@eecs.umich.edu //usedTids[tid] = false; 4278793Sgblack@eecs.umich.edu } 4285595Sgblack@eecs.umich.edu } 4295595Sgblack@eecs.umich.edu 4305595Sgblack@eecs.umich.edu ThreadContext *tc; 4315595Sgblack@eecs.umich.edu 4325595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 4335595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 4345595Sgblack@eecs.umich.edu 4355595Sgblack@eecs.umich.edu tc = o3_tc; 4365595Sgblack@eecs.umich.edu 4375595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 4385595Sgblack@eecs.umich.edu // CheckerThreadContext. 4395595Sgblack@eecs.umich.edu if (params->checker) { 4405595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 4415595Sgblack@eecs.umich.edu o3_tc, this->checker); 4425595Sgblack@eecs.umich.edu } 4435595Sgblack@eecs.umich.edu 4445595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 4455595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 4466221Snate@binkert.org o3_tc->thread = this->thread[tid]; 4475595Sgblack@eecs.umich.edu 4488793Sgblack@eecs.umich.edu if (FullSystem) { 4498793Sgblack@eecs.umich.edu // Setup quiesce event. 4508793Sgblack@eecs.umich.edu this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 4518793Sgblack@eecs.umich.edu } 4525595Sgblack@eecs.umich.edu // Give the thread the TC. 4536221Snate@binkert.org this->thread[tid]->tc = tc; 4545595Sgblack@eecs.umich.edu 4555595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4565595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4575595Sgblack@eecs.umich.edu } 4585595Sgblack@eecs.umich.edu 4598876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 4608876Sandreas.hansson@arm.com if (!params->defer_registration && !interrupts) { 4618876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 4628876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 4638876Sandreas.hansson@arm.com } 4648876Sandreas.hansson@arm.com 4656221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4666221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4675595Sgblack@eecs.umich.edu 4685595Sgblack@eecs.umich.edu lockAddr = 0; 4695595Sgblack@eecs.umich.edu lockFlag = false; 4701060SN/A} 4711060SN/A 4721060SN/Atemplate <class Impl> 4731755SN/AFullO3CPU<Impl>::~FullO3CPU() 4741060SN/A{ 4751060SN/A} 4761060SN/A 4771060SN/Atemplate <class Impl> 4781060SN/Avoid 4795595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4801062SN/A{ 4812733Sktlim@umich.edu BaseO3CPU::regStats(); 4822292SN/A 4832733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4842292SN/A timesIdled 4852292SN/A .name(name() + ".timesIdled") 4862292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4872292SN/A " unscheduled itself") 4882292SN/A .prereq(timesIdled); 4892292SN/A 4902292SN/A idleCycles 4912292SN/A .name(name() + ".idleCycles") 4922292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4932292SN/A "to idling") 4942292SN/A .prereq(idleCycles); 4952292SN/A 4968627SAli.Saidi@ARM.com quiesceCycles 4978627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 4988627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 4998627SAli.Saidi@ARM.com "for an interrupt") 5008627SAli.Saidi@ARM.com .prereq(quiesceCycles); 5018627SAli.Saidi@ARM.com 5022292SN/A // Number of Instructions simulated 5032292SN/A // -------------------------------- 5042292SN/A // Should probably be in Base CPU but need templated 5052292SN/A // MaxThreads so put in here instead 5062292SN/A committedInsts 5072292SN/A .init(numThreads) 5082292SN/A .name(name() + ".committedInsts") 5092292SN/A .desc("Number of Instructions Simulated"); 5102292SN/A 5118834Satgutier@umich.edu committedOps 5128834Satgutier@umich.edu .init(numThreads) 5138834Satgutier@umich.edu .name(name() + ".committedOps") 5148834Satgutier@umich.edu .desc("Number of Ops (including micro ops) Simulated"); 5158834Satgutier@umich.edu 5162292SN/A totalCommittedInsts 5172292SN/A .name(name() + ".committedInsts_total") 5182292SN/A .desc("Number of Instructions Simulated"); 5192292SN/A 5202292SN/A cpi 5212292SN/A .name(name() + ".cpi") 5222292SN/A .desc("CPI: Cycles Per Instruction") 5232292SN/A .precision(6); 5244392Sktlim@umich.edu cpi = numCycles / committedInsts; 5252292SN/A 5262292SN/A totalCpi 5272292SN/A .name(name() + ".cpi_total") 5282292SN/A .desc("CPI: Total CPI of All Threads") 5292292SN/A .precision(6); 5304392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 5312292SN/A 5322292SN/A ipc 5332292SN/A .name(name() + ".ipc") 5342292SN/A .desc("IPC: Instructions Per Cycle") 5352292SN/A .precision(6); 5364392Sktlim@umich.edu ipc = committedInsts / numCycles; 5372292SN/A 5382292SN/A totalIpc 5392292SN/A .name(name() + ".ipc_total") 5402292SN/A .desc("IPC: Total IPC of All Threads") 5412292SN/A .precision(6); 5424392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 5432292SN/A 5445595Sgblack@eecs.umich.edu this->fetch.regStats(); 5455595Sgblack@eecs.umich.edu this->decode.regStats(); 5465595Sgblack@eecs.umich.edu this->rename.regStats(); 5475595Sgblack@eecs.umich.edu this->iew.regStats(); 5485595Sgblack@eecs.umich.edu this->commit.regStats(); 5497897Shestness@cs.utexas.edu this->rob.regStats(); 5507897Shestness@cs.utexas.edu 5517897Shestness@cs.utexas.edu intRegfileReads 5527897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 5537897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 5547897Shestness@cs.utexas.edu .prereq(intRegfileReads); 5557897Shestness@cs.utexas.edu 5567897Shestness@cs.utexas.edu intRegfileWrites 5577897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 5587897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 5597897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 5607897Shestness@cs.utexas.edu 5617897Shestness@cs.utexas.edu fpRegfileReads 5627897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 5637897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5647897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5657897Shestness@cs.utexas.edu 5667897Shestness@cs.utexas.edu fpRegfileWrites 5677897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5687897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5697897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5707897Shestness@cs.utexas.edu 5717897Shestness@cs.utexas.edu miscRegfileReads 5727897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5737897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5747897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5757897Shestness@cs.utexas.edu 5767897Shestness@cs.utexas.edu miscRegfileWrites 5777897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5787897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5797897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5801062SN/A} 5811062SN/A 5821062SN/Atemplate <class Impl> 5831062SN/Avoid 5841755SN/AFullO3CPU<Impl>::tick() 5851060SN/A{ 5862733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5871060SN/A 5882292SN/A ++numCycles; 5892292SN/A 5902325SN/A// activity = false; 5912292SN/A 5922292SN/A //Tick each of the stages 5931060SN/A fetch.tick(); 5941060SN/A 5951060SN/A decode.tick(); 5961060SN/A 5971060SN/A rename.tick(); 5981060SN/A 5991060SN/A iew.tick(); 6001060SN/A 6011060SN/A commit.tick(); 6021060SN/A 6038793Sgblack@eecs.umich.edu if (!FullSystem) 6048793Sgblack@eecs.umich.edu doContextSwitch(); 6052292SN/A 6062292SN/A // Now advance the time buffers 6071060SN/A timeBuffer.advance(); 6081060SN/A 6091060SN/A fetchQueue.advance(); 6101060SN/A decodeQueue.advance(); 6111060SN/A renameQueue.advance(); 6121060SN/A iewQueue.advance(); 6131060SN/A 6142325SN/A activityRec.advance(); 6152292SN/A 6162292SN/A if (removeInstsThisCycle) { 6172292SN/A cleanUpRemovedInsts(); 6182292SN/A } 6192292SN/A 6202325SN/A if (!tickEvent.scheduled()) { 6212867Sktlim@umich.edu if (_status == SwitchedOut || 6222905Sktlim@umich.edu getState() == SimObject::Drained) { 6233226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 6242325SN/A // increment stat 6257823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 6263221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 6273226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 6287823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 6292325SN/A timesIdled++; 6302325SN/A } else { 6317823Ssteve.reinhardt@amd.com schedule(tickEvent, nextCycle(curTick() + ticks(1))); 6323226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 6332325SN/A } 6342292SN/A } 6352292SN/A 6368793Sgblack@eecs.umich.edu if (!FullSystem) 6378793Sgblack@eecs.umich.edu updateThreadPriority(); 6381060SN/A} 6391060SN/A 6401060SN/Atemplate <class Impl> 6411060SN/Avoid 6421755SN/AFullO3CPU<Impl>::init() 6431060SN/A{ 6445714Shsul@eecs.umich.edu BaseCPU::init(); 6451060SN/A 6468921Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 6478921Sandreas.hansson@arm.com // Set inSyscall so that the CPU doesn't squash when initially 6488921Sandreas.hansson@arm.com // setting up registers. 6496221Snate@binkert.org thread[tid]->inSyscall = true; 6508921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 6518921Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 6528921Sandreas.hansson@arm.com } 6532292SN/A 6548707Sandreas.hansson@arm.com // this CPU could still be unconnected if we are restoring from a 6558707Sandreas.hansson@arm.com // checkpoint and this CPU is to be switched in, thus we can only 6568707Sandreas.hansson@arm.com // do this here if the instruction port is actually connected, if 6578707Sandreas.hansson@arm.com // not we have to do it as part of takeOverFrom 6588707Sandreas.hansson@arm.com if (icachePort.isConnected()) 6598707Sandreas.hansson@arm.com fetch.setIcache(); 6608707Sandreas.hansson@arm.com 6618863Snilay@cs.wisc.edu if (FullSystem && !params()->defer_registration) { 6628793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6638793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6648793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6658793Sgblack@eecs.umich.edu } 6666034Ssteve.reinhardt@amd.com } 6672292SN/A 6682292SN/A // Clear inSyscall. 6696221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6706221Snate@binkert.org thread[tid]->inSyscall = false; 6712292SN/A 6722316SN/A // Initialize stages. 6732292SN/A fetch.initStage(); 6742292SN/A iew.initStage(); 6752292SN/A rename.initStage(); 6762292SN/A commit.initStage(); 6772292SN/A 6782292SN/A commit.setThreads(thread); 6792292SN/A} 6802292SN/A 6812292SN/Atemplate <class Impl> 6822292SN/Avoid 6836221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6842875Sksewell@umich.edu{ 6856221Snate@binkert.org list<ThreadID>::iterator isActive = 6865314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6872875Sksewell@umich.edu 6883226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6893226Sktlim@umich.edu 6902875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6912875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6922875Sksewell@umich.edu tid); 6932875Sksewell@umich.edu 6942875Sksewell@umich.edu activeThreads.push_back(tid); 6952875Sksewell@umich.edu } 6962875Sksewell@umich.edu} 6972875Sksewell@umich.edu 6982875Sksewell@umich.edutemplate <class Impl> 6992875Sksewell@umich.eduvoid 7006221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 7012875Sksewell@umich.edu{ 7022875Sksewell@umich.edu //Remove From Active List, if Active 7036221Snate@binkert.org list<ThreadID>::iterator thread_it = 7045314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 7052875Sksewell@umich.edu 7063226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 7073226Sktlim@umich.edu 7082875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 7092875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 7102875Sksewell@umich.edu tid); 7112875Sksewell@umich.edu activeThreads.erase(thread_it); 7122875Sksewell@umich.edu } 7132875Sksewell@umich.edu} 7142875Sksewell@umich.edu 7152875Sksewell@umich.edutemplate <class Impl> 7166221Snate@binkert.orgCounter 7178834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 7186221Snate@binkert.org{ 7196221Snate@binkert.org Counter total(0); 7206221Snate@binkert.org 7216221Snate@binkert.org ThreadID size = thread.size(); 7226221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 7236221Snate@binkert.org total += thread[i]->numInst; 7246221Snate@binkert.org 7256221Snate@binkert.org return total; 7266221Snate@binkert.org} 7276221Snate@binkert.org 7286221Snate@binkert.orgtemplate <class Impl> 7298834Satgutier@umich.eduCounter 7308834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 7318834Satgutier@umich.edu{ 7328834Satgutier@umich.edu Counter total(0); 7338834Satgutier@umich.edu 7348834Satgutier@umich.edu ThreadID size = thread.size(); 7358834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 7368834Satgutier@umich.edu total += thread[i]->numOp; 7378834Satgutier@umich.edu 7388834Satgutier@umich.edu return total; 7398834Satgutier@umich.edu} 7408834Satgutier@umich.edu 7418834Satgutier@umich.edutemplate <class Impl> 7422875Sksewell@umich.eduvoid 7436221Snate@binkert.orgFullO3CPU<Impl>::activateContext(ThreadID tid, int delay) 7442875Sksewell@umich.edu{ 7452875Sksewell@umich.edu // Needs to set each stage to running as well. 7462875Sksewell@umich.edu if (delay){ 7472875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 7487823Ssteve.reinhardt@amd.com "on cycle %d\n", tid, curTick() + ticks(delay)); 7492875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 7502875Sksewell@umich.edu } else { 7512875Sksewell@umich.edu activateThread(tid); 7522875Sksewell@umich.edu } 7532875Sksewell@umich.edu 7547823Ssteve.reinhardt@amd.com if (lastActivatedCycle < curTick()) { 7552875Sksewell@umich.edu scheduleTickEvent(delay); 7562875Sksewell@umich.edu 7572875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7582875Sksewell@umich.edu // deschedule itself. 7592875Sksewell@umich.edu activityRec.activity(); 7602875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7612875Sksewell@umich.edu 7628627SAli.Saidi@ARM.com quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 7638627SAli.Saidi@ARM.com 7647823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7652875Sksewell@umich.edu 7662875Sksewell@umich.edu _status = Running; 7672875Sksewell@umich.edu } 7682875Sksewell@umich.edu} 7692875Sksewell@umich.edu 7702875Sksewell@umich.edutemplate <class Impl> 7713221Sktlim@umich.edubool 7728737Skoansin.tan@gmail.comFullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove, 7738737Skoansin.tan@gmail.com int delay) 7742875Sksewell@umich.edu{ 7752875Sksewell@umich.edu // Schedule removal of thread data from CPU 7762875Sksewell@umich.edu if (delay){ 7772875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 7787823Ssteve.reinhardt@amd.com "on cycle %d\n", tid, curTick() + ticks(delay)); 7793221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 7803221Sktlim@umich.edu return false; 7812875Sksewell@umich.edu } else { 7822875Sksewell@umich.edu deactivateThread(tid); 7833221Sktlim@umich.edu if (remove) 7843221Sktlim@umich.edu removeThread(tid); 7853221Sktlim@umich.edu return true; 7862875Sksewell@umich.edu } 7872875Sksewell@umich.edu} 7882875Sksewell@umich.edu 7892875Sksewell@umich.edutemplate <class Impl> 7902875Sksewell@umich.eduvoid 7916221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 7922875Sksewell@umich.edu{ 7932875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7948737Skoansin.tan@gmail.com bool deallocated = scheduleDeallocateContext(tid, false, 1); 7953221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 7965570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 7973859Sbinkertn@umich.edu activeThreads.size() == 0) 7982910Sksewell@umich.edu unscheduleTickEvent(); 7998627SAli.Saidi@ARM.com 8008627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 8018627SAli.Saidi@ARM.com lastRunningCycle = curTick(); 8022875Sksewell@umich.edu _status = Idle; 8032875Sksewell@umich.edu} 8042875Sksewell@umich.edu 8052875Sksewell@umich.edutemplate <class Impl> 8062875Sksewell@umich.eduvoid 8076221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 8082875Sksewell@umich.edu{ 8092910Sksewell@umich.edu //For now, this is the same as deallocate 8102910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 8118737Skoansin.tan@gmail.com scheduleDeallocateContext(tid, true, 1); 8122875Sksewell@umich.edu} 8132875Sksewell@umich.edu 8142875Sksewell@umich.edutemplate <class Impl> 8152875Sksewell@umich.eduvoid 8166221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 8172292SN/A{ 8182847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 8192292SN/A // Will change now that the PC and thread state is internal to the CPU 8202683Sktlim@umich.edu // and not in the ThreadContext. 8218793Sgblack@eecs.umich.edu ThreadContext *src_tc; 8228793Sgblack@eecs.umich.edu if (FullSystem) 8238793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 8248793Sgblack@eecs.umich.edu else 8258793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 8262292SN/A 8272292SN/A //Bind Int Regs to Rename Map 8282292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8292292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 8302292SN/A 8312292SN/A renameMap[tid].setEntry(ireg,phys_reg); 8322292SN/A scoreboard.setReg(phys_reg); 8332292SN/A } 8342292SN/A 8352292SN/A //Bind Float Regs to Rename Map 8362292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 8372292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 8382292SN/A 8392292SN/A renameMap[tid].setEntry(freg,phys_reg); 8402292SN/A scoreboard.setReg(phys_reg); 8412292SN/A } 8422292SN/A 8432292SN/A //Copy Thread Data Into RegFile 8442847Sksewell@umich.edu //this->copyFromTC(tid); 8452292SN/A 8462847Sksewell@umich.edu //Set PC/NPC/NNPC 8477720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8482292SN/A 8492680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8502292SN/A 8512292SN/A activateContext(tid,1); 8522292SN/A 8532292SN/A //Reset ROB/IQ/LSQ Entries 8542292SN/A commit.rob->resetEntries(); 8552292SN/A iew.resetEntries(); 8562292SN/A} 8572292SN/A 8582292SN/Atemplate <class Impl> 8592292SN/Avoid 8606221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8612292SN/A{ 8622877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 8632847Sksewell@umich.edu 8642847Sksewell@umich.edu // Copy Thread Data From RegFile 8652847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 8665364Sksewell@umich.edu // this->copyToTC(tid); 8675364Sksewell@umich.edu 8685364Sksewell@umich.edu 8695364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 8705364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 8715364Sksewell@umich.edu // in SMT workloads. 8722847Sksewell@umich.edu 8732847Sksewell@umich.edu // Unbind Int Regs from Rename Map 8742292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8752292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 8762292SN/A 8772292SN/A scoreboard.unsetReg(phys_reg); 8782292SN/A freeList.addReg(phys_reg); 8792292SN/A } 8802292SN/A 8812847Sksewell@umich.edu // Unbind Float Regs from Rename Map 8825362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 8832292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 8842292SN/A 8852292SN/A scoreboard.unsetReg(phys_reg); 8862292SN/A freeList.addReg(phys_reg); 8872292SN/A } 8882292SN/A 8892847Sksewell@umich.edu // Squash Throughout Pipeline 8908138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 8918138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 8928138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 8932292SN/A decode.squash(tid); 8942935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 8952875Sksewell@umich.edu iew.squash(tid); 8965363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 8972935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 8982292SN/A 8995362Sksewell@umich.edu 9005362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 9012292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 9022292SN/A 9032847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 9043229Sktlim@umich.edu 9053229Sktlim@umich.edu // Commented out for now. This should be possible to do by 9063229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 9073229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 9083229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 9093229Sktlim@umich.edu/* 9102292SN/A if (activeThreads.size() >= 1) { 9112292SN/A commit.rob->resetEntries(); 9122292SN/A iew.resetEntries(); 9132292SN/A } 9143229Sktlim@umich.edu*/ 9152292SN/A} 9162292SN/A 9172292SN/A 9182292SN/Atemplate <class Impl> 9192292SN/Avoid 9206221Snate@binkert.orgFullO3CPU<Impl>::activateWhenReady(ThreadID tid) 9212292SN/A{ 9222733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 9232292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 9242292SN/A tid); 9252292SN/A 9262292SN/A bool ready = true; 9272292SN/A 9282292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 9292733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9302292SN/A "Phys. Int. Regs.\n", 9312292SN/A tid); 9322292SN/A ready = false; 9332292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 9342733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9352292SN/A "Phys. Float. Regs.\n", 9362292SN/A tid); 9372292SN/A ready = false; 9382292SN/A } else if (commit.rob->numFreeEntries() >= 9392292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 9402733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9412292SN/A "ROB entries.\n", 9422292SN/A tid); 9432292SN/A ready = false; 9442292SN/A } else if (iew.instQueue.numFreeEntries() >= 9452292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 9462733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9472292SN/A "IQ entries.\n", 9482292SN/A tid); 9492292SN/A ready = false; 9502292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 9512292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 9522733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9532292SN/A "LSQ entries.\n", 9542292SN/A tid); 9552292SN/A ready = false; 9562292SN/A } 9572292SN/A 9582292SN/A if (ready) { 9592292SN/A insertThread(tid); 9602292SN/A 9612292SN/A contextSwitch = false; 9622292SN/A 9632292SN/A cpuWaitList.remove(tid); 9642292SN/A } else { 9652292SN/A suspendContext(tid); 9662292SN/A 9672292SN/A //blocks fetch 9682292SN/A contextSwitch = true; 9692292SN/A 9702875Sksewell@umich.edu //@todo: dont always add to waitlist 9712292SN/A //do waitlist 9722292SN/A cpuWaitList.push_back(tid); 9731060SN/A } 9741060SN/A} 9751060SN/A 9764192Sktlim@umich.edutemplate <class Impl> 9775595Sgblack@eecs.umich.eduFault 9786221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 9795702Ssaidi@eecs.umich.edu{ 9805702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9815702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 9825702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 9835702Ssaidi@eecs.umich.edu 9845702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 9855702Ssaidi@eecs.umich.edu 9865702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9875702Ssaidi@eecs.umich.edu#endif 9885702Ssaidi@eecs.umich.edu return NoFault; 9895702Ssaidi@eecs.umich.edu} 9905702Ssaidi@eecs.umich.edu 9915702Ssaidi@eecs.umich.edutemplate <class Impl> 9925702Ssaidi@eecs.umich.edubool 9936221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 9945702Ssaidi@eecs.umich.edu{ 9955702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9965702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 9975702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 9985702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 9995702Ssaidi@eecs.umich.edu 10005702Ssaidi@eecs.umich.edu switch (palFunc) { 10015702Ssaidi@eecs.umich.edu case PAL::halt: 10025702Ssaidi@eecs.umich.edu halt(); 10035702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 10045702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 10055702Ssaidi@eecs.umich.edu break; 10065702Ssaidi@eecs.umich.edu 10075702Ssaidi@eecs.umich.edu case PAL::bpt: 10085702Ssaidi@eecs.umich.edu case PAL::bugchk: 10095702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 10105702Ssaidi@eecs.umich.edu return false; 10115702Ssaidi@eecs.umich.edu break; 10125702Ssaidi@eecs.umich.edu } 10135702Ssaidi@eecs.umich.edu#endif 10145702Ssaidi@eecs.umich.edu return true; 10155702Ssaidi@eecs.umich.edu} 10165702Ssaidi@eecs.umich.edu 10175702Ssaidi@eecs.umich.edutemplate <class Impl> 10185702Ssaidi@eecs.umich.eduFault 10195595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 10205595Sgblack@eecs.umich.edu{ 10215595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 10225647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 10235595Sgblack@eecs.umich.edu} 10245595Sgblack@eecs.umich.edu 10255595Sgblack@eecs.umich.edutemplate <class Impl> 10265595Sgblack@eecs.umich.eduvoid 10275595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 10285595Sgblack@eecs.umich.edu{ 10295595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 10305595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 10315595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 10325595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 10335595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 10345595Sgblack@eecs.umich.edu 10355595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 10365647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 10375595Sgblack@eecs.umich.edu 10385595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 10397684Sgblack@eecs.umich.edu this->trap(interrupt, 0, NULL); 10405595Sgblack@eecs.umich.edu} 10415595Sgblack@eecs.umich.edu 10421060SN/Atemplate <class Impl> 10432852Sktlim@umich.eduvoid 10447684Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) 10455595Sgblack@eecs.umich.edu{ 10465595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 10477684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 10485595Sgblack@eecs.umich.edu} 10495595Sgblack@eecs.umich.edu 10505595Sgblack@eecs.umich.edutemplate <class Impl> 10515595Sgblack@eecs.umich.eduvoid 10526221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 10535595Sgblack@eecs.umich.edu{ 10545595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 10555595Sgblack@eecs.umich.edu 10565595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 10575595Sgblack@eecs.umich.edu 10585595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 10595595Sgblack@eecs.umich.edu // instruction. 10605595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 10615595Sgblack@eecs.umich.edu 10625595Sgblack@eecs.umich.edu // Execute the actual syscall. 10635595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 10645595Sgblack@eecs.umich.edu 10655595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 10665595Sgblack@eecs.umich.edu // incrementing it. 10675595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 10685595Sgblack@eecs.umich.edu} 10695595Sgblack@eecs.umich.edu 10705595Sgblack@eecs.umich.edutemplate <class Impl> 10715595Sgblack@eecs.umich.eduvoid 10722864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 10732864Sktlim@umich.edu{ 10742918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 10752918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 10762864Sktlim@umich.edu BaseCPU::serialize(os); 10772864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 10782864Sktlim@umich.edu tickEvent.serialize(os); 10792864Sktlim@umich.edu 10802864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10812864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 10822864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10832864Sktlim@umich.edu static SimpleThread temp; 10842864Sktlim@umich.edu 10856221Snate@binkert.org ThreadID size = thread.size(); 10866221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 10872864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 10882864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10892864Sktlim@umich.edu temp.serialize(os); 10902864Sktlim@umich.edu } 10912864Sktlim@umich.edu} 10922864Sktlim@umich.edu 10932864Sktlim@umich.edutemplate <class Impl> 10942864Sktlim@umich.eduvoid 10952864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 10962864Sktlim@umich.edu{ 10972918Sktlim@umich.edu SimObject::State so_state; 10982918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 10992864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 11002864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 11012864Sktlim@umich.edu 11022864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 11032864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 11042864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 11052864Sktlim@umich.edu static SimpleThread temp; 11062864Sktlim@umich.edu 11076221Snate@binkert.org ThreadID size = thread.size(); 11086221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 11092864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 11102864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 11112864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 11122864Sktlim@umich.edu } 11132864Sktlim@umich.edu} 11142864Sktlim@umich.edu 11152864Sktlim@umich.edutemplate <class Impl> 11162905Sktlim@umich.eduunsigned int 11172843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 11181060SN/A{ 11193125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 11203512Sktlim@umich.edu 11213512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 11223512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 11233512Sktlim@umich.edu return 0; 11243512Sktlim@umich.edu } 11253512Sktlim@umich.edu 11262843Sktlim@umich.edu drainCount = 0; 11272843Sktlim@umich.edu fetch.drain(); 11282843Sktlim@umich.edu decode.drain(); 11292843Sktlim@umich.edu rename.drain(); 11302843Sktlim@umich.edu iew.drain(); 11312843Sktlim@umich.edu commit.drain(); 11322325SN/A 11332325SN/A // Wake the CPU and record activity so everything can drain out if 11342863Sktlim@umich.edu // the CPU was not able to immediately drain. 11352905Sktlim@umich.edu if (getState() != SimObject::Drained) { 11362864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 11372864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 11382864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 11392864Sktlim@umich.edu // process on the drain event. 11402864Sktlim@umich.edu drainEvent = drain_event; 11412843Sktlim@umich.edu 11422863Sktlim@umich.edu wakeCPU(); 11432863Sktlim@umich.edu activityRec.activity(); 11442852Sktlim@umich.edu 11452905Sktlim@umich.edu return 1; 11462863Sktlim@umich.edu } else { 11472905Sktlim@umich.edu return 0; 11482863Sktlim@umich.edu } 11492316SN/A} 11502310SN/A 11512316SN/Atemplate <class Impl> 11522316SN/Avoid 11532843Sktlim@umich.eduFullO3CPU<Impl>::resume() 11542316SN/A{ 11552843Sktlim@umich.edu fetch.resume(); 11562843Sktlim@umich.edu decode.resume(); 11572843Sktlim@umich.edu rename.resume(); 11582843Sktlim@umich.edu iew.resume(); 11592843Sktlim@umich.edu commit.resume(); 11602316SN/A 11612905Sktlim@umich.edu changeState(SimObject::Running); 11622905Sktlim@umich.edu 11632864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 11642864Sktlim@umich.edu return; 11652864Sktlim@umich.edu 11664762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 11673319Shsul@eecs.umich.edu 11682843Sktlim@umich.edu if (!tickEvent.scheduled()) 11695606Snate@binkert.org schedule(tickEvent, nextCycle()); 11702843Sktlim@umich.edu _status = Running; 11712843Sktlim@umich.edu} 11722316SN/A 11732843Sktlim@umich.edutemplate <class Impl> 11742843Sktlim@umich.eduvoid 11752843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 11762843Sktlim@umich.edu{ 11772843Sktlim@umich.edu if (++drainCount == NumStages) { 11782316SN/A if (tickEvent.scheduled()) 11792316SN/A tickEvent.squash(); 11802863Sktlim@umich.edu 11812905Sktlim@umich.edu changeState(SimObject::Drained); 11822863Sktlim@umich.edu 11833126Sktlim@umich.edu BaseCPU::switchOut(); 11843126Sktlim@umich.edu 11852863Sktlim@umich.edu if (drainEvent) { 11862863Sktlim@umich.edu drainEvent->process(); 11872863Sktlim@umich.edu drainEvent = NULL; 11882863Sktlim@umich.edu } 11892310SN/A } 11902843Sktlim@umich.edu assert(drainCount <= 5); 11912843Sktlim@umich.edu} 11922843Sktlim@umich.edu 11932843Sktlim@umich.edutemplate <class Impl> 11942843Sktlim@umich.eduvoid 11952843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11962843Sktlim@umich.edu{ 11972843Sktlim@umich.edu fetch.switchOut(); 11982843Sktlim@umich.edu rename.switchOut(); 11992325SN/A iew.switchOut(); 12002843Sktlim@umich.edu commit.switchOut(); 12012843Sktlim@umich.edu instList.clear(); 12022843Sktlim@umich.edu while (!removeList.empty()) { 12032843Sktlim@umich.edu removeList.pop(); 12042843Sktlim@umich.edu } 12052843Sktlim@umich.edu 12062843Sktlim@umich.edu _status = SwitchedOut; 12078887Sgeoffrey.blake@arm.com 12082843Sktlim@umich.edu if (checker) 12092843Sktlim@umich.edu checker->switchOut(); 12108887Sgeoffrey.blake@arm.com 12113126Sktlim@umich.edu if (tickEvent.scheduled()) 12123126Sktlim@umich.edu tickEvent.squash(); 12131060SN/A} 12141060SN/A 12151060SN/Atemplate <class Impl> 12161060SN/Avoid 12171755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 12181060SN/A{ 12192325SN/A // Flush out any old data from the time buffers. 12202873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 12212307SN/A timeBuffer.advance(); 12222307SN/A fetchQueue.advance(); 12232307SN/A decodeQueue.advance(); 12242307SN/A renameQueue.advance(); 12252307SN/A iewQueue.advance(); 12262307SN/A } 12272307SN/A 12282325SN/A activityRec.reset(); 12292307SN/A 12308737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 12311060SN/A 12322307SN/A fetch.takeOverFrom(); 12332307SN/A decode.takeOverFrom(); 12342307SN/A rename.takeOverFrom(); 12352307SN/A iew.takeOverFrom(); 12362307SN/A commit.takeOverFrom(); 12372307SN/A 12387507Stjones1@inf.ed.ac.uk assert(!tickEvent.scheduled() || tickEvent.squashed()); 12391060SN/A 12402325SN/A // @todo: Figure out how to properly select the tid to put onto 12412325SN/A // the active threads list. 12426221Snate@binkert.org ThreadID tid = 0; 12432307SN/A 12446221Snate@binkert.org list<ThreadID>::iterator isActive = 12455314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 12462307SN/A 12472307SN/A if (isActive == activeThreads.end()) { 12482325SN/A //May Need to Re-code this if the delay variable is the delay 12492325SN/A //needed for thread to activate 12502733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 12512307SN/A tid); 12522307SN/A 12532307SN/A activeThreads.push_back(tid); 12542307SN/A } 12552307SN/A 12562325SN/A // Set all statuses to active, schedule the CPU's tick event. 12572307SN/A // @todo: Fix up statuses so this is handled properly 12586221Snate@binkert.org ThreadID size = threadContexts.size(); 12596221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 12602680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 12612680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 12621681SN/A _status = Running; 12637507Stjones1@inf.ed.ac.uk reschedule(tickEvent, nextCycle(), true); 12641681SN/A } 12651060SN/A } 12662307SN/A if (!tickEvent.scheduled()) 12675606Snate@binkert.org schedule(tickEvent, nextCycle()); 12688627SAli.Saidi@ARM.com 12698627SAli.Saidi@ARM.com lastRunningCycle = curTick(); 12701060SN/A} 12711060SN/A 12721060SN/Atemplate <class Impl> 12735595Sgblack@eecs.umich.eduTheISA::MiscReg 12746221Snate@binkert.orgFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 12755595Sgblack@eecs.umich.edu{ 12766313Sgblack@eecs.umich.edu return this->isa[tid].readMiscRegNoEffect(misc_reg); 12775595Sgblack@eecs.umich.edu} 12785595Sgblack@eecs.umich.edu 12795595Sgblack@eecs.umich.edutemplate <class Impl> 12805595Sgblack@eecs.umich.eduTheISA::MiscReg 12816221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 12825595Sgblack@eecs.umich.edu{ 12837897Shestness@cs.utexas.edu miscRegfileReads++; 12846313Sgblack@eecs.umich.edu return this->isa[tid].readMiscReg(misc_reg, tcBase(tid)); 12855595Sgblack@eecs.umich.edu} 12865595Sgblack@eecs.umich.edu 12875595Sgblack@eecs.umich.edutemplate <class Impl> 12885595Sgblack@eecs.umich.eduvoid 12895595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 12906221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12915595Sgblack@eecs.umich.edu{ 12926313Sgblack@eecs.umich.edu this->isa[tid].setMiscRegNoEffect(misc_reg, val); 12935595Sgblack@eecs.umich.edu} 12945595Sgblack@eecs.umich.edu 12955595Sgblack@eecs.umich.edutemplate <class Impl> 12965595Sgblack@eecs.umich.eduvoid 12975595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 12986221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12995595Sgblack@eecs.umich.edu{ 13007897Shestness@cs.utexas.edu miscRegfileWrites++; 13016313Sgblack@eecs.umich.edu this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); 13025595Sgblack@eecs.umich.edu} 13035595Sgblack@eecs.umich.edu 13045595Sgblack@eecs.umich.edutemplate <class Impl> 13051060SN/Auint64_t 13061755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 13071060SN/A{ 13087897Shestness@cs.utexas.edu intRegfileReads++; 13091060SN/A return regFile.readIntReg(reg_idx); 13101060SN/A} 13111060SN/A 13121060SN/Atemplate <class Impl> 13132455SN/AFloatReg 13142455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 13151060SN/A{ 13167897Shestness@cs.utexas.edu fpRegfileReads++; 13172455SN/A return regFile.readFloatReg(reg_idx); 13181060SN/A} 13191060SN/A 13201060SN/Atemplate <class Impl> 13212455SN/AFloatRegBits 13222455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 13232455SN/A{ 13247897Shestness@cs.utexas.edu fpRegfileReads++; 13252455SN/A return regFile.readFloatRegBits(reg_idx); 13261060SN/A} 13271060SN/A 13281060SN/Atemplate <class Impl> 13291060SN/Avoid 13301755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 13311060SN/A{ 13327897Shestness@cs.utexas.edu intRegfileWrites++; 13331060SN/A regFile.setIntReg(reg_idx, val); 13341060SN/A} 13351060SN/A 13361060SN/Atemplate <class Impl> 13371060SN/Avoid 13382455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 13391060SN/A{ 13407897Shestness@cs.utexas.edu fpRegfileWrites++; 13412455SN/A regFile.setFloatReg(reg_idx, val); 13421060SN/A} 13431060SN/A 13441060SN/Atemplate <class Impl> 13451060SN/Avoid 13462455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 13472455SN/A{ 13487897Shestness@cs.utexas.edu fpRegfileWrites++; 13492455SN/A regFile.setFloatRegBits(reg_idx, val); 13501060SN/A} 13511060SN/A 13521060SN/Atemplate <class Impl> 13531060SN/Auint64_t 13546221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 13551060SN/A{ 13567897Shestness@cs.utexas.edu intRegfileReads++; 13572292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13582292SN/A 13592292SN/A return regFile.readIntReg(phys_reg); 13602292SN/A} 13612292SN/A 13622292SN/Atemplate <class Impl> 13632292SN/Afloat 13646314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 13652292SN/A{ 13667897Shestness@cs.utexas.edu fpRegfileReads++; 13676032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13682307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13692292SN/A 13702669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 13712292SN/A} 13722292SN/A 13732292SN/Atemplate <class Impl> 13742292SN/Auint64_t 13756221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 13762292SN/A{ 13777897Shestness@cs.utexas.edu fpRegfileReads++; 13786032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13792307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13802292SN/A 13812669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13821060SN/A} 13831060SN/A 13841060SN/Atemplate <class Impl> 13851060SN/Avoid 13866221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 13871060SN/A{ 13887897Shestness@cs.utexas.edu intRegfileWrites++; 13892292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13902292SN/A 13912292SN/A regFile.setIntReg(phys_reg, val); 13921060SN/A} 13931060SN/A 13941060SN/Atemplate <class Impl> 13951060SN/Avoid 13966314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 13971060SN/A{ 13987897Shestness@cs.utexas.edu fpRegfileWrites++; 13996032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 14002918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 14012292SN/A 14022669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 14031060SN/A} 14041060SN/A 14051060SN/Atemplate <class Impl> 14061060SN/Avoid 14076221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 14081060SN/A{ 14097897Shestness@cs.utexas.edu fpRegfileWrites++; 14106032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 14112918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 14121060SN/A 14132669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 14142292SN/A} 14152292SN/A 14162292SN/Atemplate <class Impl> 14177720Sgblack@eecs.umich.eduTheISA::PCState 14187720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 14192292SN/A{ 14207720Sgblack@eecs.umich.edu return commit.pcState(tid); 14211060SN/A} 14221060SN/A 14231060SN/Atemplate <class Impl> 14241060SN/Avoid 14257720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 14261060SN/A{ 14277720Sgblack@eecs.umich.edu commit.pcState(val, tid); 14282292SN/A} 14291060SN/A 14302292SN/Atemplate <class Impl> 14317720Sgblack@eecs.umich.eduAddr 14327720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 14334636Sgblack@eecs.umich.edu{ 14347720Sgblack@eecs.umich.edu return commit.instAddr(tid); 14354636Sgblack@eecs.umich.edu} 14364636Sgblack@eecs.umich.edu 14374636Sgblack@eecs.umich.edutemplate <class Impl> 14387720Sgblack@eecs.umich.eduAddr 14397720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 14404636Sgblack@eecs.umich.edu{ 14417720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 14424636Sgblack@eecs.umich.edu} 14434636Sgblack@eecs.umich.edu 14444636Sgblack@eecs.umich.edutemplate <class Impl> 14457720Sgblack@eecs.umich.eduMicroPC 14467720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 14472292SN/A{ 14487720Sgblack@eecs.umich.edu return commit.microPC(tid); 14494636Sgblack@eecs.umich.edu} 14504636Sgblack@eecs.umich.edu 14514636Sgblack@eecs.umich.edutemplate <class Impl> 14525595Sgblack@eecs.umich.eduvoid 14536221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 14545595Sgblack@eecs.umich.edu{ 14555595Sgblack@eecs.umich.edu this->thread[tid]->inSyscall = true; 14565595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 14575595Sgblack@eecs.umich.edu} 14585595Sgblack@eecs.umich.edu 14595595Sgblack@eecs.umich.edutemplate <class Impl> 14602292SN/Atypename FullO3CPU<Impl>::ListIt 14612292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14622292SN/A{ 14632292SN/A instList.push_back(inst); 14641060SN/A 14652292SN/A return --(instList.end()); 14662292SN/A} 14671060SN/A 14682292SN/Atemplate <class Impl> 14692292SN/Avoid 14708834Satgutier@umich.eduFullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 14712292SN/A{ 14722292SN/A // Keep an instruction count. 14738834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 14748834Satgutier@umich.edu thread[tid]->numInst++; 14758834Satgutier@umich.edu thread[tid]->numInsts++; 14768834Satgutier@umich.edu committedInsts[tid]++; 14778834Satgutier@umich.edu totalCommittedInsts++; 14788834Satgutier@umich.edu } 14798834Satgutier@umich.edu thread[tid]->numOp++; 14808834Satgutier@umich.edu thread[tid]->numOps++; 14818834Satgutier@umich.edu committedOps[tid]++; 14828834Satgutier@umich.edu 14837897Shestness@cs.utexas.edu system->totalNumInsts++; 14842292SN/A // Check for instruction-count-based events. 14852292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 14867897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 14872292SN/A} 14882292SN/A 14892292SN/Atemplate <class Impl> 14902292SN/Avoid 14911755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 14921060SN/A{ 14937720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 14942292SN/A "[sn:%lli]\n", 14957720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 14961060SN/A 14972292SN/A removeInstsThisCycle = true; 14981060SN/A 14991060SN/A // Remove the front instruction. 15002292SN/A removeList.push(inst->getInstListIt()); 15011060SN/A} 15021060SN/A 15031060SN/Atemplate <class Impl> 15041060SN/Avoid 15056221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 15061060SN/A{ 15072733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 15082292SN/A " list.\n", tid); 15091060SN/A 15102292SN/A ListIt end_it; 15111060SN/A 15122292SN/A bool rob_empty = false; 15132292SN/A 15142292SN/A if (instList.empty()) { 15152292SN/A return; 15162292SN/A } else if (rob.isEmpty(/*tid*/)) { 15172733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 15182292SN/A end_it = instList.begin(); 15192292SN/A rob_empty = true; 15202292SN/A } else { 15212292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 15222733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 15232292SN/A } 15242292SN/A 15252292SN/A removeInstsThisCycle = true; 15262292SN/A 15272292SN/A ListIt inst_it = instList.end(); 15282292SN/A 15292292SN/A inst_it--; 15302292SN/A 15312292SN/A // Walk through the instruction list, removing any instructions 15322292SN/A // that were inserted after the given instruction iterator, end_it. 15332292SN/A while (inst_it != end_it) { 15342292SN/A assert(!instList.empty()); 15352292SN/A 15362292SN/A squashInstIt(inst_it, tid); 15372292SN/A 15382292SN/A inst_it--; 15392292SN/A } 15402292SN/A 15412292SN/A // If the ROB was empty, then we actually need to remove the first 15422292SN/A // instruction as well. 15432292SN/A if (rob_empty) { 15442292SN/A squashInstIt(inst_it, tid); 15452292SN/A } 15461060SN/A} 15471060SN/A 15481060SN/Atemplate <class Impl> 15491060SN/Avoid 15506221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 15511062SN/A{ 15522292SN/A assert(!instList.empty()); 15532292SN/A 15542292SN/A removeInstsThisCycle = true; 15552292SN/A 15562292SN/A ListIt inst_iter = instList.end(); 15572292SN/A 15582292SN/A inst_iter--; 15592292SN/A 15602733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 15612292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15622292SN/A tid, seq_num, (*inst_iter)->seqNum); 15631062SN/A 15642292SN/A while ((*inst_iter)->seqNum > seq_num) { 15651062SN/A 15662292SN/A bool break_loop = (inst_iter == instList.begin()); 15671062SN/A 15682292SN/A squashInstIt(inst_iter, tid); 15691062SN/A 15702292SN/A inst_iter--; 15711062SN/A 15722292SN/A if (break_loop) 15732292SN/A break; 15742292SN/A } 15752292SN/A} 15762292SN/A 15772292SN/Atemplate <class Impl> 15782292SN/Ainline void 15796221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 15802292SN/A{ 15812292SN/A if ((*instIt)->threadNumber == tid) { 15822733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 15837720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15842292SN/A (*instIt)->threadNumber, 15852292SN/A (*instIt)->seqNum, 15867720Sgblack@eecs.umich.edu (*instIt)->pcState()); 15871062SN/A 15881062SN/A // Mark it as squashed. 15892292SN/A (*instIt)->setSquashed(); 15902292SN/A 15912325SN/A // @todo: Formulate a consistent method for deleting 15922325SN/A // instructions from the instruction list 15932292SN/A // Remove the instruction from the list. 15942292SN/A removeList.push(instIt); 15952292SN/A } 15962292SN/A} 15972292SN/A 15982292SN/Atemplate <class Impl> 15992292SN/Avoid 16002292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 16012292SN/A{ 16022292SN/A while (!removeList.empty()) { 16032733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 16047720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 16052292SN/A (*removeList.front())->threadNumber, 16062292SN/A (*removeList.front())->seqNum, 16077720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 16082292SN/A 16092292SN/A instList.erase(removeList.front()); 16102292SN/A 16112292SN/A removeList.pop(); 16121062SN/A } 16131062SN/A 16142292SN/A removeInstsThisCycle = false; 16151062SN/A} 16162325SN/A/* 16171062SN/Atemplate <class Impl> 16181062SN/Avoid 16191755SN/AFullO3CPU<Impl>::removeAllInsts() 16201060SN/A{ 16211060SN/A instList.clear(); 16221060SN/A} 16232325SN/A*/ 16241060SN/Atemplate <class Impl> 16251060SN/Avoid 16261755SN/AFullO3CPU<Impl>::dumpInsts() 16271060SN/A{ 16281060SN/A int num = 0; 16291060SN/A 16302292SN/A ListIt inst_list_it = instList.begin(); 16312292SN/A 16322292SN/A cprintf("Dumping Instruction List\n"); 16332292SN/A 16342292SN/A while (inst_list_it != instList.end()) { 16352292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 16362292SN/A "Squashed:%i\n\n", 16377720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 16382292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16392292SN/A (*inst_list_it)->isSquashed()); 16401060SN/A inst_list_it++; 16411060SN/A ++num; 16421060SN/A } 16431060SN/A} 16442325SN/A/* 16451060SN/Atemplate <class Impl> 16461060SN/Avoid 16471755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 16481060SN/A{ 16491060SN/A iew.wakeDependents(inst); 16501060SN/A} 16512325SN/A*/ 16522292SN/Atemplate <class Impl> 16532292SN/Avoid 16542292SN/AFullO3CPU<Impl>::wakeCPU() 16552292SN/A{ 16562325SN/A if (activityRec.active() || tickEvent.scheduled()) { 16572325SN/A DPRINTF(Activity, "CPU already running.\n"); 16582292SN/A return; 16592292SN/A } 16602292SN/A 16612325SN/A DPRINTF(Activity, "Waking up CPU\n"); 16622325SN/A 16637823Ssteve.reinhardt@amd.com idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 16647823Ssteve.reinhardt@amd.com numCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 16652292SN/A 16665606Snate@binkert.org schedule(tickEvent, nextCycle()); 16672292SN/A} 16682292SN/A 16695807Snate@binkert.orgtemplate <class Impl> 16705807Snate@binkert.orgvoid 16715807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 16725807Snate@binkert.org{ 16735807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 16745807Snate@binkert.org return; 16755807Snate@binkert.org 16765807Snate@binkert.org this->wakeCPU(); 16775807Snate@binkert.org 16785807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 16795807Snate@binkert.org this->threadContexts[0]->activate(); 16805807Snate@binkert.org} 16815807Snate@binkert.org 16822292SN/Atemplate <class Impl> 16836221Snate@binkert.orgThreadID 16842292SN/AFullO3CPU<Impl>::getFreeTid() 16852292SN/A{ 16866221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 16876221Snate@binkert.org if (!tids[tid]) { 16886221Snate@binkert.org tids[tid] = true; 16896221Snate@binkert.org return tid; 16902292SN/A } 16912292SN/A } 16922292SN/A 16936221Snate@binkert.org return InvalidThreadID; 16942292SN/A} 16952292SN/A 16962292SN/Atemplate <class Impl> 16972292SN/Avoid 16982292SN/AFullO3CPU<Impl>::doContextSwitch() 16992292SN/A{ 17002292SN/A if (contextSwitch) { 17012292SN/A 17022292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 17032292SN/A 17046221Snate@binkert.org ThreadID size = cpuWaitList.size(); 17056221Snate@binkert.org for (ThreadID tid = 0; tid < size; tid++) { 17062292SN/A activateWhenReady(tid); 17072292SN/A } 17082292SN/A 17092292SN/A if (cpuWaitList.size() == 0) 17102292SN/A contextSwitch = true; 17112292SN/A } 17122292SN/A} 17132292SN/A 17142292SN/Atemplate <class Impl> 17152292SN/Avoid 17162292SN/AFullO3CPU<Impl>::updateThreadPriority() 17172292SN/A{ 17186221Snate@binkert.org if (activeThreads.size() > 1) { 17192292SN/A //DEFAULT TO ROUND ROBIN SCHEME 17202292SN/A //e.g. Move highest priority to end of thread list 17216221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 17222292SN/A 17232292SN/A unsigned high_thread = *list_begin; 17242292SN/A 17252292SN/A activeThreads.erase(list_begin); 17262292SN/A 17272292SN/A activeThreads.push_back(high_thread); 17282292SN/A } 17292292SN/A} 17301060SN/A 17311755SN/A// Forward declaration of FullO3CPU. 17322818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1733