cpu.cc revision 8793
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 37897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 41689SN/A * All rights reserved. 51689SN/A * 61689SN/A * Redistribution and use in source and binary forms, with or without 71689SN/A * modification, are permitted provided that the following conditions are 81689SN/A * met: redistributions of source code must retain the above copyright 91689SN/A * notice, this list of conditions and the following disclaimer; 101689SN/A * redistributions in binary form must reproduce the above copyright 111689SN/A * notice, this list of conditions and the following disclaimer in the 121689SN/A * documentation and/or other materials provided with the distribution; 131689SN/A * neither the name of the copyright holders nor the names of its 141689SN/A * contributors may be used to endorse or promote products derived from 151689SN/A * this software without specific prior written permission. 161689SN/A * 171689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 302756Sksewell@umich.edu * Korey Sewell 317897Shestness@cs.utexas.edu * Rick Strong 321689SN/A */ 331689SN/A 348779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 356658Snate@binkert.org#include "config/the_isa.hh" 362733Sktlim@umich.edu#include "config/use_checker.hh" 378229Snate@binkert.org#include "cpu/o3/cpu.hh" 388229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 398229Snate@binkert.org#include "cpu/o3/thread_context.hh" 404762Snate@binkert.org#include "cpu/activity.hh" 418779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 424762Snate@binkert.org#include "cpu/simple_thread.hh" 434762Snate@binkert.org#include "cpu/thread_context.hh" 448232Snate@binkert.org#include "debug/Activity.hh" 458232Snate@binkert.org#include "debug/O3CPU.hh" 468232Snate@binkert.org#include "debug/Quiesce.hh" 474762Snate@binkert.org#include "enums/MemoryMode.hh" 484762Snate@binkert.org#include "sim/core.hh" 498793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 508779Sgblack@eecs.umich.edu#include "sim/process.hh" 514762Snate@binkert.org#include "sim/stat_control.hh" 528460SAli.Saidi@ARM.com#include "sim/system.hh" 534762Snate@binkert.org 542794Sktlim@umich.edu#if USE_CHECKER 552794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 562794Sktlim@umich.edu#endif 572794Sktlim@umich.edu 585702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 595702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 608232Snate@binkert.org#include "debug/Activity.hh" 615702Ssaidi@eecs.umich.edu#endif 625702Ssaidi@eecs.umich.edu 635529Snate@binkert.orgclass BaseCPUParams; 645529Snate@binkert.org 652669Sktlim@umich.eduusing namespace TheISA; 666221Snate@binkert.orgusing namespace std; 671060SN/A 685529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 695712Shsul@eecs.umich.edu : BaseCPU(params) 701060SN/A{ 711060SN/A} 721060SN/A 732292SN/Avoid 742733Sktlim@umich.eduBaseO3CPU::regStats() 752292SN/A{ 762292SN/A BaseCPU::regStats(); 772292SN/A} 782292SN/A 791060SN/Atemplate <class Impl> 801755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 815606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 821060SN/A{ 831060SN/A} 841060SN/A 851060SN/Atemplate <class Impl> 861060SN/Avoid 871755SN/AFullO3CPU<Impl>::TickEvent::process() 881060SN/A{ 891060SN/A cpu->tick(); 901060SN/A} 911060SN/A 921060SN/Atemplate <class Impl> 931060SN/Aconst char * 945336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 951060SN/A{ 964873Sstever@eecs.umich.edu return "FullO3CPU tick"; 971060SN/A} 981060SN/A 991060SN/Atemplate <class Impl> 1002829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 1015606Snate@binkert.org : Event(CPU_Switch_Pri) 1022829Sksewell@umich.edu{ 1032829Sksewell@umich.edu} 1042829Sksewell@umich.edu 1052829Sksewell@umich.edutemplate <class Impl> 1062829Sksewell@umich.eduvoid 1072829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1082829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1092829Sksewell@umich.edu{ 1102829Sksewell@umich.edu tid = thread_num; 1112829Sksewell@umich.edu cpu = thread_cpu; 1122829Sksewell@umich.edu} 1132829Sksewell@umich.edu 1142829Sksewell@umich.edutemplate <class Impl> 1152829Sksewell@umich.eduvoid 1162829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1172829Sksewell@umich.edu{ 1182829Sksewell@umich.edu cpu->activateThread(tid); 1192829Sksewell@umich.edu} 1202829Sksewell@umich.edu 1212829Sksewell@umich.edutemplate <class Impl> 1222829Sksewell@umich.educonst char * 1235336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1242829Sksewell@umich.edu{ 1254873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1262829Sksewell@umich.edu} 1272829Sksewell@umich.edu 1282829Sksewell@umich.edutemplate <class Impl> 1292875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1305606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1312875Sksewell@umich.edu{ 1322875Sksewell@umich.edu} 1332875Sksewell@umich.edu 1342875Sksewell@umich.edutemplate <class Impl> 1352875Sksewell@umich.eduvoid 1362875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1373859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1382875Sksewell@umich.edu{ 1392875Sksewell@umich.edu tid = thread_num; 1402875Sksewell@umich.edu cpu = thread_cpu; 1413859Sbinkertn@umich.edu remove = false; 1422875Sksewell@umich.edu} 1432875Sksewell@umich.edu 1442875Sksewell@umich.edutemplate <class Impl> 1452875Sksewell@umich.eduvoid 1462875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1472875Sksewell@umich.edu{ 1482875Sksewell@umich.edu cpu->deactivateThread(tid); 1493221Sktlim@umich.edu if (remove) 1503221Sktlim@umich.edu cpu->removeThread(tid); 1512875Sksewell@umich.edu} 1522875Sksewell@umich.edu 1532875Sksewell@umich.edutemplate <class Impl> 1542875Sksewell@umich.educonst char * 1555336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 1562875Sksewell@umich.edu{ 1574873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 1582875Sksewell@umich.edu} 1592875Sksewell@umich.edu 1602875Sksewell@umich.edutemplate <class Impl> 1615595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1622733Sktlim@umich.edu : BaseO3CPU(params), 1633781Sgblack@eecs.umich.edu itb(params->itb), 1643781Sgblack@eecs.umich.edu dtb(params->dtb), 1651060SN/A tickEvent(this), 1665737Scws3k@cs.virginia.edu#ifndef NDEBUG 1675737Scws3k@cs.virginia.edu instcount(0), 1685737Scws3k@cs.virginia.edu#endif 1692292SN/A removeInstsThisCycle(false), 1705595Sgblack@eecs.umich.edu fetch(this, params), 1715595Sgblack@eecs.umich.edu decode(this, params), 1725595Sgblack@eecs.umich.edu rename(this, params), 1735595Sgblack@eecs.umich.edu iew(this, params), 1745595Sgblack@eecs.umich.edu commit(this, params), 1751060SN/A 1765595Sgblack@eecs.umich.edu regFile(this, params->numPhysIntRegs, 1774329Sktlim@umich.edu params->numPhysFloatRegs), 1781060SN/A 1795529Snate@binkert.org freeList(params->numThreads, 1802292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1812292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1821060SN/A 1835595Sgblack@eecs.umich.edu rob(this, 1844329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 1852292SN/A params->smtROBPolicy, params->smtROBThreshold, 1865529Snate@binkert.org params->numThreads), 1871060SN/A 1885529Snate@binkert.org scoreboard(params->numThreads, 1892292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1902292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1916221Snate@binkert.org TheISA::NumMiscRegs * numThreads, 1922292SN/A TheISA::ZeroReg), 1931060SN/A 1942873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1952873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1962873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1972873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1982873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1995804Snate@binkert.org activityRec(name(), NumStages, 2002873Sktlim@umich.edu params->backComSize + params->forwardComSize, 2012873Sktlim@umich.edu params->activity), 2021060SN/A 2031060SN/A globalSeqNum(1), 2042292SN/A system(params->system), 2052843Sktlim@umich.edu drainCount(0), 2066221Snate@binkert.org deferRegistration(params->defer_registration) 2071060SN/A{ 2083221Sktlim@umich.edu if (!deferRegistration) { 2093221Sktlim@umich.edu _status = Running; 2103221Sktlim@umich.edu } else { 2113221Sktlim@umich.edu _status = Idle; 2123221Sktlim@umich.edu } 2131681SN/A 2144598Sbinkertn@umich.edu#if USE_CHECKER 2152794Sktlim@umich.edu if (params->checker) { 2162316SN/A BaseCPU *temp_checker = params->checker; 2172316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2182316SN/A checker->setSystem(params->system); 2194598Sbinkertn@umich.edu } else { 2204598Sbinkertn@umich.edu checker = NULL; 2214598Sbinkertn@umich.edu } 2222794Sktlim@umich.edu#endif // USE_CHECKER 2232316SN/A 2248793Sgblack@eecs.umich.edu if (!FullSystem) { 2258793Sgblack@eecs.umich.edu thread.resize(numThreads); 2268793Sgblack@eecs.umich.edu tids.resize(numThreads); 2278793Sgblack@eecs.umich.edu } 2281681SN/A 2292325SN/A // The stages also need their CPU pointer setup. However this 2302325SN/A // must be done at the upper level CPU because they have pointers 2312325SN/A // to the upper level CPU, and not this FullO3CPU. 2321060SN/A 2332292SN/A // Set up Pointers to the activeThreads list for each stage 2342292SN/A fetch.setActiveThreads(&activeThreads); 2352292SN/A decode.setActiveThreads(&activeThreads); 2362292SN/A rename.setActiveThreads(&activeThreads); 2372292SN/A iew.setActiveThreads(&activeThreads); 2382292SN/A commit.setActiveThreads(&activeThreads); 2391060SN/A 2401060SN/A // Give each of the stages the time buffer they will use. 2411060SN/A fetch.setTimeBuffer(&timeBuffer); 2421060SN/A decode.setTimeBuffer(&timeBuffer); 2431060SN/A rename.setTimeBuffer(&timeBuffer); 2441060SN/A iew.setTimeBuffer(&timeBuffer); 2451060SN/A commit.setTimeBuffer(&timeBuffer); 2461060SN/A 2471060SN/A // Also setup each of the stages' queues. 2481060SN/A fetch.setFetchQueue(&fetchQueue); 2491060SN/A decode.setFetchQueue(&fetchQueue); 2502292SN/A commit.setFetchQueue(&fetchQueue); 2511060SN/A decode.setDecodeQueue(&decodeQueue); 2521060SN/A rename.setDecodeQueue(&decodeQueue); 2531060SN/A rename.setRenameQueue(&renameQueue); 2541060SN/A iew.setRenameQueue(&renameQueue); 2551060SN/A iew.setIEWQueue(&iewQueue); 2561060SN/A commit.setIEWQueue(&iewQueue); 2571060SN/A commit.setRenameQueue(&renameQueue); 2581060SN/A 2592292SN/A commit.setIEWStage(&iew); 2602292SN/A rename.setIEWStage(&iew); 2612292SN/A rename.setCommitStage(&commit); 2622292SN/A 2638793Sgblack@eecs.umich.edu ThreadID active_threads; 2648793Sgblack@eecs.umich.edu if (FullSystem) { 2658793Sgblack@eecs.umich.edu active_threads = 1; 2668793Sgblack@eecs.umich.edu } else { 2678793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 2682831Sksewell@umich.edu 2698793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 2708793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 2718793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 2728793Sgblack@eecs.umich.edu "or edit your workload size."); 2738793Sgblack@eecs.umich.edu } 2742831Sksewell@umich.edu } 2752292SN/A 2762316SN/A //Make Sure That this a Valid Architeture 2772292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2782292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2792292SN/A 2802292SN/A rename.setScoreboard(&scoreboard); 2812292SN/A iew.setScoreboard(&scoreboard); 2822292SN/A 2831060SN/A // Setup the rename map for whichever stages need it. 2842292SN/A PhysRegIndex lreg_idx = 0; 2852292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2861060SN/A 2876221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2882307SN/A bool bindRegs = (tid <= active_threads - 1); 2892292SN/A 2902292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2912292SN/A params->numPhysIntRegs, 2922325SN/A lreg_idx, //Index for Logical. Regs 2932292SN/A 2942292SN/A TheISA::NumFloatRegs, 2952292SN/A params->numPhysFloatRegs, 2962325SN/A freg_idx, //Index for Float Regs 2972292SN/A 2982292SN/A TheISA::NumMiscRegs, 2992292SN/A 3002292SN/A TheISA::ZeroReg, 3012292SN/A TheISA::ZeroReg, 3022292SN/A 3032292SN/A tid, 3042292SN/A false); 3052292SN/A 3062292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3072292SN/A params->numPhysIntRegs, 3082325SN/A lreg_idx, //Index for Logical. Regs 3092292SN/A 3102292SN/A TheISA::NumFloatRegs, 3112292SN/A params->numPhysFloatRegs, 3122325SN/A freg_idx, //Index for Float Regs 3132292SN/A 3142292SN/A TheISA::NumMiscRegs, 3152292SN/A 3162292SN/A TheISA::ZeroReg, 3172292SN/A TheISA::ZeroReg, 3182292SN/A 3192292SN/A tid, 3202292SN/A bindRegs); 3213221Sktlim@umich.edu 3223221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3233221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3242292SN/A } 3252292SN/A 3262292SN/A rename.setRenameMap(renameMap); 3272292SN/A commit.setRenameMap(commitRenameMap); 3282292SN/A 3292292SN/A // Give renameMap & rename stage access to the freeList; 3306221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3316221Snate@binkert.org renameMap[tid].setFreeList(&freeList); 3321060SN/A rename.setFreeList(&freeList); 3332292SN/A 3341060SN/A // Setup the ROB for whichever stages need it. 3351060SN/A commit.setROB(&rob); 3362292SN/A 3377823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 3382292SN/A 3392829Sksewell@umich.edu lastActivatedCycle = -1; 3406221Snate@binkert.org#if 0 3413093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3426221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3436221Snate@binkert.org globalSeqNum[tid] = 1; 3446221Snate@binkert.org#endif 3453093Sksewell@umich.edu 3462292SN/A contextSwitch = false; 3475595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3485595Sgblack@eecs.umich.edu 3495595Sgblack@eecs.umich.edu // Setup any thread state. 3505595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3515595Sgblack@eecs.umich.edu 3526221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 3538793Sgblack@eecs.umich.edu if (FullSystem) { 3548793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3558793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3568793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 3578793Sgblack@eecs.umich.edu } else { 3588793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 3598793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3608793Sgblack@eecs.umich.edu tid, this->thread[tid]); 3618793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3628793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3638793Sgblack@eecs.umich.edu tid, params->workload[tid]); 3645595Sgblack@eecs.umich.edu 3658793Sgblack@eecs.umich.edu //usedTids[tid] = true; 3668793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 3678793Sgblack@eecs.umich.edu } else { 3688793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3698793Sgblack@eecs.umich.edu //when scheduling threads to CPU 3708793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3715595Sgblack@eecs.umich.edu 3728793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3738793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3748793Sgblack@eecs.umich.edu tid, dummy_proc); 3758793Sgblack@eecs.umich.edu //usedTids[tid] = false; 3768793Sgblack@eecs.umich.edu } 3775595Sgblack@eecs.umich.edu } 3785595Sgblack@eecs.umich.edu 3795595Sgblack@eecs.umich.edu ThreadContext *tc; 3805595Sgblack@eecs.umich.edu 3815595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3825595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3835595Sgblack@eecs.umich.edu 3845595Sgblack@eecs.umich.edu tc = o3_tc; 3855595Sgblack@eecs.umich.edu 3865595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3875595Sgblack@eecs.umich.edu // CheckerThreadContext. 3885595Sgblack@eecs.umich.edu#if USE_CHECKER 3895595Sgblack@eecs.umich.edu if (params->checker) { 3905595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3915595Sgblack@eecs.umich.edu o3_tc, this->checker); 3925595Sgblack@eecs.umich.edu } 3935595Sgblack@eecs.umich.edu#endif 3945595Sgblack@eecs.umich.edu 3955595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 3965595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 3976221Snate@binkert.org o3_tc->thread = this->thread[tid]; 3985595Sgblack@eecs.umich.edu 3998793Sgblack@eecs.umich.edu if (FullSystem) { 4008793Sgblack@eecs.umich.edu // Setup quiesce event. 4018793Sgblack@eecs.umich.edu this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 4028793Sgblack@eecs.umich.edu } 4035595Sgblack@eecs.umich.edu // Give the thread the TC. 4046221Snate@binkert.org this->thread[tid]->tc = tc; 4055595Sgblack@eecs.umich.edu 4065595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4075595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4085595Sgblack@eecs.umich.edu } 4095595Sgblack@eecs.umich.edu 4106221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4116221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4125595Sgblack@eecs.umich.edu 4135595Sgblack@eecs.umich.edu lockAddr = 0; 4145595Sgblack@eecs.umich.edu lockFlag = false; 4151060SN/A} 4161060SN/A 4171060SN/Atemplate <class Impl> 4181755SN/AFullO3CPU<Impl>::~FullO3CPU() 4191060SN/A{ 4201060SN/A} 4211060SN/A 4221060SN/Atemplate <class Impl> 4231060SN/Avoid 4245595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4251062SN/A{ 4262733Sktlim@umich.edu BaseO3CPU::regStats(); 4272292SN/A 4282733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4292292SN/A timesIdled 4302292SN/A .name(name() + ".timesIdled") 4312292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4322292SN/A " unscheduled itself") 4332292SN/A .prereq(timesIdled); 4342292SN/A 4352292SN/A idleCycles 4362292SN/A .name(name() + ".idleCycles") 4372292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4382292SN/A "to idling") 4392292SN/A .prereq(idleCycles); 4402292SN/A 4412292SN/A // Number of Instructions simulated 4422292SN/A // -------------------------------- 4432292SN/A // Should probably be in Base CPU but need templated 4442292SN/A // MaxThreads so put in here instead 4452292SN/A committedInsts 4462292SN/A .init(numThreads) 4472292SN/A .name(name() + ".committedInsts") 4482292SN/A .desc("Number of Instructions Simulated"); 4492292SN/A 4502292SN/A totalCommittedInsts 4512292SN/A .name(name() + ".committedInsts_total") 4522292SN/A .desc("Number of Instructions Simulated"); 4532292SN/A 4542292SN/A cpi 4552292SN/A .name(name() + ".cpi") 4562292SN/A .desc("CPI: Cycles Per Instruction") 4572292SN/A .precision(6); 4584392Sktlim@umich.edu cpi = numCycles / committedInsts; 4592292SN/A 4602292SN/A totalCpi 4612292SN/A .name(name() + ".cpi_total") 4622292SN/A .desc("CPI: Total CPI of All Threads") 4632292SN/A .precision(6); 4644392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 4652292SN/A 4662292SN/A ipc 4672292SN/A .name(name() + ".ipc") 4682292SN/A .desc("IPC: Instructions Per Cycle") 4692292SN/A .precision(6); 4704392Sktlim@umich.edu ipc = committedInsts / numCycles; 4712292SN/A 4722292SN/A totalIpc 4732292SN/A .name(name() + ".ipc_total") 4742292SN/A .desc("IPC: Total IPC of All Threads") 4752292SN/A .precision(6); 4764392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 4772292SN/A 4785595Sgblack@eecs.umich.edu this->fetch.regStats(); 4795595Sgblack@eecs.umich.edu this->decode.regStats(); 4805595Sgblack@eecs.umich.edu this->rename.regStats(); 4815595Sgblack@eecs.umich.edu this->iew.regStats(); 4825595Sgblack@eecs.umich.edu this->commit.regStats(); 4837897Shestness@cs.utexas.edu this->rob.regStats(); 4847897Shestness@cs.utexas.edu 4857897Shestness@cs.utexas.edu intRegfileReads 4867897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 4877897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 4887897Shestness@cs.utexas.edu .prereq(intRegfileReads); 4897897Shestness@cs.utexas.edu 4907897Shestness@cs.utexas.edu intRegfileWrites 4917897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 4927897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 4937897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 4947897Shestness@cs.utexas.edu 4957897Shestness@cs.utexas.edu fpRegfileReads 4967897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 4977897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 4987897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 4997897Shestness@cs.utexas.edu 5007897Shestness@cs.utexas.edu fpRegfileWrites 5017897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5027897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5037897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5047897Shestness@cs.utexas.edu 5057897Shestness@cs.utexas.edu miscRegfileReads 5067897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5077897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5087897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5097897Shestness@cs.utexas.edu 5107897Shestness@cs.utexas.edu miscRegfileWrites 5117897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5127897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5137897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5141062SN/A} 5151062SN/A 5161062SN/Atemplate <class Impl> 5172871Sktlim@umich.eduPort * 5182871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 5192871Sktlim@umich.edu{ 5202871Sktlim@umich.edu if (if_name == "dcache_port") 5212871Sktlim@umich.edu return iew.getDcachePort(); 5222871Sktlim@umich.edu else if (if_name == "icache_port") 5232871Sktlim@umich.edu return fetch.getIcachePort(); 5242871Sktlim@umich.edu else 5252871Sktlim@umich.edu panic("No Such Port\n"); 5262871Sktlim@umich.edu} 5272871Sktlim@umich.edu 5282871Sktlim@umich.edutemplate <class Impl> 5291062SN/Avoid 5301755SN/AFullO3CPU<Impl>::tick() 5311060SN/A{ 5322733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5331060SN/A 5342292SN/A ++numCycles; 5352292SN/A 5362325SN/A// activity = false; 5372292SN/A 5382292SN/A //Tick each of the stages 5391060SN/A fetch.tick(); 5401060SN/A 5411060SN/A decode.tick(); 5421060SN/A 5431060SN/A rename.tick(); 5441060SN/A 5451060SN/A iew.tick(); 5461060SN/A 5471060SN/A commit.tick(); 5481060SN/A 5498793Sgblack@eecs.umich.edu if (!FullSystem) 5508793Sgblack@eecs.umich.edu doContextSwitch(); 5512292SN/A 5522292SN/A // Now advance the time buffers 5531060SN/A timeBuffer.advance(); 5541060SN/A 5551060SN/A fetchQueue.advance(); 5561060SN/A decodeQueue.advance(); 5571060SN/A renameQueue.advance(); 5581060SN/A iewQueue.advance(); 5591060SN/A 5602325SN/A activityRec.advance(); 5612292SN/A 5622292SN/A if (removeInstsThisCycle) { 5632292SN/A cleanUpRemovedInsts(); 5642292SN/A } 5652292SN/A 5662325SN/A if (!tickEvent.scheduled()) { 5672867Sktlim@umich.edu if (_status == SwitchedOut || 5682905Sktlim@umich.edu getState() == SimObject::Drained) { 5693226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 5702325SN/A // increment stat 5717823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 5723221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 5733226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 5747823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 5752325SN/A timesIdled++; 5762325SN/A } else { 5777823Ssteve.reinhardt@amd.com schedule(tickEvent, nextCycle(curTick() + ticks(1))); 5783226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 5792325SN/A } 5802292SN/A } 5812292SN/A 5828793Sgblack@eecs.umich.edu if (!FullSystem) 5838793Sgblack@eecs.umich.edu updateThreadPriority(); 5841060SN/A} 5851060SN/A 5861060SN/Atemplate <class Impl> 5871060SN/Avoid 5881755SN/AFullO3CPU<Impl>::init() 5891060SN/A{ 5905714Shsul@eecs.umich.edu BaseCPU::init(); 5911060SN/A 5922292SN/A // Set inSyscall so that the CPU doesn't squash when initially 5932292SN/A // setting up registers. 5946221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 5956221Snate@binkert.org thread[tid]->inSyscall = true; 5962292SN/A 5978793Sgblack@eecs.umich.edu if (FullSystem) { 5988793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 5998793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6008793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6018793Sgblack@eecs.umich.edu } 6026034Ssteve.reinhardt@amd.com } 6032292SN/A 6042292SN/A // Clear inSyscall. 6056221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6066221Snate@binkert.org thread[tid]->inSyscall = false; 6072292SN/A 6082316SN/A // Initialize stages. 6092292SN/A fetch.initStage(); 6102292SN/A iew.initStage(); 6112292SN/A rename.initStage(); 6122292SN/A commit.initStage(); 6132292SN/A 6142292SN/A commit.setThreads(thread); 6152292SN/A} 6162292SN/A 6172292SN/Atemplate <class Impl> 6182292SN/Avoid 6196221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6202875Sksewell@umich.edu{ 6216221Snate@binkert.org list<ThreadID>::iterator isActive = 6225314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6232875Sksewell@umich.edu 6243226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6253226Sktlim@umich.edu 6262875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6272875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6282875Sksewell@umich.edu tid); 6292875Sksewell@umich.edu 6302875Sksewell@umich.edu activeThreads.push_back(tid); 6312875Sksewell@umich.edu } 6322875Sksewell@umich.edu} 6332875Sksewell@umich.edu 6342875Sksewell@umich.edutemplate <class Impl> 6352875Sksewell@umich.eduvoid 6366221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 6372875Sksewell@umich.edu{ 6382875Sksewell@umich.edu //Remove From Active List, if Active 6396221Snate@binkert.org list<ThreadID>::iterator thread_it = 6405314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6412875Sksewell@umich.edu 6423226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 6433226Sktlim@umich.edu 6442875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6452875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6462875Sksewell@umich.edu tid); 6472875Sksewell@umich.edu activeThreads.erase(thread_it); 6482875Sksewell@umich.edu } 6492875Sksewell@umich.edu} 6502875Sksewell@umich.edu 6512875Sksewell@umich.edutemplate <class Impl> 6526221Snate@binkert.orgCounter 6536221Snate@binkert.orgFullO3CPU<Impl>::totalInstructions() const 6546221Snate@binkert.org{ 6556221Snate@binkert.org Counter total(0); 6566221Snate@binkert.org 6576221Snate@binkert.org ThreadID size = thread.size(); 6586221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 6596221Snate@binkert.org total += thread[i]->numInst; 6606221Snate@binkert.org 6616221Snate@binkert.org return total; 6626221Snate@binkert.org} 6636221Snate@binkert.org 6646221Snate@binkert.orgtemplate <class Impl> 6652875Sksewell@umich.eduvoid 6666221Snate@binkert.orgFullO3CPU<Impl>::activateContext(ThreadID tid, int delay) 6672875Sksewell@umich.edu{ 6682875Sksewell@umich.edu // Needs to set each stage to running as well. 6692875Sksewell@umich.edu if (delay){ 6702875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 6717823Ssteve.reinhardt@amd.com "on cycle %d\n", tid, curTick() + ticks(delay)); 6722875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 6732875Sksewell@umich.edu } else { 6742875Sksewell@umich.edu activateThread(tid); 6752875Sksewell@umich.edu } 6762875Sksewell@umich.edu 6777823Ssteve.reinhardt@amd.com if (lastActivatedCycle < curTick()) { 6782875Sksewell@umich.edu scheduleTickEvent(delay); 6792875Sksewell@umich.edu 6802875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 6812875Sksewell@umich.edu // deschedule itself. 6822875Sksewell@umich.edu activityRec.activity(); 6832875Sksewell@umich.edu fetch.wakeFromQuiesce(); 6842875Sksewell@umich.edu 6857823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 6862875Sksewell@umich.edu 6872875Sksewell@umich.edu _status = Running; 6882875Sksewell@umich.edu } 6892875Sksewell@umich.edu} 6902875Sksewell@umich.edu 6912875Sksewell@umich.edutemplate <class Impl> 6923221Sktlim@umich.edubool 6936221Snate@binkert.orgFullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay) 6942875Sksewell@umich.edu{ 6952875Sksewell@umich.edu // Schedule removal of thread data from CPU 6962875Sksewell@umich.edu if (delay){ 6972875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 6987823Ssteve.reinhardt@amd.com "on cycle %d\n", tid, curTick() + ticks(delay)); 6993221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 7003221Sktlim@umich.edu return false; 7012875Sksewell@umich.edu } else { 7022875Sksewell@umich.edu deactivateThread(tid); 7033221Sktlim@umich.edu if (remove) 7043221Sktlim@umich.edu removeThread(tid); 7053221Sktlim@umich.edu return true; 7062875Sksewell@umich.edu } 7072875Sksewell@umich.edu} 7082875Sksewell@umich.edu 7092875Sksewell@umich.edutemplate <class Impl> 7102875Sksewell@umich.eduvoid 7116221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 7122875Sksewell@umich.edu{ 7132875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7143221Sktlim@umich.edu bool deallocated = deallocateContext(tid, false, 1); 7153221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 7165570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 7173859Sbinkertn@umich.edu activeThreads.size() == 0) 7182910Sksewell@umich.edu unscheduleTickEvent(); 7192875Sksewell@umich.edu _status = Idle; 7202875Sksewell@umich.edu} 7212875Sksewell@umich.edu 7222875Sksewell@umich.edutemplate <class Impl> 7232875Sksewell@umich.eduvoid 7246221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 7252875Sksewell@umich.edu{ 7262910Sksewell@umich.edu //For now, this is the same as deallocate 7272910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 7283221Sktlim@umich.edu deallocateContext(tid, true, 1); 7292875Sksewell@umich.edu} 7302875Sksewell@umich.edu 7312875Sksewell@umich.edutemplate <class Impl> 7322875Sksewell@umich.eduvoid 7336221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 7342292SN/A{ 7352847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 7362292SN/A // Will change now that the PC and thread state is internal to the CPU 7372683Sktlim@umich.edu // and not in the ThreadContext. 7388793Sgblack@eecs.umich.edu ThreadContext *src_tc; 7398793Sgblack@eecs.umich.edu if (FullSystem) 7408793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 7418793Sgblack@eecs.umich.edu else 7428793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 7432292SN/A 7442292SN/A //Bind Int Regs to Rename Map 7452292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7462292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 7472292SN/A 7482292SN/A renameMap[tid].setEntry(ireg,phys_reg); 7492292SN/A scoreboard.setReg(phys_reg); 7502292SN/A } 7512292SN/A 7522292SN/A //Bind Float Regs to Rename Map 7532292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 7542292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 7552292SN/A 7562292SN/A renameMap[tid].setEntry(freg,phys_reg); 7572292SN/A scoreboard.setReg(phys_reg); 7582292SN/A } 7592292SN/A 7602292SN/A //Copy Thread Data Into RegFile 7612847Sksewell@umich.edu //this->copyFromTC(tid); 7622292SN/A 7632847Sksewell@umich.edu //Set PC/NPC/NNPC 7647720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 7652292SN/A 7662680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 7672292SN/A 7682292SN/A activateContext(tid,1); 7692292SN/A 7702292SN/A //Reset ROB/IQ/LSQ Entries 7712292SN/A commit.rob->resetEntries(); 7722292SN/A iew.resetEntries(); 7732292SN/A} 7742292SN/A 7752292SN/Atemplate <class Impl> 7762292SN/Avoid 7776221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 7782292SN/A{ 7792877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 7802847Sksewell@umich.edu 7812847Sksewell@umich.edu // Copy Thread Data From RegFile 7822847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 7835364Sksewell@umich.edu // this->copyToTC(tid); 7845364Sksewell@umich.edu 7855364Sksewell@umich.edu 7865364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 7875364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 7885364Sksewell@umich.edu // in SMT workloads. 7892847Sksewell@umich.edu 7902847Sksewell@umich.edu // Unbind Int Regs from Rename Map 7912292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7922292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 7932292SN/A 7942292SN/A scoreboard.unsetReg(phys_reg); 7952292SN/A freeList.addReg(phys_reg); 7962292SN/A } 7972292SN/A 7982847Sksewell@umich.edu // Unbind Float Regs from Rename Map 7995362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 8002292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 8012292SN/A 8022292SN/A scoreboard.unsetReg(phys_reg); 8032292SN/A freeList.addReg(phys_reg); 8042292SN/A } 8052292SN/A 8062847Sksewell@umich.edu // Squash Throughout Pipeline 8078138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 8088138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 8098138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 8102292SN/A decode.squash(tid); 8112935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 8122875Sksewell@umich.edu iew.squash(tid); 8135363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 8142935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 8152292SN/A 8165362Sksewell@umich.edu 8175362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 8182292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 8192292SN/A 8202847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 8213229Sktlim@umich.edu 8223229Sktlim@umich.edu // Commented out for now. This should be possible to do by 8233229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 8243229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 8253229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 8263229Sktlim@umich.edu/* 8272292SN/A if (activeThreads.size() >= 1) { 8282292SN/A commit.rob->resetEntries(); 8292292SN/A iew.resetEntries(); 8302292SN/A } 8313229Sktlim@umich.edu*/ 8322292SN/A} 8332292SN/A 8342292SN/A 8352292SN/Atemplate <class Impl> 8362292SN/Avoid 8376221Snate@binkert.orgFullO3CPU<Impl>::activateWhenReady(ThreadID tid) 8382292SN/A{ 8392733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 8402292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 8412292SN/A tid); 8422292SN/A 8432292SN/A bool ready = true; 8442292SN/A 8452292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 8462733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8472292SN/A "Phys. Int. Regs.\n", 8482292SN/A tid); 8492292SN/A ready = false; 8502292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 8512733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8522292SN/A "Phys. Float. Regs.\n", 8532292SN/A tid); 8542292SN/A ready = false; 8552292SN/A } else if (commit.rob->numFreeEntries() >= 8562292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 8572733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8582292SN/A "ROB entries.\n", 8592292SN/A tid); 8602292SN/A ready = false; 8612292SN/A } else if (iew.instQueue.numFreeEntries() >= 8622292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 8632733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8642292SN/A "IQ entries.\n", 8652292SN/A tid); 8662292SN/A ready = false; 8672292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 8682292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 8692733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8702292SN/A "LSQ entries.\n", 8712292SN/A tid); 8722292SN/A ready = false; 8732292SN/A } 8742292SN/A 8752292SN/A if (ready) { 8762292SN/A insertThread(tid); 8772292SN/A 8782292SN/A contextSwitch = false; 8792292SN/A 8802292SN/A cpuWaitList.remove(tid); 8812292SN/A } else { 8822292SN/A suspendContext(tid); 8832292SN/A 8842292SN/A //blocks fetch 8852292SN/A contextSwitch = true; 8862292SN/A 8872875Sksewell@umich.edu //@todo: dont always add to waitlist 8882292SN/A //do waitlist 8892292SN/A cpuWaitList.push_back(tid); 8901060SN/A } 8911060SN/A} 8921060SN/A 8934192Sktlim@umich.edutemplate <class Impl> 8945595Sgblack@eecs.umich.eduFault 8956221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 8965702Ssaidi@eecs.umich.edu{ 8975702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 8985702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 8995702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 9005702Ssaidi@eecs.umich.edu 9015702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 9025702Ssaidi@eecs.umich.edu 9035702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9045702Ssaidi@eecs.umich.edu#endif 9055702Ssaidi@eecs.umich.edu return NoFault; 9065702Ssaidi@eecs.umich.edu} 9075702Ssaidi@eecs.umich.edu 9085702Ssaidi@eecs.umich.edutemplate <class Impl> 9095702Ssaidi@eecs.umich.edubool 9106221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 9115702Ssaidi@eecs.umich.edu{ 9125702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9135702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 9145702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 9155702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 9165702Ssaidi@eecs.umich.edu 9175702Ssaidi@eecs.umich.edu switch (palFunc) { 9185702Ssaidi@eecs.umich.edu case PAL::halt: 9195702Ssaidi@eecs.umich.edu halt(); 9205702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 9215702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 9225702Ssaidi@eecs.umich.edu break; 9235702Ssaidi@eecs.umich.edu 9245702Ssaidi@eecs.umich.edu case PAL::bpt: 9255702Ssaidi@eecs.umich.edu case PAL::bugchk: 9265702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 9275702Ssaidi@eecs.umich.edu return false; 9285702Ssaidi@eecs.umich.edu break; 9295702Ssaidi@eecs.umich.edu } 9305702Ssaidi@eecs.umich.edu#endif 9315702Ssaidi@eecs.umich.edu return true; 9325702Ssaidi@eecs.umich.edu} 9335702Ssaidi@eecs.umich.edu 9345702Ssaidi@eecs.umich.edutemplate <class Impl> 9355702Ssaidi@eecs.umich.eduFault 9365595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 9375595Sgblack@eecs.umich.edu{ 9385595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 9395647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 9405595Sgblack@eecs.umich.edu} 9415595Sgblack@eecs.umich.edu 9425595Sgblack@eecs.umich.edutemplate <class Impl> 9435595Sgblack@eecs.umich.eduvoid 9445595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 9455595Sgblack@eecs.umich.edu{ 9465595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 9475595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 9485595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9495595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9505595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9515595Sgblack@eecs.umich.edu 9525595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 9535647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 9545595Sgblack@eecs.umich.edu 9555595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 9567684Sgblack@eecs.umich.edu this->trap(interrupt, 0, NULL); 9575595Sgblack@eecs.umich.edu} 9585595Sgblack@eecs.umich.edu 9595595Sgblack@eecs.umich.edutemplate <class Impl> 9605595Sgblack@eecs.umich.eduvoid 9614192Sktlim@umich.eduFullO3CPU<Impl>::updateMemPorts() 9624192Sktlim@umich.edu{ 9634192Sktlim@umich.edu // Update all ThreadContext's memory ports (Functional/Virtual 9644192Sktlim@umich.edu // Ports) 9656221Snate@binkert.org ThreadID size = thread.size(); 9666221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) 9675497Ssaidi@eecs.umich.edu thread[i]->connectMemPorts(thread[i]->getTC()); 9684192Sktlim@umich.edu} 9694192Sktlim@umich.edu 9701060SN/Atemplate <class Impl> 9712852Sktlim@umich.eduvoid 9727684Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) 9735595Sgblack@eecs.umich.edu{ 9745595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 9757684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 9765595Sgblack@eecs.umich.edu} 9775595Sgblack@eecs.umich.edu 9785595Sgblack@eecs.umich.edutemplate <class Impl> 9795595Sgblack@eecs.umich.eduvoid 9806221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 9815595Sgblack@eecs.umich.edu{ 9825595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 9835595Sgblack@eecs.umich.edu 9845595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 9855595Sgblack@eecs.umich.edu 9865595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 9875595Sgblack@eecs.umich.edu // instruction. 9885595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 9895595Sgblack@eecs.umich.edu 9905595Sgblack@eecs.umich.edu // Execute the actual syscall. 9915595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 9925595Sgblack@eecs.umich.edu 9935595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 9945595Sgblack@eecs.umich.edu // incrementing it. 9955595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 9965595Sgblack@eecs.umich.edu} 9975595Sgblack@eecs.umich.edu 9985595Sgblack@eecs.umich.edutemplate <class Impl> 9995595Sgblack@eecs.umich.eduvoid 10002864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 10012864Sktlim@umich.edu{ 10022918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 10032918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 10042864Sktlim@umich.edu BaseCPU::serialize(os); 10052864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 10062864Sktlim@umich.edu tickEvent.serialize(os); 10072864Sktlim@umich.edu 10082864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10092864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 10102864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10112864Sktlim@umich.edu static SimpleThread temp; 10122864Sktlim@umich.edu 10136221Snate@binkert.org ThreadID size = thread.size(); 10146221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 10152864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 10162864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10172864Sktlim@umich.edu temp.serialize(os); 10182864Sktlim@umich.edu } 10192864Sktlim@umich.edu} 10202864Sktlim@umich.edu 10212864Sktlim@umich.edutemplate <class Impl> 10222864Sktlim@umich.eduvoid 10232864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 10242864Sktlim@umich.edu{ 10252918Sktlim@umich.edu SimObject::State so_state; 10262918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 10272864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 10282864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 10292864Sktlim@umich.edu 10302864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10312864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 10322864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10332864Sktlim@umich.edu static SimpleThread temp; 10342864Sktlim@umich.edu 10356221Snate@binkert.org ThreadID size = thread.size(); 10366221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 10372864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10382864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 10392864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 10402864Sktlim@umich.edu } 10412864Sktlim@umich.edu} 10422864Sktlim@umich.edu 10432864Sktlim@umich.edutemplate <class Impl> 10442905Sktlim@umich.eduunsigned int 10452843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 10461060SN/A{ 10473125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 10483512Sktlim@umich.edu 10493512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 10503512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 10513512Sktlim@umich.edu return 0; 10523512Sktlim@umich.edu } 10533512Sktlim@umich.edu 10542843Sktlim@umich.edu drainCount = 0; 10552843Sktlim@umich.edu fetch.drain(); 10562843Sktlim@umich.edu decode.drain(); 10572843Sktlim@umich.edu rename.drain(); 10582843Sktlim@umich.edu iew.drain(); 10592843Sktlim@umich.edu commit.drain(); 10602325SN/A 10612325SN/A // Wake the CPU and record activity so everything can drain out if 10622863Sktlim@umich.edu // the CPU was not able to immediately drain. 10632905Sktlim@umich.edu if (getState() != SimObject::Drained) { 10642864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 10652864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 10662864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 10672864Sktlim@umich.edu // process on the drain event. 10682864Sktlim@umich.edu drainEvent = drain_event; 10692843Sktlim@umich.edu 10702863Sktlim@umich.edu wakeCPU(); 10712863Sktlim@umich.edu activityRec.activity(); 10722852Sktlim@umich.edu 10732905Sktlim@umich.edu return 1; 10742863Sktlim@umich.edu } else { 10752905Sktlim@umich.edu return 0; 10762863Sktlim@umich.edu } 10772316SN/A} 10782310SN/A 10792316SN/Atemplate <class Impl> 10802316SN/Avoid 10812843Sktlim@umich.eduFullO3CPU<Impl>::resume() 10822316SN/A{ 10832843Sktlim@umich.edu fetch.resume(); 10842843Sktlim@umich.edu decode.resume(); 10852843Sktlim@umich.edu rename.resume(); 10862843Sktlim@umich.edu iew.resume(); 10872843Sktlim@umich.edu commit.resume(); 10882316SN/A 10892905Sktlim@umich.edu changeState(SimObject::Running); 10902905Sktlim@umich.edu 10912864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 10922864Sktlim@umich.edu return; 10932864Sktlim@umich.edu 10944762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 10953319Shsul@eecs.umich.edu 10962843Sktlim@umich.edu if (!tickEvent.scheduled()) 10975606Snate@binkert.org schedule(tickEvent, nextCycle()); 10982843Sktlim@umich.edu _status = Running; 10992843Sktlim@umich.edu} 11002316SN/A 11012843Sktlim@umich.edutemplate <class Impl> 11022843Sktlim@umich.eduvoid 11032843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 11042843Sktlim@umich.edu{ 11052843Sktlim@umich.edu if (++drainCount == NumStages) { 11062316SN/A if (tickEvent.scheduled()) 11072316SN/A tickEvent.squash(); 11082863Sktlim@umich.edu 11092905Sktlim@umich.edu changeState(SimObject::Drained); 11102863Sktlim@umich.edu 11113126Sktlim@umich.edu BaseCPU::switchOut(); 11123126Sktlim@umich.edu 11132863Sktlim@umich.edu if (drainEvent) { 11142863Sktlim@umich.edu drainEvent->process(); 11152863Sktlim@umich.edu drainEvent = NULL; 11162863Sktlim@umich.edu } 11172310SN/A } 11182843Sktlim@umich.edu assert(drainCount <= 5); 11192843Sktlim@umich.edu} 11202843Sktlim@umich.edu 11212843Sktlim@umich.edutemplate <class Impl> 11222843Sktlim@umich.eduvoid 11232843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11242843Sktlim@umich.edu{ 11252843Sktlim@umich.edu fetch.switchOut(); 11262843Sktlim@umich.edu rename.switchOut(); 11272325SN/A iew.switchOut(); 11282843Sktlim@umich.edu commit.switchOut(); 11292843Sktlim@umich.edu instList.clear(); 11302843Sktlim@umich.edu while (!removeList.empty()) { 11312843Sktlim@umich.edu removeList.pop(); 11322843Sktlim@umich.edu } 11332843Sktlim@umich.edu 11342843Sktlim@umich.edu _status = SwitchedOut; 11352843Sktlim@umich.edu#if USE_CHECKER 11362843Sktlim@umich.edu if (checker) 11372843Sktlim@umich.edu checker->switchOut(); 11382843Sktlim@umich.edu#endif 11393126Sktlim@umich.edu if (tickEvent.scheduled()) 11403126Sktlim@umich.edu tickEvent.squash(); 11411060SN/A} 11421060SN/A 11431060SN/Atemplate <class Impl> 11441060SN/Avoid 11451755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 11461060SN/A{ 11472325SN/A // Flush out any old data from the time buffers. 11482873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 11492307SN/A timeBuffer.advance(); 11502307SN/A fetchQueue.advance(); 11512307SN/A decodeQueue.advance(); 11522307SN/A renameQueue.advance(); 11532307SN/A iewQueue.advance(); 11542307SN/A } 11552307SN/A 11562325SN/A activityRec.reset(); 11572307SN/A 11584192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 11591060SN/A 11602307SN/A fetch.takeOverFrom(); 11612307SN/A decode.takeOverFrom(); 11622307SN/A rename.takeOverFrom(); 11632307SN/A iew.takeOverFrom(); 11642307SN/A commit.takeOverFrom(); 11652307SN/A 11667507Stjones1@inf.ed.ac.uk assert(!tickEvent.scheduled() || tickEvent.squashed()); 11671060SN/A 11682325SN/A // @todo: Figure out how to properly select the tid to put onto 11692325SN/A // the active threads list. 11706221Snate@binkert.org ThreadID tid = 0; 11712307SN/A 11726221Snate@binkert.org list<ThreadID>::iterator isActive = 11735314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 11742307SN/A 11752307SN/A if (isActive == activeThreads.end()) { 11762325SN/A //May Need to Re-code this if the delay variable is the delay 11772325SN/A //needed for thread to activate 11782733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 11792307SN/A tid); 11802307SN/A 11812307SN/A activeThreads.push_back(tid); 11822307SN/A } 11832307SN/A 11842325SN/A // Set all statuses to active, schedule the CPU's tick event. 11852307SN/A // @todo: Fix up statuses so this is handled properly 11866221Snate@binkert.org ThreadID size = threadContexts.size(); 11876221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 11882680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 11892680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 11901681SN/A _status = Running; 11917507Stjones1@inf.ed.ac.uk reschedule(tickEvent, nextCycle(), true); 11921681SN/A } 11931060SN/A } 11942307SN/A if (!tickEvent.scheduled()) 11955606Snate@binkert.org schedule(tickEvent, nextCycle()); 11961060SN/A} 11971060SN/A 11981060SN/Atemplate <class Impl> 11995595Sgblack@eecs.umich.eduTheISA::MiscReg 12006221Snate@binkert.orgFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 12015595Sgblack@eecs.umich.edu{ 12026313Sgblack@eecs.umich.edu return this->isa[tid].readMiscRegNoEffect(misc_reg); 12035595Sgblack@eecs.umich.edu} 12045595Sgblack@eecs.umich.edu 12055595Sgblack@eecs.umich.edutemplate <class Impl> 12065595Sgblack@eecs.umich.eduTheISA::MiscReg 12076221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 12085595Sgblack@eecs.umich.edu{ 12097897Shestness@cs.utexas.edu miscRegfileReads++; 12106313Sgblack@eecs.umich.edu return this->isa[tid].readMiscReg(misc_reg, tcBase(tid)); 12115595Sgblack@eecs.umich.edu} 12125595Sgblack@eecs.umich.edu 12135595Sgblack@eecs.umich.edutemplate <class Impl> 12145595Sgblack@eecs.umich.eduvoid 12155595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 12166221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12175595Sgblack@eecs.umich.edu{ 12186313Sgblack@eecs.umich.edu this->isa[tid].setMiscRegNoEffect(misc_reg, val); 12195595Sgblack@eecs.umich.edu} 12205595Sgblack@eecs.umich.edu 12215595Sgblack@eecs.umich.edutemplate <class Impl> 12225595Sgblack@eecs.umich.eduvoid 12235595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 12246221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12255595Sgblack@eecs.umich.edu{ 12267897Shestness@cs.utexas.edu miscRegfileWrites++; 12276313Sgblack@eecs.umich.edu this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); 12285595Sgblack@eecs.umich.edu} 12295595Sgblack@eecs.umich.edu 12305595Sgblack@eecs.umich.edutemplate <class Impl> 12311060SN/Auint64_t 12321755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 12331060SN/A{ 12347897Shestness@cs.utexas.edu intRegfileReads++; 12351060SN/A return regFile.readIntReg(reg_idx); 12361060SN/A} 12371060SN/A 12381060SN/Atemplate <class Impl> 12392455SN/AFloatReg 12402455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 12411060SN/A{ 12427897Shestness@cs.utexas.edu fpRegfileReads++; 12432455SN/A return regFile.readFloatReg(reg_idx); 12441060SN/A} 12451060SN/A 12461060SN/Atemplate <class Impl> 12472455SN/AFloatRegBits 12482455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 12492455SN/A{ 12507897Shestness@cs.utexas.edu fpRegfileReads++; 12512455SN/A return regFile.readFloatRegBits(reg_idx); 12521060SN/A} 12531060SN/A 12541060SN/Atemplate <class Impl> 12551060SN/Avoid 12561755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 12571060SN/A{ 12587897Shestness@cs.utexas.edu intRegfileWrites++; 12591060SN/A regFile.setIntReg(reg_idx, val); 12601060SN/A} 12611060SN/A 12621060SN/Atemplate <class Impl> 12631060SN/Avoid 12642455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 12651060SN/A{ 12667897Shestness@cs.utexas.edu fpRegfileWrites++; 12672455SN/A regFile.setFloatReg(reg_idx, val); 12681060SN/A} 12691060SN/A 12701060SN/Atemplate <class Impl> 12711060SN/Avoid 12722455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 12732455SN/A{ 12747897Shestness@cs.utexas.edu fpRegfileWrites++; 12752455SN/A regFile.setFloatRegBits(reg_idx, val); 12761060SN/A} 12771060SN/A 12781060SN/Atemplate <class Impl> 12791060SN/Auint64_t 12806221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 12811060SN/A{ 12827897Shestness@cs.utexas.edu intRegfileReads++; 12832292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 12842292SN/A 12852292SN/A return regFile.readIntReg(phys_reg); 12862292SN/A} 12872292SN/A 12882292SN/Atemplate <class Impl> 12892292SN/Afloat 12906314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 12912292SN/A{ 12927897Shestness@cs.utexas.edu fpRegfileReads++; 12936032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 12942307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 12952292SN/A 12962669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 12972292SN/A} 12982292SN/A 12992292SN/Atemplate <class Impl> 13002292SN/Auint64_t 13016221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 13022292SN/A{ 13037897Shestness@cs.utexas.edu fpRegfileReads++; 13046032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13052307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13062292SN/A 13072669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13081060SN/A} 13091060SN/A 13101060SN/Atemplate <class Impl> 13111060SN/Avoid 13126221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 13131060SN/A{ 13147897Shestness@cs.utexas.edu intRegfileWrites++; 13152292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13162292SN/A 13172292SN/A regFile.setIntReg(phys_reg, val); 13181060SN/A} 13191060SN/A 13201060SN/Atemplate <class Impl> 13211060SN/Avoid 13226314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 13231060SN/A{ 13247897Shestness@cs.utexas.edu fpRegfileWrites++; 13256032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13262918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13272292SN/A 13282669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 13291060SN/A} 13301060SN/A 13311060SN/Atemplate <class Impl> 13321060SN/Avoid 13336221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 13341060SN/A{ 13357897Shestness@cs.utexas.edu fpRegfileWrites++; 13366032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13372918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13381060SN/A 13392669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 13402292SN/A} 13412292SN/A 13422292SN/Atemplate <class Impl> 13437720Sgblack@eecs.umich.eduTheISA::PCState 13447720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 13452292SN/A{ 13467720Sgblack@eecs.umich.edu return commit.pcState(tid); 13471060SN/A} 13481060SN/A 13491060SN/Atemplate <class Impl> 13501060SN/Avoid 13517720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 13521060SN/A{ 13537720Sgblack@eecs.umich.edu commit.pcState(val, tid); 13542292SN/A} 13551060SN/A 13562292SN/Atemplate <class Impl> 13577720Sgblack@eecs.umich.eduAddr 13587720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 13594636Sgblack@eecs.umich.edu{ 13607720Sgblack@eecs.umich.edu return commit.instAddr(tid); 13614636Sgblack@eecs.umich.edu} 13624636Sgblack@eecs.umich.edu 13634636Sgblack@eecs.umich.edutemplate <class Impl> 13647720Sgblack@eecs.umich.eduAddr 13657720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 13664636Sgblack@eecs.umich.edu{ 13677720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 13684636Sgblack@eecs.umich.edu} 13694636Sgblack@eecs.umich.edu 13704636Sgblack@eecs.umich.edutemplate <class Impl> 13717720Sgblack@eecs.umich.eduMicroPC 13727720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 13732292SN/A{ 13747720Sgblack@eecs.umich.edu return commit.microPC(tid); 13754636Sgblack@eecs.umich.edu} 13764636Sgblack@eecs.umich.edu 13774636Sgblack@eecs.umich.edutemplate <class Impl> 13785595Sgblack@eecs.umich.eduvoid 13796221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 13805595Sgblack@eecs.umich.edu{ 13815595Sgblack@eecs.umich.edu this->thread[tid]->inSyscall = true; 13825595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 13835595Sgblack@eecs.umich.edu} 13845595Sgblack@eecs.umich.edu 13855595Sgblack@eecs.umich.edutemplate <class Impl> 13862292SN/Atypename FullO3CPU<Impl>::ListIt 13872292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 13882292SN/A{ 13892292SN/A instList.push_back(inst); 13901060SN/A 13912292SN/A return --(instList.end()); 13922292SN/A} 13931060SN/A 13942292SN/Atemplate <class Impl> 13952292SN/Avoid 13966221Snate@binkert.orgFullO3CPU<Impl>::instDone(ThreadID tid) 13972292SN/A{ 13982292SN/A // Keep an instruction count. 13992292SN/A thread[tid]->numInst++; 14002292SN/A thread[tid]->numInsts++; 14012292SN/A committedInsts[tid]++; 14022292SN/A totalCommittedInsts++; 14037897Shestness@cs.utexas.edu system->totalNumInsts++; 14042292SN/A // Check for instruction-count-based events. 14052292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 14067897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 14072292SN/A} 14082292SN/A 14092292SN/Atemplate <class Impl> 14102292SN/Avoid 14111755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 14121060SN/A{ 14137720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 14142292SN/A "[sn:%lli]\n", 14157720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 14161060SN/A 14172292SN/A removeInstsThisCycle = true; 14181060SN/A 14191060SN/A // Remove the front instruction. 14202292SN/A removeList.push(inst->getInstListIt()); 14211060SN/A} 14221060SN/A 14231060SN/Atemplate <class Impl> 14241060SN/Avoid 14256221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 14261060SN/A{ 14272733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 14282292SN/A " list.\n", tid); 14291060SN/A 14302292SN/A ListIt end_it; 14311060SN/A 14322292SN/A bool rob_empty = false; 14332292SN/A 14342292SN/A if (instList.empty()) { 14352292SN/A return; 14362292SN/A } else if (rob.isEmpty(/*tid*/)) { 14372733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 14382292SN/A end_it = instList.begin(); 14392292SN/A rob_empty = true; 14402292SN/A } else { 14412292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 14422733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 14432292SN/A } 14442292SN/A 14452292SN/A removeInstsThisCycle = true; 14462292SN/A 14472292SN/A ListIt inst_it = instList.end(); 14482292SN/A 14492292SN/A inst_it--; 14502292SN/A 14512292SN/A // Walk through the instruction list, removing any instructions 14522292SN/A // that were inserted after the given instruction iterator, end_it. 14532292SN/A while (inst_it != end_it) { 14542292SN/A assert(!instList.empty()); 14552292SN/A 14562292SN/A squashInstIt(inst_it, tid); 14572292SN/A 14582292SN/A inst_it--; 14592292SN/A } 14602292SN/A 14612292SN/A // If the ROB was empty, then we actually need to remove the first 14622292SN/A // instruction as well. 14632292SN/A if (rob_empty) { 14642292SN/A squashInstIt(inst_it, tid); 14652292SN/A } 14661060SN/A} 14671060SN/A 14681060SN/Atemplate <class Impl> 14691060SN/Avoid 14706221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 14711062SN/A{ 14722292SN/A assert(!instList.empty()); 14732292SN/A 14742292SN/A removeInstsThisCycle = true; 14752292SN/A 14762292SN/A ListIt inst_iter = instList.end(); 14772292SN/A 14782292SN/A inst_iter--; 14792292SN/A 14802733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 14812292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 14822292SN/A tid, seq_num, (*inst_iter)->seqNum); 14831062SN/A 14842292SN/A while ((*inst_iter)->seqNum > seq_num) { 14851062SN/A 14862292SN/A bool break_loop = (inst_iter == instList.begin()); 14871062SN/A 14882292SN/A squashInstIt(inst_iter, tid); 14891062SN/A 14902292SN/A inst_iter--; 14911062SN/A 14922292SN/A if (break_loop) 14932292SN/A break; 14942292SN/A } 14952292SN/A} 14962292SN/A 14972292SN/Atemplate <class Impl> 14982292SN/Ainline void 14996221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 15002292SN/A{ 15012292SN/A if ((*instIt)->threadNumber == tid) { 15022733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 15037720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15042292SN/A (*instIt)->threadNumber, 15052292SN/A (*instIt)->seqNum, 15067720Sgblack@eecs.umich.edu (*instIt)->pcState()); 15071062SN/A 15081062SN/A // Mark it as squashed. 15092292SN/A (*instIt)->setSquashed(); 15102292SN/A 15112325SN/A // @todo: Formulate a consistent method for deleting 15122325SN/A // instructions from the instruction list 15132292SN/A // Remove the instruction from the list. 15142292SN/A removeList.push(instIt); 15152292SN/A } 15162292SN/A} 15172292SN/A 15182292SN/Atemplate <class Impl> 15192292SN/Avoid 15202292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 15212292SN/A{ 15222292SN/A while (!removeList.empty()) { 15232733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 15247720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15252292SN/A (*removeList.front())->threadNumber, 15262292SN/A (*removeList.front())->seqNum, 15277720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 15282292SN/A 15292292SN/A instList.erase(removeList.front()); 15302292SN/A 15312292SN/A removeList.pop(); 15321062SN/A } 15331062SN/A 15342292SN/A removeInstsThisCycle = false; 15351062SN/A} 15362325SN/A/* 15371062SN/Atemplate <class Impl> 15381062SN/Avoid 15391755SN/AFullO3CPU<Impl>::removeAllInsts() 15401060SN/A{ 15411060SN/A instList.clear(); 15421060SN/A} 15432325SN/A*/ 15441060SN/Atemplate <class Impl> 15451060SN/Avoid 15461755SN/AFullO3CPU<Impl>::dumpInsts() 15471060SN/A{ 15481060SN/A int num = 0; 15491060SN/A 15502292SN/A ListIt inst_list_it = instList.begin(); 15512292SN/A 15522292SN/A cprintf("Dumping Instruction List\n"); 15532292SN/A 15542292SN/A while (inst_list_it != instList.end()) { 15552292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 15562292SN/A "Squashed:%i\n\n", 15577720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 15582292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 15592292SN/A (*inst_list_it)->isSquashed()); 15601060SN/A inst_list_it++; 15611060SN/A ++num; 15621060SN/A } 15631060SN/A} 15642325SN/A/* 15651060SN/Atemplate <class Impl> 15661060SN/Avoid 15671755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 15681060SN/A{ 15691060SN/A iew.wakeDependents(inst); 15701060SN/A} 15712325SN/A*/ 15722292SN/Atemplate <class Impl> 15732292SN/Avoid 15742292SN/AFullO3CPU<Impl>::wakeCPU() 15752292SN/A{ 15762325SN/A if (activityRec.active() || tickEvent.scheduled()) { 15772325SN/A DPRINTF(Activity, "CPU already running.\n"); 15782292SN/A return; 15792292SN/A } 15802292SN/A 15812325SN/A DPRINTF(Activity, "Waking up CPU\n"); 15822325SN/A 15837823Ssteve.reinhardt@amd.com idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 15847823Ssteve.reinhardt@amd.com numCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 15852292SN/A 15865606Snate@binkert.org schedule(tickEvent, nextCycle()); 15872292SN/A} 15882292SN/A 15895807Snate@binkert.orgtemplate <class Impl> 15905807Snate@binkert.orgvoid 15915807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 15925807Snate@binkert.org{ 15935807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 15945807Snate@binkert.org return; 15955807Snate@binkert.org 15965807Snate@binkert.org this->wakeCPU(); 15975807Snate@binkert.org 15985807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 15995807Snate@binkert.org this->threadContexts[0]->activate(); 16005807Snate@binkert.org} 16015807Snate@binkert.org 16022292SN/Atemplate <class Impl> 16036221Snate@binkert.orgThreadID 16042292SN/AFullO3CPU<Impl>::getFreeTid() 16052292SN/A{ 16066221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 16076221Snate@binkert.org if (!tids[tid]) { 16086221Snate@binkert.org tids[tid] = true; 16096221Snate@binkert.org return tid; 16102292SN/A } 16112292SN/A } 16122292SN/A 16136221Snate@binkert.org return InvalidThreadID; 16142292SN/A} 16152292SN/A 16162292SN/Atemplate <class Impl> 16172292SN/Avoid 16182292SN/AFullO3CPU<Impl>::doContextSwitch() 16192292SN/A{ 16202292SN/A if (contextSwitch) { 16212292SN/A 16222292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 16232292SN/A 16246221Snate@binkert.org ThreadID size = cpuWaitList.size(); 16256221Snate@binkert.org for (ThreadID tid = 0; tid < size; tid++) { 16262292SN/A activateWhenReady(tid); 16272292SN/A } 16282292SN/A 16292292SN/A if (cpuWaitList.size() == 0) 16302292SN/A contextSwitch = true; 16312292SN/A } 16322292SN/A} 16332292SN/A 16342292SN/Atemplate <class Impl> 16352292SN/Avoid 16362292SN/AFullO3CPU<Impl>::updateThreadPriority() 16372292SN/A{ 16386221Snate@binkert.org if (activeThreads.size() > 1) { 16392292SN/A //DEFAULT TO ROUND ROBIN SCHEME 16402292SN/A //e.g. Move highest priority to end of thread list 16416221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 16426221Snate@binkert.org list<ThreadID>::iterator list_end = activeThreads.end(); 16432292SN/A 16442292SN/A unsigned high_thread = *list_begin; 16452292SN/A 16462292SN/A activeThreads.erase(list_begin); 16472292SN/A 16482292SN/A activeThreads.push_back(high_thread); 16492292SN/A } 16502292SN/A} 16511060SN/A 16521755SN/A// Forward declaration of FullO3CPU. 16532818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1654