cpu.cc revision 6313
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 354762Snate@binkert.org#include "cpu/activity.hh" 364762Snate@binkert.org#include "cpu/simple_thread.hh" 374762Snate@binkert.org#include "cpu/thread_context.hh" 384762Snate@binkert.org#include "cpu/o3/isa_specific.hh" 394762Snate@binkert.org#include "cpu/o3/cpu.hh" 405595Sgblack@eecs.umich.edu#include "cpu/o3/thread_context.hh" 414762Snate@binkert.org#include "enums/MemoryMode.hh" 424762Snate@binkert.org#include "sim/core.hh" 434762Snate@binkert.org#include "sim/stat_control.hh" 444762Snate@binkert.org 451858SN/A#if FULL_SYSTEM 462356SN/A#include "cpu/quiesce_event.hh" 471060SN/A#include "sim/system.hh" 481060SN/A#else 491060SN/A#include "sim/process.hh" 501060SN/A#endif 511060SN/A 522794Sktlim@umich.edu#if USE_CHECKER 532794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 542794Sktlim@umich.edu#endif 552794Sktlim@umich.edu 565702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 575702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 585702Ssaidi@eecs.umich.edu#endif 595702Ssaidi@eecs.umich.edu 605529Snate@binkert.orgclass BaseCPUParams; 615529Snate@binkert.org 622669Sktlim@umich.eduusing namespace TheISA; 636221Snate@binkert.orgusing namespace std; 641060SN/A 655529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 665712Shsul@eecs.umich.edu : BaseCPU(params) 671060SN/A{ 681060SN/A} 691060SN/A 702292SN/Avoid 712733Sktlim@umich.eduBaseO3CPU::regStats() 722292SN/A{ 732292SN/A BaseCPU::regStats(); 742292SN/A} 752292SN/A 761060SN/Atemplate <class Impl> 771755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 785606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 791060SN/A{ 801060SN/A} 811060SN/A 821060SN/Atemplate <class Impl> 831060SN/Avoid 841755SN/AFullO3CPU<Impl>::TickEvent::process() 851060SN/A{ 861060SN/A cpu->tick(); 871060SN/A} 881060SN/A 891060SN/Atemplate <class Impl> 901060SN/Aconst char * 915336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 921060SN/A{ 934873Sstever@eecs.umich.edu return "FullO3CPU tick"; 941060SN/A} 951060SN/A 961060SN/Atemplate <class Impl> 972829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 985606Snate@binkert.org : Event(CPU_Switch_Pri) 992829Sksewell@umich.edu{ 1002829Sksewell@umich.edu} 1012829Sksewell@umich.edu 1022829Sksewell@umich.edutemplate <class Impl> 1032829Sksewell@umich.eduvoid 1042829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1052829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1062829Sksewell@umich.edu{ 1072829Sksewell@umich.edu tid = thread_num; 1082829Sksewell@umich.edu cpu = thread_cpu; 1092829Sksewell@umich.edu} 1102829Sksewell@umich.edu 1112829Sksewell@umich.edutemplate <class Impl> 1122829Sksewell@umich.eduvoid 1132829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1142829Sksewell@umich.edu{ 1152829Sksewell@umich.edu cpu->activateThread(tid); 1162829Sksewell@umich.edu} 1172829Sksewell@umich.edu 1182829Sksewell@umich.edutemplate <class Impl> 1192829Sksewell@umich.educonst char * 1205336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1212829Sksewell@umich.edu{ 1224873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1232829Sksewell@umich.edu} 1242829Sksewell@umich.edu 1252829Sksewell@umich.edutemplate <class Impl> 1262875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1275606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1282875Sksewell@umich.edu{ 1292875Sksewell@umich.edu} 1302875Sksewell@umich.edu 1312875Sksewell@umich.edutemplate <class Impl> 1322875Sksewell@umich.eduvoid 1332875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1343859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1352875Sksewell@umich.edu{ 1362875Sksewell@umich.edu tid = thread_num; 1372875Sksewell@umich.edu cpu = thread_cpu; 1383859Sbinkertn@umich.edu remove = false; 1392875Sksewell@umich.edu} 1402875Sksewell@umich.edu 1412875Sksewell@umich.edutemplate <class Impl> 1422875Sksewell@umich.eduvoid 1432875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1442875Sksewell@umich.edu{ 1452875Sksewell@umich.edu cpu->deactivateThread(tid); 1463221Sktlim@umich.edu if (remove) 1473221Sktlim@umich.edu cpu->removeThread(tid); 1482875Sksewell@umich.edu} 1492875Sksewell@umich.edu 1502875Sksewell@umich.edutemplate <class Impl> 1512875Sksewell@umich.educonst char * 1525336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 1532875Sksewell@umich.edu{ 1544873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 1552875Sksewell@umich.edu} 1562875Sksewell@umich.edu 1572875Sksewell@umich.edutemplate <class Impl> 1585595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1592733Sktlim@umich.edu : BaseO3CPU(params), 1603781Sgblack@eecs.umich.edu itb(params->itb), 1613781Sgblack@eecs.umich.edu dtb(params->dtb), 1621060SN/A tickEvent(this), 1635737Scws3k@cs.virginia.edu#ifndef NDEBUG 1645737Scws3k@cs.virginia.edu instcount(0), 1655737Scws3k@cs.virginia.edu#endif 1662292SN/A removeInstsThisCycle(false), 1675595Sgblack@eecs.umich.edu fetch(this, params), 1685595Sgblack@eecs.umich.edu decode(this, params), 1695595Sgblack@eecs.umich.edu rename(this, params), 1705595Sgblack@eecs.umich.edu iew(this, params), 1715595Sgblack@eecs.umich.edu commit(this, params), 1721060SN/A 1735595Sgblack@eecs.umich.edu regFile(this, params->numPhysIntRegs, 1744329Sktlim@umich.edu params->numPhysFloatRegs), 1751060SN/A 1765529Snate@binkert.org freeList(params->numThreads, 1772292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1782292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1791060SN/A 1805595Sgblack@eecs.umich.edu rob(this, 1814329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 1822292SN/A params->smtROBPolicy, params->smtROBThreshold, 1835529Snate@binkert.org params->numThreads), 1841060SN/A 1855529Snate@binkert.org scoreboard(params->numThreads, 1862292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1872292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1886221Snate@binkert.org TheISA::NumMiscRegs * numThreads, 1892292SN/A TheISA::ZeroReg), 1901060SN/A 1912873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1922873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1932873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1942873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1952873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1965804Snate@binkert.org activityRec(name(), NumStages, 1972873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1982873Sktlim@umich.edu params->activity), 1991060SN/A 2001060SN/A globalSeqNum(1), 2011858SN/A#if FULL_SYSTEM 2022292SN/A system(params->system), 2031060SN/A physmem(system->physmem), 2041060SN/A#endif // FULL_SYSTEM 2052843Sktlim@umich.edu drainCount(0), 2066221Snate@binkert.org deferRegistration(params->defer_registration) 2071060SN/A{ 2083221Sktlim@umich.edu if (!deferRegistration) { 2093221Sktlim@umich.edu _status = Running; 2103221Sktlim@umich.edu } else { 2113221Sktlim@umich.edu _status = Idle; 2123221Sktlim@umich.edu } 2131681SN/A 2144598Sbinkertn@umich.edu#if USE_CHECKER 2152794Sktlim@umich.edu if (params->checker) { 2162316SN/A BaseCPU *temp_checker = params->checker; 2172316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2182316SN/A#if FULL_SYSTEM 2192316SN/A checker->setSystem(params->system); 2202316SN/A#endif 2214598Sbinkertn@umich.edu } else { 2224598Sbinkertn@umich.edu checker = NULL; 2234598Sbinkertn@umich.edu } 2242794Sktlim@umich.edu#endif // USE_CHECKER 2252316SN/A 2261858SN/A#if !FULL_SYSTEM 2276221Snate@binkert.org thread.resize(numThreads); 2286221Snate@binkert.org tids.resize(numThreads); 2291681SN/A#endif 2301681SN/A 2312325SN/A // The stages also need their CPU pointer setup. However this 2322325SN/A // must be done at the upper level CPU because they have pointers 2332325SN/A // to the upper level CPU, and not this FullO3CPU. 2341060SN/A 2352292SN/A // Set up Pointers to the activeThreads list for each stage 2362292SN/A fetch.setActiveThreads(&activeThreads); 2372292SN/A decode.setActiveThreads(&activeThreads); 2382292SN/A rename.setActiveThreads(&activeThreads); 2392292SN/A iew.setActiveThreads(&activeThreads); 2402292SN/A commit.setActiveThreads(&activeThreads); 2411060SN/A 2421060SN/A // Give each of the stages the time buffer they will use. 2431060SN/A fetch.setTimeBuffer(&timeBuffer); 2441060SN/A decode.setTimeBuffer(&timeBuffer); 2451060SN/A rename.setTimeBuffer(&timeBuffer); 2461060SN/A iew.setTimeBuffer(&timeBuffer); 2471060SN/A commit.setTimeBuffer(&timeBuffer); 2481060SN/A 2491060SN/A // Also setup each of the stages' queues. 2501060SN/A fetch.setFetchQueue(&fetchQueue); 2511060SN/A decode.setFetchQueue(&fetchQueue); 2522292SN/A commit.setFetchQueue(&fetchQueue); 2531060SN/A decode.setDecodeQueue(&decodeQueue); 2541060SN/A rename.setDecodeQueue(&decodeQueue); 2551060SN/A rename.setRenameQueue(&renameQueue); 2561060SN/A iew.setRenameQueue(&renameQueue); 2571060SN/A iew.setIEWQueue(&iewQueue); 2581060SN/A commit.setIEWQueue(&iewQueue); 2591060SN/A commit.setRenameQueue(&renameQueue); 2601060SN/A 2612292SN/A commit.setIEWStage(&iew); 2622292SN/A rename.setIEWStage(&iew); 2632292SN/A rename.setCommitStage(&commit); 2642292SN/A 2652292SN/A#if !FULL_SYSTEM 2666221Snate@binkert.org ThreadID active_threads = params->workload.size(); 2672831Sksewell@umich.edu 2682831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2692831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2702831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2712831Sksewell@umich.edu "edit your workload size."); 2722831Sksewell@umich.edu } 2732292SN/A#else 2746221Snate@binkert.org ThreadID active_threads = 1; 2752292SN/A#endif 2762292SN/A 2772316SN/A //Make Sure That this a Valid Architeture 2782292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2792292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2802292SN/A 2812292SN/A rename.setScoreboard(&scoreboard); 2822292SN/A iew.setScoreboard(&scoreboard); 2832292SN/A 2841060SN/A // Setup the rename map for whichever stages need it. 2852292SN/A PhysRegIndex lreg_idx = 0; 2862292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2871060SN/A 2886221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2892307SN/A bool bindRegs = (tid <= active_threads - 1); 2902292SN/A 2912292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2922292SN/A params->numPhysIntRegs, 2932325SN/A lreg_idx, //Index for Logical. Regs 2942292SN/A 2952292SN/A TheISA::NumFloatRegs, 2962292SN/A params->numPhysFloatRegs, 2972325SN/A freg_idx, //Index for Float Regs 2982292SN/A 2992292SN/A TheISA::NumMiscRegs, 3002292SN/A 3012292SN/A TheISA::ZeroReg, 3022292SN/A TheISA::ZeroReg, 3032292SN/A 3042292SN/A tid, 3052292SN/A false); 3062292SN/A 3072292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3082292SN/A params->numPhysIntRegs, 3092325SN/A lreg_idx, //Index for Logical. Regs 3102292SN/A 3112292SN/A TheISA::NumFloatRegs, 3122292SN/A params->numPhysFloatRegs, 3132325SN/A freg_idx, //Index for Float Regs 3142292SN/A 3152292SN/A TheISA::NumMiscRegs, 3162292SN/A 3172292SN/A TheISA::ZeroReg, 3182292SN/A TheISA::ZeroReg, 3192292SN/A 3202292SN/A tid, 3212292SN/A bindRegs); 3223221Sktlim@umich.edu 3233221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3243221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3252292SN/A } 3262292SN/A 3272292SN/A rename.setRenameMap(renameMap); 3282292SN/A commit.setRenameMap(commitRenameMap); 3292292SN/A 3302292SN/A // Give renameMap & rename stage access to the freeList; 3316221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3326221Snate@binkert.org renameMap[tid].setFreeList(&freeList); 3331060SN/A rename.setFreeList(&freeList); 3342292SN/A 3351060SN/A // Setup the ROB for whichever stages need it. 3361060SN/A commit.setROB(&rob); 3372292SN/A 3382292SN/A lastRunningCycle = curTick; 3392292SN/A 3402829Sksewell@umich.edu lastActivatedCycle = -1; 3416221Snate@binkert.org#if 0 3423093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3436221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3446221Snate@binkert.org globalSeqNum[tid] = 1; 3456221Snate@binkert.org#endif 3463093Sksewell@umich.edu 3472292SN/A contextSwitch = false; 3485595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3495595Sgblack@eecs.umich.edu 3505595Sgblack@eecs.umich.edu // Setup any thread state. 3515595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3525595Sgblack@eecs.umich.edu 3536221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 3545595Sgblack@eecs.umich.edu#if FULL_SYSTEM 3555595Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3565595Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3576221Snate@binkert.org this->thread[tid] = new Thread(this, 0); 3585595Sgblack@eecs.umich.edu#else 3596221Snate@binkert.org if (tid < params->workload.size()) { 3605595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3616221Snate@binkert.org tid, this->thread[tid]); 3626221Snate@binkert.org this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3635595Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3646221Snate@binkert.org tid, params->workload[tid], tid); 3655595Sgblack@eecs.umich.edu 3666221Snate@binkert.org //usedTids[tid] = true; 3676221Snate@binkert.org //threadMap[tid] = tid; 3685595Sgblack@eecs.umich.edu } else { 3695595Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3705595Sgblack@eecs.umich.edu //when scheduling threads to CPU 3715595Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3725595Sgblack@eecs.umich.edu 3736221Snate@binkert.org this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3745595Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3756221Snate@binkert.org tid, dummy_proc, tid); 3766221Snate@binkert.org //usedTids[tid] = false; 3775595Sgblack@eecs.umich.edu } 3785595Sgblack@eecs.umich.edu#endif // !FULL_SYSTEM 3795595Sgblack@eecs.umich.edu 3805595Sgblack@eecs.umich.edu ThreadContext *tc; 3815595Sgblack@eecs.umich.edu 3825595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3835595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3845595Sgblack@eecs.umich.edu 3855595Sgblack@eecs.umich.edu tc = o3_tc; 3865595Sgblack@eecs.umich.edu 3875595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3885595Sgblack@eecs.umich.edu // CheckerThreadContext. 3895595Sgblack@eecs.umich.edu#if USE_CHECKER 3905595Sgblack@eecs.umich.edu if (params->checker) { 3915595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3925595Sgblack@eecs.umich.edu o3_tc, this->checker); 3935595Sgblack@eecs.umich.edu } 3945595Sgblack@eecs.umich.edu#endif 3955595Sgblack@eecs.umich.edu 3965595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 3975595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 3986221Snate@binkert.org o3_tc->thread = this->thread[tid]; 3995595Sgblack@eecs.umich.edu 4005595Sgblack@eecs.umich.edu#if FULL_SYSTEM 4015595Sgblack@eecs.umich.edu // Setup quiesce event. 4026221Snate@binkert.org this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 4035595Sgblack@eecs.umich.edu#endif 4045595Sgblack@eecs.umich.edu // Give the thread the TC. 4056221Snate@binkert.org this->thread[tid]->tc = tc; 4065595Sgblack@eecs.umich.edu 4075595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4085595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4095595Sgblack@eecs.umich.edu } 4105595Sgblack@eecs.umich.edu 4116221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4126221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4135595Sgblack@eecs.umich.edu 4145595Sgblack@eecs.umich.edu lockAddr = 0; 4155595Sgblack@eecs.umich.edu lockFlag = false; 4161060SN/A} 4171060SN/A 4181060SN/Atemplate <class Impl> 4191755SN/AFullO3CPU<Impl>::~FullO3CPU() 4201060SN/A{ 4211060SN/A} 4221060SN/A 4231060SN/Atemplate <class Impl> 4241060SN/Avoid 4255595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4261062SN/A{ 4272733Sktlim@umich.edu BaseO3CPU::regStats(); 4282292SN/A 4292733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4302292SN/A timesIdled 4312292SN/A .name(name() + ".timesIdled") 4322292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4332292SN/A " unscheduled itself") 4342292SN/A .prereq(timesIdled); 4352292SN/A 4362292SN/A idleCycles 4372292SN/A .name(name() + ".idleCycles") 4382292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4392292SN/A "to idling") 4402292SN/A .prereq(idleCycles); 4412292SN/A 4422292SN/A // Number of Instructions simulated 4432292SN/A // -------------------------------- 4442292SN/A // Should probably be in Base CPU but need templated 4452292SN/A // MaxThreads so put in here instead 4462292SN/A committedInsts 4472292SN/A .init(numThreads) 4482292SN/A .name(name() + ".committedInsts") 4492292SN/A .desc("Number of Instructions Simulated"); 4502292SN/A 4512292SN/A totalCommittedInsts 4522292SN/A .name(name() + ".committedInsts_total") 4532292SN/A .desc("Number of Instructions Simulated"); 4542292SN/A 4552292SN/A cpi 4562292SN/A .name(name() + ".cpi") 4572292SN/A .desc("CPI: Cycles Per Instruction") 4582292SN/A .precision(6); 4594392Sktlim@umich.edu cpi = numCycles / committedInsts; 4602292SN/A 4612292SN/A totalCpi 4622292SN/A .name(name() + ".cpi_total") 4632292SN/A .desc("CPI: Total CPI of All Threads") 4642292SN/A .precision(6); 4654392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 4662292SN/A 4672292SN/A ipc 4682292SN/A .name(name() + ".ipc") 4692292SN/A .desc("IPC: Instructions Per Cycle") 4702292SN/A .precision(6); 4714392Sktlim@umich.edu ipc = committedInsts / numCycles; 4722292SN/A 4732292SN/A totalIpc 4742292SN/A .name(name() + ".ipc_total") 4752292SN/A .desc("IPC: Total IPC of All Threads") 4762292SN/A .precision(6); 4774392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 4782292SN/A 4795595Sgblack@eecs.umich.edu this->fetch.regStats(); 4805595Sgblack@eecs.umich.edu this->decode.regStats(); 4815595Sgblack@eecs.umich.edu this->rename.regStats(); 4825595Sgblack@eecs.umich.edu this->iew.regStats(); 4835595Sgblack@eecs.umich.edu this->commit.regStats(); 4841062SN/A} 4851062SN/A 4861062SN/Atemplate <class Impl> 4872871Sktlim@umich.eduPort * 4882871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 4892871Sktlim@umich.edu{ 4902871Sktlim@umich.edu if (if_name == "dcache_port") 4912871Sktlim@umich.edu return iew.getDcachePort(); 4922871Sktlim@umich.edu else if (if_name == "icache_port") 4932871Sktlim@umich.edu return fetch.getIcachePort(); 4942871Sktlim@umich.edu else 4952871Sktlim@umich.edu panic("No Such Port\n"); 4962871Sktlim@umich.edu} 4972871Sktlim@umich.edu 4982871Sktlim@umich.edutemplate <class Impl> 4991062SN/Avoid 5001755SN/AFullO3CPU<Impl>::tick() 5011060SN/A{ 5022733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5031060SN/A 5042292SN/A ++numCycles; 5052292SN/A 5062325SN/A// activity = false; 5072292SN/A 5082292SN/A //Tick each of the stages 5091060SN/A fetch.tick(); 5101060SN/A 5111060SN/A decode.tick(); 5121060SN/A 5131060SN/A rename.tick(); 5141060SN/A 5151060SN/A iew.tick(); 5161060SN/A 5171060SN/A commit.tick(); 5181060SN/A 5192292SN/A#if !FULL_SYSTEM 5202292SN/A doContextSwitch(); 5212292SN/A#endif 5222292SN/A 5232292SN/A // Now advance the time buffers 5241060SN/A timeBuffer.advance(); 5251060SN/A 5261060SN/A fetchQueue.advance(); 5271060SN/A decodeQueue.advance(); 5281060SN/A renameQueue.advance(); 5291060SN/A iewQueue.advance(); 5301060SN/A 5312325SN/A activityRec.advance(); 5322292SN/A 5332292SN/A if (removeInstsThisCycle) { 5342292SN/A cleanUpRemovedInsts(); 5352292SN/A } 5362292SN/A 5372325SN/A if (!tickEvent.scheduled()) { 5382867Sktlim@umich.edu if (_status == SwitchedOut || 5392905Sktlim@umich.edu getState() == SimObject::Drained) { 5403226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 5412325SN/A // increment stat 5422325SN/A lastRunningCycle = curTick; 5433221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 5443226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 5452325SN/A lastRunningCycle = curTick; 5462325SN/A timesIdled++; 5472325SN/A } else { 5485606Snate@binkert.org schedule(tickEvent, nextCycle(curTick + ticks(1))); 5493226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 5502325SN/A } 5512292SN/A } 5522292SN/A 5532292SN/A#if !FULL_SYSTEM 5542292SN/A updateThreadPriority(); 5552292SN/A#endif 5561060SN/A} 5571060SN/A 5581060SN/Atemplate <class Impl> 5591060SN/Avoid 5601755SN/AFullO3CPU<Impl>::init() 5611060SN/A{ 5625714Shsul@eecs.umich.edu BaseCPU::init(); 5631060SN/A 5642292SN/A // Set inSyscall so that the CPU doesn't squash when initially 5652292SN/A // setting up registers. 5666221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 5676221Snate@binkert.org thread[tid]->inSyscall = true; 5682292SN/A 5696034Ssteve.reinhardt@amd.com#if FULL_SYSTEM 5706221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 5712680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 5726034Ssteve.reinhardt@amd.com TheISA::initCPU(src_tc, src_tc->contextId()); 5736034Ssteve.reinhardt@amd.com } 5741681SN/A#endif 5752292SN/A 5762292SN/A // Clear inSyscall. 5776221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 5786221Snate@binkert.org thread[tid]->inSyscall = false; 5792292SN/A 5802316SN/A // Initialize stages. 5812292SN/A fetch.initStage(); 5822292SN/A iew.initStage(); 5832292SN/A rename.initStage(); 5842292SN/A commit.initStage(); 5852292SN/A 5862292SN/A commit.setThreads(thread); 5872292SN/A} 5882292SN/A 5892292SN/Atemplate <class Impl> 5902292SN/Avoid 5916221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 5922875Sksewell@umich.edu{ 5936221Snate@binkert.org list<ThreadID>::iterator isActive = 5945314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 5952875Sksewell@umich.edu 5963226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 5973226Sktlim@umich.edu 5982875Sksewell@umich.edu if (isActive == activeThreads.end()) { 5992875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6002875Sksewell@umich.edu tid); 6012875Sksewell@umich.edu 6022875Sksewell@umich.edu activeThreads.push_back(tid); 6032875Sksewell@umich.edu } 6042875Sksewell@umich.edu} 6052875Sksewell@umich.edu 6062875Sksewell@umich.edutemplate <class Impl> 6072875Sksewell@umich.eduvoid 6086221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 6092875Sksewell@umich.edu{ 6102875Sksewell@umich.edu //Remove From Active List, if Active 6116221Snate@binkert.org list<ThreadID>::iterator thread_it = 6125314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6132875Sksewell@umich.edu 6143226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 6153226Sktlim@umich.edu 6162875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6172875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6182875Sksewell@umich.edu tid); 6192875Sksewell@umich.edu activeThreads.erase(thread_it); 6202875Sksewell@umich.edu } 6212875Sksewell@umich.edu} 6222875Sksewell@umich.edu 6232875Sksewell@umich.edutemplate <class Impl> 6246221Snate@binkert.orgCounter 6256221Snate@binkert.orgFullO3CPU<Impl>::totalInstructions() const 6266221Snate@binkert.org{ 6276221Snate@binkert.org Counter total(0); 6286221Snate@binkert.org 6296221Snate@binkert.org ThreadID size = thread.size(); 6306221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 6316221Snate@binkert.org total += thread[i]->numInst; 6326221Snate@binkert.org 6336221Snate@binkert.org return total; 6346221Snate@binkert.org} 6356221Snate@binkert.org 6366221Snate@binkert.orgtemplate <class Impl> 6372875Sksewell@umich.eduvoid 6386221Snate@binkert.orgFullO3CPU<Impl>::activateContext(ThreadID tid, int delay) 6392875Sksewell@umich.edu{ 6402875Sksewell@umich.edu // Needs to set each stage to running as well. 6412875Sksewell@umich.edu if (delay){ 6422875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 6435100Ssaidi@eecs.umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 6442875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 6452875Sksewell@umich.edu } else { 6462875Sksewell@umich.edu activateThread(tid); 6472875Sksewell@umich.edu } 6482875Sksewell@umich.edu 6493221Sktlim@umich.edu if (lastActivatedCycle < curTick) { 6502875Sksewell@umich.edu scheduleTickEvent(delay); 6512875Sksewell@umich.edu 6522875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 6532875Sksewell@umich.edu // deschedule itself. 6542875Sksewell@umich.edu activityRec.activity(); 6552875Sksewell@umich.edu fetch.wakeFromQuiesce(); 6562875Sksewell@umich.edu 6572875Sksewell@umich.edu lastActivatedCycle = curTick; 6582875Sksewell@umich.edu 6592875Sksewell@umich.edu _status = Running; 6602875Sksewell@umich.edu } 6612875Sksewell@umich.edu} 6622875Sksewell@umich.edu 6632875Sksewell@umich.edutemplate <class Impl> 6643221Sktlim@umich.edubool 6656221Snate@binkert.orgFullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay) 6662875Sksewell@umich.edu{ 6672875Sksewell@umich.edu // Schedule removal of thread data from CPU 6682875Sksewell@umich.edu if (delay){ 6692875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 6705100Ssaidi@eecs.umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 6713221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 6723221Sktlim@umich.edu return false; 6732875Sksewell@umich.edu } else { 6742875Sksewell@umich.edu deactivateThread(tid); 6753221Sktlim@umich.edu if (remove) 6763221Sktlim@umich.edu removeThread(tid); 6773221Sktlim@umich.edu return true; 6782875Sksewell@umich.edu } 6792875Sksewell@umich.edu} 6802875Sksewell@umich.edu 6812875Sksewell@umich.edutemplate <class Impl> 6822875Sksewell@umich.eduvoid 6836221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 6842875Sksewell@umich.edu{ 6852875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 6863221Sktlim@umich.edu bool deallocated = deallocateContext(tid, false, 1); 6873221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 6885570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 6893859Sbinkertn@umich.edu activeThreads.size() == 0) 6902910Sksewell@umich.edu unscheduleTickEvent(); 6912875Sksewell@umich.edu _status = Idle; 6922875Sksewell@umich.edu} 6932875Sksewell@umich.edu 6942875Sksewell@umich.edutemplate <class Impl> 6952875Sksewell@umich.eduvoid 6966221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 6972875Sksewell@umich.edu{ 6982910Sksewell@umich.edu //For now, this is the same as deallocate 6992910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 7003221Sktlim@umich.edu deallocateContext(tid, true, 1); 7012875Sksewell@umich.edu} 7022875Sksewell@umich.edu 7032875Sksewell@umich.edutemplate <class Impl> 7042875Sksewell@umich.eduvoid 7056221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 7062292SN/A{ 7072847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 7082292SN/A // Will change now that the PC and thread state is internal to the CPU 7092683Sktlim@umich.edu // and not in the ThreadContext. 7102292SN/A#if FULL_SYSTEM 7112680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 7122292SN/A#else 7132847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 7142292SN/A#endif 7152292SN/A 7162292SN/A //Bind Int Regs to Rename Map 7172292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7182292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 7192292SN/A 7202292SN/A renameMap[tid].setEntry(ireg,phys_reg); 7212292SN/A scoreboard.setReg(phys_reg); 7222292SN/A } 7232292SN/A 7242292SN/A //Bind Float Regs to Rename Map 7252292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 7262292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 7272292SN/A 7282292SN/A renameMap[tid].setEntry(freg,phys_reg); 7292292SN/A scoreboard.setReg(phys_reg); 7302292SN/A } 7312292SN/A 7322292SN/A //Copy Thread Data Into RegFile 7332847Sksewell@umich.edu //this->copyFromTC(tid); 7342292SN/A 7352847Sksewell@umich.edu //Set PC/NPC/NNPC 7362847Sksewell@umich.edu setPC(src_tc->readPC(), tid); 7372847Sksewell@umich.edu setNextPC(src_tc->readNextPC(), tid); 7382847Sksewell@umich.edu setNextNPC(src_tc->readNextNPC(), tid); 7392292SN/A 7402680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 7412292SN/A 7422292SN/A activateContext(tid,1); 7432292SN/A 7442292SN/A //Reset ROB/IQ/LSQ Entries 7452292SN/A commit.rob->resetEntries(); 7462292SN/A iew.resetEntries(); 7472292SN/A} 7482292SN/A 7492292SN/Atemplate <class Impl> 7502292SN/Avoid 7516221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 7522292SN/A{ 7532877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 7542847Sksewell@umich.edu 7552847Sksewell@umich.edu // Copy Thread Data From RegFile 7562847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 7575364Sksewell@umich.edu // this->copyToTC(tid); 7585364Sksewell@umich.edu 7595364Sksewell@umich.edu 7605364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 7615364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 7625364Sksewell@umich.edu // in SMT workloads. 7632847Sksewell@umich.edu 7642847Sksewell@umich.edu // Unbind Int Regs from Rename Map 7652292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7662292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 7672292SN/A 7682292SN/A scoreboard.unsetReg(phys_reg); 7692292SN/A freeList.addReg(phys_reg); 7702292SN/A } 7712292SN/A 7722847Sksewell@umich.edu // Unbind Float Regs from Rename Map 7735362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 7742292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 7752292SN/A 7762292SN/A scoreboard.unsetReg(phys_reg); 7772292SN/A freeList.addReg(phys_reg); 7782292SN/A } 7792292SN/A 7802847Sksewell@umich.edu // Squash Throughout Pipeline 7812935Sksewell@umich.edu InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 7824636Sgblack@eecs.umich.edu fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid); 7832292SN/A decode.squash(tid); 7842935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 7852875Sksewell@umich.edu iew.squash(tid); 7865363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 7872935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 7882292SN/A 7895362Sksewell@umich.edu 7905362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 7912292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 7922292SN/A 7932847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 7943229Sktlim@umich.edu 7953229Sktlim@umich.edu // Commented out for now. This should be possible to do by 7963229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 7973229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 7983229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 7993229Sktlim@umich.edu/* 8002292SN/A if (activeThreads.size() >= 1) { 8012292SN/A commit.rob->resetEntries(); 8022292SN/A iew.resetEntries(); 8032292SN/A } 8043229Sktlim@umich.edu*/ 8052292SN/A} 8062292SN/A 8072292SN/A 8082292SN/Atemplate <class Impl> 8092292SN/Avoid 8106221Snate@binkert.orgFullO3CPU<Impl>::activateWhenReady(ThreadID tid) 8112292SN/A{ 8122733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 8132292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 8142292SN/A tid); 8152292SN/A 8162292SN/A bool ready = true; 8172292SN/A 8182292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 8192733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8202292SN/A "Phys. Int. Regs.\n", 8212292SN/A tid); 8222292SN/A ready = false; 8232292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 8242733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8252292SN/A "Phys. Float. Regs.\n", 8262292SN/A tid); 8272292SN/A ready = false; 8282292SN/A } else if (commit.rob->numFreeEntries() >= 8292292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 8302733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8312292SN/A "ROB entries.\n", 8322292SN/A tid); 8332292SN/A ready = false; 8342292SN/A } else if (iew.instQueue.numFreeEntries() >= 8352292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 8362733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8372292SN/A "IQ entries.\n", 8382292SN/A tid); 8392292SN/A ready = false; 8402292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 8412292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 8422733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8432292SN/A "LSQ entries.\n", 8442292SN/A tid); 8452292SN/A ready = false; 8462292SN/A } 8472292SN/A 8482292SN/A if (ready) { 8492292SN/A insertThread(tid); 8502292SN/A 8512292SN/A contextSwitch = false; 8522292SN/A 8532292SN/A cpuWaitList.remove(tid); 8542292SN/A } else { 8552292SN/A suspendContext(tid); 8562292SN/A 8572292SN/A //blocks fetch 8582292SN/A contextSwitch = true; 8592292SN/A 8602875Sksewell@umich.edu //@todo: dont always add to waitlist 8612292SN/A //do waitlist 8622292SN/A cpuWaitList.push_back(tid); 8631060SN/A } 8641060SN/A} 8651060SN/A 8664192Sktlim@umich.edu#if FULL_SYSTEM 8674192Sktlim@umich.edutemplate <class Impl> 8685595Sgblack@eecs.umich.eduFault 8696221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 8705702Ssaidi@eecs.umich.edu{ 8715702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 8725702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 8735702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 8745702Ssaidi@eecs.umich.edu 8755702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 8765702Ssaidi@eecs.umich.edu 8775702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 8785702Ssaidi@eecs.umich.edu#endif 8795702Ssaidi@eecs.umich.edu return NoFault; 8805702Ssaidi@eecs.umich.edu} 8815702Ssaidi@eecs.umich.edu 8825702Ssaidi@eecs.umich.edutemplate <class Impl> 8835702Ssaidi@eecs.umich.edubool 8846221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 8855702Ssaidi@eecs.umich.edu{ 8865702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 8875702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 8885702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 8895702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 8905702Ssaidi@eecs.umich.edu 8915702Ssaidi@eecs.umich.edu switch (palFunc) { 8925702Ssaidi@eecs.umich.edu case PAL::halt: 8935702Ssaidi@eecs.umich.edu halt(); 8945702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 8955702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 8965702Ssaidi@eecs.umich.edu break; 8975702Ssaidi@eecs.umich.edu 8985702Ssaidi@eecs.umich.edu case PAL::bpt: 8995702Ssaidi@eecs.umich.edu case PAL::bugchk: 9005702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 9015702Ssaidi@eecs.umich.edu return false; 9025702Ssaidi@eecs.umich.edu break; 9035702Ssaidi@eecs.umich.edu } 9045702Ssaidi@eecs.umich.edu#endif 9055702Ssaidi@eecs.umich.edu return true; 9065702Ssaidi@eecs.umich.edu} 9075702Ssaidi@eecs.umich.edu 9085702Ssaidi@eecs.umich.edutemplate <class Impl> 9095702Ssaidi@eecs.umich.eduFault 9105595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 9115595Sgblack@eecs.umich.edu{ 9125595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 9135647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 9145595Sgblack@eecs.umich.edu} 9155595Sgblack@eecs.umich.edu 9165595Sgblack@eecs.umich.edutemplate <class Impl> 9175595Sgblack@eecs.umich.eduvoid 9185595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 9195595Sgblack@eecs.umich.edu{ 9205595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 9215595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 9225595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9235595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9245595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9255595Sgblack@eecs.umich.edu 9265595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 9275647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 9285595Sgblack@eecs.umich.edu 9295595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 9305595Sgblack@eecs.umich.edu this->trap(interrupt, 0); 9315595Sgblack@eecs.umich.edu} 9325595Sgblack@eecs.umich.edu 9335595Sgblack@eecs.umich.edutemplate <class Impl> 9345595Sgblack@eecs.umich.eduvoid 9354192Sktlim@umich.eduFullO3CPU<Impl>::updateMemPorts() 9364192Sktlim@umich.edu{ 9374192Sktlim@umich.edu // Update all ThreadContext's memory ports (Functional/Virtual 9384192Sktlim@umich.edu // Ports) 9396221Snate@binkert.org ThreadID size = thread.size(); 9406221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) 9415497Ssaidi@eecs.umich.edu thread[i]->connectMemPorts(thread[i]->getTC()); 9424192Sktlim@umich.edu} 9434192Sktlim@umich.edu#endif 9444192Sktlim@umich.edu 9451060SN/Atemplate <class Impl> 9462852Sktlim@umich.eduvoid 9476221Snate@binkert.orgFullO3CPU<Impl>::trap(Fault fault, ThreadID tid) 9485595Sgblack@eecs.umich.edu{ 9495595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 9505595Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid]); 9515595Sgblack@eecs.umich.edu} 9525595Sgblack@eecs.umich.edu 9535595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 9545595Sgblack@eecs.umich.edu 9555595Sgblack@eecs.umich.edutemplate <class Impl> 9565595Sgblack@eecs.umich.eduvoid 9576221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 9585595Sgblack@eecs.umich.edu{ 9595595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 9605595Sgblack@eecs.umich.edu 9615595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 9625595Sgblack@eecs.umich.edu 9635595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 9645595Sgblack@eecs.umich.edu // instruction. 9655595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 9665595Sgblack@eecs.umich.edu 9675595Sgblack@eecs.umich.edu // Execute the actual syscall. 9685595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 9695595Sgblack@eecs.umich.edu 9705595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 9715595Sgblack@eecs.umich.edu // incrementing it. 9725595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 9735595Sgblack@eecs.umich.edu} 9745595Sgblack@eecs.umich.edu 9755595Sgblack@eecs.umich.edu#endif 9765595Sgblack@eecs.umich.edu 9775595Sgblack@eecs.umich.edutemplate <class Impl> 9785595Sgblack@eecs.umich.eduvoid 9792864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 9802864Sktlim@umich.edu{ 9812918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 9822918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 9832864Sktlim@umich.edu BaseCPU::serialize(os); 9842864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 9852864Sktlim@umich.edu tickEvent.serialize(os); 9862864Sktlim@umich.edu 9872864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 9882864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 9892864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 9902864Sktlim@umich.edu static SimpleThread temp; 9912864Sktlim@umich.edu 9926221Snate@binkert.org ThreadID size = thread.size(); 9936221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 9942864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 9952864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 9962864Sktlim@umich.edu temp.serialize(os); 9972864Sktlim@umich.edu } 9982864Sktlim@umich.edu} 9992864Sktlim@umich.edu 10002864Sktlim@umich.edutemplate <class Impl> 10012864Sktlim@umich.eduvoid 10022864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 10032864Sktlim@umich.edu{ 10042918Sktlim@umich.edu SimObject::State so_state; 10052918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 10062864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 10072864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 10082864Sktlim@umich.edu 10092864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10102864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 10112864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10122864Sktlim@umich.edu static SimpleThread temp; 10132864Sktlim@umich.edu 10146221Snate@binkert.org ThreadID size = thread.size(); 10156221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 10162864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10172864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 10182864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 10192864Sktlim@umich.edu } 10202864Sktlim@umich.edu} 10212864Sktlim@umich.edu 10222864Sktlim@umich.edutemplate <class Impl> 10232905Sktlim@umich.eduunsigned int 10242843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 10251060SN/A{ 10263125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 10273512Sktlim@umich.edu 10283512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 10293512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 10303512Sktlim@umich.edu return 0; 10313512Sktlim@umich.edu } 10323512Sktlim@umich.edu 10332843Sktlim@umich.edu drainCount = 0; 10342843Sktlim@umich.edu fetch.drain(); 10352843Sktlim@umich.edu decode.drain(); 10362843Sktlim@umich.edu rename.drain(); 10372843Sktlim@umich.edu iew.drain(); 10382843Sktlim@umich.edu commit.drain(); 10392325SN/A 10402325SN/A // Wake the CPU and record activity so everything can drain out if 10412863Sktlim@umich.edu // the CPU was not able to immediately drain. 10422905Sktlim@umich.edu if (getState() != SimObject::Drained) { 10432864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 10442864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 10452864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 10462864Sktlim@umich.edu // process on the drain event. 10472864Sktlim@umich.edu drainEvent = drain_event; 10482843Sktlim@umich.edu 10492863Sktlim@umich.edu wakeCPU(); 10502863Sktlim@umich.edu activityRec.activity(); 10512852Sktlim@umich.edu 10522905Sktlim@umich.edu return 1; 10532863Sktlim@umich.edu } else { 10542905Sktlim@umich.edu return 0; 10552863Sktlim@umich.edu } 10562316SN/A} 10572310SN/A 10582316SN/Atemplate <class Impl> 10592316SN/Avoid 10602843Sktlim@umich.eduFullO3CPU<Impl>::resume() 10612316SN/A{ 10622843Sktlim@umich.edu fetch.resume(); 10632843Sktlim@umich.edu decode.resume(); 10642843Sktlim@umich.edu rename.resume(); 10652843Sktlim@umich.edu iew.resume(); 10662843Sktlim@umich.edu commit.resume(); 10672316SN/A 10682905Sktlim@umich.edu changeState(SimObject::Running); 10692905Sktlim@umich.edu 10702864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 10712864Sktlim@umich.edu return; 10722864Sktlim@umich.edu 10733319Shsul@eecs.umich.edu#if FULL_SYSTEM 10744762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 10753319Shsul@eecs.umich.edu#endif 10763319Shsul@eecs.umich.edu 10772843Sktlim@umich.edu if (!tickEvent.scheduled()) 10785606Snate@binkert.org schedule(tickEvent, nextCycle()); 10792843Sktlim@umich.edu _status = Running; 10802843Sktlim@umich.edu} 10812316SN/A 10822843Sktlim@umich.edutemplate <class Impl> 10832843Sktlim@umich.eduvoid 10842843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 10852843Sktlim@umich.edu{ 10862843Sktlim@umich.edu if (++drainCount == NumStages) { 10872316SN/A if (tickEvent.scheduled()) 10882316SN/A tickEvent.squash(); 10892863Sktlim@umich.edu 10902905Sktlim@umich.edu changeState(SimObject::Drained); 10912863Sktlim@umich.edu 10923126Sktlim@umich.edu BaseCPU::switchOut(); 10933126Sktlim@umich.edu 10942863Sktlim@umich.edu if (drainEvent) { 10952863Sktlim@umich.edu drainEvent->process(); 10962863Sktlim@umich.edu drainEvent = NULL; 10972863Sktlim@umich.edu } 10982310SN/A } 10992843Sktlim@umich.edu assert(drainCount <= 5); 11002843Sktlim@umich.edu} 11012843Sktlim@umich.edu 11022843Sktlim@umich.edutemplate <class Impl> 11032843Sktlim@umich.eduvoid 11042843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11052843Sktlim@umich.edu{ 11062843Sktlim@umich.edu fetch.switchOut(); 11072843Sktlim@umich.edu rename.switchOut(); 11082325SN/A iew.switchOut(); 11092843Sktlim@umich.edu commit.switchOut(); 11102843Sktlim@umich.edu instList.clear(); 11112843Sktlim@umich.edu while (!removeList.empty()) { 11122843Sktlim@umich.edu removeList.pop(); 11132843Sktlim@umich.edu } 11142843Sktlim@umich.edu 11152843Sktlim@umich.edu _status = SwitchedOut; 11162843Sktlim@umich.edu#if USE_CHECKER 11172843Sktlim@umich.edu if (checker) 11182843Sktlim@umich.edu checker->switchOut(); 11192843Sktlim@umich.edu#endif 11203126Sktlim@umich.edu if (tickEvent.scheduled()) 11213126Sktlim@umich.edu tickEvent.squash(); 11221060SN/A} 11231060SN/A 11241060SN/Atemplate <class Impl> 11251060SN/Avoid 11261755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 11271060SN/A{ 11282325SN/A // Flush out any old data from the time buffers. 11292873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 11302307SN/A timeBuffer.advance(); 11312307SN/A fetchQueue.advance(); 11322307SN/A decodeQueue.advance(); 11332307SN/A renameQueue.advance(); 11342307SN/A iewQueue.advance(); 11352307SN/A } 11362307SN/A 11372325SN/A activityRec.reset(); 11382307SN/A 11394192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 11401060SN/A 11412307SN/A fetch.takeOverFrom(); 11422307SN/A decode.takeOverFrom(); 11432307SN/A rename.takeOverFrom(); 11442307SN/A iew.takeOverFrom(); 11452307SN/A commit.takeOverFrom(); 11462307SN/A 11471060SN/A assert(!tickEvent.scheduled()); 11481060SN/A 11492325SN/A // @todo: Figure out how to properly select the tid to put onto 11502325SN/A // the active threads list. 11516221Snate@binkert.org ThreadID tid = 0; 11522307SN/A 11536221Snate@binkert.org list<ThreadID>::iterator isActive = 11545314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 11552307SN/A 11562307SN/A if (isActive == activeThreads.end()) { 11572325SN/A //May Need to Re-code this if the delay variable is the delay 11582325SN/A //needed for thread to activate 11592733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 11602307SN/A tid); 11612307SN/A 11622307SN/A activeThreads.push_back(tid); 11632307SN/A } 11642307SN/A 11652325SN/A // Set all statuses to active, schedule the CPU's tick event. 11662307SN/A // @todo: Fix up statuses so this is handled properly 11676221Snate@binkert.org ThreadID size = threadContexts.size(); 11686221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 11692680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 11702680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 11711681SN/A _status = Running; 11725606Snate@binkert.org schedule(tickEvent, nextCycle()); 11731681SN/A } 11741060SN/A } 11752307SN/A if (!tickEvent.scheduled()) 11765606Snate@binkert.org schedule(tickEvent, nextCycle()); 11771060SN/A} 11781060SN/A 11791060SN/Atemplate <class Impl> 11805595Sgblack@eecs.umich.eduTheISA::MiscReg 11816221Snate@binkert.orgFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 11825595Sgblack@eecs.umich.edu{ 11836313Sgblack@eecs.umich.edu return this->isa[tid].readMiscRegNoEffect(misc_reg); 11845595Sgblack@eecs.umich.edu} 11855595Sgblack@eecs.umich.edu 11865595Sgblack@eecs.umich.edutemplate <class Impl> 11875595Sgblack@eecs.umich.eduTheISA::MiscReg 11886221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 11895595Sgblack@eecs.umich.edu{ 11906313Sgblack@eecs.umich.edu return this->isa[tid].readMiscReg(misc_reg, tcBase(tid)); 11915595Sgblack@eecs.umich.edu} 11925595Sgblack@eecs.umich.edu 11935595Sgblack@eecs.umich.edutemplate <class Impl> 11945595Sgblack@eecs.umich.eduvoid 11955595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 11966221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 11975595Sgblack@eecs.umich.edu{ 11986313Sgblack@eecs.umich.edu this->isa[tid].setMiscRegNoEffect(misc_reg, val); 11995595Sgblack@eecs.umich.edu} 12005595Sgblack@eecs.umich.edu 12015595Sgblack@eecs.umich.edutemplate <class Impl> 12025595Sgblack@eecs.umich.eduvoid 12035595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 12046221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12055595Sgblack@eecs.umich.edu{ 12066313Sgblack@eecs.umich.edu this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); 12075595Sgblack@eecs.umich.edu} 12085595Sgblack@eecs.umich.edu 12095595Sgblack@eecs.umich.edutemplate <class Impl> 12101060SN/Auint64_t 12111755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 12121060SN/A{ 12131060SN/A return regFile.readIntReg(reg_idx); 12141060SN/A} 12151060SN/A 12161060SN/Atemplate <class Impl> 12172455SN/AFloatReg 12182455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 12191060SN/A{ 12202455SN/A return regFile.readFloatReg(reg_idx, width); 12211060SN/A} 12221060SN/A 12231060SN/Atemplate <class Impl> 12242455SN/AFloatReg 12252455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 12261060SN/A{ 12272455SN/A return regFile.readFloatReg(reg_idx); 12281060SN/A} 12291060SN/A 12301060SN/Atemplate <class Impl> 12312455SN/AFloatRegBits 12322455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 12331060SN/A{ 12342455SN/A return regFile.readFloatRegBits(reg_idx, width); 12352455SN/A} 12362455SN/A 12372455SN/Atemplate <class Impl> 12382455SN/AFloatRegBits 12392455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 12402455SN/A{ 12412455SN/A return regFile.readFloatRegBits(reg_idx); 12421060SN/A} 12431060SN/A 12441060SN/Atemplate <class Impl> 12451060SN/Avoid 12461755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 12471060SN/A{ 12481060SN/A regFile.setIntReg(reg_idx, val); 12491060SN/A} 12501060SN/A 12511060SN/Atemplate <class Impl> 12521060SN/Avoid 12532455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 12541060SN/A{ 12552455SN/A regFile.setFloatReg(reg_idx, val, width); 12561060SN/A} 12571060SN/A 12581060SN/Atemplate <class Impl> 12591060SN/Avoid 12602455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 12611060SN/A{ 12622455SN/A regFile.setFloatReg(reg_idx, val); 12631060SN/A} 12641060SN/A 12651060SN/Atemplate <class Impl> 12661060SN/Avoid 12672455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 12681060SN/A{ 12692455SN/A regFile.setFloatRegBits(reg_idx, val, width); 12702455SN/A} 12712455SN/A 12722455SN/Atemplate <class Impl> 12732455SN/Avoid 12742455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 12752455SN/A{ 12762455SN/A regFile.setFloatRegBits(reg_idx, val); 12771060SN/A} 12781060SN/A 12791060SN/Atemplate <class Impl> 12801060SN/Auint64_t 12816221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 12821060SN/A{ 12832292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 12842292SN/A 12852292SN/A return regFile.readIntReg(phys_reg); 12862292SN/A} 12872292SN/A 12882292SN/Atemplate <class Impl> 12892292SN/Afloat 12906221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, ThreadID tid) 12912292SN/A{ 12926032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 12932307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 12942292SN/A 12952669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 12962292SN/A} 12972292SN/A 12982292SN/Atemplate <class Impl> 12992292SN/Adouble 13006221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, ThreadID tid) 13012292SN/A{ 13026032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13032307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13042292SN/A 13052669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 13062292SN/A} 13072292SN/A 13082292SN/Atemplate <class Impl> 13092292SN/Auint64_t 13106221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 13112292SN/A{ 13126032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13132307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13142292SN/A 13152669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13161060SN/A} 13171060SN/A 13181060SN/Atemplate <class Impl> 13191060SN/Avoid 13206221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 13211060SN/A{ 13222292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13232292SN/A 13242292SN/A regFile.setIntReg(phys_reg, val); 13251060SN/A} 13261060SN/A 13271060SN/Atemplate <class Impl> 13281060SN/Avoid 13296221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, ThreadID tid) 13301060SN/A{ 13316032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13322918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13332292SN/A 13342669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 13351060SN/A} 13361060SN/A 13371060SN/Atemplate <class Impl> 13381060SN/Avoid 13396221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, ThreadID tid) 13401060SN/A{ 13416032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13422918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13432292SN/A 13442669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 13451060SN/A} 13461060SN/A 13471060SN/Atemplate <class Impl> 13481060SN/Avoid 13496221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 13501060SN/A{ 13516032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13522918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13531060SN/A 13542669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 13552292SN/A} 13562292SN/A 13572292SN/Atemplate <class Impl> 13582292SN/Auint64_t 13596221Snate@binkert.orgFullO3CPU<Impl>::readPC(ThreadID tid) 13602292SN/A{ 13612292SN/A return commit.readPC(tid); 13621060SN/A} 13631060SN/A 13641060SN/Atemplate <class Impl> 13651060SN/Avoid 13666221Snate@binkert.orgFullO3CPU<Impl>::setPC(Addr new_PC, ThreadID tid) 13671060SN/A{ 13682292SN/A commit.setPC(new_PC, tid); 13692292SN/A} 13701060SN/A 13712292SN/Atemplate <class Impl> 13722292SN/Auint64_t 13736221Snate@binkert.orgFullO3CPU<Impl>::readMicroPC(ThreadID tid) 13744636Sgblack@eecs.umich.edu{ 13754636Sgblack@eecs.umich.edu return commit.readMicroPC(tid); 13764636Sgblack@eecs.umich.edu} 13774636Sgblack@eecs.umich.edu 13784636Sgblack@eecs.umich.edutemplate <class Impl> 13794636Sgblack@eecs.umich.eduvoid 13806221Snate@binkert.orgFullO3CPU<Impl>::setMicroPC(Addr new_PC, ThreadID tid) 13814636Sgblack@eecs.umich.edu{ 13824636Sgblack@eecs.umich.edu commit.setMicroPC(new_PC, tid); 13834636Sgblack@eecs.umich.edu} 13844636Sgblack@eecs.umich.edu 13854636Sgblack@eecs.umich.edutemplate <class Impl> 13864636Sgblack@eecs.umich.eduuint64_t 13876221Snate@binkert.orgFullO3CPU<Impl>::readNextPC(ThreadID tid) 13882292SN/A{ 13892292SN/A return commit.readNextPC(tid); 13902292SN/A} 13911060SN/A 13922292SN/Atemplate <class Impl> 13932292SN/Avoid 13946221Snate@binkert.orgFullO3CPU<Impl>::setNextPC(uint64_t val, ThreadID tid) 13952292SN/A{ 13962292SN/A commit.setNextPC(val, tid); 13972292SN/A} 13981060SN/A 13992756Sksewell@umich.edutemplate <class Impl> 14002756Sksewell@umich.eduuint64_t 14016221Snate@binkert.orgFullO3CPU<Impl>::readNextNPC(ThreadID tid) 14022756Sksewell@umich.edu{ 14032756Sksewell@umich.edu return commit.readNextNPC(tid); 14042756Sksewell@umich.edu} 14052756Sksewell@umich.edu 14062756Sksewell@umich.edutemplate <class Impl> 14072756Sksewell@umich.eduvoid 14086221Snate@binkert.orgFullO3CPU<Impl>::setNextNPC(uint64_t val, ThreadID tid) 14092756Sksewell@umich.edu{ 14102756Sksewell@umich.edu commit.setNextNPC(val, tid); 14112756Sksewell@umich.edu} 14122756Sksewell@umich.edu 14132292SN/Atemplate <class Impl> 14144636Sgblack@eecs.umich.eduuint64_t 14156221Snate@binkert.orgFullO3CPU<Impl>::readNextMicroPC(ThreadID tid) 14164636Sgblack@eecs.umich.edu{ 14174636Sgblack@eecs.umich.edu return commit.readNextMicroPC(tid); 14184636Sgblack@eecs.umich.edu} 14194636Sgblack@eecs.umich.edu 14204636Sgblack@eecs.umich.edutemplate <class Impl> 14214636Sgblack@eecs.umich.eduvoid 14226221Snate@binkert.orgFullO3CPU<Impl>::setNextMicroPC(Addr new_PC, ThreadID tid) 14234636Sgblack@eecs.umich.edu{ 14244636Sgblack@eecs.umich.edu commit.setNextMicroPC(new_PC, tid); 14254636Sgblack@eecs.umich.edu} 14264636Sgblack@eecs.umich.edu 14274636Sgblack@eecs.umich.edutemplate <class Impl> 14285595Sgblack@eecs.umich.eduvoid 14296221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 14305595Sgblack@eecs.umich.edu{ 14315595Sgblack@eecs.umich.edu this->thread[tid]->inSyscall = true; 14325595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 14335595Sgblack@eecs.umich.edu} 14345595Sgblack@eecs.umich.edu 14355595Sgblack@eecs.umich.edutemplate <class Impl> 14362292SN/Atypename FullO3CPU<Impl>::ListIt 14372292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14382292SN/A{ 14392292SN/A instList.push_back(inst); 14401060SN/A 14412292SN/A return --(instList.end()); 14422292SN/A} 14431060SN/A 14442292SN/Atemplate <class Impl> 14452292SN/Avoid 14466221Snate@binkert.orgFullO3CPU<Impl>::instDone(ThreadID tid) 14472292SN/A{ 14482292SN/A // Keep an instruction count. 14492292SN/A thread[tid]->numInst++; 14502292SN/A thread[tid]->numInsts++; 14512292SN/A committedInsts[tid]++; 14522292SN/A totalCommittedInsts++; 14532292SN/A 14542292SN/A // Check for instruction-count-based events. 14552292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 14562292SN/A} 14572292SN/A 14582292SN/Atemplate <class Impl> 14592292SN/Avoid 14602292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 14612292SN/A{ 14622292SN/A removeInstsThisCycle = true; 14632292SN/A 14642292SN/A removeList.push(inst->getInstListIt()); 14651060SN/A} 14661060SN/A 14671060SN/Atemplate <class Impl> 14681060SN/Avoid 14691755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 14701060SN/A{ 14712733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 14722292SN/A "[sn:%lli]\n", 14732303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 14741060SN/A 14752292SN/A removeInstsThisCycle = true; 14761060SN/A 14771060SN/A // Remove the front instruction. 14782292SN/A removeList.push(inst->getInstListIt()); 14791060SN/A} 14801060SN/A 14811060SN/Atemplate <class Impl> 14821060SN/Avoid 14836221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 14841060SN/A{ 14852733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 14862292SN/A " list.\n", tid); 14871060SN/A 14882292SN/A ListIt end_it; 14891060SN/A 14902292SN/A bool rob_empty = false; 14912292SN/A 14922292SN/A if (instList.empty()) { 14932292SN/A return; 14942292SN/A } else if (rob.isEmpty(/*tid*/)) { 14952733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 14962292SN/A end_it = instList.begin(); 14972292SN/A rob_empty = true; 14982292SN/A } else { 14992292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 15002733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 15012292SN/A } 15022292SN/A 15032292SN/A removeInstsThisCycle = true; 15042292SN/A 15052292SN/A ListIt inst_it = instList.end(); 15062292SN/A 15072292SN/A inst_it--; 15082292SN/A 15092292SN/A // Walk through the instruction list, removing any instructions 15102292SN/A // that were inserted after the given instruction iterator, end_it. 15112292SN/A while (inst_it != end_it) { 15122292SN/A assert(!instList.empty()); 15132292SN/A 15142292SN/A squashInstIt(inst_it, tid); 15152292SN/A 15162292SN/A inst_it--; 15172292SN/A } 15182292SN/A 15192292SN/A // If the ROB was empty, then we actually need to remove the first 15202292SN/A // instruction as well. 15212292SN/A if (rob_empty) { 15222292SN/A squashInstIt(inst_it, tid); 15232292SN/A } 15241060SN/A} 15251060SN/A 15261060SN/Atemplate <class Impl> 15271060SN/Avoid 15286221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 15291062SN/A{ 15302292SN/A assert(!instList.empty()); 15312292SN/A 15322292SN/A removeInstsThisCycle = true; 15332292SN/A 15342292SN/A ListIt inst_iter = instList.end(); 15352292SN/A 15362292SN/A inst_iter--; 15372292SN/A 15382733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 15392292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15402292SN/A tid, seq_num, (*inst_iter)->seqNum); 15411062SN/A 15422292SN/A while ((*inst_iter)->seqNum > seq_num) { 15431062SN/A 15442292SN/A bool break_loop = (inst_iter == instList.begin()); 15451062SN/A 15462292SN/A squashInstIt(inst_iter, tid); 15471062SN/A 15482292SN/A inst_iter--; 15491062SN/A 15502292SN/A if (break_loop) 15512292SN/A break; 15522292SN/A } 15532292SN/A} 15542292SN/A 15552292SN/Atemplate <class Impl> 15562292SN/Ainline void 15576221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 15582292SN/A{ 15592292SN/A if ((*instIt)->threadNumber == tid) { 15602733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 15612292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 15622292SN/A (*instIt)->threadNumber, 15632292SN/A (*instIt)->seqNum, 15642292SN/A (*instIt)->readPC()); 15651062SN/A 15661062SN/A // Mark it as squashed. 15672292SN/A (*instIt)->setSquashed(); 15682292SN/A 15692325SN/A // @todo: Formulate a consistent method for deleting 15702325SN/A // instructions from the instruction list 15712292SN/A // Remove the instruction from the list. 15722292SN/A removeList.push(instIt); 15732292SN/A } 15742292SN/A} 15752292SN/A 15762292SN/Atemplate <class Impl> 15772292SN/Avoid 15782292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 15792292SN/A{ 15802292SN/A while (!removeList.empty()) { 15812733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 15822292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 15832292SN/A (*removeList.front())->threadNumber, 15842292SN/A (*removeList.front())->seqNum, 15852292SN/A (*removeList.front())->readPC()); 15862292SN/A 15872292SN/A instList.erase(removeList.front()); 15882292SN/A 15892292SN/A removeList.pop(); 15901062SN/A } 15911062SN/A 15922292SN/A removeInstsThisCycle = false; 15931062SN/A} 15942325SN/A/* 15951062SN/Atemplate <class Impl> 15961062SN/Avoid 15971755SN/AFullO3CPU<Impl>::removeAllInsts() 15981060SN/A{ 15991060SN/A instList.clear(); 16001060SN/A} 16012325SN/A*/ 16021060SN/Atemplate <class Impl> 16031060SN/Avoid 16041755SN/AFullO3CPU<Impl>::dumpInsts() 16051060SN/A{ 16061060SN/A int num = 0; 16071060SN/A 16082292SN/A ListIt inst_list_it = instList.begin(); 16092292SN/A 16102292SN/A cprintf("Dumping Instruction List\n"); 16112292SN/A 16122292SN/A while (inst_list_it != instList.end()) { 16132292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 16142292SN/A "Squashed:%i\n\n", 16152292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 16162292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16172292SN/A (*inst_list_it)->isSquashed()); 16181060SN/A inst_list_it++; 16191060SN/A ++num; 16201060SN/A } 16211060SN/A} 16222325SN/A/* 16231060SN/Atemplate <class Impl> 16241060SN/Avoid 16251755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 16261060SN/A{ 16271060SN/A iew.wakeDependents(inst); 16281060SN/A} 16292325SN/A*/ 16302292SN/Atemplate <class Impl> 16312292SN/Avoid 16322292SN/AFullO3CPU<Impl>::wakeCPU() 16332292SN/A{ 16342325SN/A if (activityRec.active() || tickEvent.scheduled()) { 16352325SN/A DPRINTF(Activity, "CPU already running.\n"); 16362292SN/A return; 16372292SN/A } 16382292SN/A 16392325SN/A DPRINTF(Activity, "Waking up CPU\n"); 16402325SN/A 16415099Ssaidi@eecs.umich.edu idleCycles += tickToCycles((curTick - 1) - lastRunningCycle); 16425099Ssaidi@eecs.umich.edu numCycles += tickToCycles((curTick - 1) - lastRunningCycle); 16432292SN/A 16445606Snate@binkert.org schedule(tickEvent, nextCycle()); 16452292SN/A} 16462292SN/A 16475807Snate@binkert.org#if FULL_SYSTEM 16485807Snate@binkert.orgtemplate <class Impl> 16495807Snate@binkert.orgvoid 16505807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 16515807Snate@binkert.org{ 16525807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 16535807Snate@binkert.org return; 16545807Snate@binkert.org 16555807Snate@binkert.org this->wakeCPU(); 16565807Snate@binkert.org 16575807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 16585807Snate@binkert.org this->threadContexts[0]->activate(); 16595807Snate@binkert.org} 16605807Snate@binkert.org#endif 16615807Snate@binkert.org 16622292SN/Atemplate <class Impl> 16636221Snate@binkert.orgThreadID 16642292SN/AFullO3CPU<Impl>::getFreeTid() 16652292SN/A{ 16666221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 16676221Snate@binkert.org if (!tids[tid]) { 16686221Snate@binkert.org tids[tid] = true; 16696221Snate@binkert.org return tid; 16702292SN/A } 16712292SN/A } 16722292SN/A 16736221Snate@binkert.org return InvalidThreadID; 16742292SN/A} 16752292SN/A 16762292SN/Atemplate <class Impl> 16772292SN/Avoid 16782292SN/AFullO3CPU<Impl>::doContextSwitch() 16792292SN/A{ 16802292SN/A if (contextSwitch) { 16812292SN/A 16822292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 16832292SN/A 16846221Snate@binkert.org ThreadID size = cpuWaitList.size(); 16856221Snate@binkert.org for (ThreadID tid = 0; tid < size; tid++) { 16862292SN/A activateWhenReady(tid); 16872292SN/A } 16882292SN/A 16892292SN/A if (cpuWaitList.size() == 0) 16902292SN/A contextSwitch = true; 16912292SN/A } 16922292SN/A} 16932292SN/A 16942292SN/Atemplate <class Impl> 16952292SN/Avoid 16962292SN/AFullO3CPU<Impl>::updateThreadPriority() 16972292SN/A{ 16986221Snate@binkert.org if (activeThreads.size() > 1) { 16992292SN/A //DEFAULT TO ROUND ROBIN SCHEME 17002292SN/A //e.g. Move highest priority to end of thread list 17016221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 17026221Snate@binkert.org list<ThreadID>::iterator list_end = activeThreads.end(); 17032292SN/A 17042292SN/A unsigned high_thread = *list_begin; 17052292SN/A 17062292SN/A activeThreads.erase(list_begin); 17072292SN/A 17082292SN/A activeThreads.push_back(high_thread); 17092292SN/A } 17102292SN/A} 17111060SN/A 17121755SN/A// Forward declaration of FullO3CPU. 17132818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1714