cpu.cc revision 5647
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 354762Snate@binkert.org#include "cpu/activity.hh" 364762Snate@binkert.org#include "cpu/simple_thread.hh" 374762Snate@binkert.org#include "cpu/thread_context.hh" 384762Snate@binkert.org#include "cpu/o3/isa_specific.hh" 394762Snate@binkert.org#include "cpu/o3/cpu.hh" 405595Sgblack@eecs.umich.edu#include "cpu/o3/thread_context.hh" 414762Snate@binkert.org#include "enums/MemoryMode.hh" 424762Snate@binkert.org#include "sim/core.hh" 434762Snate@binkert.org#include "sim/stat_control.hh" 444762Snate@binkert.org 451858SN/A#if FULL_SYSTEM 462356SN/A#include "cpu/quiesce_event.hh" 471060SN/A#include "sim/system.hh" 481060SN/A#else 491060SN/A#include "sim/process.hh" 501060SN/A#endif 511060SN/A 522794Sktlim@umich.edu#if USE_CHECKER 532794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 542794Sktlim@umich.edu#endif 552794Sktlim@umich.edu 565529Snate@binkert.orgclass BaseCPUParams; 575529Snate@binkert.org 582669Sktlim@umich.eduusing namespace TheISA; 591060SN/A 605529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 612292SN/A : BaseCPU(params), cpu_id(0) 621060SN/A{ 631060SN/A} 641060SN/A 652292SN/Avoid 662733Sktlim@umich.eduBaseO3CPU::regStats() 672292SN/A{ 682292SN/A BaseCPU::regStats(); 692292SN/A} 702292SN/A 711060SN/Atemplate <class Impl> 721755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 735606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 741060SN/A{ 751060SN/A} 761060SN/A 771060SN/Atemplate <class Impl> 781060SN/Avoid 791755SN/AFullO3CPU<Impl>::TickEvent::process() 801060SN/A{ 811060SN/A cpu->tick(); 821060SN/A} 831060SN/A 841060SN/Atemplate <class Impl> 851060SN/Aconst char * 865336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 871060SN/A{ 884873Sstever@eecs.umich.edu return "FullO3CPU tick"; 891060SN/A} 901060SN/A 911060SN/Atemplate <class Impl> 922829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 935606Snate@binkert.org : Event(CPU_Switch_Pri) 942829Sksewell@umich.edu{ 952829Sksewell@umich.edu} 962829Sksewell@umich.edu 972829Sksewell@umich.edutemplate <class Impl> 982829Sksewell@umich.eduvoid 992829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1002829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1012829Sksewell@umich.edu{ 1022829Sksewell@umich.edu tid = thread_num; 1032829Sksewell@umich.edu cpu = thread_cpu; 1042829Sksewell@umich.edu} 1052829Sksewell@umich.edu 1062829Sksewell@umich.edutemplate <class Impl> 1072829Sksewell@umich.eduvoid 1082829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1092829Sksewell@umich.edu{ 1102829Sksewell@umich.edu cpu->activateThread(tid); 1112829Sksewell@umich.edu} 1122829Sksewell@umich.edu 1132829Sksewell@umich.edutemplate <class Impl> 1142829Sksewell@umich.educonst char * 1155336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1162829Sksewell@umich.edu{ 1174873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1182829Sksewell@umich.edu} 1192829Sksewell@umich.edu 1202829Sksewell@umich.edutemplate <class Impl> 1212875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1225606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1232875Sksewell@umich.edu{ 1242875Sksewell@umich.edu} 1252875Sksewell@umich.edu 1262875Sksewell@umich.edutemplate <class Impl> 1272875Sksewell@umich.eduvoid 1282875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1293859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1302875Sksewell@umich.edu{ 1312875Sksewell@umich.edu tid = thread_num; 1322875Sksewell@umich.edu cpu = thread_cpu; 1333859Sbinkertn@umich.edu remove = false; 1342875Sksewell@umich.edu} 1352875Sksewell@umich.edu 1362875Sksewell@umich.edutemplate <class Impl> 1372875Sksewell@umich.eduvoid 1382875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1392875Sksewell@umich.edu{ 1402875Sksewell@umich.edu cpu->deactivateThread(tid); 1413221Sktlim@umich.edu if (remove) 1423221Sktlim@umich.edu cpu->removeThread(tid); 1432875Sksewell@umich.edu} 1442875Sksewell@umich.edu 1452875Sksewell@umich.edutemplate <class Impl> 1462875Sksewell@umich.educonst char * 1475336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 1482875Sksewell@umich.edu{ 1494873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 1502875Sksewell@umich.edu} 1512875Sksewell@umich.edu 1522875Sksewell@umich.edutemplate <class Impl> 1535595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1542733Sktlim@umich.edu : BaseO3CPU(params), 1553781Sgblack@eecs.umich.edu itb(params->itb), 1563781Sgblack@eecs.umich.edu dtb(params->dtb), 1571060SN/A tickEvent(this), 1582292SN/A removeInstsThisCycle(false), 1595595Sgblack@eecs.umich.edu fetch(this, params), 1605595Sgblack@eecs.umich.edu decode(this, params), 1615595Sgblack@eecs.umich.edu rename(this, params), 1625595Sgblack@eecs.umich.edu iew(this, params), 1635595Sgblack@eecs.umich.edu commit(this, params), 1641060SN/A 1655595Sgblack@eecs.umich.edu regFile(this, params->numPhysIntRegs, 1664329Sktlim@umich.edu params->numPhysFloatRegs), 1671060SN/A 1685529Snate@binkert.org freeList(params->numThreads, 1692292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1702292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1711060SN/A 1725595Sgblack@eecs.umich.edu rob(this, 1734329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 1742292SN/A params->smtROBPolicy, params->smtROBThreshold, 1755529Snate@binkert.org params->numThreads), 1761060SN/A 1775529Snate@binkert.org scoreboard(params->numThreads, 1782292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1792292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1802292SN/A TheISA::NumMiscRegs * number_of_threads, 1812292SN/A TheISA::ZeroReg), 1821060SN/A 1832873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1842873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1852873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1862873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1872873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1882873Sktlim@umich.edu activityRec(NumStages, 1892873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1902873Sktlim@umich.edu params->activity), 1911060SN/A 1921060SN/A globalSeqNum(1), 1931858SN/A#if FULL_SYSTEM 1942292SN/A system(params->system), 1951060SN/A physmem(system->physmem), 1961060SN/A#endif // FULL_SYSTEM 1972843Sktlim@umich.edu drainCount(0), 1985529Snate@binkert.org deferRegistration(params->defer_registration), 1992316SN/A numThreads(number_of_threads) 2001060SN/A{ 2013221Sktlim@umich.edu if (!deferRegistration) { 2023221Sktlim@umich.edu _status = Running; 2033221Sktlim@umich.edu } else { 2043221Sktlim@umich.edu _status = Idle; 2053221Sktlim@umich.edu } 2061681SN/A 2074598Sbinkertn@umich.edu#if USE_CHECKER 2082794Sktlim@umich.edu if (params->checker) { 2092316SN/A BaseCPU *temp_checker = params->checker; 2102316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2112316SN/A#if FULL_SYSTEM 2122316SN/A checker->setSystem(params->system); 2132316SN/A#endif 2144598Sbinkertn@umich.edu } else { 2154598Sbinkertn@umich.edu checker = NULL; 2164598Sbinkertn@umich.edu } 2172794Sktlim@umich.edu#endif // USE_CHECKER 2182316SN/A 2191858SN/A#if !FULL_SYSTEM 2202292SN/A thread.resize(number_of_threads); 2212292SN/A tids.resize(number_of_threads); 2221681SN/A#endif 2231681SN/A 2242325SN/A // The stages also need their CPU pointer setup. However this 2252325SN/A // must be done at the upper level CPU because they have pointers 2262325SN/A // to the upper level CPU, and not this FullO3CPU. 2271060SN/A 2282292SN/A // Set up Pointers to the activeThreads list for each stage 2292292SN/A fetch.setActiveThreads(&activeThreads); 2302292SN/A decode.setActiveThreads(&activeThreads); 2312292SN/A rename.setActiveThreads(&activeThreads); 2322292SN/A iew.setActiveThreads(&activeThreads); 2332292SN/A commit.setActiveThreads(&activeThreads); 2341060SN/A 2351060SN/A // Give each of the stages the time buffer they will use. 2361060SN/A fetch.setTimeBuffer(&timeBuffer); 2371060SN/A decode.setTimeBuffer(&timeBuffer); 2381060SN/A rename.setTimeBuffer(&timeBuffer); 2391060SN/A iew.setTimeBuffer(&timeBuffer); 2401060SN/A commit.setTimeBuffer(&timeBuffer); 2411060SN/A 2421060SN/A // Also setup each of the stages' queues. 2431060SN/A fetch.setFetchQueue(&fetchQueue); 2441060SN/A decode.setFetchQueue(&fetchQueue); 2452292SN/A commit.setFetchQueue(&fetchQueue); 2461060SN/A decode.setDecodeQueue(&decodeQueue); 2471060SN/A rename.setDecodeQueue(&decodeQueue); 2481060SN/A rename.setRenameQueue(&renameQueue); 2491060SN/A iew.setRenameQueue(&renameQueue); 2501060SN/A iew.setIEWQueue(&iewQueue); 2511060SN/A commit.setIEWQueue(&iewQueue); 2521060SN/A commit.setRenameQueue(&renameQueue); 2531060SN/A 2542292SN/A commit.setIEWStage(&iew); 2552292SN/A rename.setIEWStage(&iew); 2562292SN/A rename.setCommitStage(&commit); 2572292SN/A 2582292SN/A#if !FULL_SYSTEM 2592307SN/A int active_threads = params->workload.size(); 2602831Sksewell@umich.edu 2612831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2622831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2632831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2642831Sksewell@umich.edu "edit your workload size."); 2652831Sksewell@umich.edu } 2662292SN/A#else 2672307SN/A int active_threads = 1; 2682292SN/A#endif 2692292SN/A 2702316SN/A //Make Sure That this a Valid Architeture 2712292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2722292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2732292SN/A 2742292SN/A rename.setScoreboard(&scoreboard); 2752292SN/A iew.setScoreboard(&scoreboard); 2762292SN/A 2771060SN/A // Setup the rename map for whichever stages need it. 2782292SN/A PhysRegIndex lreg_idx = 0; 2792292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2801060SN/A 2812292SN/A for (int tid=0; tid < numThreads; tid++) { 2822307SN/A bool bindRegs = (tid <= active_threads - 1); 2832292SN/A 2842292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2852292SN/A params->numPhysIntRegs, 2862325SN/A lreg_idx, //Index for Logical. Regs 2872292SN/A 2882292SN/A TheISA::NumFloatRegs, 2892292SN/A params->numPhysFloatRegs, 2902325SN/A freg_idx, //Index for Float Regs 2912292SN/A 2922292SN/A TheISA::NumMiscRegs, 2932292SN/A 2942292SN/A TheISA::ZeroReg, 2952292SN/A TheISA::ZeroReg, 2962292SN/A 2972292SN/A tid, 2982292SN/A false); 2992292SN/A 3002292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3012292SN/A params->numPhysIntRegs, 3022325SN/A lreg_idx, //Index for Logical. Regs 3032292SN/A 3042292SN/A TheISA::NumFloatRegs, 3052292SN/A params->numPhysFloatRegs, 3062325SN/A freg_idx, //Index for Float Regs 3072292SN/A 3082292SN/A TheISA::NumMiscRegs, 3092292SN/A 3102292SN/A TheISA::ZeroReg, 3112292SN/A TheISA::ZeroReg, 3122292SN/A 3132292SN/A tid, 3142292SN/A bindRegs); 3153221Sktlim@umich.edu 3163221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3173221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3182292SN/A } 3192292SN/A 3202292SN/A rename.setRenameMap(renameMap); 3212292SN/A commit.setRenameMap(commitRenameMap); 3222292SN/A 3232292SN/A // Give renameMap & rename stage access to the freeList; 3242292SN/A for (int i=0; i < numThreads; i++) { 3252292SN/A renameMap[i].setFreeList(&freeList); 3262292SN/A } 3271060SN/A rename.setFreeList(&freeList); 3282292SN/A 3291060SN/A // Setup the ROB for whichever stages need it. 3301060SN/A commit.setROB(&rob); 3312292SN/A 3322292SN/A lastRunningCycle = curTick; 3332292SN/A 3342829Sksewell@umich.edu lastActivatedCycle = -1; 3352829Sksewell@umich.edu 3363093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3373093Sksewell@umich.edu //for (int i=0; i < numThreads; i++) { 3383093Sksewell@umich.edu //globalSeqNum[i] = 1; 3393093Sksewell@umich.edu //} 3403093Sksewell@umich.edu 3412292SN/A contextSwitch = false; 3425595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3435595Sgblack@eecs.umich.edu 3445595Sgblack@eecs.umich.edu // Setup any thread state. 3455595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3465595Sgblack@eecs.umich.edu 3475595Sgblack@eecs.umich.edu for (int i = 0; i < this->numThreads; ++i) { 3485595Sgblack@eecs.umich.edu#if FULL_SYSTEM 3495595Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3505595Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3515595Sgblack@eecs.umich.edu this->thread[i] = new Thread(this, 0); 3525595Sgblack@eecs.umich.edu this->thread[i]->setStatus(ThreadContext::Suspended); 3535595Sgblack@eecs.umich.edu#else 3545595Sgblack@eecs.umich.edu if (i < params->workload.size()) { 3555595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3565595Sgblack@eecs.umich.edu i, this->thread[i]); 3575595Sgblack@eecs.umich.edu this->thread[i] = new typename FullO3CPU<Impl>::Thread( 3585595Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3595595Sgblack@eecs.umich.edu i, params->workload[i], i); 3605595Sgblack@eecs.umich.edu 3615595Sgblack@eecs.umich.edu this->thread[i]->setStatus(ThreadContext::Suspended); 3625595Sgblack@eecs.umich.edu 3635595Sgblack@eecs.umich.edu //usedTids[i] = true; 3645595Sgblack@eecs.umich.edu //threadMap[i] = i; 3655595Sgblack@eecs.umich.edu } else { 3665595Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3675595Sgblack@eecs.umich.edu //when scheduling threads to CPU 3685595Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3695595Sgblack@eecs.umich.edu 3705595Sgblack@eecs.umich.edu this->thread[i] = new typename FullO3CPU<Impl>::Thread( 3715595Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3725595Sgblack@eecs.umich.edu i, dummy_proc, i); 3735595Sgblack@eecs.umich.edu //usedTids[i] = false; 3745595Sgblack@eecs.umich.edu } 3755595Sgblack@eecs.umich.edu#endif // !FULL_SYSTEM 3765595Sgblack@eecs.umich.edu 3775595Sgblack@eecs.umich.edu ThreadContext *tc; 3785595Sgblack@eecs.umich.edu 3795595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3805595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3815595Sgblack@eecs.umich.edu 3825595Sgblack@eecs.umich.edu tc = o3_tc; 3835595Sgblack@eecs.umich.edu 3845595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3855595Sgblack@eecs.umich.edu // CheckerThreadContext. 3865595Sgblack@eecs.umich.edu#if USE_CHECKER 3875595Sgblack@eecs.umich.edu if (params->checker) { 3885595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3895595Sgblack@eecs.umich.edu o3_tc, this->checker); 3905595Sgblack@eecs.umich.edu } 3915595Sgblack@eecs.umich.edu#endif 3925595Sgblack@eecs.umich.edu 3935595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 3945595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 3955595Sgblack@eecs.umich.edu o3_tc->thread = this->thread[i]; 3965595Sgblack@eecs.umich.edu 3975595Sgblack@eecs.umich.edu#if FULL_SYSTEM 3985595Sgblack@eecs.umich.edu // Setup quiesce event. 3995595Sgblack@eecs.umich.edu this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc); 4005595Sgblack@eecs.umich.edu#endif 4015595Sgblack@eecs.umich.edu // Give the thread the TC. 4025595Sgblack@eecs.umich.edu this->thread[i]->tc = tc; 4035595Sgblack@eecs.umich.edu this->thread[i]->setCpuId(params->cpu_id); 4045595Sgblack@eecs.umich.edu 4055595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4065595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4075595Sgblack@eecs.umich.edu } 4085595Sgblack@eecs.umich.edu 4095595Sgblack@eecs.umich.edu for (int i=0; i < this->numThreads; i++) { 4105595Sgblack@eecs.umich.edu this->thread[i]->setFuncExeInst(0); 4115595Sgblack@eecs.umich.edu } 4125595Sgblack@eecs.umich.edu 4135595Sgblack@eecs.umich.edu lockAddr = 0; 4145595Sgblack@eecs.umich.edu lockFlag = false; 4151060SN/A} 4161060SN/A 4175595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 4185595Sgblack@eecs.umich.edu 4195595Sgblack@eecs.umich.edutemplate <class Impl> 4205595Sgblack@eecs.umich.eduTheISA::IntReg 4215595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getSyscallArg(int i, int tid) 4225595Sgblack@eecs.umich.edu{ 4235595Sgblack@eecs.umich.edu assert(i < TheISA::NumArgumentRegs); 4245595Sgblack@eecs.umich.edu TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), 4255595Sgblack@eecs.umich.edu TheISA::ArgumentReg[i]); 4265595Sgblack@eecs.umich.edu TheISA::IntReg val = this->readArchIntReg(idx, tid); 4275595Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 4285595Sgblack@eecs.umich.edu if (bits(this->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE, tid), 3, 3)) 4295595Sgblack@eecs.umich.edu val = bits(val, 31, 0); 4305595Sgblack@eecs.umich.edu#endif 4315595Sgblack@eecs.umich.edu return val; 4325595Sgblack@eecs.umich.edu} 4335595Sgblack@eecs.umich.edu 4345595Sgblack@eecs.umich.edutemplate <class Impl> 4355595Sgblack@eecs.umich.eduvoid 4365595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid) 4375595Sgblack@eecs.umich.edu{ 4385595Sgblack@eecs.umich.edu assert(i < TheISA::NumArgumentRegs); 4395595Sgblack@eecs.umich.edu TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), 4405595Sgblack@eecs.umich.edu TheISA::ArgumentReg[i]); 4415595Sgblack@eecs.umich.edu this->setArchIntReg(idx, val, tid); 4425595Sgblack@eecs.umich.edu} 4435595Sgblack@eecs.umich.edu#endif 4445595Sgblack@eecs.umich.edu 4451060SN/Atemplate <class Impl> 4461755SN/AFullO3CPU<Impl>::~FullO3CPU() 4471060SN/A{ 4481060SN/A} 4491060SN/A 4501060SN/Atemplate <class Impl> 4511060SN/Avoid 4525595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4531062SN/A{ 4542733Sktlim@umich.edu BaseO3CPU::regStats(); 4552292SN/A 4562733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4572292SN/A timesIdled 4582292SN/A .name(name() + ".timesIdled") 4592292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4602292SN/A " unscheduled itself") 4612292SN/A .prereq(timesIdled); 4622292SN/A 4632292SN/A idleCycles 4642292SN/A .name(name() + ".idleCycles") 4652292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4662292SN/A "to idling") 4672292SN/A .prereq(idleCycles); 4682292SN/A 4692292SN/A // Number of Instructions simulated 4702292SN/A // -------------------------------- 4712292SN/A // Should probably be in Base CPU but need templated 4722292SN/A // MaxThreads so put in here instead 4732292SN/A committedInsts 4742292SN/A .init(numThreads) 4752292SN/A .name(name() + ".committedInsts") 4762292SN/A .desc("Number of Instructions Simulated"); 4772292SN/A 4782292SN/A totalCommittedInsts 4792292SN/A .name(name() + ".committedInsts_total") 4802292SN/A .desc("Number of Instructions Simulated"); 4812292SN/A 4822292SN/A cpi 4832292SN/A .name(name() + ".cpi") 4842292SN/A .desc("CPI: Cycles Per Instruction") 4852292SN/A .precision(6); 4864392Sktlim@umich.edu cpi = numCycles / committedInsts; 4872292SN/A 4882292SN/A totalCpi 4892292SN/A .name(name() + ".cpi_total") 4902292SN/A .desc("CPI: Total CPI of All Threads") 4912292SN/A .precision(6); 4924392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 4932292SN/A 4942292SN/A ipc 4952292SN/A .name(name() + ".ipc") 4962292SN/A .desc("IPC: Instructions Per Cycle") 4972292SN/A .precision(6); 4984392Sktlim@umich.edu ipc = committedInsts / numCycles; 4992292SN/A 5002292SN/A totalIpc 5012292SN/A .name(name() + ".ipc_total") 5022292SN/A .desc("IPC: Total IPC of All Threads") 5032292SN/A .precision(6); 5044392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 5052292SN/A 5065595Sgblack@eecs.umich.edu this->fetch.regStats(); 5075595Sgblack@eecs.umich.edu this->decode.regStats(); 5085595Sgblack@eecs.umich.edu this->rename.regStats(); 5095595Sgblack@eecs.umich.edu this->iew.regStats(); 5105595Sgblack@eecs.umich.edu this->commit.regStats(); 5111062SN/A} 5121062SN/A 5131062SN/Atemplate <class Impl> 5142871Sktlim@umich.eduPort * 5152871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 5162871Sktlim@umich.edu{ 5172871Sktlim@umich.edu if (if_name == "dcache_port") 5182871Sktlim@umich.edu return iew.getDcachePort(); 5192871Sktlim@umich.edu else if (if_name == "icache_port") 5202871Sktlim@umich.edu return fetch.getIcachePort(); 5212871Sktlim@umich.edu else 5222871Sktlim@umich.edu panic("No Such Port\n"); 5232871Sktlim@umich.edu} 5242871Sktlim@umich.edu 5252871Sktlim@umich.edutemplate <class Impl> 5261062SN/Avoid 5271755SN/AFullO3CPU<Impl>::tick() 5281060SN/A{ 5292733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5301060SN/A 5312292SN/A ++numCycles; 5322292SN/A 5332325SN/A// activity = false; 5342292SN/A 5352292SN/A //Tick each of the stages 5361060SN/A fetch.tick(); 5371060SN/A 5381060SN/A decode.tick(); 5391060SN/A 5401060SN/A rename.tick(); 5411060SN/A 5421060SN/A iew.tick(); 5431060SN/A 5441060SN/A commit.tick(); 5451060SN/A 5462292SN/A#if !FULL_SYSTEM 5472292SN/A doContextSwitch(); 5482292SN/A#endif 5492292SN/A 5502292SN/A // Now advance the time buffers 5511060SN/A timeBuffer.advance(); 5521060SN/A 5531060SN/A fetchQueue.advance(); 5541060SN/A decodeQueue.advance(); 5551060SN/A renameQueue.advance(); 5561060SN/A iewQueue.advance(); 5571060SN/A 5582325SN/A activityRec.advance(); 5592292SN/A 5602292SN/A if (removeInstsThisCycle) { 5612292SN/A cleanUpRemovedInsts(); 5622292SN/A } 5632292SN/A 5642325SN/A if (!tickEvent.scheduled()) { 5652867Sktlim@umich.edu if (_status == SwitchedOut || 5662905Sktlim@umich.edu getState() == SimObject::Drained) { 5673226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 5682325SN/A // increment stat 5692325SN/A lastRunningCycle = curTick; 5703221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 5713226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 5722325SN/A lastRunningCycle = curTick; 5732325SN/A timesIdled++; 5742325SN/A } else { 5755606Snate@binkert.org schedule(tickEvent, nextCycle(curTick + ticks(1))); 5763226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 5772325SN/A } 5782292SN/A } 5792292SN/A 5802292SN/A#if !FULL_SYSTEM 5812292SN/A updateThreadPriority(); 5822292SN/A#endif 5831060SN/A} 5841060SN/A 5851060SN/Atemplate <class Impl> 5861060SN/Avoid 5871755SN/AFullO3CPU<Impl>::init() 5881060SN/A{ 5892307SN/A if (!deferRegistration) { 5902680Sktlim@umich.edu registerThreadContexts(); 5912292SN/A } 5921060SN/A 5932292SN/A // Set inSyscall so that the CPU doesn't squash when initially 5942292SN/A // setting up registers. 5952292SN/A for (int i = 0; i < number_of_threads; ++i) 5962292SN/A thread[i]->inSyscall = true; 5972292SN/A 5982292SN/A for (int tid=0; tid < number_of_threads; tid++) { 5991858SN/A#if FULL_SYSTEM 6002680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 6011681SN/A#else 6022680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 6031681SN/A#endif 6042292SN/A // Threads start in the Suspended State 6052680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 6062292SN/A continue; 6071060SN/A } 6081060SN/A 6092292SN/A#if FULL_SYSTEM 6102680Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 6112292SN/A#endif 6122292SN/A } 6132292SN/A 6142292SN/A // Clear inSyscall. 6152292SN/A for (int i = 0; i < number_of_threads; ++i) 6162292SN/A thread[i]->inSyscall = false; 6172292SN/A 6182316SN/A // Initialize stages. 6192292SN/A fetch.initStage(); 6202292SN/A iew.initStage(); 6212292SN/A rename.initStage(); 6222292SN/A commit.initStage(); 6232292SN/A 6242292SN/A commit.setThreads(thread); 6252292SN/A} 6262292SN/A 6272292SN/Atemplate <class Impl> 6282292SN/Avoid 6292875Sksewell@umich.eduFullO3CPU<Impl>::activateThread(unsigned tid) 6302875Sksewell@umich.edu{ 6315314Sstever@gmail.com std::list<unsigned>::iterator isActive = 6325314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6332875Sksewell@umich.edu 6343226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6353226Sktlim@umich.edu 6362875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6372875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6382875Sksewell@umich.edu tid); 6392875Sksewell@umich.edu 6402875Sksewell@umich.edu activeThreads.push_back(tid); 6412875Sksewell@umich.edu } 6422875Sksewell@umich.edu} 6432875Sksewell@umich.edu 6442875Sksewell@umich.edutemplate <class Impl> 6452875Sksewell@umich.eduvoid 6462875Sksewell@umich.eduFullO3CPU<Impl>::deactivateThread(unsigned tid) 6472875Sksewell@umich.edu{ 6482875Sksewell@umich.edu //Remove From Active List, if Active 6495314Sstever@gmail.com std::list<unsigned>::iterator thread_it = 6505314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6512875Sksewell@umich.edu 6523226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 6533226Sktlim@umich.edu 6542875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6552875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6562875Sksewell@umich.edu tid); 6572875Sksewell@umich.edu activeThreads.erase(thread_it); 6582875Sksewell@umich.edu } 6592875Sksewell@umich.edu} 6602875Sksewell@umich.edu 6612875Sksewell@umich.edutemplate <class Impl> 6622875Sksewell@umich.eduvoid 6632875Sksewell@umich.eduFullO3CPU<Impl>::activateContext(int tid, int delay) 6642875Sksewell@umich.edu{ 6652875Sksewell@umich.edu // Needs to set each stage to running as well. 6662875Sksewell@umich.edu if (delay){ 6672875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 6685100Ssaidi@eecs.umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 6692875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 6702875Sksewell@umich.edu } else { 6712875Sksewell@umich.edu activateThread(tid); 6722875Sksewell@umich.edu } 6732875Sksewell@umich.edu 6743221Sktlim@umich.edu if (lastActivatedCycle < curTick) { 6752875Sksewell@umich.edu scheduleTickEvent(delay); 6762875Sksewell@umich.edu 6772875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 6782875Sksewell@umich.edu // deschedule itself. 6792875Sksewell@umich.edu activityRec.activity(); 6802875Sksewell@umich.edu fetch.wakeFromQuiesce(); 6812875Sksewell@umich.edu 6822875Sksewell@umich.edu lastActivatedCycle = curTick; 6832875Sksewell@umich.edu 6842875Sksewell@umich.edu _status = Running; 6852875Sksewell@umich.edu } 6862875Sksewell@umich.edu} 6872875Sksewell@umich.edu 6882875Sksewell@umich.edutemplate <class Impl> 6893221Sktlim@umich.edubool 6903221Sktlim@umich.eduFullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay) 6912875Sksewell@umich.edu{ 6922875Sksewell@umich.edu // Schedule removal of thread data from CPU 6932875Sksewell@umich.edu if (delay){ 6942875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 6955100Ssaidi@eecs.umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 6963221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 6973221Sktlim@umich.edu return false; 6982875Sksewell@umich.edu } else { 6992875Sksewell@umich.edu deactivateThread(tid); 7003221Sktlim@umich.edu if (remove) 7013221Sktlim@umich.edu removeThread(tid); 7023221Sktlim@umich.edu return true; 7032875Sksewell@umich.edu } 7042875Sksewell@umich.edu} 7052875Sksewell@umich.edu 7062875Sksewell@umich.edutemplate <class Impl> 7072875Sksewell@umich.eduvoid 7082875Sksewell@umich.eduFullO3CPU<Impl>::suspendContext(int tid) 7092875Sksewell@umich.edu{ 7102875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7113221Sktlim@umich.edu bool deallocated = deallocateContext(tid, false, 1); 7123221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 7135570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 7143859Sbinkertn@umich.edu activeThreads.size() == 0) 7152910Sksewell@umich.edu unscheduleTickEvent(); 7162875Sksewell@umich.edu _status = Idle; 7172875Sksewell@umich.edu} 7182875Sksewell@umich.edu 7192875Sksewell@umich.edutemplate <class Impl> 7202875Sksewell@umich.eduvoid 7212875Sksewell@umich.eduFullO3CPU<Impl>::haltContext(int tid) 7222875Sksewell@umich.edu{ 7232910Sksewell@umich.edu //For now, this is the same as deallocate 7242910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 7253221Sktlim@umich.edu deallocateContext(tid, true, 1); 7262875Sksewell@umich.edu} 7272875Sksewell@umich.edu 7282875Sksewell@umich.edutemplate <class Impl> 7292875Sksewell@umich.eduvoid 7302292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 7312292SN/A{ 7322847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 7332292SN/A // Will change now that the PC and thread state is internal to the CPU 7342683Sktlim@umich.edu // and not in the ThreadContext. 7352292SN/A#if FULL_SYSTEM 7362680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 7372292SN/A#else 7382847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 7392292SN/A#endif 7402292SN/A 7412292SN/A //Bind Int Regs to Rename Map 7422292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7432292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 7442292SN/A 7452292SN/A renameMap[tid].setEntry(ireg,phys_reg); 7462292SN/A scoreboard.setReg(phys_reg); 7472292SN/A } 7482292SN/A 7492292SN/A //Bind Float Regs to Rename Map 7502292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 7512292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 7522292SN/A 7532292SN/A renameMap[tid].setEntry(freg,phys_reg); 7542292SN/A scoreboard.setReg(phys_reg); 7552292SN/A } 7562292SN/A 7572292SN/A //Copy Thread Data Into RegFile 7582847Sksewell@umich.edu //this->copyFromTC(tid); 7592292SN/A 7602847Sksewell@umich.edu //Set PC/NPC/NNPC 7612847Sksewell@umich.edu setPC(src_tc->readPC(), tid); 7622847Sksewell@umich.edu setNextPC(src_tc->readNextPC(), tid); 7632847Sksewell@umich.edu setNextNPC(src_tc->readNextNPC(), tid); 7642292SN/A 7652680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 7662292SN/A 7672292SN/A activateContext(tid,1); 7682292SN/A 7692292SN/A //Reset ROB/IQ/LSQ Entries 7702292SN/A commit.rob->resetEntries(); 7712292SN/A iew.resetEntries(); 7722292SN/A} 7732292SN/A 7742292SN/Atemplate <class Impl> 7752292SN/Avoid 7762292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 7772292SN/A{ 7782877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 7792847Sksewell@umich.edu 7802847Sksewell@umich.edu // Copy Thread Data From RegFile 7812847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 7825364Sksewell@umich.edu // this->copyToTC(tid); 7835364Sksewell@umich.edu 7845364Sksewell@umich.edu 7855364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 7865364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 7875364Sksewell@umich.edu // in SMT workloads. 7882847Sksewell@umich.edu 7892847Sksewell@umich.edu // Unbind Int Regs from Rename Map 7902292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7912292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 7922292SN/A 7932292SN/A scoreboard.unsetReg(phys_reg); 7942292SN/A freeList.addReg(phys_reg); 7952292SN/A } 7962292SN/A 7972847Sksewell@umich.edu // Unbind Float Regs from Rename Map 7985362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 7992292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 8002292SN/A 8012292SN/A scoreboard.unsetReg(phys_reg); 8022292SN/A freeList.addReg(phys_reg); 8032292SN/A } 8042292SN/A 8052847Sksewell@umich.edu // Squash Throughout Pipeline 8062935Sksewell@umich.edu InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 8074636Sgblack@eecs.umich.edu fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid); 8082292SN/A decode.squash(tid); 8092935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 8102875Sksewell@umich.edu iew.squash(tid); 8115363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 8122935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 8132292SN/A 8145362Sksewell@umich.edu 8155362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 8162292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 8172292SN/A 8182847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 8193229Sktlim@umich.edu 8203229Sktlim@umich.edu // Commented out for now. This should be possible to do by 8213229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 8223229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 8233229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 8243229Sktlim@umich.edu/* 8252292SN/A if (activeThreads.size() >= 1) { 8262292SN/A commit.rob->resetEntries(); 8272292SN/A iew.resetEntries(); 8282292SN/A } 8293229Sktlim@umich.edu*/ 8302292SN/A} 8312292SN/A 8322292SN/A 8332292SN/Atemplate <class Impl> 8342292SN/Avoid 8352292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 8362292SN/A{ 8372733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 8382292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 8392292SN/A tid); 8402292SN/A 8412292SN/A bool ready = true; 8422292SN/A 8432292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 8442733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8452292SN/A "Phys. Int. Regs.\n", 8462292SN/A tid); 8472292SN/A ready = false; 8482292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 8492733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8502292SN/A "Phys. Float. Regs.\n", 8512292SN/A tid); 8522292SN/A ready = false; 8532292SN/A } else if (commit.rob->numFreeEntries() >= 8542292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 8552733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8562292SN/A "ROB entries.\n", 8572292SN/A tid); 8582292SN/A ready = false; 8592292SN/A } else if (iew.instQueue.numFreeEntries() >= 8602292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 8612733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8622292SN/A "IQ entries.\n", 8632292SN/A tid); 8642292SN/A ready = false; 8652292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 8662292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 8672733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8682292SN/A "LSQ entries.\n", 8692292SN/A tid); 8702292SN/A ready = false; 8712292SN/A } 8722292SN/A 8732292SN/A if (ready) { 8742292SN/A insertThread(tid); 8752292SN/A 8762292SN/A contextSwitch = false; 8772292SN/A 8782292SN/A cpuWaitList.remove(tid); 8792292SN/A } else { 8802292SN/A suspendContext(tid); 8812292SN/A 8822292SN/A //blocks fetch 8832292SN/A contextSwitch = true; 8842292SN/A 8852875Sksewell@umich.edu //@todo: dont always add to waitlist 8862292SN/A //do waitlist 8872292SN/A cpuWaitList.push_back(tid); 8881060SN/A } 8891060SN/A} 8901060SN/A 8914192Sktlim@umich.edu#if FULL_SYSTEM 8924192Sktlim@umich.edutemplate <class Impl> 8934192Sktlim@umich.eduvoid 8945595Sgblack@eecs.umich.eduFullO3CPU<Impl>::post_interrupt(int int_num, int index) 8955595Sgblack@eecs.umich.edu{ 8965595Sgblack@eecs.umich.edu BaseCPU::post_interrupt(int_num, index); 8975595Sgblack@eecs.umich.edu 8985595Sgblack@eecs.umich.edu if (this->thread[0]->status() == ThreadContext::Suspended) { 8995595Sgblack@eecs.umich.edu DPRINTF(IPI,"Suspended Processor awoke\n"); 9005595Sgblack@eecs.umich.edu this->threadContexts[0]->activate(); 9015595Sgblack@eecs.umich.edu } 9025595Sgblack@eecs.umich.edu} 9035595Sgblack@eecs.umich.edu 9045595Sgblack@eecs.umich.edutemplate <class Impl> 9055595Sgblack@eecs.umich.eduFault 9065595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 9075595Sgblack@eecs.umich.edu{ 9085595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 9095647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 9105595Sgblack@eecs.umich.edu} 9115595Sgblack@eecs.umich.edu 9125595Sgblack@eecs.umich.edutemplate <class Impl> 9135595Sgblack@eecs.umich.eduvoid 9145595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 9155595Sgblack@eecs.umich.edu{ 9165595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 9175595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 9185595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9195595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9205595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9215595Sgblack@eecs.umich.edu 9225595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 9235647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 9245595Sgblack@eecs.umich.edu 9255595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 9265595Sgblack@eecs.umich.edu this->trap(interrupt, 0); 9275595Sgblack@eecs.umich.edu} 9285595Sgblack@eecs.umich.edu 9295595Sgblack@eecs.umich.edutemplate <class Impl> 9305595Sgblack@eecs.umich.eduvoid 9314192Sktlim@umich.eduFullO3CPU<Impl>::updateMemPorts() 9324192Sktlim@umich.edu{ 9334192Sktlim@umich.edu // Update all ThreadContext's memory ports (Functional/Virtual 9344192Sktlim@umich.edu // Ports) 9354192Sktlim@umich.edu for (int i = 0; i < thread.size(); ++i) 9365497Ssaidi@eecs.umich.edu thread[i]->connectMemPorts(thread[i]->getTC()); 9374192Sktlim@umich.edu} 9384192Sktlim@umich.edu#endif 9394192Sktlim@umich.edu 9401060SN/Atemplate <class Impl> 9412852Sktlim@umich.eduvoid 9425595Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, unsigned tid) 9435595Sgblack@eecs.umich.edu{ 9445595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 9455595Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid]); 9465595Sgblack@eecs.umich.edu} 9475595Sgblack@eecs.umich.edu 9485595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 9495595Sgblack@eecs.umich.edu 9505595Sgblack@eecs.umich.edutemplate <class Impl> 9515595Sgblack@eecs.umich.eduvoid 9525595Sgblack@eecs.umich.eduFullO3CPU<Impl>::syscall(int64_t callnum, int tid) 9535595Sgblack@eecs.umich.edu{ 9545595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 9555595Sgblack@eecs.umich.edu 9565595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 9575595Sgblack@eecs.umich.edu 9585595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 9595595Sgblack@eecs.umich.edu // instruction. 9605595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 9615595Sgblack@eecs.umich.edu 9625595Sgblack@eecs.umich.edu // Execute the actual syscall. 9635595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 9645595Sgblack@eecs.umich.edu 9655595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 9665595Sgblack@eecs.umich.edu // incrementing it. 9675595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 9685595Sgblack@eecs.umich.edu} 9695595Sgblack@eecs.umich.edu 9705595Sgblack@eecs.umich.edutemplate <class Impl> 9715595Sgblack@eecs.umich.eduvoid 9725595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid) 9735595Sgblack@eecs.umich.edu{ 9745595Sgblack@eecs.umich.edu TheISA::setSyscallReturn(return_value, this->tcBase(tid)); 9755595Sgblack@eecs.umich.edu} 9765595Sgblack@eecs.umich.edu 9775595Sgblack@eecs.umich.edu#endif 9785595Sgblack@eecs.umich.edu 9795595Sgblack@eecs.umich.edutemplate <class Impl> 9805595Sgblack@eecs.umich.eduvoid 9812864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 9822864Sktlim@umich.edu{ 9832918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 9842918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 9852864Sktlim@umich.edu BaseCPU::serialize(os); 9862864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 9872864Sktlim@umich.edu tickEvent.serialize(os); 9882864Sktlim@umich.edu 9892864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 9902864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 9912864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 9922864Sktlim@umich.edu static SimpleThread temp; 9932864Sktlim@umich.edu 9942864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 9952864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 9962864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 9972864Sktlim@umich.edu temp.serialize(os); 9982864Sktlim@umich.edu } 9992864Sktlim@umich.edu} 10002864Sktlim@umich.edu 10012864Sktlim@umich.edutemplate <class Impl> 10022864Sktlim@umich.eduvoid 10032864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 10042864Sktlim@umich.edu{ 10052918Sktlim@umich.edu SimObject::State so_state; 10062918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 10072864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 10082864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 10092864Sktlim@umich.edu 10102864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10112864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 10122864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10132864Sktlim@umich.edu static SimpleThread temp; 10142864Sktlim@umich.edu 10152864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 10162864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10172864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 10182864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 10192864Sktlim@umich.edu } 10202864Sktlim@umich.edu} 10212864Sktlim@umich.edu 10222864Sktlim@umich.edutemplate <class Impl> 10232905Sktlim@umich.eduunsigned int 10242843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 10251060SN/A{ 10263125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 10273512Sktlim@umich.edu 10283512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 10293512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 10303512Sktlim@umich.edu return 0; 10313512Sktlim@umich.edu } 10323512Sktlim@umich.edu 10332843Sktlim@umich.edu drainCount = 0; 10342843Sktlim@umich.edu fetch.drain(); 10352843Sktlim@umich.edu decode.drain(); 10362843Sktlim@umich.edu rename.drain(); 10372843Sktlim@umich.edu iew.drain(); 10382843Sktlim@umich.edu commit.drain(); 10392325SN/A 10402325SN/A // Wake the CPU and record activity so everything can drain out if 10412863Sktlim@umich.edu // the CPU was not able to immediately drain. 10422905Sktlim@umich.edu if (getState() != SimObject::Drained) { 10432864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 10442864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 10452864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 10462864Sktlim@umich.edu // process on the drain event. 10472864Sktlim@umich.edu drainEvent = drain_event; 10482843Sktlim@umich.edu 10492863Sktlim@umich.edu wakeCPU(); 10502863Sktlim@umich.edu activityRec.activity(); 10512852Sktlim@umich.edu 10522905Sktlim@umich.edu return 1; 10532863Sktlim@umich.edu } else { 10542905Sktlim@umich.edu return 0; 10552863Sktlim@umich.edu } 10562316SN/A} 10572310SN/A 10582316SN/Atemplate <class Impl> 10592316SN/Avoid 10602843Sktlim@umich.eduFullO3CPU<Impl>::resume() 10612316SN/A{ 10622843Sktlim@umich.edu fetch.resume(); 10632843Sktlim@umich.edu decode.resume(); 10642843Sktlim@umich.edu rename.resume(); 10652843Sktlim@umich.edu iew.resume(); 10662843Sktlim@umich.edu commit.resume(); 10672316SN/A 10682905Sktlim@umich.edu changeState(SimObject::Running); 10692905Sktlim@umich.edu 10702864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 10712864Sktlim@umich.edu return; 10722864Sktlim@umich.edu 10733319Shsul@eecs.umich.edu#if FULL_SYSTEM 10744762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 10753319Shsul@eecs.umich.edu#endif 10763319Shsul@eecs.umich.edu 10772843Sktlim@umich.edu if (!tickEvent.scheduled()) 10785606Snate@binkert.org schedule(tickEvent, nextCycle()); 10792843Sktlim@umich.edu _status = Running; 10802843Sktlim@umich.edu} 10812316SN/A 10822843Sktlim@umich.edutemplate <class Impl> 10832843Sktlim@umich.eduvoid 10842843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 10852843Sktlim@umich.edu{ 10862843Sktlim@umich.edu if (++drainCount == NumStages) { 10872316SN/A if (tickEvent.scheduled()) 10882316SN/A tickEvent.squash(); 10892863Sktlim@umich.edu 10902905Sktlim@umich.edu changeState(SimObject::Drained); 10912863Sktlim@umich.edu 10923126Sktlim@umich.edu BaseCPU::switchOut(); 10933126Sktlim@umich.edu 10942863Sktlim@umich.edu if (drainEvent) { 10952863Sktlim@umich.edu drainEvent->process(); 10962863Sktlim@umich.edu drainEvent = NULL; 10972863Sktlim@umich.edu } 10982310SN/A } 10992843Sktlim@umich.edu assert(drainCount <= 5); 11002843Sktlim@umich.edu} 11012843Sktlim@umich.edu 11022843Sktlim@umich.edutemplate <class Impl> 11032843Sktlim@umich.eduvoid 11042843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11052843Sktlim@umich.edu{ 11062843Sktlim@umich.edu fetch.switchOut(); 11072843Sktlim@umich.edu rename.switchOut(); 11082325SN/A iew.switchOut(); 11092843Sktlim@umich.edu commit.switchOut(); 11102843Sktlim@umich.edu instList.clear(); 11112843Sktlim@umich.edu while (!removeList.empty()) { 11122843Sktlim@umich.edu removeList.pop(); 11132843Sktlim@umich.edu } 11142843Sktlim@umich.edu 11152843Sktlim@umich.edu _status = SwitchedOut; 11162843Sktlim@umich.edu#if USE_CHECKER 11172843Sktlim@umich.edu if (checker) 11182843Sktlim@umich.edu checker->switchOut(); 11192843Sktlim@umich.edu#endif 11203126Sktlim@umich.edu if (tickEvent.scheduled()) 11213126Sktlim@umich.edu tickEvent.squash(); 11221060SN/A} 11231060SN/A 11241060SN/Atemplate <class Impl> 11251060SN/Avoid 11261755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 11271060SN/A{ 11282325SN/A // Flush out any old data from the time buffers. 11292873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 11302307SN/A timeBuffer.advance(); 11312307SN/A fetchQueue.advance(); 11322307SN/A decodeQueue.advance(); 11332307SN/A renameQueue.advance(); 11342307SN/A iewQueue.advance(); 11352307SN/A } 11362307SN/A 11372325SN/A activityRec.reset(); 11382307SN/A 11394192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 11401060SN/A 11412307SN/A fetch.takeOverFrom(); 11422307SN/A decode.takeOverFrom(); 11432307SN/A rename.takeOverFrom(); 11442307SN/A iew.takeOverFrom(); 11452307SN/A commit.takeOverFrom(); 11462307SN/A 11471060SN/A assert(!tickEvent.scheduled()); 11481060SN/A 11492325SN/A // @todo: Figure out how to properly select the tid to put onto 11502325SN/A // the active threads list. 11512307SN/A int tid = 0; 11522307SN/A 11535314Sstever@gmail.com std::list<unsigned>::iterator isActive = 11545314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 11552307SN/A 11562307SN/A if (isActive == activeThreads.end()) { 11572325SN/A //May Need to Re-code this if the delay variable is the delay 11582325SN/A //needed for thread to activate 11592733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 11602307SN/A tid); 11612307SN/A 11622307SN/A activeThreads.push_back(tid); 11632307SN/A } 11642307SN/A 11652325SN/A // Set all statuses to active, schedule the CPU's tick event. 11662307SN/A // @todo: Fix up statuses so this is handled properly 11672680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 11682680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 11692680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 11701681SN/A _status = Running; 11715606Snate@binkert.org schedule(tickEvent, nextCycle()); 11721681SN/A } 11731060SN/A } 11742307SN/A if (!tickEvent.scheduled()) 11755606Snate@binkert.org schedule(tickEvent, nextCycle()); 11761060SN/A} 11771060SN/A 11781060SN/Atemplate <class Impl> 11795595Sgblack@eecs.umich.eduTheISA::MiscReg 11805595Sgblack@eecs.umich.eduFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid) 11815595Sgblack@eecs.umich.edu{ 11825595Sgblack@eecs.umich.edu return this->regFile.readMiscRegNoEffect(misc_reg, tid); 11835595Sgblack@eecs.umich.edu} 11845595Sgblack@eecs.umich.edu 11855595Sgblack@eecs.umich.edutemplate <class Impl> 11865595Sgblack@eecs.umich.eduTheISA::MiscReg 11875595Sgblack@eecs.umich.eduFullO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) 11885595Sgblack@eecs.umich.edu{ 11895595Sgblack@eecs.umich.edu return this->regFile.readMiscReg(misc_reg, tid); 11905595Sgblack@eecs.umich.edu} 11915595Sgblack@eecs.umich.edu 11925595Sgblack@eecs.umich.edutemplate <class Impl> 11935595Sgblack@eecs.umich.eduvoid 11945595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 11955595Sgblack@eecs.umich.edu const TheISA::MiscReg &val, unsigned tid) 11965595Sgblack@eecs.umich.edu{ 11975595Sgblack@eecs.umich.edu this->regFile.setMiscRegNoEffect(misc_reg, val, tid); 11985595Sgblack@eecs.umich.edu} 11995595Sgblack@eecs.umich.edu 12005595Sgblack@eecs.umich.edutemplate <class Impl> 12015595Sgblack@eecs.umich.eduvoid 12025595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 12035595Sgblack@eecs.umich.edu const TheISA::MiscReg &val, unsigned tid) 12045595Sgblack@eecs.umich.edu{ 12055595Sgblack@eecs.umich.edu this->regFile.setMiscReg(misc_reg, val, tid); 12065595Sgblack@eecs.umich.edu} 12075595Sgblack@eecs.umich.edu 12085595Sgblack@eecs.umich.edutemplate <class Impl> 12091060SN/Auint64_t 12101755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 12111060SN/A{ 12121060SN/A return regFile.readIntReg(reg_idx); 12131060SN/A} 12141060SN/A 12151060SN/Atemplate <class Impl> 12162455SN/AFloatReg 12172455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 12181060SN/A{ 12192455SN/A return regFile.readFloatReg(reg_idx, width); 12201060SN/A} 12211060SN/A 12221060SN/Atemplate <class Impl> 12232455SN/AFloatReg 12242455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 12251060SN/A{ 12262455SN/A return regFile.readFloatReg(reg_idx); 12271060SN/A} 12281060SN/A 12291060SN/Atemplate <class Impl> 12302455SN/AFloatRegBits 12312455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 12321060SN/A{ 12332455SN/A return regFile.readFloatRegBits(reg_idx, width); 12342455SN/A} 12352455SN/A 12362455SN/Atemplate <class Impl> 12372455SN/AFloatRegBits 12382455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 12392455SN/A{ 12402455SN/A return regFile.readFloatRegBits(reg_idx); 12411060SN/A} 12421060SN/A 12431060SN/Atemplate <class Impl> 12441060SN/Avoid 12451755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 12461060SN/A{ 12471060SN/A regFile.setIntReg(reg_idx, val); 12481060SN/A} 12491060SN/A 12501060SN/Atemplate <class Impl> 12511060SN/Avoid 12522455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 12531060SN/A{ 12542455SN/A regFile.setFloatReg(reg_idx, val, width); 12551060SN/A} 12561060SN/A 12571060SN/Atemplate <class Impl> 12581060SN/Avoid 12592455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 12601060SN/A{ 12612455SN/A regFile.setFloatReg(reg_idx, val); 12621060SN/A} 12631060SN/A 12641060SN/Atemplate <class Impl> 12651060SN/Avoid 12662455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 12671060SN/A{ 12682455SN/A regFile.setFloatRegBits(reg_idx, val, width); 12692455SN/A} 12702455SN/A 12712455SN/Atemplate <class Impl> 12722455SN/Avoid 12732455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 12742455SN/A{ 12752455SN/A regFile.setFloatRegBits(reg_idx, val); 12761060SN/A} 12771060SN/A 12781060SN/Atemplate <class Impl> 12791060SN/Auint64_t 12802292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 12811060SN/A{ 12822292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 12832292SN/A 12842292SN/A return regFile.readIntReg(phys_reg); 12852292SN/A} 12862292SN/A 12872292SN/Atemplate <class Impl> 12882292SN/Afloat 12892292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 12902292SN/A{ 12912307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 12922307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 12932292SN/A 12942669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 12952292SN/A} 12962292SN/A 12972292SN/Atemplate <class Impl> 12982292SN/Adouble 12992292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 13002292SN/A{ 13012307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 13022307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13032292SN/A 13042669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 13052292SN/A} 13062292SN/A 13072292SN/Atemplate <class Impl> 13082292SN/Auint64_t 13092292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 13102292SN/A{ 13112307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 13122307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13132292SN/A 13142669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13151060SN/A} 13161060SN/A 13171060SN/Atemplate <class Impl> 13181060SN/Avoid 13192292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 13201060SN/A{ 13212292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13222292SN/A 13232292SN/A regFile.setIntReg(phys_reg, val); 13241060SN/A} 13251060SN/A 13261060SN/Atemplate <class Impl> 13271060SN/Avoid 13282292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 13291060SN/A{ 13302918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 13312918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13322292SN/A 13332669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 13341060SN/A} 13351060SN/A 13361060SN/Atemplate <class Impl> 13371060SN/Avoid 13382292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 13391060SN/A{ 13402918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 13412918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13422292SN/A 13432669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 13441060SN/A} 13451060SN/A 13461060SN/Atemplate <class Impl> 13471060SN/Avoid 13482292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 13491060SN/A{ 13502918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 13512918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13521060SN/A 13532669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 13542292SN/A} 13552292SN/A 13562292SN/Atemplate <class Impl> 13572292SN/Auint64_t 13582292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 13592292SN/A{ 13602292SN/A return commit.readPC(tid); 13611060SN/A} 13621060SN/A 13631060SN/Atemplate <class Impl> 13641060SN/Avoid 13652292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 13661060SN/A{ 13672292SN/A commit.setPC(new_PC, tid); 13682292SN/A} 13691060SN/A 13702292SN/Atemplate <class Impl> 13712292SN/Auint64_t 13724636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readMicroPC(unsigned tid) 13734636Sgblack@eecs.umich.edu{ 13744636Sgblack@eecs.umich.edu return commit.readMicroPC(tid); 13754636Sgblack@eecs.umich.edu} 13764636Sgblack@eecs.umich.edu 13774636Sgblack@eecs.umich.edutemplate <class Impl> 13784636Sgblack@eecs.umich.eduvoid 13794636Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid) 13804636Sgblack@eecs.umich.edu{ 13814636Sgblack@eecs.umich.edu commit.setMicroPC(new_PC, tid); 13824636Sgblack@eecs.umich.edu} 13834636Sgblack@eecs.umich.edu 13844636Sgblack@eecs.umich.edutemplate <class Impl> 13854636Sgblack@eecs.umich.eduuint64_t 13862292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 13872292SN/A{ 13882292SN/A return commit.readNextPC(tid); 13892292SN/A} 13901060SN/A 13912292SN/Atemplate <class Impl> 13922292SN/Avoid 13932292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 13942292SN/A{ 13952292SN/A commit.setNextPC(val, tid); 13962292SN/A} 13971060SN/A 13982756Sksewell@umich.edutemplate <class Impl> 13992756Sksewell@umich.eduuint64_t 14002756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 14012756Sksewell@umich.edu{ 14022756Sksewell@umich.edu return commit.readNextNPC(tid); 14032756Sksewell@umich.edu} 14042756Sksewell@umich.edu 14052756Sksewell@umich.edutemplate <class Impl> 14062756Sksewell@umich.eduvoid 14072935Sksewell@umich.eduFullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) 14082756Sksewell@umich.edu{ 14092756Sksewell@umich.edu commit.setNextNPC(val, tid); 14102756Sksewell@umich.edu} 14112756Sksewell@umich.edu 14122292SN/Atemplate <class Impl> 14134636Sgblack@eecs.umich.eduuint64_t 14144636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readNextMicroPC(unsigned tid) 14154636Sgblack@eecs.umich.edu{ 14164636Sgblack@eecs.umich.edu return commit.readNextMicroPC(tid); 14174636Sgblack@eecs.umich.edu} 14184636Sgblack@eecs.umich.edu 14194636Sgblack@eecs.umich.edutemplate <class Impl> 14204636Sgblack@eecs.umich.eduvoid 14214636Sgblack@eecs.umich.eduFullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid) 14224636Sgblack@eecs.umich.edu{ 14234636Sgblack@eecs.umich.edu commit.setNextMicroPC(new_PC, tid); 14244636Sgblack@eecs.umich.edu} 14254636Sgblack@eecs.umich.edu 14264636Sgblack@eecs.umich.edutemplate <class Impl> 14275595Sgblack@eecs.umich.eduvoid 14285595Sgblack@eecs.umich.eduFullO3CPU<Impl>::squashFromTC(unsigned tid) 14295595Sgblack@eecs.umich.edu{ 14305595Sgblack@eecs.umich.edu this->thread[tid]->inSyscall = true; 14315595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 14325595Sgblack@eecs.umich.edu} 14335595Sgblack@eecs.umich.edu 14345595Sgblack@eecs.umich.edutemplate <class Impl> 14352292SN/Atypename FullO3CPU<Impl>::ListIt 14362292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14372292SN/A{ 14382292SN/A instList.push_back(inst); 14391060SN/A 14402292SN/A return --(instList.end()); 14412292SN/A} 14421060SN/A 14432292SN/Atemplate <class Impl> 14442292SN/Avoid 14452292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 14462292SN/A{ 14472292SN/A // Keep an instruction count. 14482292SN/A thread[tid]->numInst++; 14492292SN/A thread[tid]->numInsts++; 14502292SN/A committedInsts[tid]++; 14512292SN/A totalCommittedInsts++; 14522292SN/A 14532292SN/A // Check for instruction-count-based events. 14542292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 14552292SN/A} 14562292SN/A 14572292SN/Atemplate <class Impl> 14582292SN/Avoid 14592292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 14602292SN/A{ 14612292SN/A removeInstsThisCycle = true; 14622292SN/A 14632292SN/A removeList.push(inst->getInstListIt()); 14641060SN/A} 14651060SN/A 14661060SN/Atemplate <class Impl> 14671060SN/Avoid 14681755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 14691060SN/A{ 14702733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 14712292SN/A "[sn:%lli]\n", 14722303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 14731060SN/A 14742292SN/A removeInstsThisCycle = true; 14751060SN/A 14761060SN/A // Remove the front instruction. 14772292SN/A removeList.push(inst->getInstListIt()); 14781060SN/A} 14791060SN/A 14801060SN/Atemplate <class Impl> 14811060SN/Avoid 14824632Sgblack@eecs.umich.eduFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 14831060SN/A{ 14842733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 14852292SN/A " list.\n", tid); 14861060SN/A 14872292SN/A ListIt end_it; 14881060SN/A 14892292SN/A bool rob_empty = false; 14902292SN/A 14912292SN/A if (instList.empty()) { 14922292SN/A return; 14932292SN/A } else if (rob.isEmpty(/*tid*/)) { 14942733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 14952292SN/A end_it = instList.begin(); 14962292SN/A rob_empty = true; 14972292SN/A } else { 14982292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 14992733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 15002292SN/A } 15012292SN/A 15022292SN/A removeInstsThisCycle = true; 15032292SN/A 15042292SN/A ListIt inst_it = instList.end(); 15052292SN/A 15062292SN/A inst_it--; 15072292SN/A 15082292SN/A // Walk through the instruction list, removing any instructions 15092292SN/A // that were inserted after the given instruction iterator, end_it. 15102292SN/A while (inst_it != end_it) { 15112292SN/A assert(!instList.empty()); 15122292SN/A 15132292SN/A squashInstIt(inst_it, tid); 15142292SN/A 15152292SN/A inst_it--; 15162292SN/A } 15172292SN/A 15182292SN/A // If the ROB was empty, then we actually need to remove the first 15192292SN/A // instruction as well. 15202292SN/A if (rob_empty) { 15212292SN/A squashInstIt(inst_it, tid); 15222292SN/A } 15231060SN/A} 15241060SN/A 15251060SN/Atemplate <class Impl> 15261060SN/Avoid 15272292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 15282292SN/A unsigned tid) 15291062SN/A{ 15302292SN/A assert(!instList.empty()); 15312292SN/A 15322292SN/A removeInstsThisCycle = true; 15332292SN/A 15342292SN/A ListIt inst_iter = instList.end(); 15352292SN/A 15362292SN/A inst_iter--; 15372292SN/A 15382733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 15392292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15402292SN/A tid, seq_num, (*inst_iter)->seqNum); 15411062SN/A 15422292SN/A while ((*inst_iter)->seqNum > seq_num) { 15431062SN/A 15442292SN/A bool break_loop = (inst_iter == instList.begin()); 15451062SN/A 15462292SN/A squashInstIt(inst_iter, tid); 15471062SN/A 15482292SN/A inst_iter--; 15491062SN/A 15502292SN/A if (break_loop) 15512292SN/A break; 15522292SN/A } 15532292SN/A} 15542292SN/A 15552292SN/Atemplate <class Impl> 15562292SN/Ainline void 15572292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 15582292SN/A{ 15592292SN/A if ((*instIt)->threadNumber == tid) { 15602733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 15612292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 15622292SN/A (*instIt)->threadNumber, 15632292SN/A (*instIt)->seqNum, 15642292SN/A (*instIt)->readPC()); 15651062SN/A 15661062SN/A // Mark it as squashed. 15672292SN/A (*instIt)->setSquashed(); 15682292SN/A 15692325SN/A // @todo: Formulate a consistent method for deleting 15702325SN/A // instructions from the instruction list 15712292SN/A // Remove the instruction from the list. 15722292SN/A removeList.push(instIt); 15732292SN/A } 15742292SN/A} 15752292SN/A 15762292SN/Atemplate <class Impl> 15772292SN/Avoid 15782292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 15792292SN/A{ 15802292SN/A while (!removeList.empty()) { 15812733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 15822292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 15832292SN/A (*removeList.front())->threadNumber, 15842292SN/A (*removeList.front())->seqNum, 15852292SN/A (*removeList.front())->readPC()); 15862292SN/A 15872292SN/A instList.erase(removeList.front()); 15882292SN/A 15892292SN/A removeList.pop(); 15901062SN/A } 15911062SN/A 15922292SN/A removeInstsThisCycle = false; 15931062SN/A} 15942325SN/A/* 15951062SN/Atemplate <class Impl> 15961062SN/Avoid 15971755SN/AFullO3CPU<Impl>::removeAllInsts() 15981060SN/A{ 15991060SN/A instList.clear(); 16001060SN/A} 16012325SN/A*/ 16021060SN/Atemplate <class Impl> 16031060SN/Avoid 16041755SN/AFullO3CPU<Impl>::dumpInsts() 16051060SN/A{ 16061060SN/A int num = 0; 16071060SN/A 16082292SN/A ListIt inst_list_it = instList.begin(); 16092292SN/A 16102292SN/A cprintf("Dumping Instruction List\n"); 16112292SN/A 16122292SN/A while (inst_list_it != instList.end()) { 16132292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 16142292SN/A "Squashed:%i\n\n", 16152292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 16162292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16172292SN/A (*inst_list_it)->isSquashed()); 16181060SN/A inst_list_it++; 16191060SN/A ++num; 16201060SN/A } 16211060SN/A} 16222325SN/A/* 16231060SN/Atemplate <class Impl> 16241060SN/Avoid 16251755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 16261060SN/A{ 16271060SN/A iew.wakeDependents(inst); 16281060SN/A} 16292325SN/A*/ 16302292SN/Atemplate <class Impl> 16312292SN/Avoid 16322292SN/AFullO3CPU<Impl>::wakeCPU() 16332292SN/A{ 16342325SN/A if (activityRec.active() || tickEvent.scheduled()) { 16352325SN/A DPRINTF(Activity, "CPU already running.\n"); 16362292SN/A return; 16372292SN/A } 16382292SN/A 16392325SN/A DPRINTF(Activity, "Waking up CPU\n"); 16402325SN/A 16415099Ssaidi@eecs.umich.edu idleCycles += tickToCycles((curTick - 1) - lastRunningCycle); 16425099Ssaidi@eecs.umich.edu numCycles += tickToCycles((curTick - 1) - lastRunningCycle); 16432292SN/A 16445606Snate@binkert.org schedule(tickEvent, nextCycle()); 16452292SN/A} 16462292SN/A 16472292SN/Atemplate <class Impl> 16482292SN/Aint 16492292SN/AFullO3CPU<Impl>::getFreeTid() 16502292SN/A{ 16512292SN/A for (int i=0; i < numThreads; i++) { 16522292SN/A if (!tids[i]) { 16532292SN/A tids[i] = true; 16542292SN/A return i; 16552292SN/A } 16562292SN/A } 16572292SN/A 16582292SN/A return -1; 16592292SN/A} 16602292SN/A 16612292SN/Atemplate <class Impl> 16622292SN/Avoid 16632292SN/AFullO3CPU<Impl>::doContextSwitch() 16642292SN/A{ 16652292SN/A if (contextSwitch) { 16662292SN/A 16672292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 16682292SN/A 16692292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 16702292SN/A activateWhenReady(tid); 16712292SN/A } 16722292SN/A 16732292SN/A if (cpuWaitList.size() == 0) 16742292SN/A contextSwitch = true; 16752292SN/A } 16762292SN/A} 16772292SN/A 16782292SN/Atemplate <class Impl> 16792292SN/Avoid 16802292SN/AFullO3CPU<Impl>::updateThreadPriority() 16812292SN/A{ 16822292SN/A if (activeThreads.size() > 1) 16832292SN/A { 16842292SN/A //DEFAULT TO ROUND ROBIN SCHEME 16852292SN/A //e.g. Move highest priority to end of thread list 16865314Sstever@gmail.com std::list<unsigned>::iterator list_begin = activeThreads.begin(); 16875314Sstever@gmail.com std::list<unsigned>::iterator list_end = activeThreads.end(); 16882292SN/A 16892292SN/A unsigned high_thread = *list_begin; 16902292SN/A 16912292SN/A activeThreads.erase(list_begin); 16922292SN/A 16932292SN/A activeThreads.push_back(high_thread); 16942292SN/A } 16952292SN/A} 16961060SN/A 16971755SN/A// Forward declaration of FullO3CPU. 16982818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1699