cpu.cc revision 3226
1298SN/A/* 28142SAli.Saidi@ARM.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 38142SAli.Saidi@ARM.com * All rights reserved. 48142SAli.Saidi@ARM.com * 58142SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 68142SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 78142SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 88142SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 98142SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 108142SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 118142SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 128142SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 138142SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 142188SN/A * this software without specific prior written permission. 15298SN/A * 16298SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17298SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18298SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19298SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20298SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21298SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22298SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23298SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24298SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25298SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26298SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27298SN/A * 28298SN/A * Authors: Kevin Lim 29298SN/A * Korey Sewell 30298SN/A */ 31298SN/A 32298SN/A#include "config/full_system.hh" 33298SN/A#include "config/use_checker.hh" 34298SN/A 35298SN/A#if FULL_SYSTEM 36298SN/A#include "cpu/quiesce_event.hh" 37298SN/A#include "sim/system.hh" 38298SN/A#else 392665Ssaidi@eecs.umich.edu#include "sim/process.hh" 402665Ssaidi@eecs.umich.edu#endif 41298SN/A 42298SN/A#include "cpu/activity.hh" 43954SN/A#include "cpu/simple_thread.hh" 44956SN/A#include "cpu/thread_context.hh" 45956SN/A#include "cpu/o3/isa_specific.hh" 468229Snate@binkert.org#include "cpu/o3/cpu.hh" 474078Sbinkertn@umich.edu 48299SN/A#include "sim/root.hh" 49299SN/A#include "sim/stat_control.hh" 502170SN/A 515882Snate@binkert.org#if USE_CHECKER 526658Snate@binkert.org#include "cpu/checker/cpu.hh" 536658Snate@binkert.org#endif 541717SN/A 558229Snate@binkert.orgusing namespace std; 562680Sktlim@umich.eduusing namespace TheISA; 578232Snate@binkert.org 588232Snate@binkert.orgBaseO3CPU::BaseO3CPU(Params *params) 598232Snate@binkert.org : BaseCPU(params), cpu_id(0) 605529Snate@binkert.org{ 613565Sgblack@eecs.umich.edu} 62298SN/A 635606Snate@binkert.orgvoid 64298SN/ABaseO3CPU::regStats() 65695SN/A{ 66695SN/A BaseCPU::regStats(); 67954SN/A} 686118Snate@binkert.org 695780Ssteve.reinhardt@amd.comtemplate <class Impl> 706118Snate@binkert.orgFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 712080SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 725780Ssteve.reinhardt@amd.com{ 73298SN/A} 74299SN/A 751052SN/Atemplate <class Impl> 76729SN/Avoid 772107SN/AFullO3CPU<Impl>::TickEvent::process() 78298SN/A{ 795504Snate@binkert.org cpu->tick(); 805504Snate@binkert.org} 815780Ssteve.reinhardt@amd.com 825780Ssteve.reinhardt@amd.comtemplate <class Impl> 835504Snate@binkert.orgconst char * 845504Snate@binkert.orgFullO3CPU<Impl>::TickEvent::description() 85298SN/A{ 865504Snate@binkert.org return "FullO3CPU tick event"; 875504Snate@binkert.org} 885504Snate@binkert.org 895504Snate@binkert.orgtemplate <class Impl> 905504Snate@binkert.orgFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 915504Snate@binkert.org : Event(&mainEventQueue, CPU_Switch_Pri) 925504Snate@binkert.org{ 935529Snate@binkert.org} 945504Snate@binkert.org 955504Snate@binkert.orgtemplate <class Impl> 965504Snate@binkert.orgvoid 975504Snate@binkert.orgFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 985504Snate@binkert.org FullO3CPU<Impl> *thread_cpu) 995504Snate@binkert.org{ 1005504Snate@binkert.org tid = thread_num; 1015504Snate@binkert.org cpu = thread_cpu; 1025504Snate@binkert.org} 1035504Snate@binkert.org 1048142SAli.Saidi@ARM.comtemplate <class Impl> 1058142SAli.Saidi@ARM.comvoid 1068142SAli.Saidi@ARM.comFullO3CPU<Impl>::ActivateThreadEvent::process() 1078142SAli.Saidi@ARM.com{ 1088142SAli.Saidi@ARM.com cpu->activateThread(tid); 1098142SAli.Saidi@ARM.com} 1108142SAli.Saidi@ARM.com 1118142SAli.Saidi@ARM.comtemplate <class Impl> 1128142SAli.Saidi@ARM.comconst char * 1138142SAli.Saidi@ARM.comFullO3CPU<Impl>::ActivateThreadEvent::description() 1148142SAli.Saidi@ARM.com{ 1158142SAli.Saidi@ARM.com return "FullO3CPU \"Activate Thread\" event"; 1168142SAli.Saidi@ARM.com} 1178142SAli.Saidi@ARM.com 1188142SAli.Saidi@ARM.comtemplate <class Impl> 1198142SAli.Saidi@ARM.comFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1208142SAli.Saidi@ARM.com : Event(&mainEventQueue, CPU_Tick_Pri) 1218142SAli.Saidi@ARM.com{ 1228142SAli.Saidi@ARM.com} 1238142SAli.Saidi@ARM.com 1248142SAli.Saidi@ARM.comtemplate <class Impl> 1258142SAli.Saidi@ARM.comvoid 1265504Snate@binkert.orgFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1275504Snate@binkert.org FullO3CPU<Impl> *thread_cpu) 1287819Ssteve.reinhardt@amd.com{ 1297819Ssteve.reinhardt@amd.com tid = thread_num; 1307819Ssteve.reinhardt@amd.com cpu = thread_cpu; 1315504Snate@binkert.org} 1325504Snate@binkert.org 1335504Snate@binkert.orgtemplate <class Impl> 1345504Snate@binkert.orgvoid 1357823Ssteve.reinhardt@amd.comFullO3CPU<Impl>::DeallocateContextEvent::process() 1365504Snate@binkert.org{ 1377819Ssteve.reinhardt@amd.com cpu->deactivateThread(tid); 1385504Snate@binkert.org if (remove) 1395504Snate@binkert.org cpu->removeThread(tid); 1407819Ssteve.reinhardt@amd.com} 1415504Snate@binkert.org 1425504Snate@binkert.orgtemplate <class Impl> 1435504Snate@binkert.orgconst char * 1445504Snate@binkert.orgFullO3CPU<Impl>::DeallocateContextEvent::description() 1455504Snate@binkert.org{ 1465504Snate@binkert.org return "FullO3CPU \"Deallocate Context\" event"; 1475504Snate@binkert.org} 1485504Snate@binkert.org 1495504Snate@binkert.orgtemplate <class Impl> 1507819Ssteve.reinhardt@amd.comFullO3CPU<Impl>::FullO3CPU(Params *params) 1517819Ssteve.reinhardt@amd.com : BaseO3CPU(params), 1527819Ssteve.reinhardt@amd.com tickEvent(this), 1535504Snate@binkert.org removeInstsThisCycle(false), 1545504Snate@binkert.org fetch(params), 1555504Snate@binkert.org decode(params), 1565504Snate@binkert.org rename(params), 1577823Ssteve.reinhardt@amd.com iew(params), 1585504Snate@binkert.org commit(params), 1597819Ssteve.reinhardt@amd.com 1605504Snate@binkert.org regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 1615504Snate@binkert.org 1627819Ssteve.reinhardt@amd.com freeList(params->numberOfThreads, 1635504Snate@binkert.org TheISA::NumIntRegs, params->numPhysIntRegs, 1645504Snate@binkert.org TheISA::NumFloatRegs, params->numPhysFloatRegs), 1655504Snate@binkert.org 1665504Snate@binkert.org rob(params->numROBEntries, params->squashWidth, 1675504Snate@binkert.org params->smtROBPolicy, params->smtROBThreshold, 1685504Snate@binkert.org params->numberOfThreads), 1695504Snate@binkert.org 1705504Snate@binkert.org scoreboard(params->numberOfThreads, 1715504Snate@binkert.org TheISA::NumIntRegs, params->numPhysIntRegs, 1727064Snate@binkert.org TheISA::NumFloatRegs, params->numPhysFloatRegs, 1737064Snate@binkert.org TheISA::NumMiscRegs * number_of_threads, 1745504Snate@binkert.org TheISA::ZeroReg), 1755504Snate@binkert.org 1765780Ssteve.reinhardt@amd.com timeBuffer(params->backComSize, params->forwardComSize), 1775780Ssteve.reinhardt@amd.com fetchQueue(params->backComSize, params->forwardComSize), 1785741Snate@binkert.org decodeQueue(params->backComSize, params->forwardComSize), 1795741Snate@binkert.org renameQueue(params->backComSize, params->forwardComSize), 1805741Snate@binkert.org iewQueue(params->backComSize, params->forwardComSize), 1817823Ssteve.reinhardt@amd.com activityRec(NumStages, 1825741Snate@binkert.org params->backComSize + params->forwardComSize, 1835741Snate@binkert.org params->activity), 1845504Snate@binkert.org 1855808Snate@binkert.org globalSeqNum(1), 1865808Snate@binkert.org#if FULL_SYSTEM 1875808Snate@binkert.org system(params->system), 1885808Snate@binkert.org physmem(system->physmem), 1895808Snate@binkert.org#endif // FULL_SYSTEM 1905808Snate@binkert.org mem(params->mem), 1915808Snate@binkert.org drainCount(0), 1925808Snate@binkert.org deferRegistration(params->deferRegistration), 1935808Snate@binkert.org numThreads(number_of_threads) 1945504Snate@binkert.org{ 1955504Snate@binkert.org if (!deferRegistration) { 1967823Ssteve.reinhardt@amd.com _status = Running; 1977819Ssteve.reinhardt@amd.com } else { 1985504Snate@binkert.org _status = Idle; 1995504Snate@binkert.org } 2005780Ssteve.reinhardt@amd.com 2015780Ssteve.reinhardt@amd.com checker = NULL; 2025504Snate@binkert.org 2035504Snate@binkert.org if (params->checker) { 2045504Snate@binkert.org#if USE_CHECKER 2055504Snate@binkert.org BaseCPU *temp_checker = params->checker; 2065504Snate@binkert.org checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2075504Snate@binkert.org checker->setMemory(mem); 208711SN/A#if FULL_SYSTEM 209711SN/A checker->setSystem(params->system); 2105504Snate@binkert.org#endif 2115504Snate@binkert.org#else 212310SN/A panic("Checker enabled but not compiled in!"); 2135504Snate@binkert.org#endif // USE_CHECKER 2145504Snate@binkert.org } 2153373Sstever@eecs.umich.edu 2165504Snate@binkert.org#if !FULL_SYSTEM 2175504Snate@binkert.org thread.resize(number_of_threads); 2185504Snate@binkert.org tids.resize(number_of_threads); 2195504Snate@binkert.org#endif 2205504Snate@binkert.org 2215504Snate@binkert.org // The stages also need their CPU pointer setup. However this 2226227Snate@binkert.org // must be done at the upper level CPU because they have pointers 2235504Snate@binkert.org // to the upper level CPU, and not this FullO3CPU. 2245504Snate@binkert.org 2255504Snate@binkert.org // Set up Pointers to the activeThreads list for each stage 2265504Snate@binkert.org fetch.setActiveThreads(&activeThreads); 2275504Snate@binkert.org decode.setActiveThreads(&activeThreads); 2285504Snate@binkert.org rename.setActiveThreads(&activeThreads); 2295504Snate@binkert.org iew.setActiveThreads(&activeThreads); 2305504Snate@binkert.org commit.setActiveThreads(&activeThreads); 2315504Snate@binkert.org 2325504Snate@binkert.org // Give each of the stages the time buffer they will use. 2335504Snate@binkert.org fetch.setTimeBuffer(&timeBuffer); 2345504Snate@binkert.org decode.setTimeBuffer(&timeBuffer); 2355504Snate@binkert.org rename.setTimeBuffer(&timeBuffer); 2365504Snate@binkert.org iew.setTimeBuffer(&timeBuffer); 2375504Snate@binkert.org commit.setTimeBuffer(&timeBuffer); 2385504Snate@binkert.org 2395504Snate@binkert.org // Also setup each of the stages' queues. 2405504Snate@binkert.org fetch.setFetchQueue(&fetchQueue); 2415504Snate@binkert.org decode.setFetchQueue(&fetchQueue); 2425504Snate@binkert.org commit.setFetchQueue(&fetchQueue); 2435504Snate@binkert.org decode.setDecodeQueue(&decodeQueue); 2445504Snate@binkert.org rename.setDecodeQueue(&decodeQueue); 2455504Snate@binkert.org rename.setRenameQueue(&renameQueue); 2465504Snate@binkert.org iew.setRenameQueue(&renameQueue); 2475504Snate@binkert.org iew.setIEWQueue(&iewQueue); 2485504Snate@binkert.org commit.setIEWQueue(&iewQueue); 2495504Snate@binkert.org commit.setRenameQueue(&renameQueue); 2505504Snate@binkert.org 2515780Ssteve.reinhardt@amd.com commit.setIEWStage(&iew); 2525780Ssteve.reinhardt@amd.com rename.setIEWStage(&iew); 2535780Ssteve.reinhardt@amd.com rename.setCommitStage(&commit); 2545780Ssteve.reinhardt@amd.com 2555780Ssteve.reinhardt@amd.com#if !FULL_SYSTEM 2565780Ssteve.reinhardt@amd.com int active_threads = params->workload.size(); 2575780Ssteve.reinhardt@amd.com 2585780Ssteve.reinhardt@amd.com if (active_threads > Impl::MaxThreads) { 2595780Ssteve.reinhardt@amd.com panic("Workload Size too large. Increase the 'MaxThreads'" 2605952Ssaidi@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2615780Ssteve.reinhardt@amd.com "edit your workload size."); 2625780Ssteve.reinhardt@amd.com } 2635780Ssteve.reinhardt@amd.com#else 2645780Ssteve.reinhardt@amd.com int active_threads = 1; 2655780Ssteve.reinhardt@amd.com#endif 2665780Ssteve.reinhardt@amd.com 2675504Snate@binkert.org //Make Sure That this a Valid Architeture 2685504Snate@binkert.org assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2695529Snate@binkert.org assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2705504Snate@binkert.org 2715504Snate@binkert.org rename.setScoreboard(&scoreboard); 2725504Snate@binkert.org iew.setScoreboard(&scoreboard); 2737823Ssteve.reinhardt@amd.com 2747064Snate@binkert.org // Setup the rename map for whichever stages need it. 2755504Snate@binkert.org PhysRegIndex lreg_idx = 0; 2767822Ssteve.reinhardt@amd.com PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2775504Snate@binkert.org 2785504Snate@binkert.org for (int tid=0; tid < numThreads; tid++) { 2795504Snate@binkert.org bool bindRegs = (tid <= active_threads - 1); 2805504Snate@binkert.org 2815504Snate@binkert.org commitRenameMap[tid].init(TheISA::NumIntRegs, 2825529Snate@binkert.org params->numPhysIntRegs, 2835504Snate@binkert.org lreg_idx, //Index for Logical. Regs 2845504Snate@binkert.org 2855504Snate@binkert.org TheISA::NumFloatRegs, 2867823Ssteve.reinhardt@amd.com params->numPhysFloatRegs, 2877064Snate@binkert.org freg_idx, //Index for Float Regs 2885504Snate@binkert.org 2897822Ssteve.reinhardt@amd.com TheISA::NumMiscRegs, 2905504Snate@binkert.org 2915504Snate@binkert.org TheISA::ZeroReg, 2925504Snate@binkert.org TheISA::ZeroReg, 2935504Snate@binkert.org 2945504Snate@binkert.org tid, 2955529Snate@binkert.org false); 2965504Snate@binkert.org 2975504Snate@binkert.org renameMap[tid].init(TheISA::NumIntRegs, 2985504Snate@binkert.org params->numPhysIntRegs, 2997823Ssteve.reinhardt@amd.com lreg_idx, //Index for Logical. Regs 3007064Snate@binkert.org 3015504Snate@binkert.org TheISA::NumFloatRegs, 3027822Ssteve.reinhardt@amd.com params->numPhysFloatRegs, 3035504Snate@binkert.org freg_idx, //Index for Float Regs 3045504Snate@binkert.org 3055504Snate@binkert.org TheISA::NumMiscRegs, 3065504Snate@binkert.org 3075504Snate@binkert.org TheISA::ZeroReg, 3085529Snate@binkert.org TheISA::ZeroReg, 3095504Snate@binkert.org 3105504Snate@binkert.org tid, 3117823Ssteve.reinhardt@amd.com bindRegs); 3127064Snate@binkert.org 3135504Snate@binkert.org activateThreadEvent[tid].init(tid, this); 3147819Ssteve.reinhardt@amd.com deallocateContextEvent[tid].init(tid, this); 3155504Snate@binkert.org } 3165504Snate@binkert.org 3175780Ssteve.reinhardt@amd.com rename.setRenameMap(renameMap); 3185780Ssteve.reinhardt@amd.com commit.setRenameMap(commitRenameMap); 3195504Snate@binkert.org 3205504Snate@binkert.org // Give renameMap & rename stage access to the freeList; 3215504Snate@binkert.org for (int i=0; i < numThreads; i++) { 3225504Snate@binkert.org renameMap[i].setFreeList(&freeList); 3235504Snate@binkert.org } 3245504Snate@binkert.org rename.setFreeList(&freeList); 325310SN/A 326299SN/A // Setup the ROB for whichever stages need it. 3275504Snate@binkert.org commit.setROB(&rob); 3282188SN/A 3295504Snate@binkert.org lastRunningCycle = curTick; 3305504Snate@binkert.org 3315504Snate@binkert.org lastActivatedCycle = -1; 3322235SN/A 3335504Snate@binkert.org // Give renameMap & rename stage access to the freeList; 3345504Snate@binkert.org //for (int i=0; i < numThreads; i++) { 3353368Sstever@eecs.umich.edu //globalSeqNum[i] = 1; 3365504Snate@binkert.org //} 3375504Snate@binkert.org 3385504Snate@binkert.org contextSwitch = false; 3395504Snate@binkert.org} 3405504Snate@binkert.org 3415504Snate@binkert.orgtemplate <class Impl> 3423368Sstever@eecs.umich.eduFullO3CPU<Impl>::~FullO3CPU() 3435504Snate@binkert.org{ 3445504Snate@binkert.org} 3455504Snate@binkert.org 3462188SN/Atemplate <class Impl> 3472188SN/Avoid 3485504Snate@binkert.orgFullO3CPU<Impl>::fullCPURegStats() 3495504Snate@binkert.org{ 3505504Snate@binkert.org BaseO3CPU::regStats(); 3515504Snate@binkert.org 3525504Snate@binkert.org // Register any of the O3CPU's stats here. 3532188SN/A timesIdled 3545780Ssteve.reinhardt@amd.com .name(name() + ".timesIdled") 3555780Ssteve.reinhardt@amd.com .desc("Number of times that the entire CPU went into an idle state and" 3565504Snate@binkert.org " unscheduled itself") 3575504Snate@binkert.org .prereq(timesIdled); 3585504Snate@binkert.org 3598231Snate@binkert.org idleCycles 3605504Snate@binkert.org .name(name() + ".idleCycles") 3612235SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 3625504Snate@binkert.org "to idling") 3635504Snate@binkert.org .prereq(idleCycles); 3645504Snate@binkert.org 3655504Snate@binkert.org // Number of Instructions simulated 3665504Snate@binkert.org // -------------------------------- 3673368Sstever@eecs.umich.edu // Should probably be in Base CPU but need templated 3687914SBrad.Beckmann@amd.com // MaxThreads so put in here instead 3697914SBrad.Beckmann@amd.com committedInsts 3707914SBrad.Beckmann@amd.com .init(numThreads) 3717914SBrad.Beckmann@amd.com .name(name() + ".committedInsts") 3727914SBrad.Beckmann@amd.com .desc("Number of Instructions Simulated"); 3737914SBrad.Beckmann@amd.com 3747914SBrad.Beckmann@amd.com totalCommittedInsts 3757914SBrad.Beckmann@amd.com .name(name() + ".committedInsts_total") 3767914SBrad.Beckmann@amd.com .desc("Number of Instructions Simulated"); 3777914SBrad.Beckmann@amd.com 3787914SBrad.Beckmann@amd.com cpi 3797914SBrad.Beckmann@amd.com .name(name() + ".cpi") 3807914SBrad.Beckmann@amd.com .desc("CPI: Cycles Per Instruction") 3817914SBrad.Beckmann@amd.com .precision(6); 3827914SBrad.Beckmann@amd.com cpi = simTicks / committedInsts; 3837914SBrad.Beckmann@amd.com 3847914SBrad.Beckmann@amd.com totalCpi 3857914SBrad.Beckmann@amd.com .name(name() + ".cpi_total") 3867914SBrad.Beckmann@amd.com .desc("CPI: Total CPI of All Threads") 3877914SBrad.Beckmann@amd.com .precision(6); 3887914SBrad.Beckmann@amd.com totalCpi = simTicks / totalCommittedInsts; 3897914SBrad.Beckmann@amd.com 3907914SBrad.Beckmann@amd.com ipc 3917914SBrad.Beckmann@amd.com .name(name() + ".ipc") 3927914SBrad.Beckmann@amd.com .desc("IPC: Instructions Per Cycle") 3937914SBrad.Beckmann@amd.com .precision(6); 3947914SBrad.Beckmann@amd.com ipc = committedInsts / simTicks; 3957914SBrad.Beckmann@amd.com 3967914SBrad.Beckmann@amd.com totalIpc 3977914SBrad.Beckmann@amd.com .name(name() + ".ipc_total") 3987914SBrad.Beckmann@amd.com .desc("IPC: Total IPC of All Threads") 3997914SBrad.Beckmann@amd.com .precision(6); 4007914SBrad.Beckmann@amd.com totalIpc = totalCommittedInsts / simTicks; 4017914SBrad.Beckmann@amd.com 4027914SBrad.Beckmann@amd.com} 4037914SBrad.Beckmann@amd.com 4047914SBrad.Beckmann@amd.comtemplate <class Impl> 4057914SBrad.Beckmann@amd.comPort * 4067914SBrad.Beckmann@amd.comFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 4077914SBrad.Beckmann@amd.com{ 4087914SBrad.Beckmann@amd.com if (if_name == "dcache_port") 4097914SBrad.Beckmann@amd.com return iew.getDcachePort(); 4107914SBrad.Beckmann@amd.com else if (if_name == "icache_port") 4117914SBrad.Beckmann@amd.com return fetch.getIcachePort(); 4127914SBrad.Beckmann@amd.com else 4137914SBrad.Beckmann@amd.com panic("No Such Port\n"); 4147914SBrad.Beckmann@amd.com} 4157914SBrad.Beckmann@amd.com 4167914SBrad.Beckmann@amd.comtemplate <class Impl> 4177914SBrad.Beckmann@amd.comvoid 4187914SBrad.Beckmann@amd.comFullO3CPU<Impl>::tick() 4197914SBrad.Beckmann@amd.com{ 4207914SBrad.Beckmann@amd.com DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 4217914SBrad.Beckmann@amd.com 4227914SBrad.Beckmann@amd.com ++numCycles; 4237914SBrad.Beckmann@amd.com 4247914SBrad.Beckmann@amd.com// activity = false; 4257914SBrad.Beckmann@amd.com 4267914SBrad.Beckmann@amd.com //Tick each of the stages 4277914SBrad.Beckmann@amd.com fetch.tick(); 4287914SBrad.Beckmann@amd.com 4297914SBrad.Beckmann@amd.com decode.tick(); 4307914SBrad.Beckmann@amd.com 4317914SBrad.Beckmann@amd.com rename.tick(); 4327914SBrad.Beckmann@amd.com 4337914SBrad.Beckmann@amd.com iew.tick(); 4347914SBrad.Beckmann@amd.com 4357914SBrad.Beckmann@amd.com commit.tick(); 4367914SBrad.Beckmann@amd.com 4377914SBrad.Beckmann@amd.com#if !FULL_SYSTEM 4387914SBrad.Beckmann@amd.com doContextSwitch(); 4397914SBrad.Beckmann@amd.com#endif 4407914SBrad.Beckmann@amd.com 4417914SBrad.Beckmann@amd.com // Now advance the time buffers 4427914SBrad.Beckmann@amd.com timeBuffer.advance(); 4437914SBrad.Beckmann@amd.com 4447914SBrad.Beckmann@amd.com fetchQueue.advance(); 4457914SBrad.Beckmann@amd.com decodeQueue.advance(); 4467914SBrad.Beckmann@amd.com renameQueue.advance(); 4477914SBrad.Beckmann@amd.com iewQueue.advance(); 4487914SBrad.Beckmann@amd.com 4497914SBrad.Beckmann@amd.com activityRec.advance(); 4507914SBrad.Beckmann@amd.com 4517914SBrad.Beckmann@amd.com if (removeInstsThisCycle) { 4527914SBrad.Beckmann@amd.com cleanUpRemovedInsts(); 4537914SBrad.Beckmann@amd.com } 4547914SBrad.Beckmann@amd.com 4557914SBrad.Beckmann@amd.com if (!tickEvent.scheduled()) { 4567914SBrad.Beckmann@amd.com if (_status == SwitchedOut || 4577914SBrad.Beckmann@amd.com getState() == SimObject::Drained) { 4587914SBrad.Beckmann@amd.com DPRINTF(O3CPU, "Switched out!\n"); 4597914SBrad.Beckmann@amd.com // increment stat 4607914SBrad.Beckmann@amd.com lastRunningCycle = curTick; 4617914SBrad.Beckmann@amd.com } else if (!activityRec.active() || _status == Idle) { 4627914SBrad.Beckmann@amd.com DPRINTF(O3CPU, "Idle!\n"); 4637914SBrad.Beckmann@amd.com lastRunningCycle = curTick; 4647914SBrad.Beckmann@amd.com timesIdled++; 4657914SBrad.Beckmann@amd.com } else { 4667914SBrad.Beckmann@amd.com tickEvent.schedule(curTick + cycles(1)); 4677914SBrad.Beckmann@amd.com DPRINTF(O3CPU, "Scheduling next tick!\n"); 4687914SBrad.Beckmann@amd.com } 4697914SBrad.Beckmann@amd.com } 4707914SBrad.Beckmann@amd.com 4717914SBrad.Beckmann@amd.com#if !FULL_SYSTEM 4727914SBrad.Beckmann@amd.com updateThreadPriority(); 4737914SBrad.Beckmann@amd.com#endif 4747914SBrad.Beckmann@amd.com 4757914SBrad.Beckmann@amd.com} 4767914SBrad.Beckmann@amd.com 4777914SBrad.Beckmann@amd.comtemplate <class Impl> 4787914SBrad.Beckmann@amd.comvoid 4797914SBrad.Beckmann@amd.comFullO3CPU<Impl>::init() 4807914SBrad.Beckmann@amd.com{ 4817914SBrad.Beckmann@amd.com if (!deferRegistration) { 4827914SBrad.Beckmann@amd.com registerThreadContexts(); 4837914SBrad.Beckmann@amd.com } 4847914SBrad.Beckmann@amd.com 4857811Ssteve.reinhardt@amd.com // Set inSyscall so that the CPU doesn't squash when initially 486 // setting up registers. 487 for (int i = 0; i < number_of_threads; ++i) 488 thread[i]->inSyscall = true; 489 490 for (int tid=0; tid < number_of_threads; tid++) { 491#if FULL_SYSTEM 492 ThreadContext *src_tc = threadContexts[tid]; 493#else 494 ThreadContext *src_tc = thread[tid]->getTC(); 495#endif 496 // Threads start in the Suspended State 497 if (src_tc->status() != ThreadContext::Suspended) { 498 continue; 499 } 500 501#if FULL_SYSTEM 502 TheISA::initCPU(src_tc, src_tc->readCpuId()); 503#endif 504 } 505 506 // Clear inSyscall. 507 for (int i = 0; i < number_of_threads; ++i) 508 thread[i]->inSyscall = false; 509 510 // Initialize stages. 511 fetch.initStage(); 512 iew.initStage(); 513 rename.initStage(); 514 commit.initStage(); 515 516 commit.setThreads(thread); 517} 518 519template <class Impl> 520void 521FullO3CPU<Impl>::activateThread(unsigned tid) 522{ 523 list<unsigned>::iterator isActive = find( 524 activeThreads.begin(), activeThreads.end(), tid); 525 526 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 527 528 if (isActive == activeThreads.end()) { 529 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 530 tid); 531 532 activeThreads.push_back(tid); 533 } 534} 535 536template <class Impl> 537void 538FullO3CPU<Impl>::deactivateThread(unsigned tid) 539{ 540 //Remove From Active List, if Active 541 list<unsigned>::iterator thread_it = 542 find(activeThreads.begin(), activeThreads.end(), tid); 543 544 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 545 546 if (thread_it != activeThreads.end()) { 547 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 548 tid); 549 activeThreads.erase(thread_it); 550 } 551} 552 553template <class Impl> 554void 555FullO3CPU<Impl>::activateContext(int tid, int delay) 556{ 557 // Needs to set each stage to running as well. 558 if (delay){ 559 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 560 "on cycle %d\n", tid, curTick + cycles(delay)); 561 scheduleActivateThreadEvent(tid, delay); 562 } else { 563 activateThread(tid); 564 } 565 566 if (lastActivatedCycle < curTick) { 567 scheduleTickEvent(delay); 568 569 // Be sure to signal that there's some activity so the CPU doesn't 570 // deschedule itself. 571 activityRec.activity(); 572 fetch.wakeFromQuiesce(); 573 574 lastActivatedCycle = curTick; 575 576 _status = Running; 577 } 578} 579 580template <class Impl> 581bool 582FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay) 583{ 584 // Schedule removal of thread data from CPU 585 if (delay){ 586 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 587 "on cycle %d\n", tid, curTick + cycles(delay)); 588 scheduleDeallocateContextEvent(tid, remove, delay); 589 return false; 590 } else { 591 deactivateThread(tid); 592 if (remove) 593 removeThread(tid); 594 return true; 595 } 596} 597 598template <class Impl> 599void 600FullO3CPU<Impl>::suspendContext(int tid) 601{ 602 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 603 bool deallocated = deallocateContext(tid, false, 1); 604 // If this was the last thread then unschedule the tick event. 605 if ((activeThreads.size() == 1 && !deallocated) || activeThreads.size() == 0) 606 unscheduleTickEvent(); 607 _status = Idle; 608} 609 610template <class Impl> 611void 612FullO3CPU<Impl>::haltContext(int tid) 613{ 614 //For now, this is the same as deallocate 615 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 616 deallocateContext(tid, true, 1); 617} 618 619template <class Impl> 620void 621FullO3CPU<Impl>::insertThread(unsigned tid) 622{ 623 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 624 // Will change now that the PC and thread state is internal to the CPU 625 // and not in the ThreadContext. 626#if FULL_SYSTEM 627 ThreadContext *src_tc = system->threadContexts[tid]; 628#else 629 ThreadContext *src_tc = tcBase(tid); 630#endif 631 632 //Bind Int Regs to Rename Map 633 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 634 PhysRegIndex phys_reg = freeList.getIntReg(); 635 636 renameMap[tid].setEntry(ireg,phys_reg); 637 scoreboard.setReg(phys_reg); 638 } 639 640 //Bind Float Regs to Rename Map 641 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 642 PhysRegIndex phys_reg = freeList.getFloatReg(); 643 644 renameMap[tid].setEntry(freg,phys_reg); 645 scoreboard.setReg(phys_reg); 646 } 647 648 //Copy Thread Data Into RegFile 649 //this->copyFromTC(tid); 650 651 //Set PC/NPC/NNPC 652 setPC(src_tc->readPC(), tid); 653 setNextPC(src_tc->readNextPC(), tid); 654#if ISA_HAS_DELAY_SLOT 655 setNextNPC(src_tc->readNextNPC(), tid); 656#endif 657 658 src_tc->setStatus(ThreadContext::Active); 659 660 activateContext(tid,1); 661 662 //Reset ROB/IQ/LSQ Entries 663 commit.rob->resetEntries(); 664 iew.resetEntries(); 665} 666 667template <class Impl> 668void 669FullO3CPU<Impl>::removeThread(unsigned tid) 670{ 671 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 672 673 // Copy Thread Data From RegFile 674 // If thread is suspended, it might be re-allocated 675 //this->copyToTC(tid); 676 677 // Unbind Int Regs from Rename Map 678 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 679 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 680 681 scoreboard.unsetReg(phys_reg); 682 freeList.addReg(phys_reg); 683 } 684 685 // Unbind Float Regs from Rename Map 686 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 687 PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 688 689 scoreboard.unsetReg(phys_reg); 690 freeList.addReg(phys_reg); 691 } 692 693 // Squash Throughout Pipeline 694 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 695 fetch.squash(0, squash_seq_num, true, tid); 696 decode.squash(tid); 697 rename.squash(squash_seq_num, tid); 698 iew.squash(tid); 699 commit.rob->squash(squash_seq_num, tid); 700 701 assert(iew.ldstQueue.getCount(tid) == 0); 702 703 // Reset ROB/IQ/LSQ Entries 704 if (activeThreads.size() >= 1) { 705 commit.rob->resetEntries(); 706 iew.resetEntries(); 707 } 708} 709 710 711template <class Impl> 712void 713FullO3CPU<Impl>::activateWhenReady(int tid) 714{ 715 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 716 "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 717 tid); 718 719 bool ready = true; 720 721 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 722 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 723 "Phys. Int. Regs.\n", 724 tid); 725 ready = false; 726 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 727 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 728 "Phys. Float. Regs.\n", 729 tid); 730 ready = false; 731 } else if (commit.rob->numFreeEntries() >= 732 commit.rob->entryAmount(activeThreads.size() + 1)) { 733 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 734 "ROB entries.\n", 735 tid); 736 ready = false; 737 } else if (iew.instQueue.numFreeEntries() >= 738 iew.instQueue.entryAmount(activeThreads.size() + 1)) { 739 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 740 "IQ entries.\n", 741 tid); 742 ready = false; 743 } else if (iew.ldstQueue.numFreeEntries() >= 744 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 745 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 746 "LSQ entries.\n", 747 tid); 748 ready = false; 749 } 750 751 if (ready) { 752 insertThread(tid); 753 754 contextSwitch = false; 755 756 cpuWaitList.remove(tid); 757 } else { 758 suspendContext(tid); 759 760 //blocks fetch 761 contextSwitch = true; 762 763 //@todo: dont always add to waitlist 764 //do waitlist 765 cpuWaitList.push_back(tid); 766 } 767} 768 769template <class Impl> 770void 771FullO3CPU<Impl>::serialize(std::ostream &os) 772{ 773 SimObject::State so_state = SimObject::getState(); 774 SERIALIZE_ENUM(so_state); 775 BaseCPU::serialize(os); 776 nameOut(os, csprintf("%s.tickEvent", name())); 777 tickEvent.serialize(os); 778 779 // Use SimpleThread's ability to checkpoint to make it easier to 780 // write out the registers. Also make this static so it doesn't 781 // get instantiated multiple times (causes a panic in statistics). 782 static SimpleThread temp; 783 784 for (int i = 0; i < thread.size(); i++) { 785 nameOut(os, csprintf("%s.xc.%i", name(), i)); 786 temp.copyTC(thread[i]->getTC()); 787 temp.serialize(os); 788 } 789} 790 791template <class Impl> 792void 793FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 794{ 795 SimObject::State so_state; 796 UNSERIALIZE_ENUM(so_state); 797 BaseCPU::unserialize(cp, section); 798 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 799 800 // Use SimpleThread's ability to checkpoint to make it easier to 801 // read in the registers. Also make this static so it doesn't 802 // get instantiated multiple times (causes a panic in statistics). 803 static SimpleThread temp; 804 805 for (int i = 0; i < thread.size(); i++) { 806 temp.copyTC(thread[i]->getTC()); 807 temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 808 thread[i]->getTC()->copyArchRegs(temp.getTC()); 809 } 810} 811 812template <class Impl> 813unsigned int 814FullO3CPU<Impl>::drain(Event *drain_event) 815{ 816 DPRINTF(O3CPU, "Switching out\n"); 817 drainCount = 0; 818 fetch.drain(); 819 decode.drain(); 820 rename.drain(); 821 iew.drain(); 822 commit.drain(); 823 824 // Wake the CPU and record activity so everything can drain out if 825 // the CPU was not able to immediately drain. 826 if (getState() != SimObject::Drained) { 827 // A bit of a hack...set the drainEvent after all the drain() 828 // calls have been made, that way if all of the stages drain 829 // immediately, the signalDrained() function knows not to call 830 // process on the drain event. 831 drainEvent = drain_event; 832 833 wakeCPU(); 834 activityRec.activity(); 835 836 return 1; 837 } else { 838 return 0; 839 } 840} 841 842template <class Impl> 843void 844FullO3CPU<Impl>::resume() 845{ 846#if FULL_SYSTEM 847 assert(system->getMemoryMode() == System::Timing); 848#endif 849 fetch.resume(); 850 decode.resume(); 851 rename.resume(); 852 iew.resume(); 853 commit.resume(); 854 855 changeState(SimObject::Running); 856 857 if (_status == SwitchedOut || _status == Idle) 858 return; 859 860 if (!tickEvent.scheduled()) 861 tickEvent.schedule(curTick); 862 _status = Running; 863} 864 865template <class Impl> 866void 867FullO3CPU<Impl>::signalDrained() 868{ 869 if (++drainCount == NumStages) { 870 if (tickEvent.scheduled()) 871 tickEvent.squash(); 872 873 changeState(SimObject::Drained); 874 875 BaseCPU::switchOut(); 876 877 if (drainEvent) { 878 drainEvent->process(); 879 drainEvent = NULL; 880 } 881 } 882 assert(drainCount <= 5); 883} 884 885template <class Impl> 886void 887FullO3CPU<Impl>::switchOut() 888{ 889 fetch.switchOut(); 890 rename.switchOut(); 891 iew.switchOut(); 892 commit.switchOut(); 893 instList.clear(); 894 while (!removeList.empty()) { 895 removeList.pop(); 896 } 897 898 _status = SwitchedOut; 899#if USE_CHECKER 900 if (checker) 901 checker->switchOut(); 902#endif 903 if (tickEvent.scheduled()) 904 tickEvent.squash(); 905} 906 907template <class Impl> 908void 909FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 910{ 911 // Flush out any old data from the time buffers. 912 for (int i = 0; i < timeBuffer.getSize(); ++i) { 913 timeBuffer.advance(); 914 fetchQueue.advance(); 915 decodeQueue.advance(); 916 renameQueue.advance(); 917 iewQueue.advance(); 918 } 919 920 activityRec.reset(); 921 922 BaseCPU::takeOverFrom(oldCPU); 923 924 fetch.takeOverFrom(); 925 decode.takeOverFrom(); 926 rename.takeOverFrom(); 927 iew.takeOverFrom(); 928 commit.takeOverFrom(); 929 930 assert(!tickEvent.scheduled()); 931 932 // @todo: Figure out how to properly select the tid to put onto 933 // the active threads list. 934 int tid = 0; 935 936 list<unsigned>::iterator isActive = find( 937 activeThreads.begin(), activeThreads.end(), tid); 938 939 if (isActive == activeThreads.end()) { 940 //May Need to Re-code this if the delay variable is the delay 941 //needed for thread to activate 942 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 943 tid); 944 945 activeThreads.push_back(tid); 946 } 947 948 // Set all statuses to active, schedule the CPU's tick event. 949 // @todo: Fix up statuses so this is handled properly 950 for (int i = 0; i < threadContexts.size(); ++i) { 951 ThreadContext *tc = threadContexts[i]; 952 if (tc->status() == ThreadContext::Active && _status != Running) { 953 _status = Running; 954 tickEvent.schedule(curTick); 955 } 956 } 957 if (!tickEvent.scheduled()) 958 tickEvent.schedule(curTick); 959 960 Port *peer; 961 Port *icachePort = fetch.getIcachePort(); 962 if (icachePort->getPeer() == NULL) { 963 peer = oldCPU->getPort("icachePort")->getPeer(); 964 icachePort->setPeer(peer); 965 } else { 966 peer = icachePort->getPeer(); 967 } 968 peer->setPeer(icachePort); 969 970 Port *dcachePort = iew.getDcachePort(); 971 if (dcachePort->getPeer() == NULL) { 972 Port *peer = oldCPU->getPort("dcachePort")->getPeer(); 973 dcachePort->setPeer(peer); 974 } else { 975 peer = dcachePort->getPeer(); 976 } 977 peer->setPeer(dcachePort); 978} 979 980template <class Impl> 981uint64_t 982FullO3CPU<Impl>::readIntReg(int reg_idx) 983{ 984 return regFile.readIntReg(reg_idx); 985} 986 987template <class Impl> 988FloatReg 989FullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 990{ 991 return regFile.readFloatReg(reg_idx, width); 992} 993 994template <class Impl> 995FloatReg 996FullO3CPU<Impl>::readFloatReg(int reg_idx) 997{ 998 return regFile.readFloatReg(reg_idx); 999} 1000 1001template <class Impl> 1002FloatRegBits 1003FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 1004{ 1005 return regFile.readFloatRegBits(reg_idx, width); 1006} 1007 1008template <class Impl> 1009FloatRegBits 1010FullO3CPU<Impl>::readFloatRegBits(int reg_idx) 1011{ 1012 return regFile.readFloatRegBits(reg_idx); 1013} 1014 1015template <class Impl> 1016void 1017FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 1018{ 1019 regFile.setIntReg(reg_idx, val); 1020} 1021 1022template <class Impl> 1023void 1024FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 1025{ 1026 regFile.setFloatReg(reg_idx, val, width); 1027} 1028 1029template <class Impl> 1030void 1031FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 1032{ 1033 regFile.setFloatReg(reg_idx, val); 1034} 1035 1036template <class Impl> 1037void 1038FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 1039{ 1040 regFile.setFloatRegBits(reg_idx, val, width); 1041} 1042 1043template <class Impl> 1044void 1045FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 1046{ 1047 regFile.setFloatRegBits(reg_idx, val); 1048} 1049 1050template <class Impl> 1051uint64_t 1052FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 1053{ 1054 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 1055 1056 return regFile.readIntReg(phys_reg); 1057} 1058 1059template <class Impl> 1060float 1061FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 1062{ 1063 int idx = reg_idx + TheISA::FP_Base_DepTag; 1064 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1065 1066 return regFile.readFloatReg(phys_reg); 1067} 1068 1069template <class Impl> 1070double 1071FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 1072{ 1073 int idx = reg_idx + TheISA::FP_Base_DepTag; 1074 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1075 1076 return regFile.readFloatReg(phys_reg, 64); 1077} 1078 1079template <class Impl> 1080uint64_t 1081FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 1082{ 1083 int idx = reg_idx + TheISA::FP_Base_DepTag; 1084 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1085 1086 return regFile.readFloatRegBits(phys_reg); 1087} 1088 1089template <class Impl> 1090void 1091FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 1092{ 1093 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 1094 1095 regFile.setIntReg(phys_reg, val); 1096} 1097 1098template <class Impl> 1099void 1100FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 1101{ 1102 int idx = reg_idx + TheISA::FP_Base_DepTag; 1103 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1104 1105 regFile.setFloatReg(phys_reg, val); 1106} 1107 1108template <class Impl> 1109void 1110FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 1111{ 1112 int idx = reg_idx + TheISA::FP_Base_DepTag; 1113 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1114 1115 regFile.setFloatReg(phys_reg, val, 64); 1116} 1117 1118template <class Impl> 1119void 1120FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 1121{ 1122 int idx = reg_idx + TheISA::FP_Base_DepTag; 1123 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1124 1125 regFile.setFloatRegBits(phys_reg, val); 1126} 1127 1128template <class Impl> 1129uint64_t 1130FullO3CPU<Impl>::readPC(unsigned tid) 1131{ 1132 return commit.readPC(tid); 1133} 1134 1135template <class Impl> 1136void 1137FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 1138{ 1139 commit.setPC(new_PC, tid); 1140} 1141 1142template <class Impl> 1143uint64_t 1144FullO3CPU<Impl>::readNextPC(unsigned tid) 1145{ 1146 return commit.readNextPC(tid); 1147} 1148 1149template <class Impl> 1150void 1151FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 1152{ 1153 commit.setNextPC(val, tid); 1154} 1155 1156template <class Impl> 1157uint64_t 1158FullO3CPU<Impl>::readNextNPC(unsigned tid) 1159{ 1160 return commit.readNextNPC(tid); 1161} 1162 1163template <class Impl> 1164void 1165FullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) 1166{ 1167 commit.setNextNPC(val, tid); 1168} 1169 1170template <class Impl> 1171typename FullO3CPU<Impl>::ListIt 1172FullO3CPU<Impl>::addInst(DynInstPtr &inst) 1173{ 1174 instList.push_back(inst); 1175 1176 return --(instList.end()); 1177} 1178 1179template <class Impl> 1180void 1181FullO3CPU<Impl>::instDone(unsigned tid) 1182{ 1183 // Keep an instruction count. 1184 thread[tid]->numInst++; 1185 thread[tid]->numInsts++; 1186 committedInsts[tid]++; 1187 totalCommittedInsts++; 1188 1189 // Check for instruction-count-based events. 1190 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 1191} 1192 1193template <class Impl> 1194void 1195FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 1196{ 1197 removeInstsThisCycle = true; 1198 1199 removeList.push(inst->getInstListIt()); 1200} 1201 1202template <class Impl> 1203void 1204FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 1205{ 1206 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 1207 "[sn:%lli]\n", 1208 inst->threadNumber, inst->readPC(), inst->seqNum); 1209 1210 removeInstsThisCycle = true; 1211 1212 // Remove the front instruction. 1213 removeList.push(inst->getInstListIt()); 1214} 1215 1216template <class Impl> 1217void 1218FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid, 1219 bool squash_delay_slot, 1220 const InstSeqNum &delay_slot_seq_num) 1221{ 1222 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 1223 " list.\n", tid); 1224 1225 ListIt end_it; 1226 1227 bool rob_empty = false; 1228 1229 if (instList.empty()) { 1230 return; 1231 } else if (rob.isEmpty(/*tid*/)) { 1232 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 1233 end_it = instList.begin(); 1234 rob_empty = true; 1235 } else { 1236 end_it = (rob.readTailInst(tid))->getInstListIt(); 1237 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 1238 } 1239 1240 removeInstsThisCycle = true; 1241 1242 ListIt inst_it = instList.end(); 1243 1244 inst_it--; 1245 1246 // Walk through the instruction list, removing any instructions 1247 // that were inserted after the given instruction iterator, end_it. 1248 while (inst_it != end_it) { 1249 assert(!instList.empty()); 1250 1251#if ISA_HAS_DELAY_SLOT 1252 if(!squash_delay_slot && 1253 delay_slot_seq_num >= (*inst_it)->seqNum) { 1254 break; 1255 } 1256#endif 1257 squashInstIt(inst_it, tid); 1258 1259 inst_it--; 1260 } 1261 1262 // If the ROB was empty, then we actually need to remove the first 1263 // instruction as well. 1264 if (rob_empty) { 1265 squashInstIt(inst_it, tid); 1266 } 1267} 1268 1269template <class Impl> 1270void 1271FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 1272 unsigned tid) 1273{ 1274 assert(!instList.empty()); 1275 1276 removeInstsThisCycle = true; 1277 1278 ListIt inst_iter = instList.end(); 1279 1280 inst_iter--; 1281 1282 DPRINTF(O3CPU, "Deleting instructions from instruction " 1283 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 1284 tid, seq_num, (*inst_iter)->seqNum); 1285 1286 while ((*inst_iter)->seqNum > seq_num) { 1287 1288 bool break_loop = (inst_iter == instList.begin()); 1289 1290 squashInstIt(inst_iter, tid); 1291 1292 inst_iter--; 1293 1294 if (break_loop) 1295 break; 1296 } 1297} 1298 1299template <class Impl> 1300inline void 1301FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 1302{ 1303 if ((*instIt)->threadNumber == tid) { 1304 DPRINTF(O3CPU, "Squashing instruction, " 1305 "[tid:%i] [sn:%lli] PC %#x\n", 1306 (*instIt)->threadNumber, 1307 (*instIt)->seqNum, 1308 (*instIt)->readPC()); 1309 1310 // Mark it as squashed. 1311 (*instIt)->setSquashed(); 1312 1313 // @todo: Formulate a consistent method for deleting 1314 // instructions from the instruction list 1315 // Remove the instruction from the list. 1316 removeList.push(instIt); 1317 } 1318} 1319 1320template <class Impl> 1321void 1322FullO3CPU<Impl>::cleanUpRemovedInsts() 1323{ 1324 while (!removeList.empty()) { 1325 DPRINTF(O3CPU, "Removing instruction, " 1326 "[tid:%i] [sn:%lli] PC %#x\n", 1327 (*removeList.front())->threadNumber, 1328 (*removeList.front())->seqNum, 1329 (*removeList.front())->readPC()); 1330 1331 instList.erase(removeList.front()); 1332 1333 removeList.pop(); 1334 } 1335 1336 removeInstsThisCycle = false; 1337} 1338/* 1339template <class Impl> 1340void 1341FullO3CPU<Impl>::removeAllInsts() 1342{ 1343 instList.clear(); 1344} 1345*/ 1346template <class Impl> 1347void 1348FullO3CPU<Impl>::dumpInsts() 1349{ 1350 int num = 0; 1351 1352 ListIt inst_list_it = instList.begin(); 1353 1354 cprintf("Dumping Instruction List\n"); 1355 1356 while (inst_list_it != instList.end()) { 1357 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 1358 "Squashed:%i\n\n", 1359 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 1360 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 1361 (*inst_list_it)->isSquashed()); 1362 inst_list_it++; 1363 ++num; 1364 } 1365} 1366/* 1367template <class Impl> 1368void 1369FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 1370{ 1371 iew.wakeDependents(inst); 1372} 1373*/ 1374template <class Impl> 1375void 1376FullO3CPU<Impl>::wakeCPU() 1377{ 1378 if (activityRec.active() || tickEvent.scheduled()) { 1379 DPRINTF(Activity, "CPU already running.\n"); 1380 return; 1381 } 1382 1383 DPRINTF(Activity, "Waking up CPU\n"); 1384 1385 idleCycles += (curTick - 1) - lastRunningCycle; 1386 1387 tickEvent.schedule(curTick); 1388} 1389 1390template <class Impl> 1391int 1392FullO3CPU<Impl>::getFreeTid() 1393{ 1394 for (int i=0; i < numThreads; i++) { 1395 if (!tids[i]) { 1396 tids[i] = true; 1397 return i; 1398 } 1399 } 1400 1401 return -1; 1402} 1403 1404template <class Impl> 1405void 1406FullO3CPU<Impl>::doContextSwitch() 1407{ 1408 if (contextSwitch) { 1409 1410 //ADD CODE TO DEACTIVE THREAD HERE (???) 1411 1412 for (int tid=0; tid < cpuWaitList.size(); tid++) { 1413 activateWhenReady(tid); 1414 } 1415 1416 if (cpuWaitList.size() == 0) 1417 contextSwitch = true; 1418 } 1419} 1420 1421template <class Impl> 1422void 1423FullO3CPU<Impl>::updateThreadPriority() 1424{ 1425 if (activeThreads.size() > 1) 1426 { 1427 //DEFAULT TO ROUND ROBIN SCHEME 1428 //e.g. Move highest priority to end of thread list 1429 list<unsigned>::iterator list_begin = activeThreads.begin(); 1430 list<unsigned>::iterator list_end = activeThreads.end(); 1431 1432 unsigned high_thread = *list_begin; 1433 1434 activeThreads.erase(list_begin); 1435 1436 activeThreads.push_back(high_thread); 1437 } 1438} 1439 1440// Forward declaration of FullO3CPU. 1441template class FullO3CPU<O3CPUImpl>; 1442