cpu.cc revision 2935
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 351858SN/A#if FULL_SYSTEM 361060SN/A#include "sim/system.hh" 371060SN/A#else 381060SN/A#include "sim/process.hh" 391060SN/A#endif 401060SN/A 412325SN/A#include "cpu/activity.hh" 422683Sktlim@umich.edu#include "cpu/simple_thread.hh" 432680Sktlim@umich.edu#include "cpu/thread_context.hh" 442817Sksewell@umich.edu#include "cpu/o3/isa_specific.hh" 451717SN/A#include "cpu/o3/cpu.hh" 461060SN/A 472325SN/A#include "sim/root.hh" 482292SN/A#include "sim/stat_control.hh" 492292SN/A 502794Sktlim@umich.edu#if USE_CHECKER 512794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 522794Sktlim@umich.edu#endif 532794Sktlim@umich.edu 541060SN/Ausing namespace std; 552669Sktlim@umich.eduusing namespace TheISA; 561060SN/A 572733Sktlim@umich.eduBaseO3CPU::BaseO3CPU(Params *params) 582292SN/A : BaseCPU(params), cpu_id(0) 591060SN/A{ 601060SN/A} 611060SN/A 622292SN/Avoid 632733Sktlim@umich.eduBaseO3CPU::regStats() 642292SN/A{ 652292SN/A BaseCPU::regStats(); 662292SN/A} 672292SN/A 681060SN/Atemplate <class Impl> 691755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 701060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 711060SN/A{ 721060SN/A} 731060SN/A 741060SN/Atemplate <class Impl> 751060SN/Avoid 761755SN/AFullO3CPU<Impl>::TickEvent::process() 771060SN/A{ 781060SN/A cpu->tick(); 791060SN/A} 801060SN/A 811060SN/Atemplate <class Impl> 821060SN/Aconst char * 831755SN/AFullO3CPU<Impl>::TickEvent::description() 841060SN/A{ 851755SN/A return "FullO3CPU tick event"; 861060SN/A} 871060SN/A 881060SN/Atemplate <class Impl> 892829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 902829Sksewell@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri) 912829Sksewell@umich.edu{ 922829Sksewell@umich.edu} 932829Sksewell@umich.edu 942829Sksewell@umich.edutemplate <class Impl> 952829Sksewell@umich.eduvoid 962829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 972829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 982829Sksewell@umich.edu{ 992829Sksewell@umich.edu tid = thread_num; 1002829Sksewell@umich.edu cpu = thread_cpu; 1012829Sksewell@umich.edu} 1022829Sksewell@umich.edu 1032829Sksewell@umich.edutemplate <class Impl> 1042829Sksewell@umich.eduvoid 1052829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1062829Sksewell@umich.edu{ 1072829Sksewell@umich.edu cpu->activateThread(tid); 1082829Sksewell@umich.edu} 1092829Sksewell@umich.edu 1102829Sksewell@umich.edutemplate <class Impl> 1112829Sksewell@umich.educonst char * 1122829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::description() 1132829Sksewell@umich.edu{ 1142829Sksewell@umich.edu return "FullO3CPU \"Activate Thread\" event"; 1152829Sksewell@umich.edu} 1162829Sksewell@umich.edu 1172829Sksewell@umich.edutemplate <class Impl> 1182875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1192875Sksewell@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri) 1202875Sksewell@umich.edu{ 1212875Sksewell@umich.edu} 1222875Sksewell@umich.edu 1232875Sksewell@umich.edutemplate <class Impl> 1242875Sksewell@umich.eduvoid 1252875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1262875Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1272875Sksewell@umich.edu{ 1282875Sksewell@umich.edu tid = thread_num; 1292875Sksewell@umich.edu cpu = thread_cpu; 1302875Sksewell@umich.edu} 1312875Sksewell@umich.edu 1322875Sksewell@umich.edutemplate <class Impl> 1332875Sksewell@umich.eduvoid 1342875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1352875Sksewell@umich.edu{ 1362875Sksewell@umich.edu cpu->deactivateThread(tid); 1372875Sksewell@umich.edu cpu->removeThread(tid); 1382875Sksewell@umich.edu} 1392875Sksewell@umich.edu 1402875Sksewell@umich.edutemplate <class Impl> 1412875Sksewell@umich.educonst char * 1422875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::description() 1432875Sksewell@umich.edu{ 1442875Sksewell@umich.edu return "FullO3CPU \"Deallocate Context\" event"; 1452875Sksewell@umich.edu} 1462875Sksewell@umich.edu 1472875Sksewell@umich.edutemplate <class Impl> 1482292SN/AFullO3CPU<Impl>::FullO3CPU(Params *params) 1492733Sktlim@umich.edu : BaseO3CPU(params), 1501060SN/A tickEvent(this), 1512292SN/A removeInstsThisCycle(false), 1521060SN/A fetch(params), 1531060SN/A decode(params), 1541060SN/A rename(params), 1551060SN/A iew(params), 1561060SN/A commit(params), 1571060SN/A 1582292SN/A regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 1591060SN/A 1602831Sksewell@umich.edu freeList(params->numberOfThreads, 1612292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1622292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1631060SN/A 1642292SN/A rob(params->numROBEntries, params->squashWidth, 1652292SN/A params->smtROBPolicy, params->smtROBThreshold, 1662292SN/A params->numberOfThreads), 1671060SN/A 1682831Sksewell@umich.edu scoreboard(params->numberOfThreads, 1692292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1702292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1712292SN/A TheISA::NumMiscRegs * number_of_threads, 1722292SN/A TheISA::ZeroReg), 1731060SN/A 1742873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1752873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1762873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1772873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1782873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1792873Sktlim@umich.edu activityRec(NumStages, 1802873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1812873Sktlim@umich.edu params->activity), 1821060SN/A 1831060SN/A globalSeqNum(1), 1841060SN/A 1851858SN/A#if FULL_SYSTEM 1862292SN/A system(params->system), 1871060SN/A physmem(system->physmem), 1881060SN/A#endif // FULL_SYSTEM 1892292SN/A mem(params->mem), 1902843Sktlim@umich.edu drainCount(0), 1912316SN/A deferRegistration(params->deferRegistration), 1922316SN/A numThreads(number_of_threads) 1931060SN/A{ 1941060SN/A _status = Idle; 1951681SN/A 1962733Sktlim@umich.edu checker = NULL; 1972733Sktlim@umich.edu 1982794Sktlim@umich.edu if (params->checker) { 1992733Sktlim@umich.edu#if USE_CHECKER 2002316SN/A BaseCPU *temp_checker = params->checker; 2012316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2022316SN/A checker->setMemory(mem); 2032316SN/A#if FULL_SYSTEM 2042316SN/A checker->setSystem(params->system); 2052316SN/A#endif 2062794Sktlim@umich.edu#else 2072794Sktlim@umich.edu panic("Checker enabled but not compiled in!"); 2082794Sktlim@umich.edu#endif // USE_CHECKER 2092316SN/A } 2102316SN/A 2111858SN/A#if !FULL_SYSTEM 2122292SN/A thread.resize(number_of_threads); 2132292SN/A tids.resize(number_of_threads); 2141681SN/A#endif 2151681SN/A 2162325SN/A // The stages also need their CPU pointer setup. However this 2172325SN/A // must be done at the upper level CPU because they have pointers 2182325SN/A // to the upper level CPU, and not this FullO3CPU. 2191060SN/A 2202292SN/A // Set up Pointers to the activeThreads list for each stage 2212292SN/A fetch.setActiveThreads(&activeThreads); 2222292SN/A decode.setActiveThreads(&activeThreads); 2232292SN/A rename.setActiveThreads(&activeThreads); 2242292SN/A iew.setActiveThreads(&activeThreads); 2252292SN/A commit.setActiveThreads(&activeThreads); 2261060SN/A 2271060SN/A // Give each of the stages the time buffer they will use. 2281060SN/A fetch.setTimeBuffer(&timeBuffer); 2291060SN/A decode.setTimeBuffer(&timeBuffer); 2301060SN/A rename.setTimeBuffer(&timeBuffer); 2311060SN/A iew.setTimeBuffer(&timeBuffer); 2321060SN/A commit.setTimeBuffer(&timeBuffer); 2331060SN/A 2341060SN/A // Also setup each of the stages' queues. 2351060SN/A fetch.setFetchQueue(&fetchQueue); 2361060SN/A decode.setFetchQueue(&fetchQueue); 2372292SN/A commit.setFetchQueue(&fetchQueue); 2381060SN/A decode.setDecodeQueue(&decodeQueue); 2391060SN/A rename.setDecodeQueue(&decodeQueue); 2401060SN/A rename.setRenameQueue(&renameQueue); 2411060SN/A iew.setRenameQueue(&renameQueue); 2421060SN/A iew.setIEWQueue(&iewQueue); 2431060SN/A commit.setIEWQueue(&iewQueue); 2441060SN/A commit.setRenameQueue(&renameQueue); 2451060SN/A 2462292SN/A commit.setIEWStage(&iew); 2472292SN/A rename.setIEWStage(&iew); 2482292SN/A rename.setCommitStage(&commit); 2492292SN/A 2502292SN/A#if !FULL_SYSTEM 2512307SN/A int active_threads = params->workload.size(); 2522831Sksewell@umich.edu 2532831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2542831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2552831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2562831Sksewell@umich.edu "edit your workload size."); 2572831Sksewell@umich.edu } 2582292SN/A#else 2592307SN/A int active_threads = 1; 2602292SN/A#endif 2612292SN/A 2622316SN/A //Make Sure That this a Valid Architeture 2632292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2642292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2652292SN/A 2662292SN/A rename.setScoreboard(&scoreboard); 2672292SN/A iew.setScoreboard(&scoreboard); 2682292SN/A 2691060SN/A // Setup the rename map for whichever stages need it. 2702292SN/A PhysRegIndex lreg_idx = 0; 2712292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2721060SN/A 2732292SN/A for (int tid=0; tid < numThreads; tid++) { 2742307SN/A bool bindRegs = (tid <= active_threads - 1); 2752292SN/A 2762292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2772292SN/A params->numPhysIntRegs, 2782325SN/A lreg_idx, //Index for Logical. Regs 2792292SN/A 2802292SN/A TheISA::NumFloatRegs, 2812292SN/A params->numPhysFloatRegs, 2822325SN/A freg_idx, //Index for Float Regs 2832292SN/A 2842292SN/A TheISA::NumMiscRegs, 2852292SN/A 2862292SN/A TheISA::ZeroReg, 2872292SN/A TheISA::ZeroReg, 2882292SN/A 2892292SN/A tid, 2902292SN/A false); 2912292SN/A 2922292SN/A renameMap[tid].init(TheISA::NumIntRegs, 2932292SN/A params->numPhysIntRegs, 2942325SN/A lreg_idx, //Index for Logical. Regs 2952292SN/A 2962292SN/A TheISA::NumFloatRegs, 2972292SN/A params->numPhysFloatRegs, 2982325SN/A freg_idx, //Index for Float Regs 2992292SN/A 3002292SN/A TheISA::NumMiscRegs, 3012292SN/A 3022292SN/A TheISA::ZeroReg, 3032292SN/A TheISA::ZeroReg, 3042292SN/A 3052292SN/A tid, 3062292SN/A bindRegs); 3072292SN/A } 3082292SN/A 3092292SN/A rename.setRenameMap(renameMap); 3102292SN/A commit.setRenameMap(commitRenameMap); 3112292SN/A 3122292SN/A // Give renameMap & rename stage access to the freeList; 3132292SN/A for (int i=0; i < numThreads; i++) { 3142292SN/A renameMap[i].setFreeList(&freeList); 3152292SN/A } 3161060SN/A rename.setFreeList(&freeList); 3172292SN/A 3181060SN/A // Setup the ROB for whichever stages need it. 3191060SN/A commit.setROB(&rob); 3202292SN/A 3212292SN/A lastRunningCycle = curTick; 3222292SN/A 3232829Sksewell@umich.edu lastActivatedCycle = -1; 3242829Sksewell@umich.edu 3252292SN/A contextSwitch = false; 3261060SN/A} 3271060SN/A 3281060SN/Atemplate <class Impl> 3291755SN/AFullO3CPU<Impl>::~FullO3CPU() 3301060SN/A{ 3311060SN/A} 3321060SN/A 3331060SN/Atemplate <class Impl> 3341060SN/Avoid 3351755SN/AFullO3CPU<Impl>::fullCPURegStats() 3361062SN/A{ 3372733Sktlim@umich.edu BaseO3CPU::regStats(); 3382292SN/A 3392733Sktlim@umich.edu // Register any of the O3CPU's stats here. 3402292SN/A timesIdled 3412292SN/A .name(name() + ".timesIdled") 3422292SN/A .desc("Number of times that the entire CPU went into an idle state and" 3432292SN/A " unscheduled itself") 3442292SN/A .prereq(timesIdled); 3452292SN/A 3462292SN/A idleCycles 3472292SN/A .name(name() + ".idleCycles") 3482292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 3492292SN/A "to idling") 3502292SN/A .prereq(idleCycles); 3512292SN/A 3522292SN/A // Number of Instructions simulated 3532292SN/A // -------------------------------- 3542292SN/A // Should probably be in Base CPU but need templated 3552292SN/A // MaxThreads so put in here instead 3562292SN/A committedInsts 3572292SN/A .init(numThreads) 3582292SN/A .name(name() + ".committedInsts") 3592292SN/A .desc("Number of Instructions Simulated"); 3602292SN/A 3612292SN/A totalCommittedInsts 3622292SN/A .name(name() + ".committedInsts_total") 3632292SN/A .desc("Number of Instructions Simulated"); 3642292SN/A 3652292SN/A cpi 3662292SN/A .name(name() + ".cpi") 3672292SN/A .desc("CPI: Cycles Per Instruction") 3682292SN/A .precision(6); 3692292SN/A cpi = simTicks / committedInsts; 3702292SN/A 3712292SN/A totalCpi 3722292SN/A .name(name() + ".cpi_total") 3732292SN/A .desc("CPI: Total CPI of All Threads") 3742292SN/A .precision(6); 3752292SN/A totalCpi = simTicks / totalCommittedInsts; 3762292SN/A 3772292SN/A ipc 3782292SN/A .name(name() + ".ipc") 3792292SN/A .desc("IPC: Instructions Per Cycle") 3802292SN/A .precision(6); 3812292SN/A ipc = committedInsts / simTicks; 3822292SN/A 3832292SN/A totalIpc 3842292SN/A .name(name() + ".ipc_total") 3852292SN/A .desc("IPC: Total IPC of All Threads") 3862292SN/A .precision(6); 3872292SN/A totalIpc = totalCommittedInsts / simTicks; 3882292SN/A 3891062SN/A} 3901062SN/A 3911062SN/Atemplate <class Impl> 3922871Sktlim@umich.eduPort * 3932871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 3942871Sktlim@umich.edu{ 3952871Sktlim@umich.edu if (if_name == "dcache_port") 3962871Sktlim@umich.edu return iew.getDcachePort(); 3972871Sktlim@umich.edu else if (if_name == "icache_port") 3982871Sktlim@umich.edu return fetch.getIcachePort(); 3992871Sktlim@umich.edu else 4002871Sktlim@umich.edu panic("No Such Port\n"); 4012871Sktlim@umich.edu} 4022871Sktlim@umich.edu 4032871Sktlim@umich.edutemplate <class Impl> 4041062SN/Avoid 4051755SN/AFullO3CPU<Impl>::tick() 4061060SN/A{ 4072733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 4081060SN/A 4092292SN/A ++numCycles; 4102292SN/A 4112325SN/A// activity = false; 4122292SN/A 4132292SN/A //Tick each of the stages 4141060SN/A fetch.tick(); 4151060SN/A 4161060SN/A decode.tick(); 4171060SN/A 4181060SN/A rename.tick(); 4191060SN/A 4201060SN/A iew.tick(); 4211060SN/A 4221060SN/A commit.tick(); 4231060SN/A 4242292SN/A#if !FULL_SYSTEM 4252292SN/A doContextSwitch(); 4262292SN/A#endif 4272292SN/A 4282292SN/A // Now advance the time buffers 4291060SN/A timeBuffer.advance(); 4301060SN/A 4311060SN/A fetchQueue.advance(); 4321060SN/A decodeQueue.advance(); 4331060SN/A renameQueue.advance(); 4341060SN/A iewQueue.advance(); 4351060SN/A 4362325SN/A activityRec.advance(); 4372292SN/A 4382292SN/A if (removeInstsThisCycle) { 4392292SN/A cleanUpRemovedInsts(); 4402292SN/A } 4412292SN/A 4422325SN/A if (!tickEvent.scheduled()) { 4432867Sktlim@umich.edu if (_status == SwitchedOut || 4442905Sktlim@umich.edu getState() == SimObject::Drained) { 4452325SN/A // increment stat 4462325SN/A lastRunningCycle = curTick; 4472325SN/A } else if (!activityRec.active()) { 4482325SN/A lastRunningCycle = curTick; 4492325SN/A timesIdled++; 4502325SN/A } else { 4512325SN/A tickEvent.schedule(curTick + cycles(1)); 4522325SN/A } 4532292SN/A } 4542292SN/A 4552292SN/A#if !FULL_SYSTEM 4562292SN/A updateThreadPriority(); 4572292SN/A#endif 4582292SN/A 4591060SN/A} 4601060SN/A 4611060SN/Atemplate <class Impl> 4621060SN/Avoid 4631755SN/AFullO3CPU<Impl>::init() 4641060SN/A{ 4652307SN/A if (!deferRegistration) { 4662680Sktlim@umich.edu registerThreadContexts(); 4672292SN/A } 4681060SN/A 4692292SN/A // Set inSyscall so that the CPU doesn't squash when initially 4702292SN/A // setting up registers. 4712292SN/A for (int i = 0; i < number_of_threads; ++i) 4722292SN/A thread[i]->inSyscall = true; 4732292SN/A 4742292SN/A for (int tid=0; tid < number_of_threads; tid++) { 4751858SN/A#if FULL_SYSTEM 4762680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 4771681SN/A#else 4782680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 4791681SN/A#endif 4802292SN/A // Threads start in the Suspended State 4812680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 4822292SN/A continue; 4831060SN/A } 4841060SN/A 4852292SN/A#if FULL_SYSTEM 4862680Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 4872292SN/A#endif 4882292SN/A } 4892292SN/A 4902292SN/A // Clear inSyscall. 4912292SN/A for (int i = 0; i < number_of_threads; ++i) 4922292SN/A thread[i]->inSyscall = false; 4932292SN/A 4942316SN/A // Initialize stages. 4952292SN/A fetch.initStage(); 4962292SN/A iew.initStage(); 4972292SN/A rename.initStage(); 4982292SN/A commit.initStage(); 4992292SN/A 5002292SN/A commit.setThreads(thread); 5012292SN/A} 5022292SN/A 5032292SN/Atemplate <class Impl> 5042292SN/Avoid 5052875Sksewell@umich.eduFullO3CPU<Impl>::activateThread(unsigned tid) 5062875Sksewell@umich.edu{ 5072875Sksewell@umich.edu list<unsigned>::iterator isActive = find( 5082875Sksewell@umich.edu activeThreads.begin(), activeThreads.end(), tid); 5092875Sksewell@umich.edu 5102875Sksewell@umich.edu if (isActive == activeThreads.end()) { 5112875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 5122875Sksewell@umich.edu tid); 5132875Sksewell@umich.edu 5142875Sksewell@umich.edu activeThreads.push_back(tid); 5152875Sksewell@umich.edu } 5162875Sksewell@umich.edu} 5172875Sksewell@umich.edu 5182875Sksewell@umich.edutemplate <class Impl> 5192875Sksewell@umich.eduvoid 5202875Sksewell@umich.eduFullO3CPU<Impl>::deactivateThread(unsigned tid) 5212875Sksewell@umich.edu{ 5222875Sksewell@umich.edu //Remove From Active List, if Active 5232875Sksewell@umich.edu list<unsigned>::iterator thread_it = 5242875Sksewell@umich.edu find(activeThreads.begin(), activeThreads.end(), tid); 5252875Sksewell@umich.edu 5262875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 5272875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 5282875Sksewell@umich.edu tid); 5292875Sksewell@umich.edu activeThreads.erase(thread_it); 5302875Sksewell@umich.edu } 5312875Sksewell@umich.edu} 5322875Sksewell@umich.edu 5332875Sksewell@umich.edutemplate <class Impl> 5342875Sksewell@umich.eduvoid 5352875Sksewell@umich.eduFullO3CPU<Impl>::activateContext(int tid, int delay) 5362875Sksewell@umich.edu{ 5372875Sksewell@umich.edu // Needs to set each stage to running as well. 5382875Sksewell@umich.edu if (delay){ 5392875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 5402875Sksewell@umich.edu "on cycle %d\n", tid, curTick + cycles(delay)); 5412875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 5422875Sksewell@umich.edu } else { 5432875Sksewell@umich.edu activateThread(tid); 5442875Sksewell@umich.edu } 5452875Sksewell@umich.edu 5462875Sksewell@umich.edu if(lastActivatedCycle < curTick) { 5472875Sksewell@umich.edu scheduleTickEvent(delay); 5482875Sksewell@umich.edu 5492875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 5502875Sksewell@umich.edu // deschedule itself. 5512875Sksewell@umich.edu activityRec.activity(); 5522875Sksewell@umich.edu fetch.wakeFromQuiesce(); 5532875Sksewell@umich.edu 5542875Sksewell@umich.edu lastActivatedCycle = curTick; 5552875Sksewell@umich.edu 5562875Sksewell@umich.edu _status = Running; 5572875Sksewell@umich.edu } 5582875Sksewell@umich.edu} 5592875Sksewell@umich.edu 5602875Sksewell@umich.edutemplate <class Impl> 5612875Sksewell@umich.eduvoid 5622875Sksewell@umich.eduFullO3CPU<Impl>::deallocateContext(int tid, int delay) 5632875Sksewell@umich.edu{ 5642875Sksewell@umich.edu // Schedule removal of thread data from CPU 5652875Sksewell@umich.edu if (delay){ 5662875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 5672875Sksewell@umich.edu "on cycle %d\n", tid, curTick + cycles(delay)); 5682875Sksewell@umich.edu scheduleDeallocateContextEvent(tid, delay); 5692875Sksewell@umich.edu } else { 5702875Sksewell@umich.edu deactivateThread(tid); 5712875Sksewell@umich.edu removeThread(tid); 5722875Sksewell@umich.edu } 5732875Sksewell@umich.edu} 5742875Sksewell@umich.edu 5752875Sksewell@umich.edutemplate <class Impl> 5762875Sksewell@umich.eduvoid 5772875Sksewell@umich.eduFullO3CPU<Impl>::suspendContext(int tid) 5782875Sksewell@umich.edu{ 5792875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 5802911Sksewell@umich.edu deactivateThread(tid); 5812910Sksewell@umich.edu if (activeThreads.size() == 0) 5822910Sksewell@umich.edu unscheduleTickEvent(); 5832875Sksewell@umich.edu _status = Idle; 5842875Sksewell@umich.edu} 5852875Sksewell@umich.edu 5862875Sksewell@umich.edutemplate <class Impl> 5872875Sksewell@umich.eduvoid 5882875Sksewell@umich.eduFullO3CPU<Impl>::haltContext(int tid) 5892875Sksewell@umich.edu{ 5902910Sksewell@umich.edu //For now, this is the same as deallocate 5912910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 5922910Sksewell@umich.edu deallocateContext(tid, 1); 5932875Sksewell@umich.edu} 5942875Sksewell@umich.edu 5952875Sksewell@umich.edutemplate <class Impl> 5962875Sksewell@umich.eduvoid 5972292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 5982292SN/A{ 5992847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 6002292SN/A // Will change now that the PC and thread state is internal to the CPU 6012683Sktlim@umich.edu // and not in the ThreadContext. 6022292SN/A#if FULL_SYSTEM 6032680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 6042292SN/A#else 6052847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 6062292SN/A#endif 6072292SN/A 6082292SN/A //Bind Int Regs to Rename Map 6092292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6102292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 6112292SN/A 6122292SN/A renameMap[tid].setEntry(ireg,phys_reg); 6132292SN/A scoreboard.setReg(phys_reg); 6142292SN/A } 6152292SN/A 6162292SN/A //Bind Float Regs to Rename Map 6172292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 6182292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 6192292SN/A 6202292SN/A renameMap[tid].setEntry(freg,phys_reg); 6212292SN/A scoreboard.setReg(phys_reg); 6222292SN/A } 6232292SN/A 6242292SN/A //Copy Thread Data Into RegFile 6252847Sksewell@umich.edu //this->copyFromTC(tid); 6262292SN/A 6272847Sksewell@umich.edu //Set PC/NPC/NNPC 6282847Sksewell@umich.edu setPC(src_tc->readPC(), tid); 6292847Sksewell@umich.edu setNextPC(src_tc->readNextPC(), tid); 6302847Sksewell@umich.edu#if THE_ISA != ALPHA_ISA 6312847Sksewell@umich.edu setNextNPC(src_tc->readNextNPC(), tid); 6322847Sksewell@umich.edu#endif 6332292SN/A 6342680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 6352292SN/A 6362292SN/A activateContext(tid,1); 6372292SN/A 6382292SN/A //Reset ROB/IQ/LSQ Entries 6392292SN/A commit.rob->resetEntries(); 6402292SN/A iew.resetEntries(); 6412292SN/A} 6422292SN/A 6432292SN/Atemplate <class Impl> 6442292SN/Avoid 6452292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 6462292SN/A{ 6472877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 6482847Sksewell@umich.edu 6492847Sksewell@umich.edu // Copy Thread Data From RegFile 6502847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 6512847Sksewell@umich.edu //this->copyToTC(tid); 6522847Sksewell@umich.edu 6532847Sksewell@umich.edu // Unbind Int Regs from Rename Map 6542292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6552292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 6562292SN/A 6572292SN/A scoreboard.unsetReg(phys_reg); 6582292SN/A freeList.addReg(phys_reg); 6592292SN/A } 6602292SN/A 6612847Sksewell@umich.edu // Unbind Float Regs from Rename Map 6622292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 6632292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 6642292SN/A 6652292SN/A scoreboard.unsetReg(phys_reg); 6662292SN/A freeList.addReg(phys_reg); 6672292SN/A } 6682292SN/A 6692847Sksewell@umich.edu // Squash Throughout Pipeline 6702935Sksewell@umich.edu InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 6712935Sksewell@umich.edu fetch.squash(0, squash_seq_num, true, tid); 6722292SN/A decode.squash(tid); 6732935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 6742875Sksewell@umich.edu iew.squash(tid); 6752935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 6762292SN/A 6772292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 6782292SN/A 6792847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 6802292SN/A if (activeThreads.size() >= 1) { 6812292SN/A commit.rob->resetEntries(); 6822292SN/A iew.resetEntries(); 6832292SN/A } 6842292SN/A} 6852292SN/A 6862292SN/A 6872292SN/Atemplate <class Impl> 6882292SN/Avoid 6892292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 6902292SN/A{ 6912733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 6922292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 6932292SN/A tid); 6942292SN/A 6952292SN/A bool ready = true; 6962292SN/A 6972292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 6982733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 6992292SN/A "Phys. Int. Regs.\n", 7002292SN/A tid); 7012292SN/A ready = false; 7022292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 7032733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7042292SN/A "Phys. Float. Regs.\n", 7052292SN/A tid); 7062292SN/A ready = false; 7072292SN/A } else if (commit.rob->numFreeEntries() >= 7082292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 7092733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7102292SN/A "ROB entries.\n", 7112292SN/A tid); 7122292SN/A ready = false; 7132292SN/A } else if (iew.instQueue.numFreeEntries() >= 7142292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 7152733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7162292SN/A "IQ entries.\n", 7172292SN/A tid); 7182292SN/A ready = false; 7192292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 7202292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 7212733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7222292SN/A "LSQ entries.\n", 7232292SN/A tid); 7242292SN/A ready = false; 7252292SN/A } 7262292SN/A 7272292SN/A if (ready) { 7282292SN/A insertThread(tid); 7292292SN/A 7302292SN/A contextSwitch = false; 7312292SN/A 7322292SN/A cpuWaitList.remove(tid); 7332292SN/A } else { 7342292SN/A suspendContext(tid); 7352292SN/A 7362292SN/A //blocks fetch 7372292SN/A contextSwitch = true; 7382292SN/A 7392875Sksewell@umich.edu //@todo: dont always add to waitlist 7402292SN/A //do waitlist 7412292SN/A cpuWaitList.push_back(tid); 7421060SN/A } 7431060SN/A} 7441060SN/A 7451060SN/Atemplate <class Impl> 7462852Sktlim@umich.eduvoid 7472864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 7482864Sktlim@umich.edu{ 7492918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 7502918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 7512864Sktlim@umich.edu BaseCPU::serialize(os); 7522864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 7532864Sktlim@umich.edu tickEvent.serialize(os); 7542864Sktlim@umich.edu 7552864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 7562864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 7572864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 7582864Sktlim@umich.edu static SimpleThread temp; 7592864Sktlim@umich.edu 7602864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 7612864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 7622864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 7632864Sktlim@umich.edu temp.serialize(os); 7642864Sktlim@umich.edu } 7652864Sktlim@umich.edu} 7662864Sktlim@umich.edu 7672864Sktlim@umich.edutemplate <class Impl> 7682864Sktlim@umich.eduvoid 7692864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 7702864Sktlim@umich.edu{ 7712918Sktlim@umich.edu SimObject::State so_state; 7722918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 7732864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 7742864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 7752864Sktlim@umich.edu 7762864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 7772864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 7782864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 7792864Sktlim@umich.edu static SimpleThread temp; 7802864Sktlim@umich.edu 7812864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 7822864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 7832864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 7842864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 7852864Sktlim@umich.edu } 7862864Sktlim@umich.edu} 7872864Sktlim@umich.edu 7882864Sktlim@umich.edutemplate <class Impl> 7892905Sktlim@umich.eduunsigned int 7902843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 7911060SN/A{ 7922843Sktlim@umich.edu drainCount = 0; 7932843Sktlim@umich.edu fetch.drain(); 7942843Sktlim@umich.edu decode.drain(); 7952843Sktlim@umich.edu rename.drain(); 7962843Sktlim@umich.edu iew.drain(); 7972843Sktlim@umich.edu commit.drain(); 7982325SN/A 7992325SN/A // Wake the CPU and record activity so everything can drain out if 8002863Sktlim@umich.edu // the CPU was not able to immediately drain. 8012905Sktlim@umich.edu if (getState() != SimObject::Drained) { 8022864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 8032864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 8042864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 8052864Sktlim@umich.edu // process on the drain event. 8062864Sktlim@umich.edu drainEvent = drain_event; 8072843Sktlim@umich.edu 8082863Sktlim@umich.edu wakeCPU(); 8092863Sktlim@umich.edu activityRec.activity(); 8102852Sktlim@umich.edu 8112905Sktlim@umich.edu return 1; 8122863Sktlim@umich.edu } else { 8132905Sktlim@umich.edu return 0; 8142863Sktlim@umich.edu } 8152316SN/A} 8162310SN/A 8172316SN/Atemplate <class Impl> 8182316SN/Avoid 8192843Sktlim@umich.eduFullO3CPU<Impl>::resume() 8202316SN/A{ 8212905Sktlim@umich.edu assert(system->getMemoryMode() == System::Timing); 8222843Sktlim@umich.edu fetch.resume(); 8232843Sktlim@umich.edu decode.resume(); 8242843Sktlim@umich.edu rename.resume(); 8252843Sktlim@umich.edu iew.resume(); 8262843Sktlim@umich.edu commit.resume(); 8272316SN/A 8282905Sktlim@umich.edu changeState(SimObject::Running); 8292905Sktlim@umich.edu 8302864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 8312864Sktlim@umich.edu return; 8322864Sktlim@umich.edu 8332843Sktlim@umich.edu if (!tickEvent.scheduled()) 8342843Sktlim@umich.edu tickEvent.schedule(curTick); 8352843Sktlim@umich.edu _status = Running; 8362843Sktlim@umich.edu} 8372316SN/A 8382843Sktlim@umich.edutemplate <class Impl> 8392843Sktlim@umich.eduvoid 8402843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 8412843Sktlim@umich.edu{ 8422843Sktlim@umich.edu if (++drainCount == NumStages) { 8432316SN/A if (tickEvent.scheduled()) 8442316SN/A tickEvent.squash(); 8452863Sktlim@umich.edu 8462905Sktlim@umich.edu changeState(SimObject::Drained); 8472863Sktlim@umich.edu 8482863Sktlim@umich.edu if (drainEvent) { 8492863Sktlim@umich.edu drainEvent->process(); 8502863Sktlim@umich.edu drainEvent = NULL; 8512863Sktlim@umich.edu } 8522310SN/A } 8532843Sktlim@umich.edu assert(drainCount <= 5); 8542843Sktlim@umich.edu} 8552843Sktlim@umich.edu 8562843Sktlim@umich.edutemplate <class Impl> 8572843Sktlim@umich.eduvoid 8582843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 8592843Sktlim@umich.edu{ 8602843Sktlim@umich.edu fetch.switchOut(); 8612843Sktlim@umich.edu rename.switchOut(); 8622843Sktlim@umich.edu commit.switchOut(); 8632843Sktlim@umich.edu instList.clear(); 8642843Sktlim@umich.edu while (!removeList.empty()) { 8652843Sktlim@umich.edu removeList.pop(); 8662843Sktlim@umich.edu } 8672843Sktlim@umich.edu 8682843Sktlim@umich.edu _status = SwitchedOut; 8692843Sktlim@umich.edu#if USE_CHECKER 8702843Sktlim@umich.edu if (checker) 8712843Sktlim@umich.edu checker->switchOut(); 8722843Sktlim@umich.edu#endif 8731060SN/A} 8741060SN/A 8751060SN/Atemplate <class Impl> 8761060SN/Avoid 8771755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 8781060SN/A{ 8792325SN/A // Flush out any old data from the time buffers. 8802873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 8812307SN/A timeBuffer.advance(); 8822307SN/A fetchQueue.advance(); 8832307SN/A decodeQueue.advance(); 8842307SN/A renameQueue.advance(); 8852307SN/A iewQueue.advance(); 8862307SN/A } 8872307SN/A 8882325SN/A activityRec.reset(); 8892307SN/A 8901060SN/A BaseCPU::takeOverFrom(oldCPU); 8911060SN/A 8922307SN/A fetch.takeOverFrom(); 8932307SN/A decode.takeOverFrom(); 8942307SN/A rename.takeOverFrom(); 8952307SN/A iew.takeOverFrom(); 8962307SN/A commit.takeOverFrom(); 8972307SN/A 8981060SN/A assert(!tickEvent.scheduled()); 8991060SN/A 9002325SN/A // @todo: Figure out how to properly select the tid to put onto 9012325SN/A // the active threads list. 9022307SN/A int tid = 0; 9032307SN/A 9042307SN/A list<unsigned>::iterator isActive = find( 9052307SN/A activeThreads.begin(), activeThreads.end(), tid); 9062307SN/A 9072307SN/A if (isActive == activeThreads.end()) { 9082325SN/A //May Need to Re-code this if the delay variable is the delay 9092325SN/A //needed for thread to activate 9102733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 9112307SN/A tid); 9122307SN/A 9132307SN/A activeThreads.push_back(tid); 9142307SN/A } 9152307SN/A 9162325SN/A // Set all statuses to active, schedule the CPU's tick event. 9172307SN/A // @todo: Fix up statuses so this is handled properly 9182680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 9192680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 9202680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 9211681SN/A _status = Running; 9221681SN/A tickEvent.schedule(curTick); 9231681SN/A } 9241060SN/A } 9252307SN/A if (!tickEvent.scheduled()) 9262307SN/A tickEvent.schedule(curTick); 9271060SN/A} 9281060SN/A 9291060SN/Atemplate <class Impl> 9301060SN/Auint64_t 9311755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 9321060SN/A{ 9331060SN/A return regFile.readIntReg(reg_idx); 9341060SN/A} 9351060SN/A 9361060SN/Atemplate <class Impl> 9372455SN/AFloatReg 9382455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 9391060SN/A{ 9402455SN/A return regFile.readFloatReg(reg_idx, width); 9411060SN/A} 9421060SN/A 9431060SN/Atemplate <class Impl> 9442455SN/AFloatReg 9452455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 9461060SN/A{ 9472455SN/A return regFile.readFloatReg(reg_idx); 9481060SN/A} 9491060SN/A 9501060SN/Atemplate <class Impl> 9512455SN/AFloatRegBits 9522455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 9531060SN/A{ 9542455SN/A return regFile.readFloatRegBits(reg_idx, width); 9552455SN/A} 9562455SN/A 9572455SN/Atemplate <class Impl> 9582455SN/AFloatRegBits 9592455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 9602455SN/A{ 9612455SN/A return regFile.readFloatRegBits(reg_idx); 9621060SN/A} 9631060SN/A 9641060SN/Atemplate <class Impl> 9651060SN/Avoid 9661755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 9671060SN/A{ 9681060SN/A regFile.setIntReg(reg_idx, val); 9691060SN/A} 9701060SN/A 9711060SN/Atemplate <class Impl> 9721060SN/Avoid 9732455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 9741060SN/A{ 9752455SN/A regFile.setFloatReg(reg_idx, val, width); 9761060SN/A} 9771060SN/A 9781060SN/Atemplate <class Impl> 9791060SN/Avoid 9802455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 9811060SN/A{ 9822455SN/A regFile.setFloatReg(reg_idx, val); 9831060SN/A} 9841060SN/A 9851060SN/Atemplate <class Impl> 9861060SN/Avoid 9872455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 9881060SN/A{ 9892455SN/A regFile.setFloatRegBits(reg_idx, val, width); 9902455SN/A} 9912455SN/A 9922455SN/Atemplate <class Impl> 9932455SN/Avoid 9942455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 9952455SN/A{ 9962455SN/A regFile.setFloatRegBits(reg_idx, val); 9971060SN/A} 9981060SN/A 9991060SN/Atemplate <class Impl> 10001060SN/Auint64_t 10012292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 10021060SN/A{ 10032292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10042292SN/A 10052292SN/A return regFile.readIntReg(phys_reg); 10062292SN/A} 10072292SN/A 10082292SN/Atemplate <class Impl> 10092292SN/Afloat 10102292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 10112292SN/A{ 10122307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10132307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10142292SN/A 10152669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 10162292SN/A} 10172292SN/A 10182292SN/Atemplate <class Impl> 10192292SN/Adouble 10202292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 10212292SN/A{ 10222307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10232307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10242292SN/A 10252669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 10262292SN/A} 10272292SN/A 10282292SN/Atemplate <class Impl> 10292292SN/Auint64_t 10302292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 10312292SN/A{ 10322307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10332307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10342292SN/A 10352669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 10361060SN/A} 10371060SN/A 10381060SN/Atemplate <class Impl> 10391060SN/Avoid 10402292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 10411060SN/A{ 10422292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10432292SN/A 10442292SN/A regFile.setIntReg(phys_reg, val); 10451060SN/A} 10461060SN/A 10471060SN/Atemplate <class Impl> 10481060SN/Avoid 10492292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 10501060SN/A{ 10512918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 10522918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10532292SN/A 10542669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 10551060SN/A} 10561060SN/A 10571060SN/Atemplate <class Impl> 10581060SN/Avoid 10592292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 10601060SN/A{ 10612918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 10622918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10632292SN/A 10642669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 10651060SN/A} 10661060SN/A 10671060SN/Atemplate <class Impl> 10681060SN/Avoid 10692292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 10701060SN/A{ 10712918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 10722918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10731060SN/A 10742669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 10752292SN/A} 10762292SN/A 10772292SN/Atemplate <class Impl> 10782292SN/Auint64_t 10792292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 10802292SN/A{ 10812292SN/A return commit.readPC(tid); 10821060SN/A} 10831060SN/A 10841060SN/Atemplate <class Impl> 10851060SN/Avoid 10862292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 10871060SN/A{ 10882292SN/A commit.setPC(new_PC, tid); 10892292SN/A} 10901060SN/A 10912292SN/Atemplate <class Impl> 10922292SN/Auint64_t 10932292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 10942292SN/A{ 10952292SN/A return commit.readNextPC(tid); 10962292SN/A} 10971060SN/A 10982292SN/Atemplate <class Impl> 10992292SN/Avoid 11002292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 11012292SN/A{ 11022292SN/A commit.setNextPC(val, tid); 11032292SN/A} 11041060SN/A 11052756Sksewell@umich.edutemplate <class Impl> 11062756Sksewell@umich.eduuint64_t 11072756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 11082756Sksewell@umich.edu{ 11092756Sksewell@umich.edu return commit.readNextNPC(tid); 11102756Sksewell@umich.edu} 11112756Sksewell@umich.edu 11122756Sksewell@umich.edutemplate <class Impl> 11132756Sksewell@umich.eduvoid 11142935Sksewell@umich.eduFullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) 11152756Sksewell@umich.edu{ 11162756Sksewell@umich.edu commit.setNextNPC(val, tid); 11172756Sksewell@umich.edu} 11182756Sksewell@umich.edu 11192292SN/Atemplate <class Impl> 11202292SN/Atypename FullO3CPU<Impl>::ListIt 11212292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 11222292SN/A{ 11232292SN/A instList.push_back(inst); 11241060SN/A 11252292SN/A return --(instList.end()); 11262292SN/A} 11271060SN/A 11282292SN/Atemplate <class Impl> 11292292SN/Avoid 11302292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 11312292SN/A{ 11322292SN/A // Keep an instruction count. 11332292SN/A thread[tid]->numInst++; 11342292SN/A thread[tid]->numInsts++; 11352292SN/A committedInsts[tid]++; 11362292SN/A totalCommittedInsts++; 11372292SN/A 11382292SN/A // Check for instruction-count-based events. 11392292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 11402292SN/A} 11412292SN/A 11422292SN/Atemplate <class Impl> 11432292SN/Avoid 11442292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 11452292SN/A{ 11462292SN/A removeInstsThisCycle = true; 11472292SN/A 11482292SN/A removeList.push(inst->getInstListIt()); 11491060SN/A} 11501060SN/A 11511060SN/Atemplate <class Impl> 11521060SN/Avoid 11531755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 11541060SN/A{ 11552733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 11562292SN/A "[sn:%lli]\n", 11572303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 11581060SN/A 11592292SN/A removeInstsThisCycle = true; 11601060SN/A 11611060SN/A // Remove the front instruction. 11622292SN/A removeList.push(inst->getInstListIt()); 11631060SN/A} 11641060SN/A 11651060SN/Atemplate <class Impl> 11661060SN/Avoid 11672935Sksewell@umich.eduFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid, 11682935Sksewell@umich.edu bool squash_delay_slot, 11692935Sksewell@umich.edu const InstSeqNum &delay_slot_seq_num) 11701060SN/A{ 11712733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 11722292SN/A " list.\n", tid); 11731060SN/A 11742292SN/A ListIt end_it; 11751060SN/A 11762292SN/A bool rob_empty = false; 11772292SN/A 11782292SN/A if (instList.empty()) { 11792292SN/A return; 11802292SN/A } else if (rob.isEmpty(/*tid*/)) { 11812733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 11822292SN/A end_it = instList.begin(); 11832292SN/A rob_empty = true; 11842292SN/A } else { 11852292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 11862733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 11872292SN/A } 11882292SN/A 11892292SN/A removeInstsThisCycle = true; 11902292SN/A 11912292SN/A ListIt inst_it = instList.end(); 11922292SN/A 11932292SN/A inst_it--; 11942292SN/A 11952292SN/A // Walk through the instruction list, removing any instructions 11962292SN/A // that were inserted after the given instruction iterator, end_it. 11972292SN/A while (inst_it != end_it) { 11982292SN/A assert(!instList.empty()); 11992292SN/A 12002935Sksewell@umich.edu#if THE_ISA != ALPHA_ISA 12012935Sksewell@umich.edu if(!squash_delay_slot && 12022935Sksewell@umich.edu delay_slot_seq_num >= (*inst_it)->seqNum) { 12032935Sksewell@umich.edu break; 12042935Sksewell@umich.edu } 12052935Sksewell@umich.edu#endif 12062292SN/A squashInstIt(inst_it, tid); 12072292SN/A 12082292SN/A inst_it--; 12092292SN/A } 12102292SN/A 12112292SN/A // If the ROB was empty, then we actually need to remove the first 12122292SN/A // instruction as well. 12132292SN/A if (rob_empty) { 12142292SN/A squashInstIt(inst_it, tid); 12152292SN/A } 12161060SN/A} 12171060SN/A 12181060SN/Atemplate <class Impl> 12191060SN/Avoid 12202292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 12212292SN/A unsigned tid) 12221062SN/A{ 12232292SN/A assert(!instList.empty()); 12242292SN/A 12252292SN/A removeInstsThisCycle = true; 12262292SN/A 12272292SN/A ListIt inst_iter = instList.end(); 12282292SN/A 12292292SN/A inst_iter--; 12302292SN/A 12312733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 12322292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 12332292SN/A tid, seq_num, (*inst_iter)->seqNum); 12341062SN/A 12352292SN/A while ((*inst_iter)->seqNum > seq_num) { 12361062SN/A 12372292SN/A bool break_loop = (inst_iter == instList.begin()); 12381062SN/A 12392292SN/A squashInstIt(inst_iter, tid); 12401062SN/A 12412292SN/A inst_iter--; 12421062SN/A 12432292SN/A if (break_loop) 12442292SN/A break; 12452292SN/A } 12462292SN/A} 12472292SN/A 12482292SN/Atemplate <class Impl> 12492292SN/Ainline void 12502292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 12512292SN/A{ 12522292SN/A if ((*instIt)->threadNumber == tid) { 12532733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 12542292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 12552292SN/A (*instIt)->threadNumber, 12562292SN/A (*instIt)->seqNum, 12572292SN/A (*instIt)->readPC()); 12581062SN/A 12591062SN/A // Mark it as squashed. 12602292SN/A (*instIt)->setSquashed(); 12612292SN/A 12622325SN/A // @todo: Formulate a consistent method for deleting 12632325SN/A // instructions from the instruction list 12642292SN/A // Remove the instruction from the list. 12652292SN/A removeList.push(instIt); 12662292SN/A } 12672292SN/A} 12682292SN/A 12692292SN/Atemplate <class Impl> 12702292SN/Avoid 12712292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 12722292SN/A{ 12732292SN/A while (!removeList.empty()) { 12742733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 12752292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 12762292SN/A (*removeList.front())->threadNumber, 12772292SN/A (*removeList.front())->seqNum, 12782292SN/A (*removeList.front())->readPC()); 12792292SN/A 12802292SN/A instList.erase(removeList.front()); 12812292SN/A 12822292SN/A removeList.pop(); 12831062SN/A } 12841062SN/A 12852292SN/A removeInstsThisCycle = false; 12861062SN/A} 12872325SN/A/* 12881062SN/Atemplate <class Impl> 12891062SN/Avoid 12901755SN/AFullO3CPU<Impl>::removeAllInsts() 12911060SN/A{ 12921060SN/A instList.clear(); 12931060SN/A} 12942325SN/A*/ 12951060SN/Atemplate <class Impl> 12961060SN/Avoid 12971755SN/AFullO3CPU<Impl>::dumpInsts() 12981060SN/A{ 12991060SN/A int num = 0; 13001060SN/A 13012292SN/A ListIt inst_list_it = instList.begin(); 13022292SN/A 13032292SN/A cprintf("Dumping Instruction List\n"); 13042292SN/A 13052292SN/A while (inst_list_it != instList.end()) { 13062292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 13072292SN/A "Squashed:%i\n\n", 13082292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 13092292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 13102292SN/A (*inst_list_it)->isSquashed()); 13111060SN/A inst_list_it++; 13121060SN/A ++num; 13131060SN/A } 13141060SN/A} 13152325SN/A/* 13161060SN/Atemplate <class Impl> 13171060SN/Avoid 13181755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 13191060SN/A{ 13201060SN/A iew.wakeDependents(inst); 13211060SN/A} 13222325SN/A*/ 13232292SN/Atemplate <class Impl> 13242292SN/Avoid 13252292SN/AFullO3CPU<Impl>::wakeCPU() 13262292SN/A{ 13272325SN/A if (activityRec.active() || tickEvent.scheduled()) { 13282325SN/A DPRINTF(Activity, "CPU already running.\n"); 13292292SN/A return; 13302292SN/A } 13312292SN/A 13322325SN/A DPRINTF(Activity, "Waking up CPU\n"); 13332325SN/A 13342325SN/A idleCycles += (curTick - 1) - lastRunningCycle; 13352292SN/A 13362292SN/A tickEvent.schedule(curTick); 13372292SN/A} 13382292SN/A 13392292SN/Atemplate <class Impl> 13402292SN/Aint 13412292SN/AFullO3CPU<Impl>::getFreeTid() 13422292SN/A{ 13432292SN/A for (int i=0; i < numThreads; i++) { 13442292SN/A if (!tids[i]) { 13452292SN/A tids[i] = true; 13462292SN/A return i; 13472292SN/A } 13482292SN/A } 13492292SN/A 13502292SN/A return -1; 13512292SN/A} 13522292SN/A 13532292SN/Atemplate <class Impl> 13542292SN/Avoid 13552292SN/AFullO3CPU<Impl>::doContextSwitch() 13562292SN/A{ 13572292SN/A if (contextSwitch) { 13582292SN/A 13592292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 13602292SN/A 13612292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 13622292SN/A activateWhenReady(tid); 13632292SN/A } 13642292SN/A 13652292SN/A if (cpuWaitList.size() == 0) 13662292SN/A contextSwitch = true; 13672292SN/A } 13682292SN/A} 13692292SN/A 13702292SN/Atemplate <class Impl> 13712292SN/Avoid 13722292SN/AFullO3CPU<Impl>::updateThreadPriority() 13732292SN/A{ 13742292SN/A if (activeThreads.size() > 1) 13752292SN/A { 13762292SN/A //DEFAULT TO ROUND ROBIN SCHEME 13772292SN/A //e.g. Move highest priority to end of thread list 13782292SN/A list<unsigned>::iterator list_begin = activeThreads.begin(); 13792292SN/A list<unsigned>::iterator list_end = activeThreads.end(); 13802292SN/A 13812292SN/A unsigned high_thread = *list_begin; 13822292SN/A 13832292SN/A activeThreads.erase(list_begin); 13842292SN/A 13852292SN/A activeThreads.push_back(high_thread); 13862292SN/A } 13872292SN/A} 13881060SN/A 13891755SN/A// Forward declaration of FullO3CPU. 13902818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1391