cpu.cc revision 2829
111986Sandreas.sandberg@arm.com/* 211986Sandreas.sandberg@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 311986Sandreas.sandberg@arm.com * All rights reserved. 411986Sandreas.sandberg@arm.com * 511986Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 611986Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 711986Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 811986Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 911986Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1011986Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 1111986Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 1211986Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 1311986Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 1411986Sandreas.sandberg@arm.com * this software without specific prior written permission. 1511986Sandreas.sandberg@arm.com * 1611986Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711986Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811986Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911986Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011986Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111986Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211986Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311986Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411986Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511986Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611986Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711986Sandreas.sandberg@arm.com * 2811986Sandreas.sandberg@arm.com * Authors: Kevin Lim 2911986Sandreas.sandberg@arm.com * Korey Sewell 3011986Sandreas.sandberg@arm.com */ 3111986Sandreas.sandberg@arm.com 3211986Sandreas.sandberg@arm.com#include "config/full_system.hh" 3311986Sandreas.sandberg@arm.com#include "config/use_checker.hh" 3411986Sandreas.sandberg@arm.com 3511986Sandreas.sandberg@arm.com#if FULL_SYSTEM 3612037Sandreas.sandberg@arm.com#include "sim/system.hh" 3712037Sandreas.sandberg@arm.com#else 3811986Sandreas.sandberg@arm.com#include "sim/process.hh" 3911986Sandreas.sandberg@arm.com#endif 4011986Sandreas.sandberg@arm.com 4111986Sandreas.sandberg@arm.com#include "cpu/activity.hh" 4211986Sandreas.sandberg@arm.com#include "cpu/simple_thread.hh" 4311986Sandreas.sandberg@arm.com#include "cpu/thread_context.hh" 4411986Sandreas.sandberg@arm.com#include "cpu/o3/isa_specific.hh" 4511986Sandreas.sandberg@arm.com#include "cpu/o3/cpu.hh" 4611986Sandreas.sandberg@arm.com 4711986Sandreas.sandberg@arm.com#include "sim/root.hh" 4811986Sandreas.sandberg@arm.com#include "sim/stat_control.hh" 4911986Sandreas.sandberg@arm.com 5011986Sandreas.sandberg@arm.com#if USE_CHECKER 5111986Sandreas.sandberg@arm.com#include "cpu/checker/cpu.hh" 5211986Sandreas.sandberg@arm.com#endif 5311986Sandreas.sandberg@arm.com 5411986Sandreas.sandberg@arm.comusing namespace std; 5511986Sandreas.sandberg@arm.comusing namespace TheISA; 5611986Sandreas.sandberg@arm.com 5711986Sandreas.sandberg@arm.comBaseO3CPU::BaseO3CPU(Params *params) 5811986Sandreas.sandberg@arm.com : BaseCPU(params), cpu_id(0) 5911986Sandreas.sandberg@arm.com{ 6011986Sandreas.sandberg@arm.com} 6111986Sandreas.sandberg@arm.com 6212037Sandreas.sandberg@arm.comvoid 6311986Sandreas.sandberg@arm.comBaseO3CPU::regStats() 6411986Sandreas.sandberg@arm.com{ 6511986Sandreas.sandberg@arm.com BaseCPU::regStats(); 6611986Sandreas.sandberg@arm.com} 6711986Sandreas.sandberg@arm.com 6811986Sandreas.sandberg@arm.comtemplate <class Impl> 6911986Sandreas.sandberg@arm.comFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 7011986Sandreas.sandberg@arm.com : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 7111986Sandreas.sandberg@arm.com{ 7211986Sandreas.sandberg@arm.com} 7311986Sandreas.sandberg@arm.com 7411986Sandreas.sandberg@arm.comtemplate <class Impl> 7511986Sandreas.sandberg@arm.comvoid 7611986Sandreas.sandberg@arm.comFullO3CPU<Impl>::TickEvent::process() 7711986Sandreas.sandberg@arm.com{ 7811986Sandreas.sandberg@arm.com cpu->tick(); 7911986Sandreas.sandberg@arm.com} 8011986Sandreas.sandberg@arm.com 8111986Sandreas.sandberg@arm.comtemplate <class Impl> 8211986Sandreas.sandberg@arm.comconst char * 8311986Sandreas.sandberg@arm.comFullO3CPU<Impl>::TickEvent::description() 8411986Sandreas.sandberg@arm.com{ 8511986Sandreas.sandberg@arm.com return "FullO3CPU tick event"; 8611986Sandreas.sandberg@arm.com} 8711986Sandreas.sandberg@arm.com 8811986Sandreas.sandberg@arm.comtemplate <class Impl> 8911986Sandreas.sandberg@arm.comFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 9011986Sandreas.sandberg@arm.com : Event(&mainEventQueue, CPU_Tick_Pri) 9111986Sandreas.sandberg@arm.com{ 9211986Sandreas.sandberg@arm.com} 9311986Sandreas.sandberg@arm.com 9411986Sandreas.sandberg@arm.comtemplate <class Impl> 9511986Sandreas.sandberg@arm.comvoid 9611986Sandreas.sandberg@arm.comFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 9711986Sandreas.sandberg@arm.com FullO3CPU<Impl> *thread_cpu) 9811986Sandreas.sandberg@arm.com{ 99 tid = thread_num; 100 cpu = thread_cpu; 101} 102 103template <class Impl> 104void 105FullO3CPU<Impl>::ActivateThreadEvent::process() 106{ 107 cpu->activateThread(tid); 108} 109 110template <class Impl> 111const char * 112FullO3CPU<Impl>::ActivateThreadEvent::description() 113{ 114 return "FullO3CPU \"Activate Thread\" event"; 115} 116 117template <class Impl> 118FullO3CPU<Impl>::FullO3CPU(Params *params) 119 : BaseO3CPU(params), 120 tickEvent(this), 121 removeInstsThisCycle(false), 122 fetch(params), 123 decode(params), 124 rename(params), 125 iew(params), 126 commit(params), 127 128 regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 129 130 freeList(params->numberOfThreads,//number of activeThreads 131 TheISA::NumIntRegs, params->numPhysIntRegs, 132 TheISA::NumFloatRegs, params->numPhysFloatRegs), 133 134 rob(params->numROBEntries, params->squashWidth, 135 params->smtROBPolicy, params->smtROBThreshold, 136 params->numberOfThreads), 137 138 scoreboard(params->numberOfThreads,//number of activeThreads 139 TheISA::NumIntRegs, params->numPhysIntRegs, 140 TheISA::NumFloatRegs, params->numPhysFloatRegs, 141 TheISA::NumMiscRegs * number_of_threads, 142 TheISA::ZeroReg), 143 144 // For now just have these time buffers be pretty big. 145 // @todo: Make these time buffer sizes parameters or derived 146 // from latencies 147 timeBuffer(5, 5), 148 fetchQueue(5, 5), 149 decodeQueue(5, 5), 150 renameQueue(5, 5), 151 iewQueue(5, 5), 152 activityRec(NumStages, 10, params->activity), 153 154 globalSeqNum(1), 155 156#if FULL_SYSTEM 157 system(params->system), 158 physmem(system->physmem), 159#endif // FULL_SYSTEM 160 mem(params->mem), 161 switchCount(0), 162 deferRegistration(params->deferRegistration), 163 numThreads(number_of_threads) 164{ 165 _status = Idle; 166 167 checker = NULL; 168 169 if (params->checker) { 170#if USE_CHECKER 171 BaseCPU *temp_checker = params->checker; 172 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 173 checker->setMemory(mem); 174#if FULL_SYSTEM 175 checker->setSystem(params->system); 176#endif 177#else 178 panic("Checker enabled but not compiled in!"); 179#endif // USE_CHECKER 180 } 181 182#if !FULL_SYSTEM 183 thread.resize(number_of_threads); 184 tids.resize(number_of_threads); 185#endif 186 187 // The stages also need their CPU pointer setup. However this 188 // must be done at the upper level CPU because they have pointers 189 // to the upper level CPU, and not this FullO3CPU. 190 191 // Set up Pointers to the activeThreads list for each stage 192 fetch.setActiveThreads(&activeThreads); 193 decode.setActiveThreads(&activeThreads); 194 rename.setActiveThreads(&activeThreads); 195 iew.setActiveThreads(&activeThreads); 196 commit.setActiveThreads(&activeThreads); 197 198 // Give each of the stages the time buffer they will use. 199 fetch.setTimeBuffer(&timeBuffer); 200 decode.setTimeBuffer(&timeBuffer); 201 rename.setTimeBuffer(&timeBuffer); 202 iew.setTimeBuffer(&timeBuffer); 203 commit.setTimeBuffer(&timeBuffer); 204 205 // Also setup each of the stages' queues. 206 fetch.setFetchQueue(&fetchQueue); 207 decode.setFetchQueue(&fetchQueue); 208 commit.setFetchQueue(&fetchQueue); 209 decode.setDecodeQueue(&decodeQueue); 210 rename.setDecodeQueue(&decodeQueue); 211 rename.setRenameQueue(&renameQueue); 212 iew.setRenameQueue(&renameQueue); 213 iew.setIEWQueue(&iewQueue); 214 commit.setIEWQueue(&iewQueue); 215 commit.setRenameQueue(&renameQueue); 216 217 commit.setFetchStage(&fetch); 218 commit.setIEWStage(&iew); 219 rename.setIEWStage(&iew); 220 rename.setCommitStage(&commit); 221 222#if !FULL_SYSTEM 223 int active_threads = params->workload.size(); 224#else 225 int active_threads = 1; 226#endif 227 228 //Make Sure That this a Valid Architeture 229 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 230 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 231 232 rename.setScoreboard(&scoreboard); 233 iew.setScoreboard(&scoreboard); 234 235 // Setup the rename map for whichever stages need it. 236 PhysRegIndex lreg_idx = 0; 237 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 238 239 for (int tid=0; tid < numThreads; tid++) { 240 bool bindRegs = (tid <= active_threads - 1); 241 242 commitRenameMap[tid].init(TheISA::NumIntRegs, 243 params->numPhysIntRegs, 244 lreg_idx, //Index for Logical. Regs 245 246 TheISA::NumFloatRegs, 247 params->numPhysFloatRegs, 248 freg_idx, //Index for Float Regs 249 250 TheISA::NumMiscRegs, 251 252 TheISA::ZeroReg, 253 TheISA::ZeroReg, 254 255 tid, 256 false); 257 258 renameMap[tid].init(TheISA::NumIntRegs, 259 params->numPhysIntRegs, 260 lreg_idx, //Index for Logical. Regs 261 262 TheISA::NumFloatRegs, 263 params->numPhysFloatRegs, 264 freg_idx, //Index for Float Regs 265 266 TheISA::NumMiscRegs, 267 268 TheISA::ZeroReg, 269 TheISA::ZeroReg, 270 271 tid, 272 bindRegs); 273 } 274 275 rename.setRenameMap(renameMap); 276 commit.setRenameMap(commitRenameMap); 277 278 // Give renameMap & rename stage access to the freeList; 279 for (int i=0; i < numThreads; i++) { 280 renameMap[i].setFreeList(&freeList); 281 } 282 rename.setFreeList(&freeList); 283 284 // Setup the ROB for whichever stages need it. 285 commit.setROB(&rob); 286 287 lastRunningCycle = curTick; 288 289 lastActivatedCycle = -1; 290 291 contextSwitch = false; 292} 293 294template <class Impl> 295FullO3CPU<Impl>::~FullO3CPU() 296{ 297} 298 299template <class Impl> 300void 301FullO3CPU<Impl>::fullCPURegStats() 302{ 303 BaseO3CPU::regStats(); 304 305 // Register any of the O3CPU's stats here. 306 timesIdled 307 .name(name() + ".timesIdled") 308 .desc("Number of times that the entire CPU went into an idle state and" 309 " unscheduled itself") 310 .prereq(timesIdled); 311 312 idleCycles 313 .name(name() + ".idleCycles") 314 .desc("Total number of cycles that the CPU has spent unscheduled due " 315 "to idling") 316 .prereq(idleCycles); 317 318 // Number of Instructions simulated 319 // -------------------------------- 320 // Should probably be in Base CPU but need templated 321 // MaxThreads so put in here instead 322 committedInsts 323 .init(numThreads) 324 .name(name() + ".committedInsts") 325 .desc("Number of Instructions Simulated"); 326 327 totalCommittedInsts 328 .name(name() + ".committedInsts_total") 329 .desc("Number of Instructions Simulated"); 330 331 cpi 332 .name(name() + ".cpi") 333 .desc("CPI: Cycles Per Instruction") 334 .precision(6); 335 cpi = simTicks / committedInsts; 336 337 totalCpi 338 .name(name() + ".cpi_total") 339 .desc("CPI: Total CPI of All Threads") 340 .precision(6); 341 totalCpi = simTicks / totalCommittedInsts; 342 343 ipc 344 .name(name() + ".ipc") 345 .desc("IPC: Instructions Per Cycle") 346 .precision(6); 347 ipc = committedInsts / simTicks; 348 349 totalIpc 350 .name(name() + ".ipc_total") 351 .desc("IPC: Total IPC of All Threads") 352 .precision(6); 353 totalIpc = totalCommittedInsts / simTicks; 354 355} 356 357template <class Impl> 358void 359FullO3CPU<Impl>::tick() 360{ 361 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 362 363 ++numCycles; 364 365// activity = false; 366 367 //Tick each of the stages 368 fetch.tick(); 369 370 decode.tick(); 371 372 rename.tick(); 373 374 iew.tick(); 375 376 commit.tick(); 377 378#if !FULL_SYSTEM 379 doContextSwitch(); 380#endif 381 382 // Now advance the time buffers 383 timeBuffer.advance(); 384 385 fetchQueue.advance(); 386 decodeQueue.advance(); 387 renameQueue.advance(); 388 iewQueue.advance(); 389 390 activityRec.advance(); 391 392 if (removeInstsThisCycle) { 393 cleanUpRemovedInsts(); 394 } 395 396 if (!tickEvent.scheduled()) { 397 if (_status == SwitchedOut) { 398 // increment stat 399 lastRunningCycle = curTick; 400 } else if (!activityRec.active()) { 401 lastRunningCycle = curTick; 402 timesIdled++; 403 } else { 404 tickEvent.schedule(curTick + cycles(1)); 405 } 406 } 407 408#if !FULL_SYSTEM 409 updateThreadPriority(); 410#endif 411 412} 413 414template <class Impl> 415void 416FullO3CPU<Impl>::init() 417{ 418 if (!deferRegistration) { 419 registerThreadContexts(); 420 } 421 422 // Set inSyscall so that the CPU doesn't squash when initially 423 // setting up registers. 424 for (int i = 0; i < number_of_threads; ++i) 425 thread[i]->inSyscall = true; 426 427 for (int tid=0; tid < number_of_threads; tid++) { 428#if FULL_SYSTEM 429 ThreadContext *src_tc = threadContexts[tid]; 430#else 431 ThreadContext *src_tc = thread[tid]->getTC(); 432#endif 433 // Threads start in the Suspended State 434 if (src_tc->status() != ThreadContext::Suspended) { 435 continue; 436 } 437 438#if FULL_SYSTEM 439 TheISA::initCPU(src_tc, src_tc->readCpuId()); 440#endif 441 } 442 443 // Clear inSyscall. 444 for (int i = 0; i < number_of_threads; ++i) 445 thread[i]->inSyscall = false; 446 447 // Initialize stages. 448 fetch.initStage(); 449 iew.initStage(); 450 rename.initStage(); 451 commit.initStage(); 452 453 commit.setThreads(thread); 454} 455 456template <class Impl> 457void 458FullO3CPU<Impl>::insertThread(unsigned tid) 459{ 460 DPRINTF(O3CPU,"[tid:%i] Initializing thread data"); 461 // Will change now that the PC and thread state is internal to the CPU 462 // and not in the ThreadContext. 463#if 0 464#if FULL_SYSTEM 465 ThreadContext *src_tc = system->threadContexts[tid]; 466#else 467 ThreadContext *src_tc = thread[tid]; 468#endif 469 470 //Bind Int Regs to Rename Map 471 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 472 PhysRegIndex phys_reg = freeList.getIntReg(); 473 474 renameMap[tid].setEntry(ireg,phys_reg); 475 scoreboard.setReg(phys_reg); 476 } 477 478 //Bind Float Regs to Rename Map 479 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 480 PhysRegIndex phys_reg = freeList.getFloatReg(); 481 482 renameMap[tid].setEntry(freg,phys_reg); 483 scoreboard.setReg(phys_reg); 484 } 485 486 //Copy Thread Data Into RegFile 487 this->copyFromTC(tid); 488 489 //Set PC/NPC 490 regFile.pc[tid] = src_tc->readPC(); 491 regFile.npc[tid] = src_tc->readNextPC(); 492 493 src_tc->setStatus(ThreadContext::Active); 494 495 activateContext(tid,1); 496 497 //Reset ROB/IQ/LSQ Entries 498 commit.rob->resetEntries(); 499 iew.resetEntries(); 500#endif 501} 502 503template <class Impl> 504void 505FullO3CPU<Impl>::removeThread(unsigned tid) 506{ 507 DPRINTF(O3CPU,"[tid:%i] Removing thread data"); 508#if 0 509 //Unbind Int Regs from Rename Map 510 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 511 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 512 513 scoreboard.unsetReg(phys_reg); 514 freeList.addReg(phys_reg); 515 } 516 517 //Unbind Float Regs from Rename Map 518 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 519 PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 520 521 scoreboard.unsetReg(phys_reg); 522 freeList.addReg(phys_reg); 523 } 524 525 //Copy Thread Data From RegFile 526 /* Fix Me: 527 * Do we really need to do this if we are removing a thread 528 * in the sense that it's finished (exiting)? If the thread is just 529 * being suspended we might... 530 */ 531// this->copyToTC(tid); 532 533 //Squash Throughout Pipeline 534 fetch.squash(0,tid); 535 decode.squash(tid); 536 rename.squash(tid); 537 538 assert(iew.ldstQueue.getCount(tid) == 0); 539 540 //Reset ROB/IQ/LSQ Entries 541 if (activeThreads.size() >= 1) { 542 commit.rob->resetEntries(); 543 iew.resetEntries(); 544 } 545#endif 546} 547 548 549template <class Impl> 550void 551FullO3CPU<Impl>::activateWhenReady(int tid) 552{ 553 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 554 "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 555 tid); 556 557 bool ready = true; 558 559 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 560 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 561 "Phys. Int. Regs.\n", 562 tid); 563 ready = false; 564 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 565 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 566 "Phys. Float. Regs.\n", 567 tid); 568 ready = false; 569 } else if (commit.rob->numFreeEntries() >= 570 commit.rob->entryAmount(activeThreads.size() + 1)) { 571 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 572 "ROB entries.\n", 573 tid); 574 ready = false; 575 } else if (iew.instQueue.numFreeEntries() >= 576 iew.instQueue.entryAmount(activeThreads.size() + 1)) { 577 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 578 "IQ entries.\n", 579 tid); 580 ready = false; 581 } else if (iew.ldstQueue.numFreeEntries() >= 582 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 583 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 584 "LSQ entries.\n", 585 tid); 586 ready = false; 587 } 588 589 if (ready) { 590 insertThread(tid); 591 592 contextSwitch = false; 593 594 cpuWaitList.remove(tid); 595 } else { 596 suspendContext(tid); 597 598 //blocks fetch 599 contextSwitch = true; 600 601 //do waitlist 602 cpuWaitList.push_back(tid); 603 } 604} 605 606template <class Impl> 607void 608FullO3CPU<Impl>::activateThread(unsigned int tid) 609{ 610 list<unsigned>::iterator isActive = find( 611 activeThreads.begin(), activeThreads.end(), tid); 612 613 if (isActive == activeThreads.end()) { 614 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 615 tid); 616 617 activeThreads.push_back(tid); 618 } 619} 620 621 622template <class Impl> 623void 624FullO3CPU<Impl>::activateContext(int tid, int delay) 625{ 626 // Needs to set each stage to running as well. 627 if (delay){ 628 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 629 "on cycle %d\n", tid, curTick + cycles(delay)); 630 scheduleActivateThreadEvent(tid, delay); 631 } else { 632 activateThread(tid); 633 } 634 635 if(lastActivatedCycle < curTick) { 636 scheduleTickEvent(delay); 637 638 // Be sure to signal that there's some activity so the CPU doesn't 639 // deschedule itself. 640 activityRec.activity(); 641 fetch.wakeFromQuiesce(); 642 643 lastActivatedCycle = curTick; 644 645 _status = Running; 646 } 647} 648 649template <class Impl> 650void 651FullO3CPU<Impl>::suspendContext(int tid) 652{ 653 DPRINTF(O3CPU,"[tid: %i]: Suspended ...\n", tid); 654 unscheduleTickEvent(); 655 _status = Idle; 656/* 657 //Remove From Active List, if Active 658 list<unsigned>::iterator isActive = find( 659 activeThreads.begin(), activeThreads.end(), tid); 660 661 if (isActive != activeThreads.end()) { 662 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 663 tid); 664 activeThreads.erase(isActive); 665 } 666*/ 667} 668 669template <class Impl> 670void 671FullO3CPU<Impl>::deallocateContext(int tid) 672{ 673 DPRINTF(O3CPU,"[tid:%i]: Deallocating ...", tid); 674/* 675 //Remove From Active List, if Active 676 list<unsigned>::iterator isActive = find( 677 activeThreads.begin(), activeThreads.end(), tid); 678 679 if (isActive != activeThreads.end()) { 680 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 681 tid); 682 activeThreads.erase(isActive); 683 684 removeThread(tid); 685 } 686*/ 687} 688 689template <class Impl> 690void 691FullO3CPU<Impl>::haltContext(int tid) 692{ 693 DPRINTF(O3CPU,"[tid:%i]: Halted ...", tid); 694/* 695 //Remove From Active List, if Active 696 list<unsigned>::iterator isActive = find( 697 activeThreads.begin(), activeThreads.end(), tid); 698 699 if (isActive != activeThreads.end()) { 700 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 701 tid); 702 activeThreads.erase(isActive); 703 704 removeThread(tid); 705 } 706*/ 707} 708 709template <class Impl> 710void 711FullO3CPU<Impl>::switchOut(Sampler *_sampler) 712{ 713 sampler = _sampler; 714 switchCount = 0; 715 fetch.switchOut(); 716 decode.switchOut(); 717 rename.switchOut(); 718 iew.switchOut(); 719 commit.switchOut(); 720 721 // Wake the CPU and record activity so everything can drain out if 722 // the CPU is currently idle. 723 wakeCPU(); 724 activityRec.activity(); 725} 726 727template <class Impl> 728void 729FullO3CPU<Impl>::signalSwitched() 730{ 731 if (++switchCount == NumStages) { 732 fetch.doSwitchOut(); 733 rename.doSwitchOut(); 734 commit.doSwitchOut(); 735 instList.clear(); 736 while (!removeList.empty()) { 737 removeList.pop(); 738 } 739 740#if USE_CHECKER 741 if (checker) 742 checker->switchOut(sampler); 743#endif 744 745 if (tickEvent.scheduled()) 746 tickEvent.squash(); 747 sampler->signalSwitched(); 748 _status = SwitchedOut; 749 } 750 assert(switchCount <= 5); 751} 752 753template <class Impl> 754void 755FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 756{ 757 // Flush out any old data from the time buffers. 758 for (int i = 0; i < 10; ++i) { 759 timeBuffer.advance(); 760 fetchQueue.advance(); 761 decodeQueue.advance(); 762 renameQueue.advance(); 763 iewQueue.advance(); 764 } 765 766 activityRec.reset(); 767 768 BaseCPU::takeOverFrom(oldCPU); 769 770 fetch.takeOverFrom(); 771 decode.takeOverFrom(); 772 rename.takeOverFrom(); 773 iew.takeOverFrom(); 774 commit.takeOverFrom(); 775 776 assert(!tickEvent.scheduled()); 777 778 // @todo: Figure out how to properly select the tid to put onto 779 // the active threads list. 780 int tid = 0; 781 782 list<unsigned>::iterator isActive = find( 783 activeThreads.begin(), activeThreads.end(), tid); 784 785 if (isActive == activeThreads.end()) { 786 //May Need to Re-code this if the delay variable is the delay 787 //needed for thread to activate 788 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 789 tid); 790 791 activeThreads.push_back(tid); 792 } 793 794 // Set all statuses to active, schedule the CPU's tick event. 795 // @todo: Fix up statuses so this is handled properly 796 for (int i = 0; i < threadContexts.size(); ++i) { 797 ThreadContext *tc = threadContexts[i]; 798 if (tc->status() == ThreadContext::Active && _status != Running) { 799 _status = Running; 800 tickEvent.schedule(curTick); 801 } 802 } 803 if (!tickEvent.scheduled()) 804 tickEvent.schedule(curTick); 805} 806 807template <class Impl> 808uint64_t 809FullO3CPU<Impl>::readIntReg(int reg_idx) 810{ 811 return regFile.readIntReg(reg_idx); 812} 813 814template <class Impl> 815FloatReg 816FullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 817{ 818 return regFile.readFloatReg(reg_idx, width); 819} 820 821template <class Impl> 822FloatReg 823FullO3CPU<Impl>::readFloatReg(int reg_idx) 824{ 825 return regFile.readFloatReg(reg_idx); 826} 827 828template <class Impl> 829FloatRegBits 830FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 831{ 832 return regFile.readFloatRegBits(reg_idx, width); 833} 834 835template <class Impl> 836FloatRegBits 837FullO3CPU<Impl>::readFloatRegBits(int reg_idx) 838{ 839 return regFile.readFloatRegBits(reg_idx); 840} 841 842template <class Impl> 843void 844FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 845{ 846 regFile.setIntReg(reg_idx, val); 847} 848 849template <class Impl> 850void 851FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 852{ 853 regFile.setFloatReg(reg_idx, val, width); 854} 855 856template <class Impl> 857void 858FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 859{ 860 regFile.setFloatReg(reg_idx, val); 861} 862 863template <class Impl> 864void 865FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 866{ 867 regFile.setFloatRegBits(reg_idx, val, width); 868} 869 870template <class Impl> 871void 872FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 873{ 874 regFile.setFloatRegBits(reg_idx, val); 875} 876 877template <class Impl> 878uint64_t 879FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 880{ 881 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 882 883 return regFile.readIntReg(phys_reg); 884} 885 886template <class Impl> 887float 888FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 889{ 890 int idx = reg_idx + TheISA::FP_Base_DepTag; 891 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 892 893 return regFile.readFloatReg(phys_reg); 894} 895 896template <class Impl> 897double 898FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 899{ 900 int idx = reg_idx + TheISA::FP_Base_DepTag; 901 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 902 903 return regFile.readFloatReg(phys_reg, 64); 904} 905 906template <class Impl> 907uint64_t 908FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 909{ 910 int idx = reg_idx + TheISA::FP_Base_DepTag; 911 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 912 913 return regFile.readFloatRegBits(phys_reg); 914} 915 916template <class Impl> 917void 918FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 919{ 920 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 921 922 regFile.setIntReg(phys_reg, val); 923} 924 925template <class Impl> 926void 927FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 928{ 929 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 930 931 regFile.setFloatReg(phys_reg, val); 932} 933 934template <class Impl> 935void 936FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 937{ 938 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 939 940 regFile.setFloatReg(phys_reg, val, 64); 941} 942 943template <class Impl> 944void 945FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 946{ 947 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 948 949 regFile.setFloatRegBits(phys_reg, val); 950} 951 952template <class Impl> 953uint64_t 954FullO3CPU<Impl>::readPC(unsigned tid) 955{ 956 return commit.readPC(tid); 957} 958 959template <class Impl> 960void 961FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 962{ 963 commit.setPC(new_PC, tid); 964} 965 966template <class Impl> 967uint64_t 968FullO3CPU<Impl>::readNextPC(unsigned tid) 969{ 970 return commit.readNextPC(tid); 971} 972 973template <class Impl> 974void 975FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 976{ 977 commit.setNextPC(val, tid); 978} 979 980#if THE_ISA != ALPHA_ISA 981template <class Impl> 982uint64_t 983FullO3CPU<Impl>::readNextNPC(unsigned tid) 984{ 985 return commit.readNextNPC(tid); 986} 987 988template <class Impl> 989void 990FullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid) 991{ 992 commit.setNextNPC(val, tid); 993} 994#endif 995 996template <class Impl> 997typename FullO3CPU<Impl>::ListIt 998FullO3CPU<Impl>::addInst(DynInstPtr &inst) 999{ 1000 instList.push_back(inst); 1001 1002 return --(instList.end()); 1003} 1004 1005template <class Impl> 1006void 1007FullO3CPU<Impl>::instDone(unsigned tid) 1008{ 1009 // Keep an instruction count. 1010 thread[tid]->numInst++; 1011 thread[tid]->numInsts++; 1012 committedInsts[tid]++; 1013 totalCommittedInsts++; 1014 1015 // Check for instruction-count-based events. 1016 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 1017} 1018 1019template <class Impl> 1020void 1021FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 1022{ 1023 removeInstsThisCycle = true; 1024 1025 removeList.push(inst->getInstListIt()); 1026} 1027 1028template <class Impl> 1029void 1030FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 1031{ 1032 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 1033 "[sn:%lli]\n", 1034 inst->threadNumber, inst->readPC(), inst->seqNum); 1035 1036 removeInstsThisCycle = true; 1037 1038 // Remove the front instruction. 1039 removeList.push(inst->getInstListIt()); 1040} 1041 1042template <class Impl> 1043void 1044FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 1045{ 1046 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 1047 " list.\n", tid); 1048 1049 ListIt end_it; 1050 1051 bool rob_empty = false; 1052 1053 if (instList.empty()) { 1054 return; 1055 } else if (rob.isEmpty(/*tid*/)) { 1056 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 1057 end_it = instList.begin(); 1058 rob_empty = true; 1059 } else { 1060 end_it = (rob.readTailInst(tid))->getInstListIt(); 1061 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 1062 } 1063 1064 removeInstsThisCycle = true; 1065 1066 ListIt inst_it = instList.end(); 1067 1068 inst_it--; 1069 1070 // Walk through the instruction list, removing any instructions 1071 // that were inserted after the given instruction iterator, end_it. 1072 while (inst_it != end_it) { 1073 assert(!instList.empty()); 1074 1075 squashInstIt(inst_it, tid); 1076 1077 inst_it--; 1078 } 1079 1080 // If the ROB was empty, then we actually need to remove the first 1081 // instruction as well. 1082 if (rob_empty) { 1083 squashInstIt(inst_it, tid); 1084 } 1085} 1086 1087template <class Impl> 1088void 1089FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 1090 unsigned tid) 1091{ 1092 assert(!instList.empty()); 1093 1094 removeInstsThisCycle = true; 1095 1096 ListIt inst_iter = instList.end(); 1097 1098 inst_iter--; 1099 1100 DPRINTF(O3CPU, "Deleting instructions from instruction " 1101 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 1102 tid, seq_num, (*inst_iter)->seqNum); 1103 1104 while ((*inst_iter)->seqNum > seq_num) { 1105 1106 bool break_loop = (inst_iter == instList.begin()); 1107 1108 squashInstIt(inst_iter, tid); 1109 1110 inst_iter--; 1111 1112 if (break_loop) 1113 break; 1114 } 1115} 1116 1117template <class Impl> 1118inline void 1119FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 1120{ 1121 if ((*instIt)->threadNumber == tid) { 1122 DPRINTF(O3CPU, "Squashing instruction, " 1123 "[tid:%i] [sn:%lli] PC %#x\n", 1124 (*instIt)->threadNumber, 1125 (*instIt)->seqNum, 1126 (*instIt)->readPC()); 1127 1128 // Mark it as squashed. 1129 (*instIt)->setSquashed(); 1130 1131 // @todo: Formulate a consistent method for deleting 1132 // instructions from the instruction list 1133 // Remove the instruction from the list. 1134 removeList.push(instIt); 1135 } 1136} 1137 1138template <class Impl> 1139void 1140FullO3CPU<Impl>::cleanUpRemovedInsts() 1141{ 1142 while (!removeList.empty()) { 1143 DPRINTF(O3CPU, "Removing instruction, " 1144 "[tid:%i] [sn:%lli] PC %#x\n", 1145 (*removeList.front())->threadNumber, 1146 (*removeList.front())->seqNum, 1147 (*removeList.front())->readPC()); 1148 1149 instList.erase(removeList.front()); 1150 1151 removeList.pop(); 1152 } 1153 1154 removeInstsThisCycle = false; 1155} 1156/* 1157template <class Impl> 1158void 1159FullO3CPU<Impl>::removeAllInsts() 1160{ 1161 instList.clear(); 1162} 1163*/ 1164template <class Impl> 1165void 1166FullO3CPU<Impl>::dumpInsts() 1167{ 1168 int num = 0; 1169 1170 ListIt inst_list_it = instList.begin(); 1171 1172 cprintf("Dumping Instruction List\n"); 1173 1174 while (inst_list_it != instList.end()) { 1175 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 1176 "Squashed:%i\n\n", 1177 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 1178 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 1179 (*inst_list_it)->isSquashed()); 1180 inst_list_it++; 1181 ++num; 1182 } 1183} 1184/* 1185template <class Impl> 1186void 1187FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 1188{ 1189 iew.wakeDependents(inst); 1190} 1191*/ 1192template <class Impl> 1193void 1194FullO3CPU<Impl>::wakeCPU() 1195{ 1196 if (activityRec.active() || tickEvent.scheduled()) { 1197 DPRINTF(Activity, "CPU already running.\n"); 1198 return; 1199 } 1200 1201 DPRINTF(Activity, "Waking up CPU\n"); 1202 1203 idleCycles += (curTick - 1) - lastRunningCycle; 1204 1205 tickEvent.schedule(curTick); 1206} 1207 1208template <class Impl> 1209int 1210FullO3CPU<Impl>::getFreeTid() 1211{ 1212 for (int i=0; i < numThreads; i++) { 1213 if (!tids[i]) { 1214 tids[i] = true; 1215 return i; 1216 } 1217 } 1218 1219 return -1; 1220} 1221 1222template <class Impl> 1223void 1224FullO3CPU<Impl>::doContextSwitch() 1225{ 1226 if (contextSwitch) { 1227 1228 //ADD CODE TO DEACTIVE THREAD HERE (???) 1229 1230 for (int tid=0; tid < cpuWaitList.size(); tid++) { 1231 activateWhenReady(tid); 1232 } 1233 1234 if (cpuWaitList.size() == 0) 1235 contextSwitch = true; 1236 } 1237} 1238 1239template <class Impl> 1240void 1241FullO3CPU<Impl>::updateThreadPriority() 1242{ 1243 if (activeThreads.size() > 1) 1244 { 1245 //DEFAULT TO ROUND ROBIN SCHEME 1246 //e.g. Move highest priority to end of thread list 1247 list<unsigned>::iterator list_begin = activeThreads.begin(); 1248 list<unsigned>::iterator list_end = activeThreads.end(); 1249 1250 unsigned high_thread = *list_begin; 1251 1252 activeThreads.erase(list_begin); 1253 1254 activeThreads.push_back(high_thread); 1255 } 1256} 1257 1258// Forward declaration of FullO3CPU. 1259template class FullO3CPU<O3CPUImpl>; 1260