cpu.cc revision 2756
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 331858SN/A 341858SN/A#if FULL_SYSTEM 351060SN/A#include "sim/system.hh" 361060SN/A#else 371060SN/A#include "sim/process.hh" 381060SN/A#endif 391060SN/A 402325SN/A#include "cpu/activity.hh" 412316SN/A#include "cpu/checker/cpu.hh" 422683Sktlim@umich.edu#include "cpu/simple_thread.hh" 432680Sktlim@umich.edu#include "cpu/thread_context.hh" 441717SN/A#include "cpu/o3/alpha_dyn_inst.hh" 451717SN/A#include "cpu/o3/alpha_impl.hh" 461717SN/A#include "cpu/o3/cpu.hh" 471060SN/A 482325SN/A#include "sim/root.hh" 492292SN/A#include "sim/stat_control.hh" 502292SN/A 511060SN/Ausing namespace std; 522669Sktlim@umich.eduusing namespace TheISA; 531060SN/A 542292SN/ABaseFullCPU::BaseFullCPU(Params *params) 552292SN/A : BaseCPU(params), cpu_id(0) 561060SN/A{ 571060SN/A} 581060SN/A 592292SN/Avoid 602292SN/ABaseFullCPU::regStats() 612292SN/A{ 622292SN/A BaseCPU::regStats(); 632292SN/A} 642292SN/A 651060SN/Atemplate <class Impl> 661755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 671060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 681060SN/A{ 691060SN/A} 701060SN/A 711060SN/Atemplate <class Impl> 721060SN/Avoid 731755SN/AFullO3CPU<Impl>::TickEvent::process() 741060SN/A{ 751060SN/A cpu->tick(); 761060SN/A} 771060SN/A 781060SN/Atemplate <class Impl> 791060SN/Aconst char * 801755SN/AFullO3CPU<Impl>::TickEvent::description() 811060SN/A{ 821755SN/A return "FullO3CPU tick event"; 831060SN/A} 841060SN/A 851060SN/Atemplate <class Impl> 862292SN/AFullO3CPU<Impl>::FullO3CPU(Params *params) 871061SN/A : BaseFullCPU(params), 881060SN/A tickEvent(this), 892292SN/A removeInstsThisCycle(false), 901060SN/A fetch(params), 911060SN/A decode(params), 921060SN/A rename(params), 931060SN/A iew(params), 941060SN/A commit(params), 951060SN/A 962292SN/A regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 971060SN/A 982292SN/A freeList(params->numberOfThreads,//number of activeThreads 992292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1002292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1011060SN/A 1022292SN/A rob(params->numROBEntries, params->squashWidth, 1032292SN/A params->smtROBPolicy, params->smtROBThreshold, 1042292SN/A params->numberOfThreads), 1051060SN/A 1062292SN/A scoreboard(params->numberOfThreads,//number of activeThreads 1072292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1082292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1092292SN/A TheISA::NumMiscRegs * number_of_threads, 1102292SN/A TheISA::ZeroReg), 1111060SN/A 1121060SN/A // For now just have these time buffers be pretty big. 1132325SN/A // @todo: Make these time buffer sizes parameters or derived 1142325SN/A // from latencies 1151061SN/A timeBuffer(5, 5), 1161061SN/A fetchQueue(5, 5), 1171061SN/A decodeQueue(5, 5), 1181061SN/A renameQueue(5, 5), 1191061SN/A iewQueue(5, 5), 1202325SN/A activityRec(NumStages, 10, params->activity), 1211060SN/A 1221060SN/A globalSeqNum(1), 1231060SN/A 1241858SN/A#if FULL_SYSTEM 1252292SN/A system(params->system), 1261060SN/A physmem(system->physmem), 1271060SN/A#endif // FULL_SYSTEM 1282292SN/A mem(params->mem), 1292316SN/A switchCount(0), 1302316SN/A deferRegistration(params->deferRegistration), 1312316SN/A numThreads(number_of_threads) 1321060SN/A{ 1331060SN/A _status = Idle; 1341681SN/A 1352316SN/A if (params->checker) { 1362316SN/A BaseCPU *temp_checker = params->checker; 1372316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 1382316SN/A checker->setMemory(mem); 1392316SN/A#if FULL_SYSTEM 1402316SN/A checker->setSystem(params->system); 1412316SN/A#endif 1422316SN/A } else { 1432316SN/A checker = NULL; 1442316SN/A } 1452316SN/A 1461858SN/A#if !FULL_SYSTEM 1472292SN/A thread.resize(number_of_threads); 1482292SN/A tids.resize(number_of_threads); 1491681SN/A#endif 1501681SN/A 1512325SN/A // The stages also need their CPU pointer setup. However this 1522325SN/A // must be done at the upper level CPU because they have pointers 1532325SN/A // to the upper level CPU, and not this FullO3CPU. 1541060SN/A 1552292SN/A // Set up Pointers to the activeThreads list for each stage 1562292SN/A fetch.setActiveThreads(&activeThreads); 1572292SN/A decode.setActiveThreads(&activeThreads); 1582292SN/A rename.setActiveThreads(&activeThreads); 1592292SN/A iew.setActiveThreads(&activeThreads); 1602292SN/A commit.setActiveThreads(&activeThreads); 1611060SN/A 1621060SN/A // Give each of the stages the time buffer they will use. 1631060SN/A fetch.setTimeBuffer(&timeBuffer); 1641060SN/A decode.setTimeBuffer(&timeBuffer); 1651060SN/A rename.setTimeBuffer(&timeBuffer); 1661060SN/A iew.setTimeBuffer(&timeBuffer); 1671060SN/A commit.setTimeBuffer(&timeBuffer); 1681060SN/A 1691060SN/A // Also setup each of the stages' queues. 1701060SN/A fetch.setFetchQueue(&fetchQueue); 1711060SN/A decode.setFetchQueue(&fetchQueue); 1722292SN/A commit.setFetchQueue(&fetchQueue); 1731060SN/A decode.setDecodeQueue(&decodeQueue); 1741060SN/A rename.setDecodeQueue(&decodeQueue); 1751060SN/A rename.setRenameQueue(&renameQueue); 1761060SN/A iew.setRenameQueue(&renameQueue); 1771060SN/A iew.setIEWQueue(&iewQueue); 1781060SN/A commit.setIEWQueue(&iewQueue); 1791060SN/A commit.setRenameQueue(&renameQueue); 1801060SN/A 1812316SN/A commit.setFetchStage(&fetch); 1822292SN/A commit.setIEWStage(&iew); 1832292SN/A rename.setIEWStage(&iew); 1842292SN/A rename.setCommitStage(&commit); 1852292SN/A 1862292SN/A#if !FULL_SYSTEM 1872307SN/A int active_threads = params->workload.size(); 1882292SN/A#else 1892307SN/A int active_threads = 1; 1902292SN/A#endif 1912292SN/A 1922316SN/A //Make Sure That this a Valid Architeture 1932292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 1942292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 1952292SN/A 1962292SN/A rename.setScoreboard(&scoreboard); 1972292SN/A iew.setScoreboard(&scoreboard); 1982292SN/A 1991060SN/A // Setup the rename map for whichever stages need it. 2002292SN/A PhysRegIndex lreg_idx = 0; 2012292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2021060SN/A 2032292SN/A for (int tid=0; tid < numThreads; tid++) { 2042307SN/A bool bindRegs = (tid <= active_threads - 1); 2052292SN/A 2062292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2072292SN/A params->numPhysIntRegs, 2082325SN/A lreg_idx, //Index for Logical. Regs 2092292SN/A 2102292SN/A TheISA::NumFloatRegs, 2112292SN/A params->numPhysFloatRegs, 2122325SN/A freg_idx, //Index for Float Regs 2132292SN/A 2142292SN/A TheISA::NumMiscRegs, 2152292SN/A 2162292SN/A TheISA::ZeroReg, 2172292SN/A TheISA::ZeroReg, 2182292SN/A 2192292SN/A tid, 2202292SN/A false); 2212292SN/A 2222292SN/A renameMap[tid].init(TheISA::NumIntRegs, 2232292SN/A params->numPhysIntRegs, 2242325SN/A lreg_idx, //Index for Logical. Regs 2252292SN/A 2262292SN/A TheISA::NumFloatRegs, 2272292SN/A params->numPhysFloatRegs, 2282325SN/A freg_idx, //Index for Float Regs 2292292SN/A 2302292SN/A TheISA::NumMiscRegs, 2312292SN/A 2322292SN/A TheISA::ZeroReg, 2332292SN/A TheISA::ZeroReg, 2342292SN/A 2352292SN/A tid, 2362292SN/A bindRegs); 2372292SN/A } 2382292SN/A 2392292SN/A rename.setRenameMap(renameMap); 2402292SN/A commit.setRenameMap(commitRenameMap); 2412292SN/A 2422292SN/A // Give renameMap & rename stage access to the freeList; 2432292SN/A for (int i=0; i < numThreads; i++) { 2442292SN/A renameMap[i].setFreeList(&freeList); 2452292SN/A } 2461060SN/A rename.setFreeList(&freeList); 2472292SN/A 2481060SN/A // Setup the ROB for whichever stages need it. 2491060SN/A commit.setROB(&rob); 2502292SN/A 2512292SN/A lastRunningCycle = curTick; 2522292SN/A 2532292SN/A contextSwitch = false; 2541060SN/A} 2551060SN/A 2561060SN/Atemplate <class Impl> 2571755SN/AFullO3CPU<Impl>::~FullO3CPU() 2581060SN/A{ 2591060SN/A} 2601060SN/A 2611060SN/Atemplate <class Impl> 2621060SN/Avoid 2631755SN/AFullO3CPU<Impl>::fullCPURegStats() 2641062SN/A{ 2652292SN/A BaseFullCPU::regStats(); 2662292SN/A 2671062SN/A // Register any of the FullCPU's stats here. 2682292SN/A timesIdled 2692292SN/A .name(name() + ".timesIdled") 2702292SN/A .desc("Number of times that the entire CPU went into an idle state and" 2712292SN/A " unscheduled itself") 2722292SN/A .prereq(timesIdled); 2732292SN/A 2742292SN/A idleCycles 2752292SN/A .name(name() + ".idleCycles") 2762292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 2772292SN/A "to idling") 2782292SN/A .prereq(idleCycles); 2792292SN/A 2802292SN/A // Number of Instructions simulated 2812292SN/A // -------------------------------- 2822292SN/A // Should probably be in Base CPU but need templated 2832292SN/A // MaxThreads so put in here instead 2842292SN/A committedInsts 2852292SN/A .init(numThreads) 2862292SN/A .name(name() + ".committedInsts") 2872292SN/A .desc("Number of Instructions Simulated"); 2882292SN/A 2892292SN/A totalCommittedInsts 2902292SN/A .name(name() + ".committedInsts_total") 2912292SN/A .desc("Number of Instructions Simulated"); 2922292SN/A 2932292SN/A cpi 2942292SN/A .name(name() + ".cpi") 2952292SN/A .desc("CPI: Cycles Per Instruction") 2962292SN/A .precision(6); 2972292SN/A cpi = simTicks / committedInsts; 2982292SN/A 2992292SN/A totalCpi 3002292SN/A .name(name() + ".cpi_total") 3012292SN/A .desc("CPI: Total CPI of All Threads") 3022292SN/A .precision(6); 3032292SN/A totalCpi = simTicks / totalCommittedInsts; 3042292SN/A 3052292SN/A ipc 3062292SN/A .name(name() + ".ipc") 3072292SN/A .desc("IPC: Instructions Per Cycle") 3082292SN/A .precision(6); 3092292SN/A ipc = committedInsts / simTicks; 3102292SN/A 3112292SN/A totalIpc 3122292SN/A .name(name() + ".ipc_total") 3132292SN/A .desc("IPC: Total IPC of All Threads") 3142292SN/A .precision(6); 3152292SN/A totalIpc = totalCommittedInsts / simTicks; 3162292SN/A 3171062SN/A} 3181062SN/A 3191062SN/Atemplate <class Impl> 3201062SN/Avoid 3211755SN/AFullO3CPU<Impl>::tick() 3221060SN/A{ 3231755SN/A DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullO3CPU.\n"); 3241060SN/A 3252292SN/A ++numCycles; 3262292SN/A 3272325SN/A// activity = false; 3282292SN/A 3292292SN/A //Tick each of the stages 3301060SN/A fetch.tick(); 3311060SN/A 3321060SN/A decode.tick(); 3331060SN/A 3341060SN/A rename.tick(); 3351060SN/A 3361060SN/A iew.tick(); 3371060SN/A 3381060SN/A commit.tick(); 3391060SN/A 3402292SN/A#if !FULL_SYSTEM 3412292SN/A doContextSwitch(); 3422292SN/A#endif 3432292SN/A 3442292SN/A // Now advance the time buffers 3451060SN/A timeBuffer.advance(); 3461060SN/A 3471060SN/A fetchQueue.advance(); 3481060SN/A decodeQueue.advance(); 3491060SN/A renameQueue.advance(); 3501060SN/A iewQueue.advance(); 3511060SN/A 3522325SN/A activityRec.advance(); 3532292SN/A 3542292SN/A if (removeInstsThisCycle) { 3552292SN/A cleanUpRemovedInsts(); 3562292SN/A } 3572292SN/A 3582325SN/A if (!tickEvent.scheduled()) { 3592325SN/A if (_status == SwitchedOut) { 3602325SN/A // increment stat 3612325SN/A lastRunningCycle = curTick; 3622325SN/A } else if (!activityRec.active()) { 3632325SN/A lastRunningCycle = curTick; 3642325SN/A timesIdled++; 3652325SN/A } else { 3662325SN/A tickEvent.schedule(curTick + cycles(1)); 3672325SN/A } 3682292SN/A } 3692292SN/A 3702292SN/A#if !FULL_SYSTEM 3712292SN/A updateThreadPriority(); 3722292SN/A#endif 3732292SN/A 3741060SN/A} 3751060SN/A 3761060SN/Atemplate <class Impl> 3771060SN/Avoid 3781755SN/AFullO3CPU<Impl>::init() 3791060SN/A{ 3802307SN/A if (!deferRegistration) { 3812680Sktlim@umich.edu registerThreadContexts(); 3822292SN/A } 3831060SN/A 3842292SN/A // Set inSyscall so that the CPU doesn't squash when initially 3852292SN/A // setting up registers. 3862292SN/A for (int i = 0; i < number_of_threads; ++i) 3872292SN/A thread[i]->inSyscall = true; 3882292SN/A 3892292SN/A for (int tid=0; tid < number_of_threads; tid++) { 3901858SN/A#if FULL_SYSTEM 3912680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 3921681SN/A#else 3932680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 3941681SN/A#endif 3952292SN/A // Threads start in the Suspended State 3962680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 3972292SN/A continue; 3981060SN/A } 3991060SN/A 4002292SN/A#if FULL_SYSTEM 4012680Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 4022292SN/A#endif 4032292SN/A } 4042292SN/A 4052292SN/A // Clear inSyscall. 4062292SN/A for (int i = 0; i < number_of_threads; ++i) 4072292SN/A thread[i]->inSyscall = false; 4082292SN/A 4092316SN/A // Initialize stages. 4102292SN/A fetch.initStage(); 4112292SN/A iew.initStage(); 4122292SN/A rename.initStage(); 4132292SN/A commit.initStage(); 4142292SN/A 4152292SN/A commit.setThreads(thread); 4162292SN/A} 4172292SN/A 4182292SN/Atemplate <class Impl> 4192292SN/Avoid 4202292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 4212292SN/A{ 4222292SN/A DPRINTF(FullCPU,"[tid:%i] Initializing thread data"); 4232292SN/A // Will change now that the PC and thread state is internal to the CPU 4242683Sktlim@umich.edu // and not in the ThreadContext. 4252292SN/A#if 0 4262292SN/A#if FULL_SYSTEM 4272680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 4282292SN/A#else 4292683Sktlim@umich.edu ThreadContext *src_tc = thread[tid]; 4302292SN/A#endif 4312292SN/A 4322292SN/A //Bind Int Regs to Rename Map 4332292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 4342292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 4352292SN/A 4362292SN/A renameMap[tid].setEntry(ireg,phys_reg); 4372292SN/A scoreboard.setReg(phys_reg); 4382292SN/A } 4392292SN/A 4402292SN/A //Bind Float Regs to Rename Map 4412292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 4422292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 4432292SN/A 4442292SN/A renameMap[tid].setEntry(freg,phys_reg); 4452292SN/A scoreboard.setReg(phys_reg); 4462292SN/A } 4472292SN/A 4482292SN/A //Copy Thread Data Into RegFile 4492680Sktlim@umich.edu this->copyFromTC(tid); 4502292SN/A 4512292SN/A //Set PC/NPC 4522680Sktlim@umich.edu regFile.pc[tid] = src_tc->readPC(); 4532680Sktlim@umich.edu regFile.npc[tid] = src_tc->readNextPC(); 4542292SN/A 4552680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 4562292SN/A 4572292SN/A activateContext(tid,1); 4582292SN/A 4592292SN/A //Reset ROB/IQ/LSQ Entries 4602292SN/A commit.rob->resetEntries(); 4612292SN/A iew.resetEntries(); 4622292SN/A#endif 4632292SN/A} 4642292SN/A 4652292SN/Atemplate <class Impl> 4662292SN/Avoid 4672292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 4682292SN/A{ 4692292SN/A DPRINTF(FullCPU,"[tid:%i] Removing thread data"); 4702292SN/A#if 0 4712292SN/A //Unbind Int Regs from Rename Map 4722292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 4732292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 4742292SN/A 4752292SN/A scoreboard.unsetReg(phys_reg); 4762292SN/A freeList.addReg(phys_reg); 4772292SN/A } 4782292SN/A 4792292SN/A //Unbind Float Regs from Rename Map 4802292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 4812292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 4822292SN/A 4832292SN/A scoreboard.unsetReg(phys_reg); 4842292SN/A freeList.addReg(phys_reg); 4852292SN/A } 4862292SN/A 4872292SN/A //Copy Thread Data From RegFile 4882292SN/A /* Fix Me: 4892292SN/A * Do we really need to do this if we are removing a thread 4902292SN/A * in the sense that it's finished (exiting)? If the thread is just 4912292SN/A * being suspended we might... 4922292SN/A */ 4932680Sktlim@umich.edu// this->copyToTC(tid); 4942292SN/A 4952292SN/A //Squash Throughout Pipeline 4962292SN/A fetch.squash(0,tid); 4972292SN/A decode.squash(tid); 4982292SN/A rename.squash(tid); 4992292SN/A 5002292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 5012292SN/A 5022292SN/A //Reset ROB/IQ/LSQ Entries 5032292SN/A if (activeThreads.size() >= 1) { 5042292SN/A commit.rob->resetEntries(); 5052292SN/A iew.resetEntries(); 5062292SN/A } 5072292SN/A#endif 5082292SN/A} 5092292SN/A 5102292SN/A 5112292SN/Atemplate <class Impl> 5122292SN/Avoid 5132292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 5142292SN/A{ 5152292SN/A DPRINTF(FullCPU,"[tid:%i]: Checking if resources are available for incoming" 5162292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 5172292SN/A tid); 5182292SN/A 5192292SN/A bool ready = true; 5202292SN/A 5212292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 5222292SN/A DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 5232292SN/A "Phys. Int. Regs.\n", 5242292SN/A tid); 5252292SN/A ready = false; 5262292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 5272292SN/A DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 5282292SN/A "Phys. Float. Regs.\n", 5292292SN/A tid); 5302292SN/A ready = false; 5312292SN/A } else if (commit.rob->numFreeEntries() >= 5322292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 5332292SN/A DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 5342292SN/A "ROB entries.\n", 5352292SN/A tid); 5362292SN/A ready = false; 5372292SN/A } else if (iew.instQueue.numFreeEntries() >= 5382292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 5392292SN/A DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 5402292SN/A "IQ entries.\n", 5412292SN/A tid); 5422292SN/A ready = false; 5432292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 5442292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 5452292SN/A DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 5462292SN/A "LSQ entries.\n", 5472292SN/A tid); 5482292SN/A ready = false; 5492292SN/A } 5502292SN/A 5512292SN/A if (ready) { 5522292SN/A insertThread(tid); 5532292SN/A 5542292SN/A contextSwitch = false; 5552292SN/A 5562292SN/A cpuWaitList.remove(tid); 5572292SN/A } else { 5582292SN/A suspendContext(tid); 5592292SN/A 5602292SN/A //blocks fetch 5612292SN/A contextSwitch = true; 5622292SN/A 5632292SN/A //do waitlist 5642292SN/A cpuWaitList.push_back(tid); 5651060SN/A } 5661060SN/A} 5671060SN/A 5681060SN/Atemplate <class Impl> 5691060SN/Avoid 5702292SN/AFullO3CPU<Impl>::activateContext(int tid, int delay) 5711060SN/A{ 5721060SN/A // Needs to set each stage to running as well. 5732292SN/A list<unsigned>::iterator isActive = find( 5742292SN/A activeThreads.begin(), activeThreads.end(), tid); 5752292SN/A 5762292SN/A if (isActive == activeThreads.end()) { 5772292SN/A //May Need to Re-code this if the delay variable is the 5782292SN/A //delay needed for thread to activate 5792292SN/A DPRINTF(FullCPU, "Adding Thread %i to active threads list\n", 5802292SN/A tid); 5812292SN/A 5822292SN/A activeThreads.push_back(tid); 5832292SN/A } 5842292SN/A 5852307SN/A assert(_status == Idle || _status == SwitchedOut); 5861060SN/A 5871060SN/A scheduleTickEvent(delay); 5881060SN/A 5892292SN/A // Be sure to signal that there's some activity so the CPU doesn't 5902292SN/A // deschedule itself. 5912325SN/A activityRec.activity(); 5922292SN/A fetch.wakeFromQuiesce(); 5932292SN/A 5941060SN/A _status = Running; 5951060SN/A} 5961060SN/A 5971060SN/Atemplate <class Impl> 5981060SN/Avoid 5992292SN/AFullO3CPU<Impl>::suspendContext(int tid) 6001060SN/A{ 6012292SN/A DPRINTF(FullCPU,"[tid: %i]: Suspended ...\n", tid); 6022292SN/A unscheduleTickEvent(); 6032292SN/A _status = Idle; 6042292SN/A/* 6052292SN/A //Remove From Active List, if Active 6062292SN/A list<unsigned>::iterator isActive = find( 6072292SN/A activeThreads.begin(), activeThreads.end(), tid); 6082292SN/A 6092292SN/A if (isActive != activeThreads.end()) { 6102292SN/A DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", 6112292SN/A tid); 6122292SN/A activeThreads.erase(isActive); 6132292SN/A } 6142292SN/A*/ 6151060SN/A} 6161060SN/A 6171060SN/Atemplate <class Impl> 6181060SN/Avoid 6192292SN/AFullO3CPU<Impl>::deallocateContext(int tid) 6201060SN/A{ 6212292SN/A DPRINTF(FullCPU,"[tid:%i]: Deallocating ...", tid); 6222292SN/A/* 6232292SN/A //Remove From Active List, if Active 6242292SN/A list<unsigned>::iterator isActive = find( 6252292SN/A activeThreads.begin(), activeThreads.end(), tid); 6262292SN/A 6272292SN/A if (isActive != activeThreads.end()) { 6282292SN/A DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", 6292292SN/A tid); 6302292SN/A activeThreads.erase(isActive); 6312292SN/A 6322292SN/A removeThread(tid); 6332292SN/A } 6342292SN/A*/ 6351060SN/A} 6361060SN/A 6371060SN/Atemplate <class Impl> 6381060SN/Avoid 6392292SN/AFullO3CPU<Impl>::haltContext(int tid) 6401060SN/A{ 6412292SN/A DPRINTF(FullCPU,"[tid:%i]: Halted ...", tid); 6422292SN/A/* 6432292SN/A //Remove From Active List, if Active 6442292SN/A list<unsigned>::iterator isActive = find( 6452292SN/A activeThreads.begin(), activeThreads.end(), tid); 6462292SN/A 6472292SN/A if (isActive != activeThreads.end()) { 6482292SN/A DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", 6492292SN/A tid); 6502292SN/A activeThreads.erase(isActive); 6512292SN/A 6522292SN/A removeThread(tid); 6532292SN/A } 6542292SN/A*/ 6551060SN/A} 6561060SN/A 6571060SN/Atemplate <class Impl> 6581060SN/Avoid 6592316SN/AFullO3CPU<Impl>::switchOut(Sampler *_sampler) 6601060SN/A{ 6612316SN/A sampler = _sampler; 6622316SN/A switchCount = 0; 6632307SN/A fetch.switchOut(); 6642307SN/A decode.switchOut(); 6652307SN/A rename.switchOut(); 6662307SN/A iew.switchOut(); 6672307SN/A commit.switchOut(); 6682325SN/A 6692325SN/A // Wake the CPU and record activity so everything can drain out if 6702325SN/A // the CPU is currently idle. 6712325SN/A wakeCPU(); 6722325SN/A activityRec.activity(); 6732316SN/A} 6742310SN/A 6752316SN/Atemplate <class Impl> 6762316SN/Avoid 6772316SN/AFullO3CPU<Impl>::signalSwitched() 6782316SN/A{ 6792325SN/A if (++switchCount == NumStages) { 6802316SN/A fetch.doSwitchOut(); 6812316SN/A rename.doSwitchOut(); 6822316SN/A commit.doSwitchOut(); 6832316SN/A instList.clear(); 6842316SN/A while (!removeList.empty()) { 6852316SN/A removeList.pop(); 6862316SN/A } 6872316SN/A 6882316SN/A if (checker) 6892316SN/A checker->switchOut(sampler); 6902316SN/A 6912316SN/A if (tickEvent.scheduled()) 6922316SN/A tickEvent.squash(); 6932316SN/A sampler->signalSwitched(); 6942316SN/A _status = SwitchedOut; 6952310SN/A } 6962316SN/A assert(switchCount <= 5); 6971060SN/A} 6981060SN/A 6991060SN/Atemplate <class Impl> 7001060SN/Avoid 7011755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 7021060SN/A{ 7032325SN/A // Flush out any old data from the time buffers. 7042325SN/A for (int i = 0; i < 10; ++i) { 7052307SN/A timeBuffer.advance(); 7062307SN/A fetchQueue.advance(); 7072307SN/A decodeQueue.advance(); 7082307SN/A renameQueue.advance(); 7092307SN/A iewQueue.advance(); 7102307SN/A } 7112307SN/A 7122325SN/A activityRec.reset(); 7132307SN/A 7141060SN/A BaseCPU::takeOverFrom(oldCPU); 7151060SN/A 7162307SN/A fetch.takeOverFrom(); 7172307SN/A decode.takeOverFrom(); 7182307SN/A rename.takeOverFrom(); 7192307SN/A iew.takeOverFrom(); 7202307SN/A commit.takeOverFrom(); 7212307SN/A 7221060SN/A assert(!tickEvent.scheduled()); 7231060SN/A 7242325SN/A // @todo: Figure out how to properly select the tid to put onto 7252325SN/A // the active threads list. 7262307SN/A int tid = 0; 7272307SN/A 7282307SN/A list<unsigned>::iterator isActive = find( 7292307SN/A activeThreads.begin(), activeThreads.end(), tid); 7302307SN/A 7312307SN/A if (isActive == activeThreads.end()) { 7322325SN/A //May Need to Re-code this if the delay variable is the delay 7332325SN/A //needed for thread to activate 7342307SN/A DPRINTF(FullCPU, "Adding Thread %i to active threads list\n", 7352307SN/A tid); 7362307SN/A 7372307SN/A activeThreads.push_back(tid); 7382307SN/A } 7392307SN/A 7402325SN/A // Set all statuses to active, schedule the CPU's tick event. 7412307SN/A // @todo: Fix up statuses so this is handled properly 7422680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 7432680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 7442680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 7451681SN/A _status = Running; 7461681SN/A tickEvent.schedule(curTick); 7471681SN/A } 7481060SN/A } 7492307SN/A if (!tickEvent.scheduled()) 7502307SN/A tickEvent.schedule(curTick); 7511060SN/A} 7521060SN/A 7531060SN/Atemplate <class Impl> 7541060SN/Auint64_t 7551755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 7561060SN/A{ 7571060SN/A return regFile.readIntReg(reg_idx); 7581060SN/A} 7591060SN/A 7601060SN/Atemplate <class Impl> 7612455SN/AFloatReg 7622455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 7631060SN/A{ 7642455SN/A return regFile.readFloatReg(reg_idx, width); 7651060SN/A} 7661060SN/A 7671060SN/Atemplate <class Impl> 7682455SN/AFloatReg 7692455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 7701060SN/A{ 7712455SN/A return regFile.readFloatReg(reg_idx); 7721060SN/A} 7731060SN/A 7741060SN/Atemplate <class Impl> 7752455SN/AFloatRegBits 7762455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 7771060SN/A{ 7782455SN/A return regFile.readFloatRegBits(reg_idx, width); 7792455SN/A} 7802455SN/A 7812455SN/Atemplate <class Impl> 7822455SN/AFloatRegBits 7832455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 7842455SN/A{ 7852455SN/A return regFile.readFloatRegBits(reg_idx); 7861060SN/A} 7871060SN/A 7881060SN/Atemplate <class Impl> 7891060SN/Avoid 7901755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 7911060SN/A{ 7921060SN/A regFile.setIntReg(reg_idx, val); 7931060SN/A} 7941060SN/A 7951060SN/Atemplate <class Impl> 7961060SN/Avoid 7972455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 7981060SN/A{ 7992455SN/A regFile.setFloatReg(reg_idx, val, width); 8001060SN/A} 8011060SN/A 8021060SN/Atemplate <class Impl> 8031060SN/Avoid 8042455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 8051060SN/A{ 8062455SN/A regFile.setFloatReg(reg_idx, val); 8071060SN/A} 8081060SN/A 8091060SN/Atemplate <class Impl> 8101060SN/Avoid 8112455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 8121060SN/A{ 8132455SN/A regFile.setFloatRegBits(reg_idx, val, width); 8142455SN/A} 8152455SN/A 8162455SN/Atemplate <class Impl> 8172455SN/Avoid 8182455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 8192455SN/A{ 8202455SN/A regFile.setFloatRegBits(reg_idx, val); 8211060SN/A} 8221060SN/A 8231060SN/Atemplate <class Impl> 8241060SN/Auint64_t 8252292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 8261060SN/A{ 8272292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8282292SN/A 8292292SN/A return regFile.readIntReg(phys_reg); 8302292SN/A} 8312292SN/A 8322292SN/Atemplate <class Impl> 8332292SN/Afloat 8342292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 8352292SN/A{ 8362307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 8372307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 8382292SN/A 8392669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 8402292SN/A} 8412292SN/A 8422292SN/Atemplate <class Impl> 8432292SN/Adouble 8442292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 8452292SN/A{ 8462307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 8472307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 8482292SN/A 8492669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 8502292SN/A} 8512292SN/A 8522292SN/Atemplate <class Impl> 8532292SN/Auint64_t 8542292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 8552292SN/A{ 8562307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 8572307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 8582292SN/A 8592669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 8601060SN/A} 8611060SN/A 8621060SN/Atemplate <class Impl> 8631060SN/Avoid 8642292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 8651060SN/A{ 8662292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8672292SN/A 8682292SN/A regFile.setIntReg(phys_reg, val); 8691060SN/A} 8701060SN/A 8711060SN/Atemplate <class Impl> 8721060SN/Avoid 8732292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 8741060SN/A{ 8752292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8762292SN/A 8772669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 8781060SN/A} 8791060SN/A 8801060SN/Atemplate <class Impl> 8811060SN/Avoid 8822292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 8831060SN/A{ 8842292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8852292SN/A 8862669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 8871060SN/A} 8881060SN/A 8891060SN/Atemplate <class Impl> 8901060SN/Avoid 8912292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 8921060SN/A{ 8932292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8941060SN/A 8952669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 8962292SN/A} 8972292SN/A 8982292SN/Atemplate <class Impl> 8992292SN/Auint64_t 9002292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 9012292SN/A{ 9022292SN/A return commit.readPC(tid); 9031060SN/A} 9041060SN/A 9051060SN/Atemplate <class Impl> 9061060SN/Avoid 9072292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 9081060SN/A{ 9092292SN/A commit.setPC(new_PC, tid); 9102292SN/A} 9111060SN/A 9122292SN/Atemplate <class Impl> 9132292SN/Auint64_t 9142292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 9152292SN/A{ 9162292SN/A return commit.readNextPC(tid); 9172292SN/A} 9181060SN/A 9192292SN/Atemplate <class Impl> 9202292SN/Avoid 9212292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 9222292SN/A{ 9232292SN/A commit.setNextPC(val, tid); 9242292SN/A} 9251060SN/A 9262756Sksewell@umich.edu#if THE_ISA != ALPHA_ISA 9272756Sksewell@umich.edutemplate <class Impl> 9282756Sksewell@umich.eduuint64_t 9292756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 9302756Sksewell@umich.edu{ 9312756Sksewell@umich.edu return commit.readNextNPC(tid); 9322756Sksewell@umich.edu} 9332756Sksewell@umich.edu 9342756Sksewell@umich.edutemplate <class Impl> 9352756Sksewell@umich.eduvoid 9362756Sksewell@umich.eduFullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid) 9372756Sksewell@umich.edu{ 9382756Sksewell@umich.edu commit.setNextNPC(val, tid); 9392756Sksewell@umich.edu} 9402756Sksewell@umich.edu#endif 9412756Sksewell@umich.edu 9422292SN/Atemplate <class Impl> 9432292SN/Atypename FullO3CPU<Impl>::ListIt 9442292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 9452292SN/A{ 9462292SN/A instList.push_back(inst); 9471060SN/A 9482292SN/A return --(instList.end()); 9492292SN/A} 9501060SN/A 9512292SN/Atemplate <class Impl> 9522292SN/Avoid 9532292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 9542292SN/A{ 9552292SN/A // Keep an instruction count. 9562292SN/A thread[tid]->numInst++; 9572292SN/A thread[tid]->numInsts++; 9582292SN/A committedInsts[tid]++; 9592292SN/A totalCommittedInsts++; 9602292SN/A 9612292SN/A // Check for instruction-count-based events. 9622292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 9632292SN/A} 9642292SN/A 9652292SN/Atemplate <class Impl> 9662292SN/Avoid 9672292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 9682292SN/A{ 9692292SN/A removeInstsThisCycle = true; 9702292SN/A 9712292SN/A removeList.push(inst->getInstListIt()); 9721060SN/A} 9731060SN/A 9741060SN/Atemplate <class Impl> 9751060SN/Avoid 9761755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 9771060SN/A{ 9782292SN/A DPRINTF(FullCPU, "FullCPU: Removing committed instruction [tid:%i] PC %#x " 9792292SN/A "[sn:%lli]\n", 9802303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 9811060SN/A 9822292SN/A removeInstsThisCycle = true; 9831060SN/A 9841060SN/A // Remove the front instruction. 9852292SN/A removeList.push(inst->getInstListIt()); 9861060SN/A} 9871060SN/A 9881060SN/Atemplate <class Impl> 9891060SN/Avoid 9902292SN/AFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 9911060SN/A{ 9922292SN/A DPRINTF(FullCPU, "FullCPU: Thread %i: Deleting instructions from instruction" 9932292SN/A " list.\n", tid); 9941060SN/A 9952292SN/A ListIt end_it; 9961060SN/A 9972292SN/A bool rob_empty = false; 9982292SN/A 9992292SN/A if (instList.empty()) { 10002292SN/A return; 10012292SN/A } else if (rob.isEmpty(/*tid*/)) { 10022292SN/A DPRINTF(FullCPU, "FullCPU: ROB is empty, squashing all insts.\n"); 10032292SN/A end_it = instList.begin(); 10042292SN/A rob_empty = true; 10052292SN/A } else { 10062292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 10072292SN/A DPRINTF(FullCPU, "FullCPU: ROB is not empty, squashing insts not in ROB.\n"); 10082292SN/A } 10092292SN/A 10102292SN/A removeInstsThisCycle = true; 10112292SN/A 10122292SN/A ListIt inst_it = instList.end(); 10132292SN/A 10142292SN/A inst_it--; 10152292SN/A 10162292SN/A // Walk through the instruction list, removing any instructions 10172292SN/A // that were inserted after the given instruction iterator, end_it. 10182292SN/A while (inst_it != end_it) { 10192292SN/A assert(!instList.empty()); 10202292SN/A 10212292SN/A squashInstIt(inst_it, tid); 10222292SN/A 10232292SN/A inst_it--; 10242292SN/A } 10252292SN/A 10262292SN/A // If the ROB was empty, then we actually need to remove the first 10272292SN/A // instruction as well. 10282292SN/A if (rob_empty) { 10292292SN/A squashInstIt(inst_it, tid); 10302292SN/A } 10311060SN/A} 10321060SN/A 10331060SN/Atemplate <class Impl> 10341060SN/Avoid 10352292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 10362292SN/A unsigned tid) 10371062SN/A{ 10382292SN/A assert(!instList.empty()); 10392292SN/A 10402292SN/A removeInstsThisCycle = true; 10412292SN/A 10422292SN/A ListIt inst_iter = instList.end(); 10432292SN/A 10442292SN/A inst_iter--; 10452292SN/A 10461062SN/A DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction " 10472292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 10482292SN/A tid, seq_num, (*inst_iter)->seqNum); 10491062SN/A 10502292SN/A while ((*inst_iter)->seqNum > seq_num) { 10511062SN/A 10522292SN/A bool break_loop = (inst_iter == instList.begin()); 10531062SN/A 10542292SN/A squashInstIt(inst_iter, tid); 10551062SN/A 10562292SN/A inst_iter--; 10571062SN/A 10582292SN/A if (break_loop) 10592292SN/A break; 10602292SN/A } 10612292SN/A} 10622292SN/A 10632292SN/Atemplate <class Impl> 10642292SN/Ainline void 10652292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 10662292SN/A{ 10672292SN/A if ((*instIt)->threadNumber == tid) { 10682292SN/A DPRINTF(FullCPU, "FullCPU: Squashing instruction, " 10692292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 10702292SN/A (*instIt)->threadNumber, 10712292SN/A (*instIt)->seqNum, 10722292SN/A (*instIt)->readPC()); 10731062SN/A 10741062SN/A // Mark it as squashed. 10752292SN/A (*instIt)->setSquashed(); 10762292SN/A 10772325SN/A // @todo: Formulate a consistent method for deleting 10782325SN/A // instructions from the instruction list 10792292SN/A // Remove the instruction from the list. 10802292SN/A removeList.push(instIt); 10812292SN/A } 10822292SN/A} 10832292SN/A 10842292SN/Atemplate <class Impl> 10852292SN/Avoid 10862292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 10872292SN/A{ 10882292SN/A while (!removeList.empty()) { 10892292SN/A DPRINTF(FullCPU, "FullCPU: Removing instruction, " 10902292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 10912292SN/A (*removeList.front())->threadNumber, 10922292SN/A (*removeList.front())->seqNum, 10932292SN/A (*removeList.front())->readPC()); 10942292SN/A 10952292SN/A instList.erase(removeList.front()); 10962292SN/A 10972292SN/A removeList.pop(); 10981062SN/A } 10991062SN/A 11002292SN/A removeInstsThisCycle = false; 11011062SN/A} 11022325SN/A/* 11031062SN/Atemplate <class Impl> 11041062SN/Avoid 11051755SN/AFullO3CPU<Impl>::removeAllInsts() 11061060SN/A{ 11071060SN/A instList.clear(); 11081060SN/A} 11092325SN/A*/ 11101060SN/Atemplate <class Impl> 11111060SN/Avoid 11121755SN/AFullO3CPU<Impl>::dumpInsts() 11131060SN/A{ 11141060SN/A int num = 0; 11151060SN/A 11162292SN/A ListIt inst_list_it = instList.begin(); 11172292SN/A 11182292SN/A cprintf("Dumping Instruction List\n"); 11192292SN/A 11202292SN/A while (inst_list_it != instList.end()) { 11212292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 11222292SN/A "Squashed:%i\n\n", 11232292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 11242292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 11252292SN/A (*inst_list_it)->isSquashed()); 11261060SN/A inst_list_it++; 11271060SN/A ++num; 11281060SN/A } 11291060SN/A} 11302325SN/A/* 11311060SN/Atemplate <class Impl> 11321060SN/Avoid 11331755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 11341060SN/A{ 11351060SN/A iew.wakeDependents(inst); 11361060SN/A} 11372325SN/A*/ 11382292SN/Atemplate <class Impl> 11392292SN/Avoid 11402292SN/AFullO3CPU<Impl>::wakeCPU() 11412292SN/A{ 11422325SN/A if (activityRec.active() || tickEvent.scheduled()) { 11432325SN/A DPRINTF(Activity, "CPU already running.\n"); 11442292SN/A return; 11452292SN/A } 11462292SN/A 11472325SN/A DPRINTF(Activity, "Waking up CPU\n"); 11482325SN/A 11492325SN/A idleCycles += (curTick - 1) - lastRunningCycle; 11502292SN/A 11512292SN/A tickEvent.schedule(curTick); 11522292SN/A} 11532292SN/A 11542292SN/Atemplate <class Impl> 11552292SN/Aint 11562292SN/AFullO3CPU<Impl>::getFreeTid() 11572292SN/A{ 11582292SN/A for (int i=0; i < numThreads; i++) { 11592292SN/A if (!tids[i]) { 11602292SN/A tids[i] = true; 11612292SN/A return i; 11622292SN/A } 11632292SN/A } 11642292SN/A 11652292SN/A return -1; 11662292SN/A} 11672292SN/A 11682292SN/Atemplate <class Impl> 11692292SN/Avoid 11702292SN/AFullO3CPU<Impl>::doContextSwitch() 11712292SN/A{ 11722292SN/A if (contextSwitch) { 11732292SN/A 11742292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 11752292SN/A 11762292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 11772292SN/A activateWhenReady(tid); 11782292SN/A } 11792292SN/A 11802292SN/A if (cpuWaitList.size() == 0) 11812292SN/A contextSwitch = true; 11822292SN/A } 11832292SN/A} 11842292SN/A 11852292SN/Atemplate <class Impl> 11862292SN/Avoid 11872292SN/AFullO3CPU<Impl>::updateThreadPriority() 11882292SN/A{ 11892292SN/A if (activeThreads.size() > 1) 11902292SN/A { 11912292SN/A //DEFAULT TO ROUND ROBIN SCHEME 11922292SN/A //e.g. Move highest priority to end of thread list 11932292SN/A list<unsigned>::iterator list_begin = activeThreads.begin(); 11942292SN/A list<unsigned>::iterator list_end = activeThreads.end(); 11952292SN/A 11962292SN/A unsigned high_thread = *list_begin; 11972292SN/A 11982292SN/A activeThreads.erase(list_begin); 11992292SN/A 12002292SN/A activeThreads.push_back(high_thread); 12012292SN/A } 12022292SN/A} 12031060SN/A 12041755SN/A// Forward declaration of FullO3CPU. 12051755SN/Atemplate class FullO3CPU<AlphaSimpleImpl>; 1206