cpu.cc revision 2733
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311858SN/A#include "config/full_system.hh" 322733Sktlim@umich.edu#include "config/use_checker.hh" 331858SN/A 341858SN/A#if FULL_SYSTEM 351060SN/A#include "sim/system.hh" 361060SN/A#else 371060SN/A#include "sim/process.hh" 381060SN/A#endif 391060SN/A 402325SN/A#include "cpu/activity.hh" 412316SN/A#include "cpu/checker/cpu.hh" 422683Sktlim@umich.edu#include "cpu/simple_thread.hh" 432680Sktlim@umich.edu#include "cpu/thread_context.hh" 441717SN/A#include "cpu/o3/alpha_dyn_inst.hh" 451717SN/A#include "cpu/o3/alpha_impl.hh" 461717SN/A#include "cpu/o3/cpu.hh" 471060SN/A 482325SN/A#include "sim/root.hh" 492292SN/A#include "sim/stat_control.hh" 502292SN/A 511060SN/Ausing namespace std; 522669Sktlim@umich.eduusing namespace TheISA; 531060SN/A 542733Sktlim@umich.eduBaseO3CPU::BaseO3CPU(Params *params) 552292SN/A : BaseCPU(params), cpu_id(0) 561060SN/A{ 571060SN/A} 581060SN/A 592292SN/Avoid 602733Sktlim@umich.eduBaseO3CPU::regStats() 612292SN/A{ 622292SN/A BaseCPU::regStats(); 632292SN/A} 642292SN/A 651060SN/Atemplate <class Impl> 661755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 671060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 681060SN/A{ 691060SN/A} 701060SN/A 711060SN/Atemplate <class Impl> 721060SN/Avoid 731755SN/AFullO3CPU<Impl>::TickEvent::process() 741060SN/A{ 751060SN/A cpu->tick(); 761060SN/A} 771060SN/A 781060SN/Atemplate <class Impl> 791060SN/Aconst char * 801755SN/AFullO3CPU<Impl>::TickEvent::description() 811060SN/A{ 821755SN/A return "FullO3CPU tick event"; 831060SN/A} 841060SN/A 851060SN/Atemplate <class Impl> 862292SN/AFullO3CPU<Impl>::FullO3CPU(Params *params) 872733Sktlim@umich.edu : BaseO3CPU(params), 881060SN/A tickEvent(this), 892292SN/A removeInstsThisCycle(false), 901060SN/A fetch(params), 911060SN/A decode(params), 921060SN/A rename(params), 931060SN/A iew(params), 941060SN/A commit(params), 951060SN/A 962292SN/A regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 971060SN/A 982292SN/A freeList(params->numberOfThreads,//number of activeThreads 992292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1002292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1011060SN/A 1022292SN/A rob(params->numROBEntries, params->squashWidth, 1032292SN/A params->smtROBPolicy, params->smtROBThreshold, 1042292SN/A params->numberOfThreads), 1051060SN/A 1062292SN/A scoreboard(params->numberOfThreads,//number of activeThreads 1072292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1082292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1092292SN/A TheISA::NumMiscRegs * number_of_threads, 1102292SN/A TheISA::ZeroReg), 1111060SN/A 1121060SN/A // For now just have these time buffers be pretty big. 1132325SN/A // @todo: Make these time buffer sizes parameters or derived 1142325SN/A // from latencies 1151061SN/A timeBuffer(5, 5), 1161061SN/A fetchQueue(5, 5), 1171061SN/A decodeQueue(5, 5), 1181061SN/A renameQueue(5, 5), 1191061SN/A iewQueue(5, 5), 1202325SN/A activityRec(NumStages, 10, params->activity), 1211060SN/A 1221060SN/A globalSeqNum(1), 1231060SN/A 1241858SN/A#if FULL_SYSTEM 1252292SN/A system(params->system), 1261060SN/A physmem(system->physmem), 1271060SN/A#endif // FULL_SYSTEM 1282292SN/A mem(params->mem), 1292316SN/A switchCount(0), 1302316SN/A deferRegistration(params->deferRegistration), 1312316SN/A numThreads(number_of_threads) 1321060SN/A{ 1331060SN/A _status = Idle; 1341681SN/A 1352733Sktlim@umich.edu checker = NULL; 1362733Sktlim@umich.edu 1372733Sktlim@umich.edu#if USE_CHECKER 1382316SN/A if (params->checker) { 1392316SN/A BaseCPU *temp_checker = params->checker; 1402316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 1412316SN/A checker->setMemory(mem); 1422316SN/A#if FULL_SYSTEM 1432316SN/A checker->setSystem(params->system); 1442316SN/A#endif 1452316SN/A } 1462733Sktlim@umich.edu#endif 1472316SN/A 1481858SN/A#if !FULL_SYSTEM 1492292SN/A thread.resize(number_of_threads); 1502292SN/A tids.resize(number_of_threads); 1511681SN/A#endif 1521681SN/A 1532325SN/A // The stages also need their CPU pointer setup. However this 1542325SN/A // must be done at the upper level CPU because they have pointers 1552325SN/A // to the upper level CPU, and not this FullO3CPU. 1561060SN/A 1572292SN/A // Set up Pointers to the activeThreads list for each stage 1582292SN/A fetch.setActiveThreads(&activeThreads); 1592292SN/A decode.setActiveThreads(&activeThreads); 1602292SN/A rename.setActiveThreads(&activeThreads); 1612292SN/A iew.setActiveThreads(&activeThreads); 1622292SN/A commit.setActiveThreads(&activeThreads); 1631060SN/A 1641060SN/A // Give each of the stages the time buffer they will use. 1651060SN/A fetch.setTimeBuffer(&timeBuffer); 1661060SN/A decode.setTimeBuffer(&timeBuffer); 1671060SN/A rename.setTimeBuffer(&timeBuffer); 1681060SN/A iew.setTimeBuffer(&timeBuffer); 1691060SN/A commit.setTimeBuffer(&timeBuffer); 1701060SN/A 1711060SN/A // Also setup each of the stages' queues. 1721060SN/A fetch.setFetchQueue(&fetchQueue); 1731060SN/A decode.setFetchQueue(&fetchQueue); 1742292SN/A commit.setFetchQueue(&fetchQueue); 1751060SN/A decode.setDecodeQueue(&decodeQueue); 1761060SN/A rename.setDecodeQueue(&decodeQueue); 1771060SN/A rename.setRenameQueue(&renameQueue); 1781060SN/A iew.setRenameQueue(&renameQueue); 1791060SN/A iew.setIEWQueue(&iewQueue); 1801060SN/A commit.setIEWQueue(&iewQueue); 1811060SN/A commit.setRenameQueue(&renameQueue); 1821060SN/A 1832316SN/A commit.setFetchStage(&fetch); 1842292SN/A commit.setIEWStage(&iew); 1852292SN/A rename.setIEWStage(&iew); 1862292SN/A rename.setCommitStage(&commit); 1872292SN/A 1882292SN/A#if !FULL_SYSTEM 1892307SN/A int active_threads = params->workload.size(); 1902292SN/A#else 1912307SN/A int active_threads = 1; 1922292SN/A#endif 1932292SN/A 1942316SN/A //Make Sure That this a Valid Architeture 1952292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 1962292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 1972292SN/A 1982292SN/A rename.setScoreboard(&scoreboard); 1992292SN/A iew.setScoreboard(&scoreboard); 2002292SN/A 2011060SN/A // Setup the rename map for whichever stages need it. 2022292SN/A PhysRegIndex lreg_idx = 0; 2032292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2041060SN/A 2052292SN/A for (int tid=0; tid < numThreads; tid++) { 2062307SN/A bool bindRegs = (tid <= active_threads - 1); 2072292SN/A 2082292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2092292SN/A params->numPhysIntRegs, 2102325SN/A lreg_idx, //Index for Logical. Regs 2112292SN/A 2122292SN/A TheISA::NumFloatRegs, 2132292SN/A params->numPhysFloatRegs, 2142325SN/A freg_idx, //Index for Float Regs 2152292SN/A 2162292SN/A TheISA::NumMiscRegs, 2172292SN/A 2182292SN/A TheISA::ZeroReg, 2192292SN/A TheISA::ZeroReg, 2202292SN/A 2212292SN/A tid, 2222292SN/A false); 2232292SN/A 2242292SN/A renameMap[tid].init(TheISA::NumIntRegs, 2252292SN/A params->numPhysIntRegs, 2262325SN/A lreg_idx, //Index for Logical. Regs 2272292SN/A 2282292SN/A TheISA::NumFloatRegs, 2292292SN/A params->numPhysFloatRegs, 2302325SN/A freg_idx, //Index for Float Regs 2312292SN/A 2322292SN/A TheISA::NumMiscRegs, 2332292SN/A 2342292SN/A TheISA::ZeroReg, 2352292SN/A TheISA::ZeroReg, 2362292SN/A 2372292SN/A tid, 2382292SN/A bindRegs); 2392292SN/A } 2402292SN/A 2412292SN/A rename.setRenameMap(renameMap); 2422292SN/A commit.setRenameMap(commitRenameMap); 2432292SN/A 2442292SN/A // Give renameMap & rename stage access to the freeList; 2452292SN/A for (int i=0; i < numThreads; i++) { 2462292SN/A renameMap[i].setFreeList(&freeList); 2472292SN/A } 2481060SN/A rename.setFreeList(&freeList); 2492292SN/A 2501060SN/A // Setup the ROB for whichever stages need it. 2511060SN/A commit.setROB(&rob); 2522292SN/A 2532292SN/A lastRunningCycle = curTick; 2542292SN/A 2552292SN/A contextSwitch = false; 2561060SN/A} 2571060SN/A 2581060SN/Atemplate <class Impl> 2591755SN/AFullO3CPU<Impl>::~FullO3CPU() 2601060SN/A{ 2611060SN/A} 2621060SN/A 2631060SN/Atemplate <class Impl> 2641060SN/Avoid 2651755SN/AFullO3CPU<Impl>::fullCPURegStats() 2661062SN/A{ 2672733Sktlim@umich.edu BaseO3CPU::regStats(); 2682292SN/A 2692733Sktlim@umich.edu // Register any of the O3CPU's stats here. 2702292SN/A timesIdled 2712292SN/A .name(name() + ".timesIdled") 2722292SN/A .desc("Number of times that the entire CPU went into an idle state and" 2732292SN/A " unscheduled itself") 2742292SN/A .prereq(timesIdled); 2752292SN/A 2762292SN/A idleCycles 2772292SN/A .name(name() + ".idleCycles") 2782292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 2792292SN/A "to idling") 2802292SN/A .prereq(idleCycles); 2812292SN/A 2822292SN/A // Number of Instructions simulated 2832292SN/A // -------------------------------- 2842292SN/A // Should probably be in Base CPU but need templated 2852292SN/A // MaxThreads so put in here instead 2862292SN/A committedInsts 2872292SN/A .init(numThreads) 2882292SN/A .name(name() + ".committedInsts") 2892292SN/A .desc("Number of Instructions Simulated"); 2902292SN/A 2912292SN/A totalCommittedInsts 2922292SN/A .name(name() + ".committedInsts_total") 2932292SN/A .desc("Number of Instructions Simulated"); 2942292SN/A 2952292SN/A cpi 2962292SN/A .name(name() + ".cpi") 2972292SN/A .desc("CPI: Cycles Per Instruction") 2982292SN/A .precision(6); 2992292SN/A cpi = simTicks / committedInsts; 3002292SN/A 3012292SN/A totalCpi 3022292SN/A .name(name() + ".cpi_total") 3032292SN/A .desc("CPI: Total CPI of All Threads") 3042292SN/A .precision(6); 3052292SN/A totalCpi = simTicks / totalCommittedInsts; 3062292SN/A 3072292SN/A ipc 3082292SN/A .name(name() + ".ipc") 3092292SN/A .desc("IPC: Instructions Per Cycle") 3102292SN/A .precision(6); 3112292SN/A ipc = committedInsts / simTicks; 3122292SN/A 3132292SN/A totalIpc 3142292SN/A .name(name() + ".ipc_total") 3152292SN/A .desc("IPC: Total IPC of All Threads") 3162292SN/A .precision(6); 3172292SN/A totalIpc = totalCommittedInsts / simTicks; 3182292SN/A 3191062SN/A} 3201062SN/A 3211062SN/Atemplate <class Impl> 3221062SN/Avoid 3231755SN/AFullO3CPU<Impl>::tick() 3241060SN/A{ 3252733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 3261060SN/A 3272292SN/A ++numCycles; 3282292SN/A 3292325SN/A// activity = false; 3302292SN/A 3312292SN/A //Tick each of the stages 3321060SN/A fetch.tick(); 3331060SN/A 3341060SN/A decode.tick(); 3351060SN/A 3361060SN/A rename.tick(); 3371060SN/A 3381060SN/A iew.tick(); 3391060SN/A 3401060SN/A commit.tick(); 3411060SN/A 3422292SN/A#if !FULL_SYSTEM 3432292SN/A doContextSwitch(); 3442292SN/A#endif 3452292SN/A 3462292SN/A // Now advance the time buffers 3471060SN/A timeBuffer.advance(); 3481060SN/A 3491060SN/A fetchQueue.advance(); 3501060SN/A decodeQueue.advance(); 3511060SN/A renameQueue.advance(); 3521060SN/A iewQueue.advance(); 3531060SN/A 3542325SN/A activityRec.advance(); 3552292SN/A 3562292SN/A if (removeInstsThisCycle) { 3572292SN/A cleanUpRemovedInsts(); 3582292SN/A } 3592292SN/A 3602325SN/A if (!tickEvent.scheduled()) { 3612325SN/A if (_status == SwitchedOut) { 3622325SN/A // increment stat 3632325SN/A lastRunningCycle = curTick; 3642325SN/A } else if (!activityRec.active()) { 3652325SN/A lastRunningCycle = curTick; 3662325SN/A timesIdled++; 3672325SN/A } else { 3682325SN/A tickEvent.schedule(curTick + cycles(1)); 3692325SN/A } 3702292SN/A } 3712292SN/A 3722292SN/A#if !FULL_SYSTEM 3732292SN/A updateThreadPriority(); 3742292SN/A#endif 3752292SN/A 3761060SN/A} 3771060SN/A 3781060SN/Atemplate <class Impl> 3791060SN/Avoid 3801755SN/AFullO3CPU<Impl>::init() 3811060SN/A{ 3822307SN/A if (!deferRegistration) { 3832680Sktlim@umich.edu registerThreadContexts(); 3842292SN/A } 3851060SN/A 3862292SN/A // Set inSyscall so that the CPU doesn't squash when initially 3872292SN/A // setting up registers. 3882292SN/A for (int i = 0; i < number_of_threads; ++i) 3892292SN/A thread[i]->inSyscall = true; 3902292SN/A 3912292SN/A for (int tid=0; tid < number_of_threads; tid++) { 3921858SN/A#if FULL_SYSTEM 3932680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 3941681SN/A#else 3952680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 3961681SN/A#endif 3972292SN/A // Threads start in the Suspended State 3982680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 3992292SN/A continue; 4001060SN/A } 4011060SN/A 4022292SN/A#if FULL_SYSTEM 4032680Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 4042292SN/A#endif 4052292SN/A } 4062292SN/A 4072292SN/A // Clear inSyscall. 4082292SN/A for (int i = 0; i < number_of_threads; ++i) 4092292SN/A thread[i]->inSyscall = false; 4102292SN/A 4112316SN/A // Initialize stages. 4122292SN/A fetch.initStage(); 4132292SN/A iew.initStage(); 4142292SN/A rename.initStage(); 4152292SN/A commit.initStage(); 4162292SN/A 4172292SN/A commit.setThreads(thread); 4182292SN/A} 4192292SN/A 4202292SN/Atemplate <class Impl> 4212292SN/Avoid 4222292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 4232292SN/A{ 4242733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread data"); 4252292SN/A // Will change now that the PC and thread state is internal to the CPU 4262683Sktlim@umich.edu // and not in the ThreadContext. 4272292SN/A#if 0 4282292SN/A#if FULL_SYSTEM 4292680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 4302292SN/A#else 4312683Sktlim@umich.edu ThreadContext *src_tc = thread[tid]; 4322292SN/A#endif 4332292SN/A 4342292SN/A //Bind Int Regs to Rename Map 4352292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 4362292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 4372292SN/A 4382292SN/A renameMap[tid].setEntry(ireg,phys_reg); 4392292SN/A scoreboard.setReg(phys_reg); 4402292SN/A } 4412292SN/A 4422292SN/A //Bind Float Regs to Rename Map 4432292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 4442292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 4452292SN/A 4462292SN/A renameMap[tid].setEntry(freg,phys_reg); 4472292SN/A scoreboard.setReg(phys_reg); 4482292SN/A } 4492292SN/A 4502292SN/A //Copy Thread Data Into RegFile 4512680Sktlim@umich.edu this->copyFromTC(tid); 4522292SN/A 4532292SN/A //Set PC/NPC 4542680Sktlim@umich.edu regFile.pc[tid] = src_tc->readPC(); 4552680Sktlim@umich.edu regFile.npc[tid] = src_tc->readNextPC(); 4562292SN/A 4572680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 4582292SN/A 4592292SN/A activateContext(tid,1); 4602292SN/A 4612292SN/A //Reset ROB/IQ/LSQ Entries 4622292SN/A commit.rob->resetEntries(); 4632292SN/A iew.resetEntries(); 4642292SN/A#endif 4652292SN/A} 4662292SN/A 4672292SN/Atemplate <class Impl> 4682292SN/Avoid 4692292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 4702292SN/A{ 4712733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread data"); 4722292SN/A#if 0 4732292SN/A //Unbind Int Regs from Rename Map 4742292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 4752292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 4762292SN/A 4772292SN/A scoreboard.unsetReg(phys_reg); 4782292SN/A freeList.addReg(phys_reg); 4792292SN/A } 4802292SN/A 4812292SN/A //Unbind Float Regs from Rename Map 4822292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 4832292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 4842292SN/A 4852292SN/A scoreboard.unsetReg(phys_reg); 4862292SN/A freeList.addReg(phys_reg); 4872292SN/A } 4882292SN/A 4892292SN/A //Copy Thread Data From RegFile 4902292SN/A /* Fix Me: 4912292SN/A * Do we really need to do this if we are removing a thread 4922292SN/A * in the sense that it's finished (exiting)? If the thread is just 4932292SN/A * being suspended we might... 4942292SN/A */ 4952680Sktlim@umich.edu// this->copyToTC(tid); 4962292SN/A 4972292SN/A //Squash Throughout Pipeline 4982292SN/A fetch.squash(0,tid); 4992292SN/A decode.squash(tid); 5002292SN/A rename.squash(tid); 5012292SN/A 5022292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 5032292SN/A 5042292SN/A //Reset ROB/IQ/LSQ Entries 5052292SN/A if (activeThreads.size() >= 1) { 5062292SN/A commit.rob->resetEntries(); 5072292SN/A iew.resetEntries(); 5082292SN/A } 5092292SN/A#endif 5102292SN/A} 5112292SN/A 5122292SN/A 5132292SN/Atemplate <class Impl> 5142292SN/Avoid 5152292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 5162292SN/A{ 5172733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 5182292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 5192292SN/A tid); 5202292SN/A 5212292SN/A bool ready = true; 5222292SN/A 5232292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 5242733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5252292SN/A "Phys. Int. Regs.\n", 5262292SN/A tid); 5272292SN/A ready = false; 5282292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 5292733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5302292SN/A "Phys. Float. Regs.\n", 5312292SN/A tid); 5322292SN/A ready = false; 5332292SN/A } else if (commit.rob->numFreeEntries() >= 5342292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 5352733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5362292SN/A "ROB entries.\n", 5372292SN/A tid); 5382292SN/A ready = false; 5392292SN/A } else if (iew.instQueue.numFreeEntries() >= 5402292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 5412733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5422292SN/A "IQ entries.\n", 5432292SN/A tid); 5442292SN/A ready = false; 5452292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 5462292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 5472733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5482292SN/A "LSQ entries.\n", 5492292SN/A tid); 5502292SN/A ready = false; 5512292SN/A } 5522292SN/A 5532292SN/A if (ready) { 5542292SN/A insertThread(tid); 5552292SN/A 5562292SN/A contextSwitch = false; 5572292SN/A 5582292SN/A cpuWaitList.remove(tid); 5592292SN/A } else { 5602292SN/A suspendContext(tid); 5612292SN/A 5622292SN/A //blocks fetch 5632292SN/A contextSwitch = true; 5642292SN/A 5652292SN/A //do waitlist 5662292SN/A cpuWaitList.push_back(tid); 5671060SN/A } 5681060SN/A} 5691060SN/A 5701060SN/Atemplate <class Impl> 5711060SN/Avoid 5722292SN/AFullO3CPU<Impl>::activateContext(int tid, int delay) 5731060SN/A{ 5741060SN/A // Needs to set each stage to running as well. 5752292SN/A list<unsigned>::iterator isActive = find( 5762292SN/A activeThreads.begin(), activeThreads.end(), tid); 5772292SN/A 5782292SN/A if (isActive == activeThreads.end()) { 5792292SN/A //May Need to Re-code this if the delay variable is the 5802292SN/A //delay needed for thread to activate 5812733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 5822292SN/A tid); 5832292SN/A 5842292SN/A activeThreads.push_back(tid); 5852292SN/A } 5862292SN/A 5872307SN/A assert(_status == Idle || _status == SwitchedOut); 5881060SN/A 5891060SN/A scheduleTickEvent(delay); 5901060SN/A 5912292SN/A // Be sure to signal that there's some activity so the CPU doesn't 5922292SN/A // deschedule itself. 5932325SN/A activityRec.activity(); 5942292SN/A fetch.wakeFromQuiesce(); 5952292SN/A 5961060SN/A _status = Running; 5971060SN/A} 5981060SN/A 5991060SN/Atemplate <class Impl> 6001060SN/Avoid 6012292SN/AFullO3CPU<Impl>::suspendContext(int tid) 6021060SN/A{ 6032733Sktlim@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspended ...\n", tid); 6042292SN/A unscheduleTickEvent(); 6052292SN/A _status = Idle; 6062292SN/A/* 6072292SN/A //Remove From Active List, if Active 6082292SN/A list<unsigned>::iterator isActive = find( 6092292SN/A activeThreads.begin(), activeThreads.end(), tid); 6102292SN/A 6112292SN/A if (isActive != activeThreads.end()) { 6122733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6132292SN/A tid); 6142292SN/A activeThreads.erase(isActive); 6152292SN/A } 6162292SN/A*/ 6171060SN/A} 6181060SN/A 6191060SN/Atemplate <class Impl> 6201060SN/Avoid 6212292SN/AFullO3CPU<Impl>::deallocateContext(int tid) 6221060SN/A{ 6232733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Deallocating ...", tid); 6242292SN/A/* 6252292SN/A //Remove From Active List, if Active 6262292SN/A list<unsigned>::iterator isActive = find( 6272292SN/A activeThreads.begin(), activeThreads.end(), tid); 6282292SN/A 6292292SN/A if (isActive != activeThreads.end()) { 6302733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6312292SN/A tid); 6322292SN/A activeThreads.erase(isActive); 6332292SN/A 6342292SN/A removeThread(tid); 6352292SN/A } 6362292SN/A*/ 6371060SN/A} 6381060SN/A 6391060SN/Atemplate <class Impl> 6401060SN/Avoid 6412292SN/AFullO3CPU<Impl>::haltContext(int tid) 6421060SN/A{ 6432733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halted ...", tid); 6442292SN/A/* 6452292SN/A //Remove From Active List, if Active 6462292SN/A list<unsigned>::iterator isActive = find( 6472292SN/A activeThreads.begin(), activeThreads.end(), tid); 6482292SN/A 6492292SN/A if (isActive != activeThreads.end()) { 6502733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6512292SN/A tid); 6522292SN/A activeThreads.erase(isActive); 6532292SN/A 6542292SN/A removeThread(tid); 6552292SN/A } 6562292SN/A*/ 6571060SN/A} 6581060SN/A 6591060SN/Atemplate <class Impl> 6601060SN/Avoid 6612316SN/AFullO3CPU<Impl>::switchOut(Sampler *_sampler) 6621060SN/A{ 6632316SN/A sampler = _sampler; 6642316SN/A switchCount = 0; 6652307SN/A fetch.switchOut(); 6662307SN/A decode.switchOut(); 6672307SN/A rename.switchOut(); 6682307SN/A iew.switchOut(); 6692307SN/A commit.switchOut(); 6702325SN/A 6712325SN/A // Wake the CPU and record activity so everything can drain out if 6722325SN/A // the CPU is currently idle. 6732325SN/A wakeCPU(); 6742325SN/A activityRec.activity(); 6752316SN/A} 6762310SN/A 6772316SN/Atemplate <class Impl> 6782316SN/Avoid 6792316SN/AFullO3CPU<Impl>::signalSwitched() 6802316SN/A{ 6812325SN/A if (++switchCount == NumStages) { 6822316SN/A fetch.doSwitchOut(); 6832316SN/A rename.doSwitchOut(); 6842316SN/A commit.doSwitchOut(); 6852316SN/A instList.clear(); 6862316SN/A while (!removeList.empty()) { 6872316SN/A removeList.pop(); 6882316SN/A } 6892316SN/A 6902316SN/A if (checker) 6912316SN/A checker->switchOut(sampler); 6922316SN/A 6932316SN/A if (tickEvent.scheduled()) 6942316SN/A tickEvent.squash(); 6952316SN/A sampler->signalSwitched(); 6962316SN/A _status = SwitchedOut; 6972310SN/A } 6982316SN/A assert(switchCount <= 5); 6991060SN/A} 7001060SN/A 7011060SN/Atemplate <class Impl> 7021060SN/Avoid 7031755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 7041060SN/A{ 7052325SN/A // Flush out any old data from the time buffers. 7062325SN/A for (int i = 0; i < 10; ++i) { 7072307SN/A timeBuffer.advance(); 7082307SN/A fetchQueue.advance(); 7092307SN/A decodeQueue.advance(); 7102307SN/A renameQueue.advance(); 7112307SN/A iewQueue.advance(); 7122307SN/A } 7132307SN/A 7142325SN/A activityRec.reset(); 7152307SN/A 7161060SN/A BaseCPU::takeOverFrom(oldCPU); 7171060SN/A 7182307SN/A fetch.takeOverFrom(); 7192307SN/A decode.takeOverFrom(); 7202307SN/A rename.takeOverFrom(); 7212307SN/A iew.takeOverFrom(); 7222307SN/A commit.takeOverFrom(); 7232307SN/A 7241060SN/A assert(!tickEvent.scheduled()); 7251060SN/A 7262325SN/A // @todo: Figure out how to properly select the tid to put onto 7272325SN/A // the active threads list. 7282307SN/A int tid = 0; 7292307SN/A 7302307SN/A list<unsigned>::iterator isActive = find( 7312307SN/A activeThreads.begin(), activeThreads.end(), tid); 7322307SN/A 7332307SN/A if (isActive == activeThreads.end()) { 7342325SN/A //May Need to Re-code this if the delay variable is the delay 7352325SN/A //needed for thread to activate 7362733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 7372307SN/A tid); 7382307SN/A 7392307SN/A activeThreads.push_back(tid); 7402307SN/A } 7412307SN/A 7422325SN/A // Set all statuses to active, schedule the CPU's tick event. 7432307SN/A // @todo: Fix up statuses so this is handled properly 7442680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 7452680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 7462680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 7471681SN/A _status = Running; 7481681SN/A tickEvent.schedule(curTick); 7491681SN/A } 7501060SN/A } 7512307SN/A if (!tickEvent.scheduled()) 7522307SN/A tickEvent.schedule(curTick); 7531060SN/A} 7541060SN/A 7551060SN/Atemplate <class Impl> 7561060SN/Auint64_t 7571755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 7581060SN/A{ 7591060SN/A return regFile.readIntReg(reg_idx); 7601060SN/A} 7611060SN/A 7621060SN/Atemplate <class Impl> 7632455SN/AFloatReg 7642455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 7651060SN/A{ 7662455SN/A return regFile.readFloatReg(reg_idx, width); 7671060SN/A} 7681060SN/A 7691060SN/Atemplate <class Impl> 7702455SN/AFloatReg 7712455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 7721060SN/A{ 7732455SN/A return regFile.readFloatReg(reg_idx); 7741060SN/A} 7751060SN/A 7761060SN/Atemplate <class Impl> 7772455SN/AFloatRegBits 7782455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 7791060SN/A{ 7802455SN/A return regFile.readFloatRegBits(reg_idx, width); 7812455SN/A} 7822455SN/A 7832455SN/Atemplate <class Impl> 7842455SN/AFloatRegBits 7852455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 7862455SN/A{ 7872455SN/A return regFile.readFloatRegBits(reg_idx); 7881060SN/A} 7891060SN/A 7901060SN/Atemplate <class Impl> 7911060SN/Avoid 7921755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 7931060SN/A{ 7941060SN/A regFile.setIntReg(reg_idx, val); 7951060SN/A} 7961060SN/A 7971060SN/Atemplate <class Impl> 7981060SN/Avoid 7992455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 8001060SN/A{ 8012455SN/A regFile.setFloatReg(reg_idx, val, width); 8021060SN/A} 8031060SN/A 8041060SN/Atemplate <class Impl> 8051060SN/Avoid 8062455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 8071060SN/A{ 8082455SN/A regFile.setFloatReg(reg_idx, val); 8091060SN/A} 8101060SN/A 8111060SN/Atemplate <class Impl> 8121060SN/Avoid 8132455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 8141060SN/A{ 8152455SN/A regFile.setFloatRegBits(reg_idx, val, width); 8162455SN/A} 8172455SN/A 8182455SN/Atemplate <class Impl> 8192455SN/Avoid 8202455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 8212455SN/A{ 8222455SN/A regFile.setFloatRegBits(reg_idx, val); 8231060SN/A} 8241060SN/A 8251060SN/Atemplate <class Impl> 8261060SN/Auint64_t 8272292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 8281060SN/A{ 8292292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8302292SN/A 8312292SN/A return regFile.readIntReg(phys_reg); 8322292SN/A} 8332292SN/A 8342292SN/Atemplate <class Impl> 8352292SN/Afloat 8362292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 8372292SN/A{ 8382307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 8392307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 8402292SN/A 8412669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 8422292SN/A} 8432292SN/A 8442292SN/Atemplate <class Impl> 8452292SN/Adouble 8462292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 8472292SN/A{ 8482307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 8492307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 8502292SN/A 8512669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 8522292SN/A} 8532292SN/A 8542292SN/Atemplate <class Impl> 8552292SN/Auint64_t 8562292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 8572292SN/A{ 8582307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 8592307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 8602292SN/A 8612669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 8621060SN/A} 8631060SN/A 8641060SN/Atemplate <class Impl> 8651060SN/Avoid 8662292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 8671060SN/A{ 8682292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8692292SN/A 8702292SN/A regFile.setIntReg(phys_reg, val); 8711060SN/A} 8721060SN/A 8731060SN/Atemplate <class Impl> 8741060SN/Avoid 8752292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 8761060SN/A{ 8772292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8782292SN/A 8792669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 8801060SN/A} 8811060SN/A 8821060SN/Atemplate <class Impl> 8831060SN/Avoid 8842292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 8851060SN/A{ 8862292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8872292SN/A 8882669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 8891060SN/A} 8901060SN/A 8911060SN/Atemplate <class Impl> 8921060SN/Avoid 8932292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 8941060SN/A{ 8952292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8961060SN/A 8972669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 8982292SN/A} 8992292SN/A 9002292SN/Atemplate <class Impl> 9012292SN/Auint64_t 9022292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 9032292SN/A{ 9042292SN/A return commit.readPC(tid); 9051060SN/A} 9061060SN/A 9071060SN/Atemplate <class Impl> 9081060SN/Avoid 9092292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 9101060SN/A{ 9112292SN/A commit.setPC(new_PC, tid); 9122292SN/A} 9131060SN/A 9142292SN/Atemplate <class Impl> 9152292SN/Auint64_t 9162292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 9172292SN/A{ 9182292SN/A return commit.readNextPC(tid); 9192292SN/A} 9201060SN/A 9212292SN/Atemplate <class Impl> 9222292SN/Avoid 9232292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 9242292SN/A{ 9252292SN/A commit.setNextPC(val, tid); 9262292SN/A} 9271060SN/A 9282292SN/Atemplate <class Impl> 9292292SN/Atypename FullO3CPU<Impl>::ListIt 9302292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 9312292SN/A{ 9322292SN/A instList.push_back(inst); 9331060SN/A 9342292SN/A return --(instList.end()); 9352292SN/A} 9361060SN/A 9372292SN/Atemplate <class Impl> 9382292SN/Avoid 9392292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 9402292SN/A{ 9412292SN/A // Keep an instruction count. 9422292SN/A thread[tid]->numInst++; 9432292SN/A thread[tid]->numInsts++; 9442292SN/A committedInsts[tid]++; 9452292SN/A totalCommittedInsts++; 9462292SN/A 9472292SN/A // Check for instruction-count-based events. 9482292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 9492292SN/A} 9502292SN/A 9512292SN/Atemplate <class Impl> 9522292SN/Avoid 9532292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 9542292SN/A{ 9552292SN/A removeInstsThisCycle = true; 9562292SN/A 9572292SN/A removeList.push(inst->getInstListIt()); 9581060SN/A} 9591060SN/A 9601060SN/Atemplate <class Impl> 9611060SN/Avoid 9621755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 9631060SN/A{ 9642733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 9652292SN/A "[sn:%lli]\n", 9662303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 9671060SN/A 9682292SN/A removeInstsThisCycle = true; 9691060SN/A 9701060SN/A // Remove the front instruction. 9712292SN/A removeList.push(inst->getInstListIt()); 9721060SN/A} 9731060SN/A 9741060SN/Atemplate <class Impl> 9751060SN/Avoid 9762292SN/AFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 9771060SN/A{ 9782733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 9792292SN/A " list.\n", tid); 9801060SN/A 9812292SN/A ListIt end_it; 9821060SN/A 9832292SN/A bool rob_empty = false; 9842292SN/A 9852292SN/A if (instList.empty()) { 9862292SN/A return; 9872292SN/A } else if (rob.isEmpty(/*tid*/)) { 9882733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 9892292SN/A end_it = instList.begin(); 9902292SN/A rob_empty = true; 9912292SN/A } else { 9922292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 9932733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 9942292SN/A } 9952292SN/A 9962292SN/A removeInstsThisCycle = true; 9972292SN/A 9982292SN/A ListIt inst_it = instList.end(); 9992292SN/A 10002292SN/A inst_it--; 10012292SN/A 10022292SN/A // Walk through the instruction list, removing any instructions 10032292SN/A // that were inserted after the given instruction iterator, end_it. 10042292SN/A while (inst_it != end_it) { 10052292SN/A assert(!instList.empty()); 10062292SN/A 10072292SN/A squashInstIt(inst_it, tid); 10082292SN/A 10092292SN/A inst_it--; 10102292SN/A } 10112292SN/A 10122292SN/A // If the ROB was empty, then we actually need to remove the first 10132292SN/A // instruction as well. 10142292SN/A if (rob_empty) { 10152292SN/A squashInstIt(inst_it, tid); 10162292SN/A } 10171060SN/A} 10181060SN/A 10191060SN/Atemplate <class Impl> 10201060SN/Avoid 10212292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 10222292SN/A unsigned tid) 10231062SN/A{ 10242292SN/A assert(!instList.empty()); 10252292SN/A 10262292SN/A removeInstsThisCycle = true; 10272292SN/A 10282292SN/A ListIt inst_iter = instList.end(); 10292292SN/A 10302292SN/A inst_iter--; 10312292SN/A 10322733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 10332292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 10342292SN/A tid, seq_num, (*inst_iter)->seqNum); 10351062SN/A 10362292SN/A while ((*inst_iter)->seqNum > seq_num) { 10371062SN/A 10382292SN/A bool break_loop = (inst_iter == instList.begin()); 10391062SN/A 10402292SN/A squashInstIt(inst_iter, tid); 10411062SN/A 10422292SN/A inst_iter--; 10431062SN/A 10442292SN/A if (break_loop) 10452292SN/A break; 10462292SN/A } 10472292SN/A} 10482292SN/A 10492292SN/Atemplate <class Impl> 10502292SN/Ainline void 10512292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 10522292SN/A{ 10532292SN/A if ((*instIt)->threadNumber == tid) { 10542733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 10552292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 10562292SN/A (*instIt)->threadNumber, 10572292SN/A (*instIt)->seqNum, 10582292SN/A (*instIt)->readPC()); 10591062SN/A 10601062SN/A // Mark it as squashed. 10612292SN/A (*instIt)->setSquashed(); 10622292SN/A 10632325SN/A // @todo: Formulate a consistent method for deleting 10642325SN/A // instructions from the instruction list 10652292SN/A // Remove the instruction from the list. 10662292SN/A removeList.push(instIt); 10672292SN/A } 10682292SN/A} 10692292SN/A 10702292SN/Atemplate <class Impl> 10712292SN/Avoid 10722292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 10732292SN/A{ 10742292SN/A while (!removeList.empty()) { 10752733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 10762292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 10772292SN/A (*removeList.front())->threadNumber, 10782292SN/A (*removeList.front())->seqNum, 10792292SN/A (*removeList.front())->readPC()); 10802292SN/A 10812292SN/A instList.erase(removeList.front()); 10822292SN/A 10832292SN/A removeList.pop(); 10841062SN/A } 10851062SN/A 10862292SN/A removeInstsThisCycle = false; 10871062SN/A} 10882325SN/A/* 10891062SN/Atemplate <class Impl> 10901062SN/Avoid 10911755SN/AFullO3CPU<Impl>::removeAllInsts() 10921060SN/A{ 10931060SN/A instList.clear(); 10941060SN/A} 10952325SN/A*/ 10961060SN/Atemplate <class Impl> 10971060SN/Avoid 10981755SN/AFullO3CPU<Impl>::dumpInsts() 10991060SN/A{ 11001060SN/A int num = 0; 11011060SN/A 11022292SN/A ListIt inst_list_it = instList.begin(); 11032292SN/A 11042292SN/A cprintf("Dumping Instruction List\n"); 11052292SN/A 11062292SN/A while (inst_list_it != instList.end()) { 11072292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 11082292SN/A "Squashed:%i\n\n", 11092292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 11102292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 11112292SN/A (*inst_list_it)->isSquashed()); 11121060SN/A inst_list_it++; 11131060SN/A ++num; 11141060SN/A } 11151060SN/A} 11162325SN/A/* 11171060SN/Atemplate <class Impl> 11181060SN/Avoid 11191755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 11201060SN/A{ 11211060SN/A iew.wakeDependents(inst); 11221060SN/A} 11232325SN/A*/ 11242292SN/Atemplate <class Impl> 11252292SN/Avoid 11262292SN/AFullO3CPU<Impl>::wakeCPU() 11272292SN/A{ 11282325SN/A if (activityRec.active() || tickEvent.scheduled()) { 11292325SN/A DPRINTF(Activity, "CPU already running.\n"); 11302292SN/A return; 11312292SN/A } 11322292SN/A 11332325SN/A DPRINTF(Activity, "Waking up CPU\n"); 11342325SN/A 11352325SN/A idleCycles += (curTick - 1) - lastRunningCycle; 11362292SN/A 11372292SN/A tickEvent.schedule(curTick); 11382292SN/A} 11392292SN/A 11402292SN/Atemplate <class Impl> 11412292SN/Aint 11422292SN/AFullO3CPU<Impl>::getFreeTid() 11432292SN/A{ 11442292SN/A for (int i=0; i < numThreads; i++) { 11452292SN/A if (!tids[i]) { 11462292SN/A tids[i] = true; 11472292SN/A return i; 11482292SN/A } 11492292SN/A } 11502292SN/A 11512292SN/A return -1; 11522292SN/A} 11532292SN/A 11542292SN/Atemplate <class Impl> 11552292SN/Avoid 11562292SN/AFullO3CPU<Impl>::doContextSwitch() 11572292SN/A{ 11582292SN/A if (contextSwitch) { 11592292SN/A 11602292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 11612292SN/A 11622292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 11632292SN/A activateWhenReady(tid); 11642292SN/A } 11652292SN/A 11662292SN/A if (cpuWaitList.size() == 0) 11672292SN/A contextSwitch = true; 11682292SN/A } 11692292SN/A} 11702292SN/A 11712292SN/Atemplate <class Impl> 11722292SN/Avoid 11732292SN/AFullO3CPU<Impl>::updateThreadPriority() 11742292SN/A{ 11752292SN/A if (activeThreads.size() > 1) 11762292SN/A { 11772292SN/A //DEFAULT TO ROUND ROBIN SCHEME 11782292SN/A //e.g. Move highest priority to end of thread list 11792292SN/A list<unsigned>::iterator list_begin = activeThreads.begin(); 11802292SN/A list<unsigned>::iterator list_end = activeThreads.end(); 11812292SN/A 11822292SN/A unsigned high_thread = *list_begin; 11832292SN/A 11842292SN/A activeThreads.erase(list_begin); 11852292SN/A 11862292SN/A activeThreads.push_back(high_thread); 11872292SN/A } 11882292SN/A} 11891060SN/A 11901755SN/A// Forward declaration of FullO3CPU. 11911755SN/Atemplate class FullO3CPU<AlphaSimpleImpl>; 1192