cpu.cc revision 2680
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311858SN/A#include "config/full_system.hh" 321858SN/A 331858SN/A#if FULL_SYSTEM 341060SN/A#include "sim/system.hh" 351060SN/A#else 361060SN/A#include "sim/process.hh" 371060SN/A#endif 381060SN/A 392325SN/A#include "cpu/activity.hh" 402316SN/A#include "cpu/checker/cpu.hh" 412190SN/A#include "cpu/cpu_exec_context.hh" 422680Sktlim@umich.edu#include "cpu/thread_context.hh" 431717SN/A#include "cpu/o3/alpha_dyn_inst.hh" 441717SN/A#include "cpu/o3/alpha_impl.hh" 451717SN/A#include "cpu/o3/cpu.hh" 461060SN/A 472325SN/A#include "sim/root.hh" 482292SN/A#include "sim/stat_control.hh" 492292SN/A 501060SN/Ausing namespace std; 512669Sktlim@umich.eduusing namespace TheISA; 521060SN/A 532292SN/ABaseFullCPU::BaseFullCPU(Params *params) 542292SN/A : BaseCPU(params), cpu_id(0) 551060SN/A{ 561060SN/A} 571060SN/A 582292SN/Avoid 592292SN/ABaseFullCPU::regStats() 602292SN/A{ 612292SN/A BaseCPU::regStats(); 622292SN/A} 632292SN/A 641060SN/Atemplate <class Impl> 651755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 661060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 671060SN/A{ 681060SN/A} 691060SN/A 701060SN/Atemplate <class Impl> 711060SN/Avoid 721755SN/AFullO3CPU<Impl>::TickEvent::process() 731060SN/A{ 741060SN/A cpu->tick(); 751060SN/A} 761060SN/A 771060SN/Atemplate <class Impl> 781060SN/Aconst char * 791755SN/AFullO3CPU<Impl>::TickEvent::description() 801060SN/A{ 811755SN/A return "FullO3CPU tick event"; 821060SN/A} 831060SN/A 841060SN/Atemplate <class Impl> 852292SN/AFullO3CPU<Impl>::FullO3CPU(Params *params) 861061SN/A : BaseFullCPU(params), 871060SN/A tickEvent(this), 882292SN/A removeInstsThisCycle(false), 891060SN/A fetch(params), 901060SN/A decode(params), 911060SN/A rename(params), 921060SN/A iew(params), 931060SN/A commit(params), 941060SN/A 952292SN/A regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 961060SN/A 972292SN/A freeList(params->numberOfThreads,//number of activeThreads 982292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 992292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1001060SN/A 1012292SN/A rob(params->numROBEntries, params->squashWidth, 1022292SN/A params->smtROBPolicy, params->smtROBThreshold, 1032292SN/A params->numberOfThreads), 1041060SN/A 1052292SN/A scoreboard(params->numberOfThreads,//number of activeThreads 1062292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1072292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1082292SN/A TheISA::NumMiscRegs * number_of_threads, 1092292SN/A TheISA::ZeroReg), 1101060SN/A 1111060SN/A // For now just have these time buffers be pretty big. 1122325SN/A // @todo: Make these time buffer sizes parameters or derived 1132325SN/A // from latencies 1141061SN/A timeBuffer(5, 5), 1151061SN/A fetchQueue(5, 5), 1161061SN/A decodeQueue(5, 5), 1171061SN/A renameQueue(5, 5), 1181061SN/A iewQueue(5, 5), 1192325SN/A activityRec(NumStages, 10, params->activity), 1201060SN/A 1211060SN/A globalSeqNum(1), 1221060SN/A 1231858SN/A#if FULL_SYSTEM 1242292SN/A system(params->system), 1251681SN/A memCtrl(system->memctrl), 1261060SN/A physmem(system->physmem), 1271060SN/A#endif // FULL_SYSTEM 1282292SN/A mem(params->mem), 1292316SN/A switchCount(0), 1302316SN/A deferRegistration(params->deferRegistration), 1312316SN/A numThreads(number_of_threads) 1321060SN/A{ 1331060SN/A _status = Idle; 1341681SN/A 1352316SN/A if (params->checker) { 1362316SN/A BaseCPU *temp_checker = params->checker; 1372316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 1382316SN/A checker->setMemory(mem); 1392316SN/A#if FULL_SYSTEM 1402316SN/A checker->setSystem(params->system); 1412316SN/A#endif 1422316SN/A } else { 1432316SN/A checker = NULL; 1442316SN/A } 1452316SN/A 1461858SN/A#if !FULL_SYSTEM 1472292SN/A thread.resize(number_of_threads); 1482292SN/A tids.resize(number_of_threads); 1491681SN/A#endif 1501681SN/A 1512325SN/A // The stages also need their CPU pointer setup. However this 1522325SN/A // must be done at the upper level CPU because they have pointers 1532325SN/A // to the upper level CPU, and not this FullO3CPU. 1541060SN/A 1552292SN/A // Set up Pointers to the activeThreads list for each stage 1562292SN/A fetch.setActiveThreads(&activeThreads); 1572292SN/A decode.setActiveThreads(&activeThreads); 1582292SN/A rename.setActiveThreads(&activeThreads); 1592292SN/A iew.setActiveThreads(&activeThreads); 1602292SN/A commit.setActiveThreads(&activeThreads); 1611060SN/A 1621060SN/A // Give each of the stages the time buffer they will use. 1631060SN/A fetch.setTimeBuffer(&timeBuffer); 1641060SN/A decode.setTimeBuffer(&timeBuffer); 1651060SN/A rename.setTimeBuffer(&timeBuffer); 1661060SN/A iew.setTimeBuffer(&timeBuffer); 1671060SN/A commit.setTimeBuffer(&timeBuffer); 1681060SN/A 1691060SN/A // Also setup each of the stages' queues. 1701060SN/A fetch.setFetchQueue(&fetchQueue); 1711060SN/A decode.setFetchQueue(&fetchQueue); 1722292SN/A commit.setFetchQueue(&fetchQueue); 1731060SN/A decode.setDecodeQueue(&decodeQueue); 1741060SN/A rename.setDecodeQueue(&decodeQueue); 1751060SN/A rename.setRenameQueue(&renameQueue); 1761060SN/A iew.setRenameQueue(&renameQueue); 1771060SN/A iew.setIEWQueue(&iewQueue); 1781060SN/A commit.setIEWQueue(&iewQueue); 1791060SN/A commit.setRenameQueue(&renameQueue); 1801060SN/A 1812316SN/A commit.setFetchStage(&fetch); 1822292SN/A commit.setIEWStage(&iew); 1832292SN/A rename.setIEWStage(&iew); 1842292SN/A rename.setCommitStage(&commit); 1852292SN/A 1862292SN/A#if !FULL_SYSTEM 1872307SN/A int active_threads = params->workload.size(); 1882292SN/A#else 1892307SN/A int active_threads = 1; 1902292SN/A#endif 1912292SN/A 1922316SN/A //Make Sure That this a Valid Architeture 1932292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 1942292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 1952292SN/A 1962292SN/A rename.setScoreboard(&scoreboard); 1972292SN/A iew.setScoreboard(&scoreboard); 1982292SN/A 1991060SN/A // Setup the rename map for whichever stages need it. 2002292SN/A PhysRegIndex lreg_idx = 0; 2012292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2021060SN/A 2032292SN/A for (int tid=0; tid < numThreads; tid++) { 2042307SN/A bool bindRegs = (tid <= active_threads - 1); 2052292SN/A 2062292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2072292SN/A params->numPhysIntRegs, 2082325SN/A lreg_idx, //Index for Logical. Regs 2092292SN/A 2102292SN/A TheISA::NumFloatRegs, 2112292SN/A params->numPhysFloatRegs, 2122325SN/A freg_idx, //Index for Float Regs 2132292SN/A 2142292SN/A TheISA::NumMiscRegs, 2152292SN/A 2162292SN/A TheISA::ZeroReg, 2172292SN/A TheISA::ZeroReg, 2182292SN/A 2192292SN/A tid, 2202292SN/A false); 2212292SN/A 2222292SN/A renameMap[tid].init(TheISA::NumIntRegs, 2232292SN/A params->numPhysIntRegs, 2242325SN/A lreg_idx, //Index for Logical. Regs 2252292SN/A 2262292SN/A TheISA::NumFloatRegs, 2272292SN/A params->numPhysFloatRegs, 2282325SN/A freg_idx, //Index for Float Regs 2292292SN/A 2302292SN/A TheISA::NumMiscRegs, 2312292SN/A 2322292SN/A TheISA::ZeroReg, 2332292SN/A TheISA::ZeroReg, 2342292SN/A 2352292SN/A tid, 2362292SN/A bindRegs); 2372292SN/A } 2382292SN/A 2392292SN/A rename.setRenameMap(renameMap); 2402292SN/A commit.setRenameMap(commitRenameMap); 2412292SN/A 2422292SN/A // Give renameMap & rename stage access to the freeList; 2432292SN/A for (int i=0; i < numThreads; i++) { 2442292SN/A renameMap[i].setFreeList(&freeList); 2452292SN/A } 2461060SN/A rename.setFreeList(&freeList); 2472292SN/A 2482292SN/A // Setup the page table for whichever stages need it. 2492292SN/A#if !FULL_SYSTEM 2502303SN/A// fetch.setPageTable(pTable); 2512303SN/A// iew.setPageTable(pTable); 2522292SN/A#endif 2531060SN/A 2541060SN/A // Setup the ROB for whichever stages need it. 2551060SN/A commit.setROB(&rob); 2562292SN/A 2572292SN/A lastRunningCycle = curTick; 2582292SN/A 2592292SN/A contextSwitch = false; 2601060SN/A} 2611060SN/A 2621060SN/Atemplate <class Impl> 2631755SN/AFullO3CPU<Impl>::~FullO3CPU() 2641060SN/A{ 2651060SN/A} 2661060SN/A 2671060SN/Atemplate <class Impl> 2681060SN/Avoid 2691755SN/AFullO3CPU<Impl>::fullCPURegStats() 2701062SN/A{ 2712292SN/A BaseFullCPU::regStats(); 2722292SN/A 2731062SN/A // Register any of the FullCPU's stats here. 2742292SN/A timesIdled 2752292SN/A .name(name() + ".timesIdled") 2762292SN/A .desc("Number of times that the entire CPU went into an idle state and" 2772292SN/A " unscheduled itself") 2782292SN/A .prereq(timesIdled); 2792292SN/A 2802292SN/A idleCycles 2812292SN/A .name(name() + ".idleCycles") 2822292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 2832292SN/A "to idling") 2842292SN/A .prereq(idleCycles); 2852292SN/A 2862292SN/A // Number of Instructions simulated 2872292SN/A // -------------------------------- 2882292SN/A // Should probably be in Base CPU but need templated 2892292SN/A // MaxThreads so put in here instead 2902292SN/A committedInsts 2912292SN/A .init(numThreads) 2922292SN/A .name(name() + ".committedInsts") 2932292SN/A .desc("Number of Instructions Simulated"); 2942292SN/A 2952292SN/A totalCommittedInsts 2962292SN/A .name(name() + ".committedInsts_total") 2972292SN/A .desc("Number of Instructions Simulated"); 2982292SN/A 2992292SN/A cpi 3002292SN/A .name(name() + ".cpi") 3012292SN/A .desc("CPI: Cycles Per Instruction") 3022292SN/A .precision(6); 3032292SN/A cpi = simTicks / committedInsts; 3042292SN/A 3052292SN/A totalCpi 3062292SN/A .name(name() + ".cpi_total") 3072292SN/A .desc("CPI: Total CPI of All Threads") 3082292SN/A .precision(6); 3092292SN/A totalCpi = simTicks / totalCommittedInsts; 3102292SN/A 3112292SN/A ipc 3122292SN/A .name(name() + ".ipc") 3132292SN/A .desc("IPC: Instructions Per Cycle") 3142292SN/A .precision(6); 3152292SN/A ipc = committedInsts / simTicks; 3162292SN/A 3172292SN/A totalIpc 3182292SN/A .name(name() + ".ipc_total") 3192292SN/A .desc("IPC: Total IPC of All Threads") 3202292SN/A .precision(6); 3212292SN/A totalIpc = totalCommittedInsts / simTicks; 3222292SN/A 3231062SN/A} 3241062SN/A 3251062SN/Atemplate <class Impl> 3261062SN/Avoid 3271755SN/AFullO3CPU<Impl>::tick() 3281060SN/A{ 3291755SN/A DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullO3CPU.\n"); 3301060SN/A 3312292SN/A ++numCycles; 3322292SN/A 3332325SN/A// activity = false; 3342292SN/A 3352292SN/A //Tick each of the stages 3361060SN/A fetch.tick(); 3371060SN/A 3381060SN/A decode.tick(); 3391060SN/A 3401060SN/A rename.tick(); 3411060SN/A 3421060SN/A iew.tick(); 3431060SN/A 3441060SN/A commit.tick(); 3451060SN/A 3462292SN/A#if !FULL_SYSTEM 3472292SN/A doContextSwitch(); 3482292SN/A#endif 3492292SN/A 3502292SN/A // Now advance the time buffers 3511060SN/A timeBuffer.advance(); 3521060SN/A 3531060SN/A fetchQueue.advance(); 3541060SN/A decodeQueue.advance(); 3551060SN/A renameQueue.advance(); 3561060SN/A iewQueue.advance(); 3571060SN/A 3582325SN/A activityRec.advance(); 3592292SN/A 3602292SN/A if (removeInstsThisCycle) { 3612292SN/A cleanUpRemovedInsts(); 3622292SN/A } 3632292SN/A 3642325SN/A if (!tickEvent.scheduled()) { 3652325SN/A if (_status == SwitchedOut) { 3662325SN/A // increment stat 3672325SN/A lastRunningCycle = curTick; 3682325SN/A } else if (!activityRec.active()) { 3692325SN/A lastRunningCycle = curTick; 3702325SN/A timesIdled++; 3712325SN/A } else { 3722325SN/A tickEvent.schedule(curTick + cycles(1)); 3732325SN/A } 3742292SN/A } 3752292SN/A 3762292SN/A#if !FULL_SYSTEM 3772292SN/A updateThreadPriority(); 3782292SN/A#endif 3792292SN/A 3801060SN/A} 3811060SN/A 3821060SN/Atemplate <class Impl> 3831060SN/Avoid 3841755SN/AFullO3CPU<Impl>::init() 3851060SN/A{ 3862307SN/A if (!deferRegistration) { 3872680Sktlim@umich.edu registerThreadContexts(); 3882292SN/A } 3891060SN/A 3902292SN/A // Set inSyscall so that the CPU doesn't squash when initially 3912292SN/A // setting up registers. 3922292SN/A for (int i = 0; i < number_of_threads; ++i) 3932292SN/A thread[i]->inSyscall = true; 3942292SN/A 3952292SN/A for (int tid=0; tid < number_of_threads; tid++) { 3961858SN/A#if FULL_SYSTEM 3972680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 3981681SN/A#else 3992680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 4001681SN/A#endif 4012292SN/A // Threads start in the Suspended State 4022680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 4032292SN/A continue; 4041060SN/A } 4051060SN/A 4062292SN/A#if FULL_SYSTEM 4072680Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 4082292SN/A#endif 4092292SN/A } 4102292SN/A 4112292SN/A // Clear inSyscall. 4122292SN/A for (int i = 0; i < number_of_threads; ++i) 4132292SN/A thread[i]->inSyscall = false; 4142292SN/A 4152316SN/A // Initialize stages. 4162292SN/A fetch.initStage(); 4172292SN/A iew.initStage(); 4182292SN/A rename.initStage(); 4192292SN/A commit.initStage(); 4202292SN/A 4212292SN/A commit.setThreads(thread); 4222292SN/A} 4232292SN/A 4242292SN/Atemplate <class Impl> 4252292SN/Avoid 4262292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 4272292SN/A{ 4282292SN/A DPRINTF(FullCPU,"[tid:%i] Initializing thread data"); 4292292SN/A // Will change now that the PC and thread state is internal to the CPU 4302292SN/A // and not in the CPUExecContext. 4312292SN/A#if 0 4322292SN/A#if FULL_SYSTEM 4332680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 4342292SN/A#else 4352680Sktlim@umich.edu CPUExecContext *src_tc = thread[tid]; 4362292SN/A#endif 4372292SN/A 4382292SN/A //Bind Int Regs to Rename Map 4392292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 4402292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 4412292SN/A 4422292SN/A renameMap[tid].setEntry(ireg,phys_reg); 4432292SN/A scoreboard.setReg(phys_reg); 4442292SN/A } 4452292SN/A 4462292SN/A //Bind Float Regs to Rename Map 4472292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 4482292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 4492292SN/A 4502292SN/A renameMap[tid].setEntry(freg,phys_reg); 4512292SN/A scoreboard.setReg(phys_reg); 4522292SN/A } 4532292SN/A 4542292SN/A //Copy Thread Data Into RegFile 4552680Sktlim@umich.edu this->copyFromTC(tid); 4562292SN/A 4572292SN/A //Set PC/NPC 4582680Sktlim@umich.edu regFile.pc[tid] = src_tc->readPC(); 4592680Sktlim@umich.edu regFile.npc[tid] = src_tc->readNextPC(); 4602292SN/A 4612680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 4622292SN/A 4632292SN/A activateContext(tid,1); 4642292SN/A 4652292SN/A //Reset ROB/IQ/LSQ Entries 4662292SN/A commit.rob->resetEntries(); 4672292SN/A iew.resetEntries(); 4682292SN/A#endif 4692292SN/A} 4702292SN/A 4712292SN/Atemplate <class Impl> 4722292SN/Avoid 4732292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 4742292SN/A{ 4752292SN/A DPRINTF(FullCPU,"[tid:%i] Removing thread data"); 4762292SN/A#if 0 4772292SN/A //Unbind Int Regs from Rename Map 4782292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 4792292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 4802292SN/A 4812292SN/A scoreboard.unsetReg(phys_reg); 4822292SN/A freeList.addReg(phys_reg); 4832292SN/A } 4842292SN/A 4852292SN/A //Unbind Float Regs from Rename Map 4862292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 4872292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 4882292SN/A 4892292SN/A scoreboard.unsetReg(phys_reg); 4902292SN/A freeList.addReg(phys_reg); 4912292SN/A } 4922292SN/A 4932292SN/A //Copy Thread Data From RegFile 4942292SN/A /* Fix Me: 4952292SN/A * Do we really need to do this if we are removing a thread 4962292SN/A * in the sense that it's finished (exiting)? If the thread is just 4972292SN/A * being suspended we might... 4982292SN/A */ 4992680Sktlim@umich.edu// this->copyToTC(tid); 5002292SN/A 5012292SN/A //Squash Throughout Pipeline 5022292SN/A fetch.squash(0,tid); 5032292SN/A decode.squash(tid); 5042292SN/A rename.squash(tid); 5052292SN/A 5062292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 5072292SN/A 5082292SN/A //Reset ROB/IQ/LSQ Entries 5092292SN/A if (activeThreads.size() >= 1) { 5102292SN/A commit.rob->resetEntries(); 5112292SN/A iew.resetEntries(); 5122292SN/A } 5132292SN/A#endif 5142292SN/A} 5152292SN/A 5162292SN/A 5172292SN/Atemplate <class Impl> 5182292SN/Avoid 5192292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 5202292SN/A{ 5212292SN/A DPRINTF(FullCPU,"[tid:%i]: Checking if resources are available for incoming" 5222292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 5232292SN/A tid); 5242292SN/A 5252292SN/A bool ready = true; 5262292SN/A 5272292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 5282292SN/A DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 5292292SN/A "Phys. Int. Regs.\n", 5302292SN/A tid); 5312292SN/A ready = false; 5322292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 5332292SN/A DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 5342292SN/A "Phys. Float. Regs.\n", 5352292SN/A tid); 5362292SN/A ready = false; 5372292SN/A } else if (commit.rob->numFreeEntries() >= 5382292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 5392292SN/A DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 5402292SN/A "ROB entries.\n", 5412292SN/A tid); 5422292SN/A ready = false; 5432292SN/A } else if (iew.instQueue.numFreeEntries() >= 5442292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 5452292SN/A DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 5462292SN/A "IQ entries.\n", 5472292SN/A tid); 5482292SN/A ready = false; 5492292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 5502292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 5512292SN/A DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 5522292SN/A "LSQ entries.\n", 5532292SN/A tid); 5542292SN/A ready = false; 5552292SN/A } 5562292SN/A 5572292SN/A if (ready) { 5582292SN/A insertThread(tid); 5592292SN/A 5602292SN/A contextSwitch = false; 5612292SN/A 5622292SN/A cpuWaitList.remove(tid); 5632292SN/A } else { 5642292SN/A suspendContext(tid); 5652292SN/A 5662292SN/A //blocks fetch 5672292SN/A contextSwitch = true; 5682292SN/A 5692292SN/A //do waitlist 5702292SN/A cpuWaitList.push_back(tid); 5711060SN/A } 5721060SN/A} 5731060SN/A 5741060SN/Atemplate <class Impl> 5751060SN/Avoid 5762292SN/AFullO3CPU<Impl>::activateContext(int tid, int delay) 5771060SN/A{ 5781060SN/A // Needs to set each stage to running as well. 5792292SN/A list<unsigned>::iterator isActive = find( 5802292SN/A activeThreads.begin(), activeThreads.end(), tid); 5812292SN/A 5822292SN/A if (isActive == activeThreads.end()) { 5832292SN/A //May Need to Re-code this if the delay variable is the 5842292SN/A //delay needed for thread to activate 5852292SN/A DPRINTF(FullCPU, "Adding Thread %i to active threads list\n", 5862292SN/A tid); 5872292SN/A 5882292SN/A activeThreads.push_back(tid); 5892292SN/A } 5902292SN/A 5912307SN/A assert(_status == Idle || _status == SwitchedOut); 5921060SN/A 5931060SN/A scheduleTickEvent(delay); 5941060SN/A 5952292SN/A // Be sure to signal that there's some activity so the CPU doesn't 5962292SN/A // deschedule itself. 5972325SN/A activityRec.activity(); 5982292SN/A fetch.wakeFromQuiesce(); 5992292SN/A 6001060SN/A _status = Running; 6011060SN/A} 6021060SN/A 6031060SN/Atemplate <class Impl> 6041060SN/Avoid 6052292SN/AFullO3CPU<Impl>::suspendContext(int tid) 6061060SN/A{ 6072292SN/A DPRINTF(FullCPU,"[tid: %i]: Suspended ...\n", tid); 6082292SN/A unscheduleTickEvent(); 6092292SN/A _status = Idle; 6102292SN/A/* 6112292SN/A //Remove From Active List, if Active 6122292SN/A list<unsigned>::iterator isActive = find( 6132292SN/A activeThreads.begin(), activeThreads.end(), tid); 6142292SN/A 6152292SN/A if (isActive != activeThreads.end()) { 6162292SN/A DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", 6172292SN/A tid); 6182292SN/A activeThreads.erase(isActive); 6192292SN/A } 6202292SN/A*/ 6211060SN/A} 6221060SN/A 6231060SN/Atemplate <class Impl> 6241060SN/Avoid 6252292SN/AFullO3CPU<Impl>::deallocateContext(int tid) 6261060SN/A{ 6272292SN/A DPRINTF(FullCPU,"[tid:%i]: Deallocating ...", tid); 6282292SN/A/* 6292292SN/A //Remove From Active List, if Active 6302292SN/A list<unsigned>::iterator isActive = find( 6312292SN/A activeThreads.begin(), activeThreads.end(), tid); 6322292SN/A 6332292SN/A if (isActive != activeThreads.end()) { 6342292SN/A DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", 6352292SN/A tid); 6362292SN/A activeThreads.erase(isActive); 6372292SN/A 6382292SN/A removeThread(tid); 6392292SN/A } 6402292SN/A*/ 6411060SN/A} 6421060SN/A 6431060SN/Atemplate <class Impl> 6441060SN/Avoid 6452292SN/AFullO3CPU<Impl>::haltContext(int tid) 6461060SN/A{ 6472292SN/A DPRINTF(FullCPU,"[tid:%i]: Halted ...", tid); 6482292SN/A/* 6492292SN/A //Remove From Active List, if Active 6502292SN/A list<unsigned>::iterator isActive = find( 6512292SN/A activeThreads.begin(), activeThreads.end(), tid); 6522292SN/A 6532292SN/A if (isActive != activeThreads.end()) { 6542292SN/A DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", 6552292SN/A tid); 6562292SN/A activeThreads.erase(isActive); 6572292SN/A 6582292SN/A removeThread(tid); 6592292SN/A } 6602292SN/A*/ 6611060SN/A} 6621060SN/A 6631060SN/Atemplate <class Impl> 6641060SN/Avoid 6652316SN/AFullO3CPU<Impl>::switchOut(Sampler *_sampler) 6661060SN/A{ 6672316SN/A sampler = _sampler; 6682316SN/A switchCount = 0; 6692307SN/A fetch.switchOut(); 6702307SN/A decode.switchOut(); 6712307SN/A rename.switchOut(); 6722307SN/A iew.switchOut(); 6732307SN/A commit.switchOut(); 6742325SN/A 6752325SN/A // Wake the CPU and record activity so everything can drain out if 6762325SN/A // the CPU is currently idle. 6772325SN/A wakeCPU(); 6782325SN/A activityRec.activity(); 6792316SN/A} 6802310SN/A 6812316SN/Atemplate <class Impl> 6822316SN/Avoid 6832316SN/AFullO3CPU<Impl>::signalSwitched() 6842316SN/A{ 6852325SN/A if (++switchCount == NumStages) { 6862316SN/A fetch.doSwitchOut(); 6872316SN/A rename.doSwitchOut(); 6882316SN/A commit.doSwitchOut(); 6892316SN/A instList.clear(); 6902316SN/A while (!removeList.empty()) { 6912316SN/A removeList.pop(); 6922316SN/A } 6932316SN/A 6942316SN/A if (checker) 6952316SN/A checker->switchOut(sampler); 6962316SN/A 6972316SN/A if (tickEvent.scheduled()) 6982316SN/A tickEvent.squash(); 6992316SN/A sampler->signalSwitched(); 7002316SN/A _status = SwitchedOut; 7012310SN/A } 7022316SN/A assert(switchCount <= 5); 7031060SN/A} 7041060SN/A 7051060SN/Atemplate <class Impl> 7061060SN/Avoid 7071755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 7081060SN/A{ 7092325SN/A // Flush out any old data from the time buffers. 7102325SN/A for (int i = 0; i < 10; ++i) { 7112307SN/A timeBuffer.advance(); 7122307SN/A fetchQueue.advance(); 7132307SN/A decodeQueue.advance(); 7142307SN/A renameQueue.advance(); 7152307SN/A iewQueue.advance(); 7162307SN/A } 7172307SN/A 7182325SN/A activityRec.reset(); 7192307SN/A 7201060SN/A BaseCPU::takeOverFrom(oldCPU); 7211060SN/A 7222307SN/A fetch.takeOverFrom(); 7232307SN/A decode.takeOverFrom(); 7242307SN/A rename.takeOverFrom(); 7252307SN/A iew.takeOverFrom(); 7262307SN/A commit.takeOverFrom(); 7272307SN/A 7281060SN/A assert(!tickEvent.scheduled()); 7291060SN/A 7302325SN/A // @todo: Figure out how to properly select the tid to put onto 7312325SN/A // the active threads list. 7322307SN/A int tid = 0; 7332307SN/A 7342307SN/A list<unsigned>::iterator isActive = find( 7352307SN/A activeThreads.begin(), activeThreads.end(), tid); 7362307SN/A 7372307SN/A if (isActive == activeThreads.end()) { 7382325SN/A //May Need to Re-code this if the delay variable is the delay 7392325SN/A //needed for thread to activate 7402307SN/A DPRINTF(FullCPU, "Adding Thread %i to active threads list\n", 7412307SN/A tid); 7422307SN/A 7432307SN/A activeThreads.push_back(tid); 7442307SN/A } 7452307SN/A 7462325SN/A // Set all statuses to active, schedule the CPU's tick event. 7472307SN/A // @todo: Fix up statuses so this is handled properly 7482680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 7492680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 7502680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 7511681SN/A _status = Running; 7521681SN/A tickEvent.schedule(curTick); 7531681SN/A } 7541060SN/A } 7552307SN/A if (!tickEvent.scheduled()) 7562307SN/A tickEvent.schedule(curTick); 7571060SN/A} 7581060SN/A 7591060SN/Atemplate <class Impl> 7601060SN/Auint64_t 7611755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 7621060SN/A{ 7631060SN/A return regFile.readIntReg(reg_idx); 7641060SN/A} 7651060SN/A 7661060SN/Atemplate <class Impl> 7672455SN/AFloatReg 7682455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 7691060SN/A{ 7702455SN/A return regFile.readFloatReg(reg_idx, width); 7711060SN/A} 7721060SN/A 7731060SN/Atemplate <class Impl> 7742455SN/AFloatReg 7752455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 7761060SN/A{ 7772455SN/A return regFile.readFloatReg(reg_idx); 7781060SN/A} 7791060SN/A 7801060SN/Atemplate <class Impl> 7812455SN/AFloatRegBits 7822455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 7831060SN/A{ 7842455SN/A return regFile.readFloatRegBits(reg_idx, width); 7852455SN/A} 7862455SN/A 7872455SN/Atemplate <class Impl> 7882455SN/AFloatRegBits 7892455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 7902455SN/A{ 7912455SN/A return regFile.readFloatRegBits(reg_idx); 7921060SN/A} 7931060SN/A 7941060SN/Atemplate <class Impl> 7951060SN/Avoid 7961755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 7971060SN/A{ 7981060SN/A regFile.setIntReg(reg_idx, val); 7991060SN/A} 8001060SN/A 8011060SN/Atemplate <class Impl> 8021060SN/Avoid 8032455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 8041060SN/A{ 8052455SN/A regFile.setFloatReg(reg_idx, val, width); 8061060SN/A} 8071060SN/A 8081060SN/Atemplate <class Impl> 8091060SN/Avoid 8102455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 8111060SN/A{ 8122455SN/A regFile.setFloatReg(reg_idx, val); 8131060SN/A} 8141060SN/A 8151060SN/Atemplate <class Impl> 8161060SN/Avoid 8172455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 8181060SN/A{ 8192455SN/A regFile.setFloatRegBits(reg_idx, val, width); 8202455SN/A} 8212455SN/A 8222455SN/Atemplate <class Impl> 8232455SN/Avoid 8242455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 8252455SN/A{ 8262455SN/A regFile.setFloatRegBits(reg_idx, val); 8271060SN/A} 8281060SN/A 8291060SN/Atemplate <class Impl> 8301060SN/Auint64_t 8312292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 8321060SN/A{ 8332292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8342292SN/A 8352292SN/A return regFile.readIntReg(phys_reg); 8362292SN/A} 8372292SN/A 8382292SN/Atemplate <class Impl> 8392292SN/Afloat 8402292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 8412292SN/A{ 8422307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 8432307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 8442292SN/A 8452669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 8462292SN/A} 8472292SN/A 8482292SN/Atemplate <class Impl> 8492292SN/Adouble 8502292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 8512292SN/A{ 8522307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 8532307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 8542292SN/A 8552669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 8562292SN/A} 8572292SN/A 8582292SN/Atemplate <class Impl> 8592292SN/Auint64_t 8602292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 8612292SN/A{ 8622307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 8632307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 8642292SN/A 8652669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 8661060SN/A} 8671060SN/A 8681060SN/Atemplate <class Impl> 8691060SN/Avoid 8702292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 8711060SN/A{ 8722292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8732292SN/A 8742292SN/A regFile.setIntReg(phys_reg, val); 8751060SN/A} 8761060SN/A 8771060SN/Atemplate <class Impl> 8781060SN/Avoid 8792292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 8801060SN/A{ 8812292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8822292SN/A 8832669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 8841060SN/A} 8851060SN/A 8861060SN/Atemplate <class Impl> 8871060SN/Avoid 8882292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 8891060SN/A{ 8902292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8912292SN/A 8922669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 8931060SN/A} 8941060SN/A 8951060SN/Atemplate <class Impl> 8961060SN/Avoid 8972292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 8981060SN/A{ 8992292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 9001060SN/A 9012669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 9022292SN/A} 9032292SN/A 9042292SN/Atemplate <class Impl> 9052292SN/Auint64_t 9062292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 9072292SN/A{ 9082292SN/A return commit.readPC(tid); 9091060SN/A} 9101060SN/A 9111060SN/Atemplate <class Impl> 9121060SN/Avoid 9132292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 9141060SN/A{ 9152292SN/A commit.setPC(new_PC, tid); 9162292SN/A} 9171060SN/A 9182292SN/Atemplate <class Impl> 9192292SN/Auint64_t 9202292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 9212292SN/A{ 9222292SN/A return commit.readNextPC(tid); 9232292SN/A} 9241060SN/A 9252292SN/Atemplate <class Impl> 9262292SN/Avoid 9272292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 9282292SN/A{ 9292292SN/A commit.setNextPC(val, tid); 9302292SN/A} 9311060SN/A 9322292SN/Atemplate <class Impl> 9332292SN/Atypename FullO3CPU<Impl>::ListIt 9342292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 9352292SN/A{ 9362292SN/A instList.push_back(inst); 9371060SN/A 9382292SN/A return --(instList.end()); 9392292SN/A} 9401060SN/A 9412292SN/Atemplate <class Impl> 9422292SN/Avoid 9432292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 9442292SN/A{ 9452292SN/A // Keep an instruction count. 9462292SN/A thread[tid]->numInst++; 9472292SN/A thread[tid]->numInsts++; 9482292SN/A committedInsts[tid]++; 9492292SN/A totalCommittedInsts++; 9502292SN/A 9512292SN/A // Check for instruction-count-based events. 9522292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 9532292SN/A} 9542292SN/A 9552292SN/Atemplate <class Impl> 9562292SN/Avoid 9572292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 9582292SN/A{ 9592292SN/A removeInstsThisCycle = true; 9602292SN/A 9612292SN/A removeList.push(inst->getInstListIt()); 9621060SN/A} 9631060SN/A 9641060SN/Atemplate <class Impl> 9651060SN/Avoid 9661755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 9671060SN/A{ 9682292SN/A DPRINTF(FullCPU, "FullCPU: Removing committed instruction [tid:%i] PC %#x " 9692292SN/A "[sn:%lli]\n", 9702303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 9711060SN/A 9722292SN/A removeInstsThisCycle = true; 9731060SN/A 9741060SN/A // Remove the front instruction. 9752292SN/A removeList.push(inst->getInstListIt()); 9761060SN/A} 9771060SN/A 9781060SN/Atemplate <class Impl> 9791060SN/Avoid 9802292SN/AFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 9811060SN/A{ 9822292SN/A DPRINTF(FullCPU, "FullCPU: Thread %i: Deleting instructions from instruction" 9832292SN/A " list.\n", tid); 9841060SN/A 9852292SN/A ListIt end_it; 9861060SN/A 9872292SN/A bool rob_empty = false; 9882292SN/A 9892292SN/A if (instList.empty()) { 9902292SN/A return; 9912292SN/A } else if (rob.isEmpty(/*tid*/)) { 9922292SN/A DPRINTF(FullCPU, "FullCPU: ROB is empty, squashing all insts.\n"); 9932292SN/A end_it = instList.begin(); 9942292SN/A rob_empty = true; 9952292SN/A } else { 9962292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 9972292SN/A DPRINTF(FullCPU, "FullCPU: ROB is not empty, squashing insts not in ROB.\n"); 9982292SN/A } 9992292SN/A 10002292SN/A removeInstsThisCycle = true; 10012292SN/A 10022292SN/A ListIt inst_it = instList.end(); 10032292SN/A 10042292SN/A inst_it--; 10052292SN/A 10062292SN/A // Walk through the instruction list, removing any instructions 10072292SN/A // that were inserted after the given instruction iterator, end_it. 10082292SN/A while (inst_it != end_it) { 10092292SN/A assert(!instList.empty()); 10102292SN/A 10112292SN/A squashInstIt(inst_it, tid); 10122292SN/A 10132292SN/A inst_it--; 10142292SN/A } 10152292SN/A 10162292SN/A // If the ROB was empty, then we actually need to remove the first 10172292SN/A // instruction as well. 10182292SN/A if (rob_empty) { 10192292SN/A squashInstIt(inst_it, tid); 10202292SN/A } 10211060SN/A} 10221060SN/A 10231060SN/Atemplate <class Impl> 10241060SN/Avoid 10252292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 10262292SN/A unsigned tid) 10271062SN/A{ 10282292SN/A assert(!instList.empty()); 10292292SN/A 10302292SN/A removeInstsThisCycle = true; 10312292SN/A 10322292SN/A ListIt inst_iter = instList.end(); 10332292SN/A 10342292SN/A inst_iter--; 10352292SN/A 10361062SN/A DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction " 10372292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 10382292SN/A tid, seq_num, (*inst_iter)->seqNum); 10391062SN/A 10402292SN/A while ((*inst_iter)->seqNum > seq_num) { 10411062SN/A 10422292SN/A bool break_loop = (inst_iter == instList.begin()); 10431062SN/A 10442292SN/A squashInstIt(inst_iter, tid); 10451062SN/A 10462292SN/A inst_iter--; 10471062SN/A 10482292SN/A if (break_loop) 10492292SN/A break; 10502292SN/A } 10512292SN/A} 10522292SN/A 10532292SN/Atemplate <class Impl> 10542292SN/Ainline void 10552292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 10562292SN/A{ 10572292SN/A if ((*instIt)->threadNumber == tid) { 10582292SN/A DPRINTF(FullCPU, "FullCPU: Squashing instruction, " 10592292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 10602292SN/A (*instIt)->threadNumber, 10612292SN/A (*instIt)->seqNum, 10622292SN/A (*instIt)->readPC()); 10631062SN/A 10641062SN/A // Mark it as squashed. 10652292SN/A (*instIt)->setSquashed(); 10662292SN/A 10672325SN/A // @todo: Formulate a consistent method for deleting 10682325SN/A // instructions from the instruction list 10692292SN/A // Remove the instruction from the list. 10702292SN/A removeList.push(instIt); 10712292SN/A } 10722292SN/A} 10732292SN/A 10742292SN/Atemplate <class Impl> 10752292SN/Avoid 10762292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 10772292SN/A{ 10782292SN/A while (!removeList.empty()) { 10792292SN/A DPRINTF(FullCPU, "FullCPU: Removing instruction, " 10802292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 10812292SN/A (*removeList.front())->threadNumber, 10822292SN/A (*removeList.front())->seqNum, 10832292SN/A (*removeList.front())->readPC()); 10842292SN/A 10852292SN/A instList.erase(removeList.front()); 10862292SN/A 10872292SN/A removeList.pop(); 10881062SN/A } 10891062SN/A 10902292SN/A removeInstsThisCycle = false; 10911062SN/A} 10922325SN/A/* 10931062SN/Atemplate <class Impl> 10941062SN/Avoid 10951755SN/AFullO3CPU<Impl>::removeAllInsts() 10961060SN/A{ 10971060SN/A instList.clear(); 10981060SN/A} 10992325SN/A*/ 11001060SN/Atemplate <class Impl> 11011060SN/Avoid 11021755SN/AFullO3CPU<Impl>::dumpInsts() 11031060SN/A{ 11041060SN/A int num = 0; 11051060SN/A 11062292SN/A ListIt inst_list_it = instList.begin(); 11072292SN/A 11082292SN/A cprintf("Dumping Instruction List\n"); 11092292SN/A 11102292SN/A while (inst_list_it != instList.end()) { 11112292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 11122292SN/A "Squashed:%i\n\n", 11132292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 11142292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 11152292SN/A (*inst_list_it)->isSquashed()); 11161060SN/A inst_list_it++; 11171060SN/A ++num; 11181060SN/A } 11191060SN/A} 11202325SN/A/* 11211060SN/Atemplate <class Impl> 11221060SN/Avoid 11231755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 11241060SN/A{ 11251060SN/A iew.wakeDependents(inst); 11261060SN/A} 11272325SN/A*/ 11282292SN/Atemplate <class Impl> 11292292SN/Avoid 11302292SN/AFullO3CPU<Impl>::wakeCPU() 11312292SN/A{ 11322325SN/A if (activityRec.active() || tickEvent.scheduled()) { 11332325SN/A DPRINTF(Activity, "CPU already running.\n"); 11342292SN/A return; 11352292SN/A } 11362292SN/A 11372325SN/A DPRINTF(Activity, "Waking up CPU\n"); 11382325SN/A 11392325SN/A idleCycles += (curTick - 1) - lastRunningCycle; 11402292SN/A 11412292SN/A tickEvent.schedule(curTick); 11422292SN/A} 11432292SN/A 11442292SN/Atemplate <class Impl> 11452292SN/Aint 11462292SN/AFullO3CPU<Impl>::getFreeTid() 11472292SN/A{ 11482292SN/A for (int i=0; i < numThreads; i++) { 11492292SN/A if (!tids[i]) { 11502292SN/A tids[i] = true; 11512292SN/A return i; 11522292SN/A } 11532292SN/A } 11542292SN/A 11552292SN/A return -1; 11562292SN/A} 11572292SN/A 11582292SN/Atemplate <class Impl> 11592292SN/Avoid 11602292SN/AFullO3CPU<Impl>::doContextSwitch() 11612292SN/A{ 11622292SN/A if (contextSwitch) { 11632292SN/A 11642292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 11652292SN/A 11662292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 11672292SN/A activateWhenReady(tid); 11682292SN/A } 11692292SN/A 11702292SN/A if (cpuWaitList.size() == 0) 11712292SN/A contextSwitch = true; 11722292SN/A } 11732292SN/A} 11742292SN/A 11752292SN/Atemplate <class Impl> 11762292SN/Avoid 11772292SN/AFullO3CPU<Impl>::updateThreadPriority() 11782292SN/A{ 11792292SN/A if (activeThreads.size() > 1) 11802292SN/A { 11812292SN/A //DEFAULT TO ROUND ROBIN SCHEME 11822292SN/A //e.g. Move highest priority to end of thread list 11832292SN/A list<unsigned>::iterator list_begin = activeThreads.begin(); 11842292SN/A list<unsigned>::iterator list_end = activeThreads.end(); 11852292SN/A 11862292SN/A unsigned high_thread = *list_begin; 11872292SN/A 11882292SN/A activeThreads.erase(list_begin); 11892292SN/A 11902292SN/A activeThreads.push_back(high_thread); 11912292SN/A } 11922292SN/A} 11931060SN/A 11941755SN/A// Forward declaration of FullO3CPU. 11951755SN/Atemplate class FullO3CPU<AlphaSimpleImpl>; 1196