cpu.cc revision 2665
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311858SN/A#include "config/full_system.hh" 321858SN/A 331858SN/A#if FULL_SYSTEM 341060SN/A#include "sim/system.hh" 351060SN/A#else 361060SN/A#include "sim/process.hh" 371060SN/A#endif 381696SN/A#include "sim/root.hh" 391060SN/A 402190SN/A#include "cpu/cpu_exec_context.hh" 412190SN/A#include "cpu/exec_context.hh" 421717SN/A#include "cpu/o3/alpha_dyn_inst.hh" 431717SN/A#include "cpu/o3/alpha_impl.hh" 441717SN/A#include "cpu/o3/cpu.hh" 451060SN/A 461060SN/Ausing namespace std; 471060SN/A 481061SN/ABaseFullCPU::BaseFullCPU(Params ¶ms) 491681SN/A : BaseCPU(¶ms), cpu_id(0) 501060SN/A{ 511060SN/A} 521060SN/A 531060SN/Atemplate <class Impl> 541755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 551060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 561060SN/A{ 571060SN/A} 581060SN/A 591060SN/Atemplate <class Impl> 601060SN/Avoid 611755SN/AFullO3CPU<Impl>::TickEvent::process() 621060SN/A{ 631060SN/A cpu->tick(); 641060SN/A} 651060SN/A 661060SN/Atemplate <class Impl> 671060SN/Aconst char * 681755SN/AFullO3CPU<Impl>::TickEvent::description() 691060SN/A{ 701755SN/A return "FullO3CPU tick event"; 711060SN/A} 721060SN/A 731060SN/A//Call constructor to all the pipeline stages here 741060SN/Atemplate <class Impl> 751755SN/AFullO3CPU<Impl>::FullO3CPU(Params ¶ms) 761858SN/A#if FULL_SYSTEM 771061SN/A : BaseFullCPU(params), 781060SN/A#else 791061SN/A : BaseFullCPU(params), 801060SN/A#endif // FULL_SYSTEM 811060SN/A tickEvent(this), 821060SN/A fetch(params), 831060SN/A decode(params), 841060SN/A rename(params), 851060SN/A iew(params), 861060SN/A commit(params), 871060SN/A 881060SN/A regFile(params.numPhysIntRegs, params.numPhysFloatRegs), 891060SN/A 902107SN/A freeList(TheISA::NumIntRegs, params.numPhysIntRegs, 912107SN/A TheISA::NumFloatRegs, params.numPhysFloatRegs), 921060SN/A 932107SN/A renameMap(TheISA::NumIntRegs, params.numPhysIntRegs, 942107SN/A TheISA::NumFloatRegs, params.numPhysFloatRegs, 952107SN/A TheISA::NumMiscRegs, 962107SN/A TheISA::ZeroReg, 972107SN/A TheISA::ZeroReg + TheISA::NumIntRegs), 981060SN/A 991060SN/A rob(params.numROBEntries, params.squashWidth), 1001060SN/A 1011060SN/A // What to pass to these time buffers? 1021060SN/A // For now just have these time buffers be pretty big. 1031061SN/A timeBuffer(5, 5), 1041061SN/A fetchQueue(5, 5), 1051061SN/A decodeQueue(5, 5), 1061061SN/A renameQueue(5, 5), 1071061SN/A iewQueue(5, 5), 1081060SN/A 1092190SN/A cpuXC(NULL), 1101060SN/A 1111060SN/A globalSeqNum(1), 1121060SN/A 1131858SN/A#if FULL_SYSTEM 1141060SN/A system(params.system), 1151681SN/A memCtrl(system->memctrl), 1161060SN/A physmem(system->physmem), 1171060SN/A itb(params.itb), 1181060SN/A dtb(params.dtb), 1191060SN/A mem(params.mem), 1201060SN/A#else 1211681SN/A // Hardcoded for a single thread!! 1221681SN/A mem(params.workload[0]->getMemory()), 1231060SN/A#endif // FULL_SYSTEM 1241060SN/A 1251060SN/A icacheInterface(params.icacheInterface), 1261060SN/A dcacheInterface(params.dcacheInterface), 1271060SN/A deferRegistration(params.defReg), 1281060SN/A numInsts(0), 1291060SN/A funcExeInst(0) 1301060SN/A{ 1311060SN/A _status = Idle; 1321681SN/A 1331858SN/A#if !FULL_SYSTEM 1341681SN/A thread.resize(this->number_of_threads); 1351681SN/A#endif 1361681SN/A 1371681SN/A for (int i = 0; i < this->number_of_threads; ++i) { 1381858SN/A#if FULL_SYSTEM 1391681SN/A assert(i == 0); 1402190SN/A thread[i] = new CPUExecContext(this, 0, system, itb, dtb, mem); 1412190SN/A system->execContexts[i] = thread[i]->getProxy(); 1421060SN/A 1431681SN/A execContexts.push_back(system->execContexts[i]); 1441060SN/A#else 1451681SN/A if (i < params.workload.size()) { 1461681SN/A DPRINTF(FullCPU, "FullCPU: Workload[%i]'s starting PC is %#x, " 1471681SN/A "process is %#x", 1481681SN/A i, params.workload[i]->prog_entry, thread[i]); 1492190SN/A thread[i] = new CPUExecContext(this, i, params.workload[i], i); 1501681SN/A } 1511681SN/A assert(params.workload[i]->getMemory() != NULL); 1521681SN/A assert(mem != NULL); 1532190SN/A execContexts.push_back(thread[i]->getProxy()); 1541681SN/A#endif // !FULL_SYSTEM 1551681SN/A } 1561060SN/A 1571681SN/A // Note that this is a hack so that my code which still uses xc-> will 1581681SN/A // still work. I should remove this eventually 1592190SN/A cpuXC = thread[0]; 1601060SN/A 1611060SN/A // The stages also need their CPU pointer setup. However this must be 1621060SN/A // done at the upper level CPU because they have pointers to the upper 1631755SN/A // level CPU, and not this FullO3CPU. 1641060SN/A 1651060SN/A // Give each of the stages the time buffer they will use. 1661060SN/A fetch.setTimeBuffer(&timeBuffer); 1671060SN/A decode.setTimeBuffer(&timeBuffer); 1681060SN/A rename.setTimeBuffer(&timeBuffer); 1691060SN/A iew.setTimeBuffer(&timeBuffer); 1701060SN/A commit.setTimeBuffer(&timeBuffer); 1711060SN/A 1721060SN/A // Also setup each of the stages' queues. 1731060SN/A fetch.setFetchQueue(&fetchQueue); 1741060SN/A decode.setFetchQueue(&fetchQueue); 1751060SN/A decode.setDecodeQueue(&decodeQueue); 1761060SN/A rename.setDecodeQueue(&decodeQueue); 1771060SN/A rename.setRenameQueue(&renameQueue); 1781060SN/A iew.setRenameQueue(&renameQueue); 1791060SN/A iew.setIEWQueue(&iewQueue); 1801060SN/A commit.setIEWQueue(&iewQueue); 1811060SN/A commit.setRenameQueue(&renameQueue); 1821060SN/A 1831060SN/A // Setup the rename map for whichever stages need it. 1841060SN/A rename.setRenameMap(&renameMap); 1851060SN/A iew.setRenameMap(&renameMap); 1861060SN/A 1871060SN/A // Setup the free list for whichever stages need it. 1881060SN/A rename.setFreeList(&freeList); 1891060SN/A renameMap.setFreeList(&freeList); 1901060SN/A 1911060SN/A // Setup the ROB for whichever stages need it. 1921060SN/A commit.setROB(&rob); 1931060SN/A} 1941060SN/A 1951060SN/Atemplate <class Impl> 1961755SN/AFullO3CPU<Impl>::~FullO3CPU() 1971060SN/A{ 1981060SN/A} 1991060SN/A 2001060SN/Atemplate <class Impl> 2011060SN/Avoid 2021755SN/AFullO3CPU<Impl>::fullCPURegStats() 2031062SN/A{ 2041062SN/A // Register any of the FullCPU's stats here. 2051062SN/A} 2061062SN/A 2071062SN/Atemplate <class Impl> 2081062SN/Avoid 2091755SN/AFullO3CPU<Impl>::tick() 2101060SN/A{ 2111755SN/A DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullO3CPU.\n"); 2121060SN/A 2131060SN/A //Tick each of the stages if they're actually running. 2141060SN/A //Will want to figure out a way to unschedule itself if they're all 2151060SN/A //going to be idle for a long time. 2161060SN/A fetch.tick(); 2171060SN/A 2181060SN/A decode.tick(); 2191060SN/A 2201060SN/A rename.tick(); 2211060SN/A 2221060SN/A iew.tick(); 2231060SN/A 2241060SN/A commit.tick(); 2251060SN/A 2261060SN/A // Now advance the time buffers, unless the stage is stalled. 2271060SN/A timeBuffer.advance(); 2281060SN/A 2291060SN/A fetchQueue.advance(); 2301060SN/A decodeQueue.advance(); 2311060SN/A renameQueue.advance(); 2321060SN/A iewQueue.advance(); 2331060SN/A 2341060SN/A if (_status == Running && !tickEvent.scheduled()) 2351060SN/A tickEvent.schedule(curTick + 1); 2361060SN/A} 2371060SN/A 2381060SN/Atemplate <class Impl> 2391060SN/Avoid 2401755SN/AFullO3CPU<Impl>::init() 2411060SN/A{ 2421060SN/A if(!deferRegistration) 2431060SN/A { 2441060SN/A this->registerExecContexts(); 2451060SN/A 2461060SN/A // Need to do a copy of the xc->regs into the CPU's regfile so 2471060SN/A // that it can start properly. 2481858SN/A#if FULL_SYSTEM 2491681SN/A ExecContext *src_xc = system->execContexts[0]; 2502190SN/A TheISA::initCPU(src_xc, src_xc->readCpuId()); 2511681SN/A#else 2522190SN/A ExecContext *src_xc = thread[0]->getProxy(); 2531681SN/A#endif 2541060SN/A // First loop through the integer registers. 2552107SN/A for (int i = 0; i < TheISA::NumIntRegs; ++i) 2561060SN/A { 2572190SN/A regFile.intRegFile[i] = src_xc->readIntReg(i); 2581060SN/A } 2591060SN/A 2601060SN/A // Then loop through the floating point registers. 2612107SN/A for (int i = 0; i < TheISA::NumFloatRegs; ++i) 2621060SN/A { 2632455SN/A regFile.floatRegFile.setRegBits(i, src_xc->readRegBits(i)) 2641060SN/A } 2652159SN/A/* 2661060SN/A // Then loop through the misc registers. 2671681SN/A regFile.miscRegs.fpcr = src_xc->regs.miscRegs.fpcr; 2681681SN/A regFile.miscRegs.uniq = src_xc->regs.miscRegs.uniq; 2691681SN/A regFile.miscRegs.lock_flag = src_xc->regs.miscRegs.lock_flag; 2701681SN/A regFile.miscRegs.lock_addr = src_xc->regs.miscRegs.lock_addr; 2712159SN/A*/ 2721060SN/A // Then finally set the PC and the next PC. 2732190SN/A regFile.pc = src_xc->readPC(); 2742190SN/A regFile.npc = src_xc->readNextPC(); 2751060SN/A } 2761060SN/A} 2771060SN/A 2781060SN/Atemplate <class Impl> 2791060SN/Avoid 2801755SN/AFullO3CPU<Impl>::activateContext(int thread_num, int delay) 2811060SN/A{ 2821060SN/A // Needs to set each stage to running as well. 2831060SN/A 2841060SN/A scheduleTickEvent(delay); 2851060SN/A 2861060SN/A _status = Running; 2871060SN/A} 2881060SN/A 2891060SN/Atemplate <class Impl> 2901060SN/Avoid 2911755SN/AFullO3CPU<Impl>::suspendContext(int thread_num) 2921060SN/A{ 2931060SN/A panic("suspendContext unimplemented!"); 2941060SN/A} 2951060SN/A 2961060SN/Atemplate <class Impl> 2971060SN/Avoid 2981755SN/AFullO3CPU<Impl>::deallocateContext(int thread_num) 2991060SN/A{ 3001060SN/A panic("deallocateContext unimplemented!"); 3011060SN/A} 3021060SN/A 3031060SN/Atemplate <class Impl> 3041060SN/Avoid 3051755SN/AFullO3CPU<Impl>::haltContext(int thread_num) 3061060SN/A{ 3071060SN/A panic("haltContext unimplemented!"); 3081060SN/A} 3091060SN/A 3101060SN/Atemplate <class Impl> 3111060SN/Avoid 3121755SN/AFullO3CPU<Impl>::switchOut() 3131060SN/A{ 3141755SN/A panic("FullO3CPU does not have a switch out function.\n"); 3151060SN/A} 3161060SN/A 3171060SN/Atemplate <class Impl> 3181060SN/Avoid 3191755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 3201060SN/A{ 3211060SN/A BaseCPU::takeOverFrom(oldCPU); 3221060SN/A 3231060SN/A assert(!tickEvent.scheduled()); 3241060SN/A 3251060SN/A // Set all status's to active, schedule the 3261060SN/A // CPU's tick event. 3271060SN/A for (int i = 0; i < execContexts.size(); ++i) { 3281681SN/A ExecContext *xc = execContexts[i]; 3291681SN/A if (xc->status() == ExecContext::Active && _status != Running) { 3301681SN/A _status = Running; 3311681SN/A tickEvent.schedule(curTick); 3321681SN/A } 3331060SN/A } 3341060SN/A} 3351060SN/A 3361060SN/Atemplate <class Impl> 3371060SN/AInstSeqNum 3381755SN/AFullO3CPU<Impl>::getAndIncrementInstSeq() 3391060SN/A{ 3401060SN/A // Hopefully this works right. 3411060SN/A return globalSeqNum++; 3421060SN/A} 3431060SN/A 3441060SN/Atemplate <class Impl> 3451060SN/Auint64_t 3461755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 3471060SN/A{ 3481060SN/A return regFile.readIntReg(reg_idx); 3491060SN/A} 3501060SN/A 3511060SN/Atemplate <class Impl> 3522455SN/AFloatReg 3532455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 3541060SN/A{ 3552455SN/A return regFile.readFloatReg(reg_idx, width); 3561060SN/A} 3571060SN/A 3581060SN/Atemplate <class Impl> 3592455SN/AFloatReg 3602455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 3611060SN/A{ 3622455SN/A return regFile.readFloatReg(reg_idx); 3631060SN/A} 3641060SN/A 3651060SN/Atemplate <class Impl> 3662455SN/AFloatRegBits 3672455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 3681060SN/A{ 3692455SN/A return regFile.readFloatRegBits(reg_idx, width); 3702455SN/A} 3712455SN/A 3722455SN/Atemplate <class Impl> 3732455SN/AFloatRegBits 3742455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 3752455SN/A{ 3762455SN/A return regFile.readFloatRegBits(reg_idx); 3771060SN/A} 3781060SN/A 3791060SN/Atemplate <class Impl> 3801060SN/Avoid 3811755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 3821060SN/A{ 3831060SN/A regFile.setIntReg(reg_idx, val); 3841060SN/A} 3851060SN/A 3861060SN/Atemplate <class Impl> 3871060SN/Avoid 3882455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 3891060SN/A{ 3902455SN/A regFile.setFloatReg(reg_idx, val, width); 3911060SN/A} 3921060SN/A 3931060SN/Atemplate <class Impl> 3941060SN/Avoid 3952455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 3961060SN/A{ 3972455SN/A regFile.setFloatReg(reg_idx, val); 3981060SN/A} 3991060SN/A 4001060SN/Atemplate <class Impl> 4011060SN/Avoid 4022455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 4031060SN/A{ 4042455SN/A regFile.setFloatRegBits(reg_idx, val, width); 4052455SN/A} 4062455SN/A 4072455SN/Atemplate <class Impl> 4082455SN/Avoid 4092455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 4102455SN/A{ 4112455SN/A regFile.setFloatRegBits(reg_idx, val); 4121060SN/A} 4131060SN/A 4141060SN/Atemplate <class Impl> 4151060SN/Auint64_t 4161755SN/AFullO3CPU<Impl>::readPC() 4171060SN/A{ 4181060SN/A return regFile.readPC(); 4191060SN/A} 4201060SN/A 4211060SN/Atemplate <class Impl> 4221060SN/Avoid 4231755SN/AFullO3CPU<Impl>::setNextPC(uint64_t val) 4241060SN/A{ 4251060SN/A regFile.setNextPC(val); 4261060SN/A} 4271060SN/A 4281060SN/Atemplate <class Impl> 4291060SN/Avoid 4301755SN/AFullO3CPU<Impl>::setPC(Addr new_PC) 4311060SN/A{ 4321060SN/A regFile.setPC(new_PC); 4331060SN/A} 4341060SN/A 4351060SN/Atemplate <class Impl> 4361060SN/Avoid 4371755SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 4381060SN/A{ 4391060SN/A instList.push_back(inst); 4401060SN/A} 4411060SN/A 4421060SN/Atemplate <class Impl> 4431060SN/Avoid 4441755SN/AFullO3CPU<Impl>::instDone() 4451060SN/A{ 4461060SN/A // Keep an instruction count. 4471060SN/A numInsts++; 4481060SN/A 4491060SN/A // Check for instruction-count-based events. 4501060SN/A comInstEventQueue[0]->serviceEvents(numInsts); 4511060SN/A} 4521060SN/A 4531060SN/Atemplate <class Impl> 4541060SN/Avoid 4551755SN/AFullO3CPU<Impl>::removeBackInst(DynInstPtr &inst) 4561060SN/A{ 4571061SN/A DynInstPtr inst_to_delete; 4581060SN/A 4591060SN/A // Walk through the instruction list, removing any instructions 4601060SN/A // that were inserted after the given instruction, inst. 4611060SN/A while (instList.back() != inst) 4621060SN/A { 4631060SN/A assert(!instList.empty()); 4641060SN/A 4651060SN/A // Obtain the pointer to the instruction. 4661060SN/A inst_to_delete = instList.back(); 4671060SN/A 4681061SN/A DPRINTF(FullCPU, "FullCPU: Removing instruction %i, PC %#x\n", 4691061SN/A inst_to_delete->seqNum, inst_to_delete->readPC()); 4701060SN/A 4711060SN/A // Remove the instruction from the list. 4721060SN/A instList.pop_back(); 4731060SN/A 4741061SN/A // Mark it as squashed. 4751061SN/A inst_to_delete->setSquashed(); 4761060SN/A } 4771060SN/A} 4781060SN/A 4791060SN/Atemplate <class Impl> 4801060SN/Avoid 4811755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 4821060SN/A{ 4831062SN/A DynInstPtr inst_to_remove; 4841060SN/A 4851062SN/A // The front instruction should be the same one being asked to be removed. 4861060SN/A assert(instList.front() == inst); 4871060SN/A 4881060SN/A // Remove the front instruction. 4891062SN/A inst_to_remove = inst; 4901060SN/A instList.pop_front(); 4911060SN/A 4921062SN/A DPRINTF(FullCPU, "FullCPU: Removing committed instruction %#x, PC %#x\n", 4931062SN/A inst_to_remove, inst_to_remove->readPC()); 4941060SN/A} 4951060SN/A 4961060SN/Atemplate <class Impl> 4971060SN/Avoid 4981755SN/AFullO3CPU<Impl>::removeInstsNotInROB() 4991060SN/A{ 5001060SN/A DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction " 5011060SN/A "list.\n"); 5021060SN/A 5031061SN/A DynInstPtr rob_tail = rob.readTailInst(); 5041060SN/A 5051060SN/A removeBackInst(rob_tail); 5061060SN/A} 5071060SN/A 5081060SN/Atemplate <class Impl> 5091060SN/Avoid 5101755SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num) 5111062SN/A{ 5121062SN/A DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction " 5131062SN/A "list.\n"); 5141062SN/A 5151062SN/A DynInstPtr inst_to_delete; 5161062SN/A 5171062SN/A while (instList.back()->seqNum > seq_num) { 5181062SN/A assert(!instList.empty()); 5191062SN/A 5201062SN/A // Obtain the pointer to the instruction. 5211062SN/A inst_to_delete = instList.back(); 5221062SN/A 5231062SN/A DPRINTF(FullCPU, "FullCPU: Removing instruction %i, PC %#x\n", 5241062SN/A inst_to_delete->seqNum, inst_to_delete->readPC()); 5251062SN/A 5261062SN/A // Remove the instruction from the list. 5271681SN/A instList.back() = NULL; 5281062SN/A instList.pop_back(); 5291062SN/A 5301062SN/A // Mark it as squashed. 5311062SN/A inst_to_delete->setSquashed(); 5321062SN/A } 5331062SN/A 5341062SN/A} 5351062SN/A 5361062SN/Atemplate <class Impl> 5371062SN/Avoid 5381755SN/AFullO3CPU<Impl>::removeAllInsts() 5391060SN/A{ 5401060SN/A instList.clear(); 5411060SN/A} 5421060SN/A 5431060SN/Atemplate <class Impl> 5441060SN/Avoid 5451755SN/AFullO3CPU<Impl>::dumpInsts() 5461060SN/A{ 5471060SN/A int num = 0; 5481061SN/A typename list<DynInstPtr>::iterator inst_list_it = instList.begin(); 5491060SN/A 5501060SN/A while (inst_list_it != instList.end()) 5511060SN/A { 5521061SN/A cprintf("Instruction:%i\nPC:%#x\nSN:%lli\nIssued:%i\nSquashed:%i\n\n", 5531061SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->seqNum, 5541061SN/A (*inst_list_it)->isIssued(), (*inst_list_it)->isSquashed()); 5551060SN/A inst_list_it++; 5561060SN/A ++num; 5571060SN/A } 5581060SN/A} 5591060SN/A 5601060SN/Atemplate <class Impl> 5611060SN/Avoid 5621755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 5631060SN/A{ 5641060SN/A iew.wakeDependents(inst); 5651060SN/A} 5661060SN/A 5671755SN/A// Forward declaration of FullO3CPU. 5681755SN/Atemplate class FullO3CPU<AlphaSimpleImpl>; 569