cpu.cc revision 14085
11689SN/A/* 213601Sgiacomo.travaglini@arm.com * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019 ARM Limited 39916Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 152325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 167897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432756Sksewell@umich.edu * Korey Sewell 447897Shestness@cs.utexas.edu * Rick Strong 451689SN/A */ 461689SN/A 4711793Sbrandon.potter@amd.com#include "cpu/o3/cpu.hh" 4811793Sbrandon.potter@amd.com 4912109SRekai.GonzalezAlberquilla@arm.com#include "arch/generic/traits.hh" 508779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 516658Snate@binkert.org#include "config/the_isa.hh" 5211793Sbrandon.potter@amd.com#include "cpu/activity.hh" 538887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 548887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 558229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 568229Snate@binkert.org#include "cpu/o3/thread_context.hh" 578779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 584762Snate@binkert.org#include "cpu/simple_thread.hh" 594762Snate@binkert.org#include "cpu/thread_context.hh" 608232Snate@binkert.org#include "debug/Activity.hh" 619152Satgutier@umich.edu#include "debug/Drain.hh" 628232Snate@binkert.org#include "debug/O3CPU.hh" 638232Snate@binkert.org#include "debug/Quiesce.hh" 644762Snate@binkert.org#include "enums/MemoryMode.hh" 654762Snate@binkert.org#include "sim/core.hh" 668793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 678779Sgblack@eecs.umich.edu#include "sim/process.hh" 684762Snate@binkert.org#include "sim/stat_control.hh" 698460SAli.Saidi@ARM.com#include "sim/system.hh" 704762Snate@binkert.org 715702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 725702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 738232Snate@binkert.org#include "debug/Activity.hh" 7411793Sbrandon.potter@amd.com 755702Ssaidi@eecs.umich.edu#endif 765702Ssaidi@eecs.umich.edu 778737Skoansin.tan@gmail.comstruct BaseCPUParams; 785529Snate@binkert.org 792669Sktlim@umich.eduusing namespace TheISA; 806221Snate@binkert.orgusing namespace std; 811060SN/A 825529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 835712Shsul@eecs.umich.edu : BaseCPU(params) 841060SN/A{ 851060SN/A} 861060SN/A 872292SN/Avoid 882733Sktlim@umich.eduBaseO3CPU::regStats() 892292SN/A{ 902292SN/A BaseCPU::regStats(); 912292SN/A} 922292SN/A 938707Sandreas.hansson@arm.comtemplate<class Impl> 948707Sandreas.hansson@arm.combool 958975Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 968707Sandreas.hansson@arm.com{ 978707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 9811284Sandreas.hansson@arm.com // We shouldn't ever get a cacheable block in Modified state 9910821Sandreas.hansson@arm.com assert(pkt->req->isUncacheable() || 10011284Sandreas.hansson@arm.com !(pkt->cacheResponding() && !pkt->hasSharers())); 1018948Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 1028707Sandreas.hansson@arm.com 1038707Sandreas.hansson@arm.com return true; 1048707Sandreas.hansson@arm.com} 1058707Sandreas.hansson@arm.com 1068707Sandreas.hansson@arm.comtemplate<class Impl> 1078707Sandreas.hansson@arm.comvoid 10810713Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvReqRetry() 1098707Sandreas.hansson@arm.com{ 11010713Sandreas.hansson@arm.com fetch->recvReqRetry(); 1118707Sandreas.hansson@arm.com} 1128707Sandreas.hansson@arm.com 1138707Sandreas.hansson@arm.comtemplate <class Impl> 1148707Sandreas.hansson@arm.combool 1158975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 1168707Sandreas.hansson@arm.com{ 1178975Sandreas.hansson@arm.com return lsq->recvTimingResp(pkt); 1188707Sandreas.hansson@arm.com} 1198707Sandreas.hansson@arm.com 1208707Sandreas.hansson@arm.comtemplate <class Impl> 1218975Sandreas.hansson@arm.comvoid 1228975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 1238948Sandreas.hansson@arm.com{ 12411148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 12511148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 12611151Smitch.hayenga@arm.com cpu->wakeup(tid); 12711148Smitch.hayenga@arm.com } 12810529Smorr@cs.wisc.edu } 1298975Sandreas.hansson@arm.com lsq->recvTimingSnoopReq(pkt); 1308948Sandreas.hansson@arm.com} 1318948Sandreas.hansson@arm.com 1328948Sandreas.hansson@arm.comtemplate <class Impl> 1338707Sandreas.hansson@arm.comvoid 13410713Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvReqRetry() 1358707Sandreas.hansson@arm.com{ 13610713Sandreas.hansson@arm.com lsq->recvReqRetry(); 1378707Sandreas.hansson@arm.com} 1388707Sandreas.hansson@arm.com 1391060SN/Atemplate <class Impl> 1405595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1412733Sktlim@umich.edu : BaseO3CPU(params), 1423781Sgblack@eecs.umich.edu itb(params->itb), 1433781Sgblack@eecs.umich.edu dtb(params->dtb), 14412127Sspwilson2@wisc.edu tickEvent([this]{ tick(); }, "FullO3CPU tick", 14512127Sspwilson2@wisc.edu false, Event::CPU_Tick_Pri), 14613641Sqtt2@cornell.edu threadExitEvent([this]{ exitThreads(); }, "FullO3CPU exit threads", 14713641Sqtt2@cornell.edu false, Event::CPU_Exit_Pri), 1485737Scws3k@cs.virginia.edu#ifndef NDEBUG 1495737Scws3k@cs.virginia.edu instcount(0), 1505737Scws3k@cs.virginia.edu#endif 1512292SN/A removeInstsThisCycle(false), 1525595Sgblack@eecs.umich.edu fetch(this, params), 1535595Sgblack@eecs.umich.edu decode(this, params), 1545595Sgblack@eecs.umich.edu rename(this, params), 1555595Sgblack@eecs.umich.edu iew(this, params), 1565595Sgblack@eecs.umich.edu commit(this, params), 1571060SN/A 15812109SRekai.GonzalezAlberquilla@arm.com /* It is mandatory that all SMT threads use the same renaming mode as 15912109SRekai.GonzalezAlberquilla@arm.com * they are sharing registers and rename */ 16013601Sgiacomo.travaglini@arm.com vecMode(RenameMode<TheISA::ISA>::init(params->isa[0])), 1619915Ssteve.reinhardt@amd.com regFile(params->numPhysIntRegs, 1629920Syasuko.eckert@amd.com params->numPhysFloatRegs, 16312109SRekai.GonzalezAlberquilla@arm.com params->numPhysVecRegs, 16413610Sgiacomo.gabrielli@arm.com params->numPhysVecPredRegs, 16512109SRekai.GonzalezAlberquilla@arm.com params->numPhysCCRegs, 16612109SRekai.GonzalezAlberquilla@arm.com vecMode), 1671060SN/A 1689919Ssteve.reinhardt@amd.com freeList(name() + ".freelist", ®File), 1691060SN/A 1709954SFaissal.Sleiman@arm.com rob(this, params), 1711060SN/A 1729916Ssteve.reinhardt@amd.com scoreboard(name() + ".scoreboard", 17312105Snathanael.premillieu@arm.com regFile.totalNumPhysRegs()), 1741060SN/A 1759384SAndreas.Sandberg@arm.com isa(numThreads, NULL), 1769384SAndreas.Sandberg@arm.com 1778707Sandreas.hansson@arm.com icachePort(&fetch, this), 1788707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 1798707Sandreas.hansson@arm.com 1802873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1812873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1822873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1832873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1842873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1855804Snate@binkert.org activityRec(name(), NumStages, 1862873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1872873Sktlim@umich.edu params->activity), 1881060SN/A 1891060SN/A globalSeqNum(1), 1902292SN/A system(params->system), 1919180Sandreas.hansson@arm.com lastRunningCycle(curCycle()) 1921060SN/A{ 1939433SAndreas.Sandberg@ARM.com if (!params->switched_out) { 1943221Sktlim@umich.edu _status = Running; 1953221Sktlim@umich.edu } else { 1969152Satgutier@umich.edu _status = SwitchedOut; 1973221Sktlim@umich.edu } 1981681SN/A 1992794Sktlim@umich.edu if (params->checker) { 2002316SN/A BaseCPU *temp_checker = params->checker; 2018733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 2028707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2032316SN/A checker->setSystem(params->system); 2044598Sbinkertn@umich.edu } else { 2054598Sbinkertn@umich.edu checker = NULL; 2064598Sbinkertn@umich.edu } 2072316SN/A 2088793Sgblack@eecs.umich.edu if (!FullSystem) { 2098793Sgblack@eecs.umich.edu thread.resize(numThreads); 2108793Sgblack@eecs.umich.edu tids.resize(numThreads); 2118793Sgblack@eecs.umich.edu } 2121681SN/A 2132325SN/A // The stages also need their CPU pointer setup. However this 2142325SN/A // must be done at the upper level CPU because they have pointers 2152325SN/A // to the upper level CPU, and not this FullO3CPU. 2161060SN/A 2172292SN/A // Set up Pointers to the activeThreads list for each stage 2182292SN/A fetch.setActiveThreads(&activeThreads); 2192292SN/A decode.setActiveThreads(&activeThreads); 2202292SN/A rename.setActiveThreads(&activeThreads); 2212292SN/A iew.setActiveThreads(&activeThreads); 2222292SN/A commit.setActiveThreads(&activeThreads); 2231060SN/A 2241060SN/A // Give each of the stages the time buffer they will use. 2251060SN/A fetch.setTimeBuffer(&timeBuffer); 2261060SN/A decode.setTimeBuffer(&timeBuffer); 2271060SN/A rename.setTimeBuffer(&timeBuffer); 2281060SN/A iew.setTimeBuffer(&timeBuffer); 2291060SN/A commit.setTimeBuffer(&timeBuffer); 2301060SN/A 2311060SN/A // Also setup each of the stages' queues. 2321060SN/A fetch.setFetchQueue(&fetchQueue); 2331060SN/A decode.setFetchQueue(&fetchQueue); 2342292SN/A commit.setFetchQueue(&fetchQueue); 2351060SN/A decode.setDecodeQueue(&decodeQueue); 2361060SN/A rename.setDecodeQueue(&decodeQueue); 2371060SN/A rename.setRenameQueue(&renameQueue); 2381060SN/A iew.setRenameQueue(&renameQueue); 2391060SN/A iew.setIEWQueue(&iewQueue); 2401060SN/A commit.setIEWQueue(&iewQueue); 2411060SN/A commit.setRenameQueue(&renameQueue); 2421060SN/A 2432292SN/A commit.setIEWStage(&iew); 2442292SN/A rename.setIEWStage(&iew); 2452292SN/A rename.setCommitStage(&commit); 2462292SN/A 2478793Sgblack@eecs.umich.edu ThreadID active_threads; 2488793Sgblack@eecs.umich.edu if (FullSystem) { 2498793Sgblack@eecs.umich.edu active_threads = 1; 2508793Sgblack@eecs.umich.edu } else { 2518793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 2522831Sksewell@umich.edu 2538793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 2548793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 2558793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 2568793Sgblack@eecs.umich.edu "or edit your workload size."); 2578793Sgblack@eecs.umich.edu } 2582831Sksewell@umich.edu } 2592292SN/A 2602316SN/A //Make Sure That this a Valid Architeture 2612292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2622292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 26312109SRekai.GonzalezAlberquilla@arm.com assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs); 26413610Sgiacomo.gabrielli@arm.com assert(params->numPhysVecPredRegs >= numThreads * TheISA::NumVecPredRegs); 2659920Syasuko.eckert@amd.com assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs); 2662292SN/A 2672292SN/A rename.setScoreboard(&scoreboard); 2682292SN/A iew.setScoreboard(&scoreboard); 2692292SN/A 2701060SN/A // Setup the rename map for whichever stages need it. 2716221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2729384SAndreas.Sandberg@arm.com isa[tid] = params->isa[tid]; 27313601Sgiacomo.travaglini@arm.com assert(RenameMode<TheISA::ISA>::equalsInit(isa[tid], isa[0])); 2749384SAndreas.Sandberg@arm.com 2759919Ssteve.reinhardt@amd.com // Only Alpha has an FP zero register, so for other ISAs we 2769919Ssteve.reinhardt@amd.com // use an invalid FP register index to avoid special treatment 2779919Ssteve.reinhardt@amd.com // of any valid FP reg. 2789919Ssteve.reinhardt@amd.com RegIndex invalidFPReg = TheISA::NumFloatRegs + 1; 2799919Ssteve.reinhardt@amd.com RegIndex fpZeroReg = 2809919Ssteve.reinhardt@amd.com (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg; 2812292SN/A 2829919Ssteve.reinhardt@amd.com commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 28312109SRekai.GonzalezAlberquilla@arm.com &freeList, 28412109SRekai.GonzalezAlberquilla@arm.com vecMode); 2852292SN/A 2869919Ssteve.reinhardt@amd.com renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 28712109SRekai.GonzalezAlberquilla@arm.com &freeList, vecMode); 2882292SN/A } 2892292SN/A 2909919Ssteve.reinhardt@amd.com // Initialize rename map to assign physical registers to the 2919919Ssteve.reinhardt@amd.com // architectural registers for active threads only. 2929919Ssteve.reinhardt@amd.com for (ThreadID tid = 0; tid < active_threads; tid++) { 2939919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) { 2949919Ssteve.reinhardt@amd.com // Note that we can't use the rename() method because we don't 2959919Ssteve.reinhardt@amd.com // want special treatment for the zero register at this point 29612105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getIntReg(); 29712106SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg); 29812106SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg); 2999919Ssteve.reinhardt@amd.com } 3009919Ssteve.reinhardt@amd.com 3019919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) { 30212105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getFloatReg(); 30312106SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg); 30412106SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry( 30512106SRekai.GonzalezAlberquilla@arm.com RegId(FloatRegClass, ridx), phys_reg); 3069919Ssteve.reinhardt@amd.com } 3079920Syasuko.eckert@amd.com 30812109SRekai.GonzalezAlberquilla@arm.com /* Here we need two 'interfaces' the 'whole register' and the 30912109SRekai.GonzalezAlberquilla@arm.com * 'register element'. At any point only one of them will be 31012109SRekai.GonzalezAlberquilla@arm.com * active. */ 31112109SRekai.GonzalezAlberquilla@arm.com if (vecMode == Enums::Full) { 31212109SRekai.GonzalezAlberquilla@arm.com /* Initialize the full-vector interface */ 31312109SRekai.GonzalezAlberquilla@arm.com for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) { 31412109SRekai.GonzalezAlberquilla@arm.com RegId rid = RegId(VecRegClass, ridx); 31512109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = freeList.getVecReg(); 31612109SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(rid, phys_reg); 31712109SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(rid, phys_reg); 31812109SRekai.GonzalezAlberquilla@arm.com } 31912109SRekai.GonzalezAlberquilla@arm.com } else { 32012109SRekai.GonzalezAlberquilla@arm.com /* Initialize the vector-element interface */ 32112109SRekai.GonzalezAlberquilla@arm.com for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) { 32212109SRekai.GonzalezAlberquilla@arm.com for (ElemIndex ldx = 0; ldx < TheISA::NumVecElemPerVecReg; 32312109SRekai.GonzalezAlberquilla@arm.com ++ldx) { 32412109SRekai.GonzalezAlberquilla@arm.com RegId lrid = RegId(VecElemClass, ridx, ldx); 32512109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_elem = freeList.getVecElem(); 32612109SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(lrid, phys_elem); 32712109SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(lrid, phys_elem); 32812109SRekai.GonzalezAlberquilla@arm.com } 32912109SRekai.GonzalezAlberquilla@arm.com } 33012109SRekai.GonzalezAlberquilla@arm.com } 33112109SRekai.GonzalezAlberquilla@arm.com 33213610Sgiacomo.gabrielli@arm.com for (RegIndex ridx = 0; ridx < TheISA::NumVecPredRegs; ++ridx) { 33313610Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_reg = freeList.getVecPredReg(); 33413610Sgiacomo.gabrielli@arm.com renameMap[tid].setEntry(RegId(VecPredRegClass, ridx), phys_reg); 33513610Sgiacomo.gabrielli@arm.com commitRenameMap[tid].setEntry( 33613610Sgiacomo.gabrielli@arm.com RegId(VecPredRegClass, ridx), phys_reg); 33713610Sgiacomo.gabrielli@arm.com } 33813610Sgiacomo.gabrielli@arm.com 3399920Syasuko.eckert@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) { 34012105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getCCReg(); 34112106SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg); 34212106SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg); 3439920Syasuko.eckert@amd.com } 3449919Ssteve.reinhardt@amd.com } 3459919Ssteve.reinhardt@amd.com 3462292SN/A rename.setRenameMap(renameMap); 3472292SN/A commit.setRenameMap(commitRenameMap); 3481060SN/A rename.setFreeList(&freeList); 3492292SN/A 3501060SN/A // Setup the ROB for whichever stages need it. 3511060SN/A commit.setROB(&rob); 3522292SN/A 3539158Sandreas.hansson@arm.com lastActivatedCycle = 0; 3543093Sksewell@umich.edu 3555595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3565595Sgblack@eecs.umich.edu 3575595Sgblack@eecs.umich.edu // Setup any thread state. 3585595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3595595Sgblack@eecs.umich.edu 3606221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 3618793Sgblack@eecs.umich.edu if (FullSystem) { 3628793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3638793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3648793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 3658793Sgblack@eecs.umich.edu } else { 3668793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 3678793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3688793Sgblack@eecs.umich.edu tid, this->thread[tid]); 3698793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3708793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3718793Sgblack@eecs.umich.edu tid, params->workload[tid]); 3725595Sgblack@eecs.umich.edu 3738793Sgblack@eecs.umich.edu //usedTids[tid] = true; 3748793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 3758793Sgblack@eecs.umich.edu } else { 3768793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3778793Sgblack@eecs.umich.edu //when scheduling threads to CPU 3788793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3795595Sgblack@eecs.umich.edu 3808793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3818793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3828793Sgblack@eecs.umich.edu tid, dummy_proc); 3838793Sgblack@eecs.umich.edu //usedTids[tid] = false; 3848793Sgblack@eecs.umich.edu } 3855595Sgblack@eecs.umich.edu } 3865595Sgblack@eecs.umich.edu 3875595Sgblack@eecs.umich.edu ThreadContext *tc; 3885595Sgblack@eecs.umich.edu 3895595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3905595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3915595Sgblack@eecs.umich.edu 3925595Sgblack@eecs.umich.edu tc = o3_tc; 3935595Sgblack@eecs.umich.edu 3945595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3955595Sgblack@eecs.umich.edu // CheckerThreadContext. 3965595Sgblack@eecs.umich.edu if (params->checker) { 3975595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3985595Sgblack@eecs.umich.edu o3_tc, this->checker); 3995595Sgblack@eecs.umich.edu } 4005595Sgblack@eecs.umich.edu 4015595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 4025595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 4036221Snate@binkert.org o3_tc->thread = this->thread[tid]; 4045595Sgblack@eecs.umich.edu 40511627Smichael.lebeane@amd.com // Setup quiesce event. 40611627Smichael.lebeane@amd.com this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 40711627Smichael.lebeane@amd.com 4085595Sgblack@eecs.umich.edu // Give the thread the TC. 4096221Snate@binkert.org this->thread[tid]->tc = tc; 4105595Sgblack@eecs.umich.edu 4115595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4125595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4135595Sgblack@eecs.umich.edu } 4145595Sgblack@eecs.umich.edu 4158876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 41611150Smitch.hayenga@arm.com if (!params->switched_out && interrupts.empty()) { 4178876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 4188876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 4198876Sandreas.hansson@arm.com } 4208876Sandreas.hansson@arm.com 4216221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4226221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4231060SN/A} 4241060SN/A 4251060SN/Atemplate <class Impl> 4261755SN/AFullO3CPU<Impl>::~FullO3CPU() 4271060SN/A{ 4281060SN/A} 4291060SN/A 4301060SN/Atemplate <class Impl> 4311060SN/Avoid 43210023Smatt.horsnell@ARM.comFullO3CPU<Impl>::regProbePoints() 43310023Smatt.horsnell@ARM.com{ 43410464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 43510464SAndreas.Sandberg@ARM.com 43610023Smatt.horsnell@ARM.com ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete"); 43710023Smatt.horsnell@ARM.com ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete"); 43810464SAndreas.Sandberg@ARM.com 43910023Smatt.horsnell@ARM.com fetch.regProbePoints(); 44011246Sradhika.jagtap@ARM.com rename.regProbePoints(); 44110023Smatt.horsnell@ARM.com iew.regProbePoints(); 44210023Smatt.horsnell@ARM.com commit.regProbePoints(); 44310023Smatt.horsnell@ARM.com} 44410023Smatt.horsnell@ARM.com 44510023Smatt.horsnell@ARM.comtemplate <class Impl> 44610023Smatt.horsnell@ARM.comvoid 4475595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4481062SN/A{ 4492733Sktlim@umich.edu BaseO3CPU::regStats(); 4502292SN/A 4512733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4522292SN/A timesIdled 4532292SN/A .name(name() + ".timesIdled") 4542292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4552292SN/A " unscheduled itself") 4562292SN/A .prereq(timesIdled); 4572292SN/A 4582292SN/A idleCycles 4592292SN/A .name(name() + ".idleCycles") 4602292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4612292SN/A "to idling") 4622292SN/A .prereq(idleCycles); 4632292SN/A 4648627SAli.Saidi@ARM.com quiesceCycles 4658627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 4668627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 4678627SAli.Saidi@ARM.com "for an interrupt") 4688627SAli.Saidi@ARM.com .prereq(quiesceCycles); 4698627SAli.Saidi@ARM.com 4702292SN/A // Number of Instructions simulated 4712292SN/A // -------------------------------- 4722292SN/A // Should probably be in Base CPU but need templated 4732292SN/A // MaxThreads so put in here instead 4742292SN/A committedInsts 4752292SN/A .init(numThreads) 4762292SN/A .name(name() + ".committedInsts") 47710225Snilay@cs.wisc.edu .desc("Number of Instructions Simulated") 47810225Snilay@cs.wisc.edu .flags(Stats::total); 4792292SN/A 4808834Satgutier@umich.edu committedOps 4818834Satgutier@umich.edu .init(numThreads) 4828834Satgutier@umich.edu .name(name() + ".committedOps") 48310225Snilay@cs.wisc.edu .desc("Number of Ops (including micro ops) Simulated") 48410225Snilay@cs.wisc.edu .flags(Stats::total); 4852292SN/A 4862292SN/A cpi 4872292SN/A .name(name() + ".cpi") 4882292SN/A .desc("CPI: Cycles Per Instruction") 4892292SN/A .precision(6); 4904392Sktlim@umich.edu cpi = numCycles / committedInsts; 4912292SN/A 4922292SN/A totalCpi 4932292SN/A .name(name() + ".cpi_total") 4942292SN/A .desc("CPI: Total CPI of All Threads") 4952292SN/A .precision(6); 49610225Snilay@cs.wisc.edu totalCpi = numCycles / sum(committedInsts); 4972292SN/A 4982292SN/A ipc 4992292SN/A .name(name() + ".ipc") 5002292SN/A .desc("IPC: Instructions Per Cycle") 5012292SN/A .precision(6); 5024392Sktlim@umich.edu ipc = committedInsts / numCycles; 5032292SN/A 5042292SN/A totalIpc 5052292SN/A .name(name() + ".ipc_total") 5062292SN/A .desc("IPC: Total IPC of All Threads") 5072292SN/A .precision(6); 50810225Snilay@cs.wisc.edu totalIpc = sum(committedInsts) / numCycles; 5092292SN/A 5105595Sgblack@eecs.umich.edu this->fetch.regStats(); 5115595Sgblack@eecs.umich.edu this->decode.regStats(); 5125595Sgblack@eecs.umich.edu this->rename.regStats(); 5135595Sgblack@eecs.umich.edu this->iew.regStats(); 5145595Sgblack@eecs.umich.edu this->commit.regStats(); 5157897Shestness@cs.utexas.edu this->rob.regStats(); 5167897Shestness@cs.utexas.edu 5177897Shestness@cs.utexas.edu intRegfileReads 5187897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 5197897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 5207897Shestness@cs.utexas.edu .prereq(intRegfileReads); 5217897Shestness@cs.utexas.edu 5227897Shestness@cs.utexas.edu intRegfileWrites 5237897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 5247897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 5257897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 5267897Shestness@cs.utexas.edu 5277897Shestness@cs.utexas.edu fpRegfileReads 5287897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 5297897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5307897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5317897Shestness@cs.utexas.edu 5327897Shestness@cs.utexas.edu fpRegfileWrites 5337897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5347897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5357897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5367897Shestness@cs.utexas.edu 53712109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads 53812109SRekai.GonzalezAlberquilla@arm.com .name(name() + ".vec_regfile_reads") 53912109SRekai.GonzalezAlberquilla@arm.com .desc("number of vector regfile reads") 54012109SRekai.GonzalezAlberquilla@arm.com .prereq(vecRegfileReads); 54112109SRekai.GonzalezAlberquilla@arm.com 54212109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites 54312109SRekai.GonzalezAlberquilla@arm.com .name(name() + ".vec_regfile_writes") 54412109SRekai.GonzalezAlberquilla@arm.com .desc("number of vector regfile writes") 54512109SRekai.GonzalezAlberquilla@arm.com .prereq(vecRegfileWrites); 54612109SRekai.GonzalezAlberquilla@arm.com 54713610Sgiacomo.gabrielli@arm.com vecPredRegfileReads 54813610Sgiacomo.gabrielli@arm.com .name(name() + ".pred_regfile_reads") 54913610Sgiacomo.gabrielli@arm.com .desc("number of predicate regfile reads") 55013610Sgiacomo.gabrielli@arm.com .prereq(vecPredRegfileReads); 55113610Sgiacomo.gabrielli@arm.com 55213610Sgiacomo.gabrielli@arm.com vecPredRegfileWrites 55313610Sgiacomo.gabrielli@arm.com .name(name() + ".pred_regfile_writes") 55413610Sgiacomo.gabrielli@arm.com .desc("number of predicate regfile writes") 55513610Sgiacomo.gabrielli@arm.com .prereq(vecPredRegfileWrites); 55613610Sgiacomo.gabrielli@arm.com 5579920Syasuko.eckert@amd.com ccRegfileReads 5589920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_reads") 5599920Syasuko.eckert@amd.com .desc("number of cc regfile reads") 5609920Syasuko.eckert@amd.com .prereq(ccRegfileReads); 5619920Syasuko.eckert@amd.com 5629920Syasuko.eckert@amd.com ccRegfileWrites 5639920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_writes") 5649920Syasuko.eckert@amd.com .desc("number of cc regfile writes") 5659920Syasuko.eckert@amd.com .prereq(ccRegfileWrites); 5669920Syasuko.eckert@amd.com 5677897Shestness@cs.utexas.edu miscRegfileReads 5687897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5697897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5707897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5717897Shestness@cs.utexas.edu 5727897Shestness@cs.utexas.edu miscRegfileWrites 5737897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5747897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5757897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5761062SN/A} 5771062SN/A 5781062SN/Atemplate <class Impl> 5791062SN/Avoid 5801755SN/AFullO3CPU<Impl>::tick() 5811060SN/A{ 5822733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5839444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 58410913Sandreas.sandberg@arm.com assert(drainState() != DrainState::Drained); 5851060SN/A 5862292SN/A ++numCycles; 58712284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 5882292SN/A 5892325SN/A// activity = false; 5902292SN/A 5912292SN/A //Tick each of the stages 5921060SN/A fetch.tick(); 5931060SN/A 5941060SN/A decode.tick(); 5951060SN/A 5961060SN/A rename.tick(); 5971060SN/A 5981060SN/A iew.tick(); 5991060SN/A 6001060SN/A commit.tick(); 6011060SN/A 6022292SN/A // Now advance the time buffers 6031060SN/A timeBuffer.advance(); 6041060SN/A 6051060SN/A fetchQueue.advance(); 6061060SN/A decodeQueue.advance(); 6071060SN/A renameQueue.advance(); 6081060SN/A iewQueue.advance(); 6091060SN/A 6102325SN/A activityRec.advance(); 6112292SN/A 6122292SN/A if (removeInstsThisCycle) { 6132292SN/A cleanUpRemovedInsts(); 6142292SN/A } 6152292SN/A 6162325SN/A if (!tickEvent.scheduled()) { 6179444SAndreas.Sandberg@ARM.com if (_status == SwitchedOut) { 6183226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 6192325SN/A // increment stat 6209179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6213221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 6223226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 6239179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6242325SN/A timesIdled++; 6252325SN/A } else { 6269180Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(Cycles(1))); 6273226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 6282325SN/A } 6292292SN/A } 6302292SN/A 6318793Sgblack@eecs.umich.edu if (!FullSystem) 6328793Sgblack@eecs.umich.edu updateThreadPriority(); 6339444SAndreas.Sandberg@ARM.com 6349444SAndreas.Sandberg@ARM.com tryDrain(); 6351060SN/A} 6361060SN/A 6371060SN/Atemplate <class Impl> 6381060SN/Avoid 6391755SN/AFullO3CPU<Impl>::init() 6401060SN/A{ 6415714Shsul@eecs.umich.edu BaseCPU::init(); 6421060SN/A 6438921Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 6449382SAli.Saidi@ARM.com // Set noSquashFromTC so that the CPU doesn't squash when initially 6458921Sandreas.hansson@arm.com // setting up registers. 6469382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 6478921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 6488921Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 6498921Sandreas.hansson@arm.com } 6502292SN/A 6519433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 6528793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6538793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6548793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6558793Sgblack@eecs.umich.edu } 6566034Ssteve.reinhardt@amd.com } 6572292SN/A 6589382SAli.Saidi@ARM.com // Clear noSquashFromTC. 6596221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6609382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6612292SN/A 6629427SAndreas.Sandberg@ARM.com commit.setThreads(thread); 6639427SAndreas.Sandberg@ARM.com} 6642292SN/A 6659427SAndreas.Sandberg@ARM.comtemplate <class Impl> 6669427SAndreas.Sandberg@ARM.comvoid 6679427SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::startup() 6689427SAndreas.Sandberg@ARM.com{ 6699992Snilay@cs.wisc.edu BaseCPU::startup(); 6709461Snilay@cs.wisc.edu for (int tid = 0; tid < numThreads; ++tid) 6719461Snilay@cs.wisc.edu isa[tid]->startup(threadContexts[tid]); 6729461Snilay@cs.wisc.edu 6739427SAndreas.Sandberg@ARM.com fetch.startupStage(); 6749444SAndreas.Sandberg@ARM.com decode.startupStage(); 6759427SAndreas.Sandberg@ARM.com iew.startupStage(); 6769427SAndreas.Sandberg@ARM.com rename.startupStage(); 6779427SAndreas.Sandberg@ARM.com commit.startupStage(); 6782292SN/A} 6792292SN/A 6802292SN/Atemplate <class Impl> 6812292SN/Avoid 6826221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6832875Sksewell@umich.edu{ 6846221Snate@binkert.org list<ThreadID>::iterator isActive = 6855314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6862875Sksewell@umich.edu 68713831SAndrea.Mondelli@ucf.edu DPRINTF(O3CPU, "[tid:%i] Calling activate thread.\n", tid); 6889444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6893226Sktlim@umich.edu 6902875Sksewell@umich.edu if (isActive == activeThreads.end()) { 69113831SAndrea.Mondelli@ucf.edu DPRINTF(O3CPU, "[tid:%i] Adding to active threads list\n", 6922875Sksewell@umich.edu tid); 6932875Sksewell@umich.edu 6942875Sksewell@umich.edu activeThreads.push_back(tid); 6952875Sksewell@umich.edu } 6962875Sksewell@umich.edu} 6972875Sksewell@umich.edu 6982875Sksewell@umich.edutemplate <class Impl> 6992875Sksewell@umich.eduvoid 7006221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 7012875Sksewell@umich.edu{ 7022875Sksewell@umich.edu //Remove From Active List, if Active 7036221Snate@binkert.org list<ThreadID>::iterator thread_it = 7045314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 7052875Sksewell@umich.edu 70613831SAndrea.Mondelli@ucf.edu DPRINTF(O3CPU, "[tid:%i] Calling deactivate thread.\n", tid); 7079444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7083226Sktlim@umich.edu 7092875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 71013831SAndrea.Mondelli@ucf.edu DPRINTF(O3CPU,"[tid:%i] Removing from active threads list\n", 7112875Sksewell@umich.edu tid); 7122875Sksewell@umich.edu activeThreads.erase(thread_it); 7132875Sksewell@umich.edu } 71410331Smitch.hayenga@arm.com 71510331Smitch.hayenga@arm.com fetch.deactivateThread(tid); 71610331Smitch.hayenga@arm.com commit.deactivateThread(tid); 7172875Sksewell@umich.edu} 7182875Sksewell@umich.edu 7192875Sksewell@umich.edutemplate <class Impl> 7206221Snate@binkert.orgCounter 7218834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 7226221Snate@binkert.org{ 7236221Snate@binkert.org Counter total(0); 7246221Snate@binkert.org 7256221Snate@binkert.org ThreadID size = thread.size(); 7266221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 7276221Snate@binkert.org total += thread[i]->numInst; 7286221Snate@binkert.org 7296221Snate@binkert.org return total; 7306221Snate@binkert.org} 7316221Snate@binkert.org 7326221Snate@binkert.orgtemplate <class Impl> 7338834Satgutier@umich.eduCounter 7348834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 7358834Satgutier@umich.edu{ 7368834Satgutier@umich.edu Counter total(0); 7378834Satgutier@umich.edu 7388834Satgutier@umich.edu ThreadID size = thread.size(); 7398834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 7408834Satgutier@umich.edu total += thread[i]->numOp; 7418834Satgutier@umich.edu 7428834Satgutier@umich.edu return total; 7438834Satgutier@umich.edu} 7448834Satgutier@umich.edu 7458834Satgutier@umich.edutemplate <class Impl> 7462875Sksewell@umich.eduvoid 74710407Smitch.hayenga@arm.comFullO3CPU<Impl>::activateContext(ThreadID tid) 7482875Sksewell@umich.edu{ 7499444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7509444SAndreas.Sandberg@ARM.com 7512875Sksewell@umich.edu // Needs to set each stage to running as well. 75210407Smitch.hayenga@arm.com activateThread(tid); 7532875Sksewell@umich.edu 7549444SAndreas.Sandberg@ARM.com // We don't want to wake the CPU if it is drained. In that case, 7559444SAndreas.Sandberg@ARM.com // we just want to flag the thread as active and schedule the tick 7569444SAndreas.Sandberg@ARM.com // event from drainResume() instead. 75710913Sandreas.sandberg@arm.com if (drainState() == DrainState::Drained) 7589444SAndreas.Sandberg@ARM.com return; 7599444SAndreas.Sandberg@ARM.com 7609158Sandreas.hansson@arm.com // If we are time 0 or if the last activation time is in the past, 7619158Sandreas.hansson@arm.com // schedule the next tick and wake up the fetch unit 7629158Sandreas.hansson@arm.com if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 76310407Smitch.hayenga@arm.com scheduleTickEvent(Cycles(0)); 7642875Sksewell@umich.edu 7652875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7662875Sksewell@umich.edu // deschedule itself. 7672875Sksewell@umich.edu activityRec.activity(); 7682875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7692875Sksewell@umich.edu 7709180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 7719180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 7729179Sandreas.hansson@arm.com if (cycles != 0) 7739179Sandreas.hansson@arm.com --cycles; 7749179Sandreas.hansson@arm.com quiesceCycles += cycles; 7758627SAli.Saidi@ARM.com 7767823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7772875Sksewell@umich.edu 7782875Sksewell@umich.edu _status = Running; 77911526Sdavid.guillen@arm.com 78011526Sdavid.guillen@arm.com BaseCPU::activateContext(tid); 7812875Sksewell@umich.edu } 7822875Sksewell@umich.edu} 7832875Sksewell@umich.edu 7842875Sksewell@umich.edutemplate <class Impl> 78510407Smitch.hayenga@arm.comvoid 7866221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 7872875Sksewell@umich.edu{ 78813831SAndrea.Mondelli@ucf.edu DPRINTF(O3CPU,"[tid:%i] Suspending Thread Context.\n", tid); 7899444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 79010408Smitch.hayenga@arm.com 79110408Smitch.hayenga@arm.com deactivateThread(tid); 79210407Smitch.hayenga@arm.com 7933221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 79410683Salexandru.dutu@amd.com if (activeThreads.size() == 0) { 7952910Sksewell@umich.edu unscheduleTickEvent(); 79610683Salexandru.dutu@amd.com lastRunningCycle = curCycle(); 79710683Salexandru.dutu@amd.com _status = Idle; 79810683Salexandru.dutu@amd.com } 7998627SAli.Saidi@ARM.com 8008627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 80111526Sdavid.guillen@arm.com 80211526Sdavid.guillen@arm.com BaseCPU::suspendContext(tid); 8032875Sksewell@umich.edu} 8042875Sksewell@umich.edu 8052875Sksewell@umich.edutemplate <class Impl> 8062875Sksewell@umich.eduvoid 8076221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 8082875Sksewell@umich.edu{ 8092910Sksewell@umich.edu //For now, this is the same as deallocate 81013831SAndrea.Mondelli@ucf.edu DPRINTF(O3CPU,"[tid:%i] Halt Context called. Deallocating\n", tid); 8119444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 81210408Smitch.hayenga@arm.com 81310408Smitch.hayenga@arm.com deactivateThread(tid); 81410408Smitch.hayenga@arm.com removeThread(tid); 81512284Sjose.marinho@arm.com 81612284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_SLEEP); 8172875Sksewell@umich.edu} 8182875Sksewell@umich.edu 8192875Sksewell@umich.edutemplate <class Impl> 8202875Sksewell@umich.eduvoid 8216221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 8222292SN/A{ 8232847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 8242292SN/A // Will change now that the PC and thread state is internal to the CPU 8252683Sktlim@umich.edu // and not in the ThreadContext. 8268793Sgblack@eecs.umich.edu ThreadContext *src_tc; 8278793Sgblack@eecs.umich.edu if (FullSystem) 8288793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 8298793Sgblack@eecs.umich.edu else 8308793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 8312292SN/A 8322292SN/A //Bind Int Regs to Rename Map 83312104Snathanael.premillieu@arm.com 83412106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs; 83512106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 83612105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getIntReg(); 83712104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 8382292SN/A scoreboard.setReg(phys_reg); 8392292SN/A } 8402292SN/A 8412292SN/A //Bind Float Regs to Rename Map 84212106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs; 84312106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 84412105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getFloatReg(); 84512104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 8462292SN/A scoreboard.setReg(phys_reg); 8472292SN/A } 8482292SN/A 8499920Syasuko.eckert@amd.com //Bind condition-code Regs to Rename Map 85012106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs; 85112106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 85212105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getCCReg(); 85312104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 8549920Syasuko.eckert@amd.com scoreboard.setReg(phys_reg); 8559920Syasuko.eckert@amd.com } 8569920Syasuko.eckert@amd.com 8572292SN/A //Copy Thread Data Into RegFile 8582847Sksewell@umich.edu //this->copyFromTC(tid); 8592292SN/A 8602847Sksewell@umich.edu //Set PC/NPC/NNPC 8617720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8622292SN/A 8632680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8642292SN/A 86510407Smitch.hayenga@arm.com activateContext(tid); 8662292SN/A 8672292SN/A //Reset ROB/IQ/LSQ Entries 8682292SN/A commit.rob->resetEntries(); 8692292SN/A} 8702292SN/A 8712292SN/Atemplate <class Impl> 8722292SN/Avoid 8736221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8742292SN/A{ 8752877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 8762847Sksewell@umich.edu 8772847Sksewell@umich.edu // Copy Thread Data From RegFile 8782847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 8795364Sksewell@umich.edu // this->copyToTC(tid); 8805364Sksewell@umich.edu 8815364Sksewell@umich.edu 8825364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 8835364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 8845364Sksewell@umich.edu // in SMT workloads. 8852847Sksewell@umich.edu 88613641Sqtt2@cornell.edu // clear all thread-specific states in each stage of the pipeline 88713641Sqtt2@cornell.edu // since this thread is going to be completely removed from the CPU 88813641Sqtt2@cornell.edu commit.clearStates(tid); 88913641Sqtt2@cornell.edu fetch.clearStates(tid); 89013641Sqtt2@cornell.edu decode.clearStates(tid); 89113641Sqtt2@cornell.edu rename.clearStates(tid); 89213641Sqtt2@cornell.edu iew.clearStates(tid); 8932292SN/A 89413641Sqtt2@cornell.edu // at this step, all instructions in the pipeline should be already 89513641Sqtt2@cornell.edu // either committed successfully or squashed. All thread-specific 89613641Sqtt2@cornell.edu // queues in the pipeline must be empty. 8975362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 8982292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 89913641Sqtt2@cornell.edu assert(commit.rob->isEmpty(tid)); 9002292SN/A 9012847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 9023229Sktlim@umich.edu 9033229Sktlim@umich.edu // Commented out for now. This should be possible to do by 9043229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 9053229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 9063229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 9073229Sktlim@umich.edu/* 9082292SN/A if (activeThreads.size() >= 1) { 9092292SN/A commit.rob->resetEntries(); 9102292SN/A iew.resetEntries(); 9112292SN/A } 9123229Sktlim@umich.edu*/ 9132292SN/A} 9142292SN/A 9154192Sktlim@umich.edutemplate <class Impl> 91613601Sgiacomo.travaglini@arm.comvoid 91713601Sgiacomo.travaglini@arm.comFullO3CPU<Impl>::switchRenameMode(ThreadID tid, UnifiedFreeList* freelist) 91813601Sgiacomo.travaglini@arm.com{ 91913601Sgiacomo.travaglini@arm.com auto pc = this->pcState(tid); 92013601Sgiacomo.travaglini@arm.com 92113601Sgiacomo.travaglini@arm.com // new_mode is the new vector renaming mode 92213601Sgiacomo.travaglini@arm.com auto new_mode = RenameMode<TheISA::ISA>::mode(pc); 92313601Sgiacomo.travaglini@arm.com 92413601Sgiacomo.travaglini@arm.com // We update vecMode only if there has been a change 92513601Sgiacomo.travaglini@arm.com if (new_mode != vecMode) { 92613601Sgiacomo.travaglini@arm.com vecMode = new_mode; 92713601Sgiacomo.travaglini@arm.com 92813601Sgiacomo.travaglini@arm.com renameMap[tid].switchMode(vecMode); 92913601Sgiacomo.travaglini@arm.com commitRenameMap[tid].switchMode(vecMode); 93013601Sgiacomo.travaglini@arm.com renameMap[tid].switchFreeList(freelist); 93113601Sgiacomo.travaglini@arm.com } 93213601Sgiacomo.travaglini@arm.com} 93313601Sgiacomo.travaglini@arm.com 93413601Sgiacomo.travaglini@arm.comtemplate <class Impl> 9355702Ssaidi@eecs.umich.eduFault 9365595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 9375595Sgblack@eecs.umich.edu{ 9385595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 93911150Smitch.hayenga@arm.com return this->interrupts[0]->getInterrupt(this->threadContexts[0]); 9405595Sgblack@eecs.umich.edu} 9415595Sgblack@eecs.umich.edu 9425595Sgblack@eecs.umich.edutemplate <class Impl> 9435595Sgblack@eecs.umich.eduvoid 94410379Sandreas.hansson@arm.comFullO3CPU<Impl>::processInterrupts(const Fault &interrupt) 9455595Sgblack@eecs.umich.edu{ 9465595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 9475595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 9485595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9495595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9505595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9515595Sgblack@eecs.umich.edu 9525595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 95311150Smitch.hayenga@arm.com this->interrupts[0]->updateIntrInfo(this->threadContexts[0]); 9545595Sgblack@eecs.umich.edu 9555595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 95610417Sandreas.hansson@arm.com this->trap(interrupt, 0, nullptr); 9575595Sgblack@eecs.umich.edu} 9585595Sgblack@eecs.umich.edu 9591060SN/Atemplate <class Impl> 9602852Sktlim@umich.eduvoid 96110417Sandreas.hansson@arm.comFullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid, 96210417Sandreas.hansson@arm.com const StaticInstPtr &inst) 9635595Sgblack@eecs.umich.edu{ 9645595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 9657684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 9665595Sgblack@eecs.umich.edu} 9675595Sgblack@eecs.umich.edu 9685595Sgblack@eecs.umich.edutemplate <class Impl> 9695595Sgblack@eecs.umich.eduvoid 97011877Sbrandon.potter@amd.comFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault) 9715595Sgblack@eecs.umich.edu{ 9725595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 9735595Sgblack@eecs.umich.edu 9745595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 9755595Sgblack@eecs.umich.edu 9765595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 9775595Sgblack@eecs.umich.edu // instruction. 9785595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 9795595Sgblack@eecs.umich.edu 9805595Sgblack@eecs.umich.edu // Execute the actual syscall. 98111877Sbrandon.potter@amd.com this->thread[tid]->syscall(callnum, fault); 9825595Sgblack@eecs.umich.edu 9835595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 9845595Sgblack@eecs.umich.edu // incrementing it. 9855595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 9865595Sgblack@eecs.umich.edu} 9875595Sgblack@eecs.umich.edu 9885595Sgblack@eecs.umich.edutemplate <class Impl> 9895595Sgblack@eecs.umich.eduvoid 99010905Sandreas.sandberg@arm.comFullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const 9912864Sktlim@umich.edu{ 99210905Sandreas.sandberg@arm.com thread[tid]->serialize(cp); 9932864Sktlim@umich.edu} 9942864Sktlim@umich.edu 9952864Sktlim@umich.edutemplate <class Impl> 9962864Sktlim@umich.eduvoid 99710905Sandreas.sandberg@arm.comFullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid) 9982864Sktlim@umich.edu{ 99910905Sandreas.sandberg@arm.com thread[tid]->unserialize(cp); 10002864Sktlim@umich.edu} 10012864Sktlim@umich.edu 10022864Sktlim@umich.edutemplate <class Impl> 100310913Sandreas.sandberg@arm.comDrainState 100410913Sandreas.sandberg@arm.comFullO3CPU<Impl>::drain() 10051060SN/A{ 100612276Sanouk.vanlaer@arm.com // Deschedule any power gating event (if any) 100712276Sanouk.vanlaer@arm.com deschedulePowerGatingEvent(); 100812276Sanouk.vanlaer@arm.com 10099444SAndreas.Sandberg@ARM.com // If the CPU isn't doing anything, then return immediately. 101010913Sandreas.sandberg@arm.com if (switchedOut()) 101110913Sandreas.sandberg@arm.com return DrainState::Drained; 10123512Sktlim@umich.edu 10139444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Draining...\n"); 10143512Sktlim@umich.edu 10159444SAndreas.Sandberg@ARM.com // We only need to signal a drain to the commit stage as this 10169444SAndreas.Sandberg@ARM.com // initiates squashing controls the draining. Once the commit 10179444SAndreas.Sandberg@ARM.com // stage commits an instruction where it is safe to stop, it'll 10189444SAndreas.Sandberg@ARM.com // squash the rest of the instructions in the pipeline and force 10199444SAndreas.Sandberg@ARM.com // the fetch stage to stall. The pipeline will be drained once all 10209444SAndreas.Sandberg@ARM.com // in-flight instructions have retired. 10212843Sktlim@umich.edu commit.drain(); 10222325SN/A 10232325SN/A // Wake the CPU and record activity so everything can drain out if 10242863Sktlim@umich.edu // the CPU was not able to immediately drain. 102514085Sgiacomo.travaglini@arm.com if (!isCpuDrained()) { 102612143Sanouk.vanlaer@arm.com // If a thread is suspended, wake it up so it can be drained 102712143Sanouk.vanlaer@arm.com for (auto t : threadContexts) { 102812143Sanouk.vanlaer@arm.com if (t->status() == ThreadContext::Suspended){ 102912143Sanouk.vanlaer@arm.com DPRINTF(Drain, "Currently suspended so activate %i \n", 103012143Sanouk.vanlaer@arm.com t->threadId()); 103112143Sanouk.vanlaer@arm.com t->activate(); 103212143Sanouk.vanlaer@arm.com // As the thread is now active, change the power state as well 103312143Sanouk.vanlaer@arm.com activateContext(t->threadId()); 103412143Sanouk.vanlaer@arm.com } 103512143Sanouk.vanlaer@arm.com } 103612143Sanouk.vanlaer@arm.com 10372863Sktlim@umich.edu wakeCPU(); 10382863Sktlim@umich.edu activityRec.activity(); 10392852Sktlim@umich.edu 10409152Satgutier@umich.edu DPRINTF(Drain, "CPU not drained\n"); 10419152Satgutier@umich.edu 104210913Sandreas.sandberg@arm.com return DrainState::Draining; 10432863Sktlim@umich.edu } else { 10449444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU is already drained\n"); 10459444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 10469444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 10479444SAndreas.Sandberg@ARM.com 10489444SAndreas.Sandberg@ARM.com // Flush out any old data from the time buffers. In 10499444SAndreas.Sandberg@ARM.com // particular, there might be some data in flight from the 10509444SAndreas.Sandberg@ARM.com // fetch stage that isn't visible in any of the CPU buffers we 105114085Sgiacomo.travaglini@arm.com // test in isCpuDrained(). 10529444SAndreas.Sandberg@ARM.com for (int i = 0; i < timeBuffer.getSize(); ++i) { 10539444SAndreas.Sandberg@ARM.com timeBuffer.advance(); 10549444SAndreas.Sandberg@ARM.com fetchQueue.advance(); 10559444SAndreas.Sandberg@ARM.com decodeQueue.advance(); 10569444SAndreas.Sandberg@ARM.com renameQueue.advance(); 10579444SAndreas.Sandberg@ARM.com iewQueue.advance(); 10589444SAndreas.Sandberg@ARM.com } 10599444SAndreas.Sandberg@ARM.com 10609444SAndreas.Sandberg@ARM.com drainSanityCheck(); 106110913Sandreas.sandberg@arm.com return DrainState::Drained; 10622863Sktlim@umich.edu } 10632316SN/A} 10642310SN/A 10652316SN/Atemplate <class Impl> 10669444SAndreas.Sandberg@ARM.combool 10679444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::tryDrain() 10689444SAndreas.Sandberg@ARM.com{ 106914085Sgiacomo.travaglini@arm.com if (drainState() != DrainState::Draining || !isCpuDrained()) 10709444SAndreas.Sandberg@ARM.com return false; 10719444SAndreas.Sandberg@ARM.com 10729444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 10739444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 10749444SAndreas.Sandberg@ARM.com 10759444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 107610913Sandreas.sandberg@arm.com signalDrainDone(); 10779444SAndreas.Sandberg@ARM.com 10789444SAndreas.Sandberg@ARM.com return true; 10799444SAndreas.Sandberg@ARM.com} 10809444SAndreas.Sandberg@ARM.com 10819444SAndreas.Sandberg@ARM.comtemplate <class Impl> 10829444SAndreas.Sandberg@ARM.comvoid 10839444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::drainSanityCheck() const 10849444SAndreas.Sandberg@ARM.com{ 108514085Sgiacomo.travaglini@arm.com assert(isCpuDrained()); 10869444SAndreas.Sandberg@ARM.com fetch.drainSanityCheck(); 10879444SAndreas.Sandberg@ARM.com decode.drainSanityCheck(); 10889444SAndreas.Sandberg@ARM.com rename.drainSanityCheck(); 10899444SAndreas.Sandberg@ARM.com iew.drainSanityCheck(); 10909444SAndreas.Sandberg@ARM.com commit.drainSanityCheck(); 10919444SAndreas.Sandberg@ARM.com} 10929444SAndreas.Sandberg@ARM.com 10939444SAndreas.Sandberg@ARM.comtemplate <class Impl> 10949444SAndreas.Sandberg@ARM.combool 109514085Sgiacomo.travaglini@arm.comFullO3CPU<Impl>::isCpuDrained() const 10969444SAndreas.Sandberg@ARM.com{ 10979444SAndreas.Sandberg@ARM.com bool drained(true); 10989444SAndreas.Sandberg@ARM.com 10999444SAndreas.Sandberg@ARM.com if (!instList.empty() || !removeList.empty()) { 11009444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Main CPU structures not drained.\n"); 11019444SAndreas.Sandberg@ARM.com drained = false; 11029444SAndreas.Sandberg@ARM.com } 11039444SAndreas.Sandberg@ARM.com 11049444SAndreas.Sandberg@ARM.com if (!fetch.isDrained()) { 11059444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Fetch not drained.\n"); 11069444SAndreas.Sandberg@ARM.com drained = false; 11079444SAndreas.Sandberg@ARM.com } 11089444SAndreas.Sandberg@ARM.com 11099444SAndreas.Sandberg@ARM.com if (!decode.isDrained()) { 11109444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Decode not drained.\n"); 11119444SAndreas.Sandberg@ARM.com drained = false; 11129444SAndreas.Sandberg@ARM.com } 11139444SAndreas.Sandberg@ARM.com 11149444SAndreas.Sandberg@ARM.com if (!rename.isDrained()) { 11159444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Rename not drained.\n"); 11169444SAndreas.Sandberg@ARM.com drained = false; 11179444SAndreas.Sandberg@ARM.com } 11189444SAndreas.Sandberg@ARM.com 11199444SAndreas.Sandberg@ARM.com if (!iew.isDrained()) { 11209444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "IEW not drained.\n"); 11219444SAndreas.Sandberg@ARM.com drained = false; 11229444SAndreas.Sandberg@ARM.com } 11239444SAndreas.Sandberg@ARM.com 11249444SAndreas.Sandberg@ARM.com if (!commit.isDrained()) { 11259444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Commit not drained.\n"); 11269444SAndreas.Sandberg@ARM.com drained = false; 11279444SAndreas.Sandberg@ARM.com } 11289444SAndreas.Sandberg@ARM.com 11299444SAndreas.Sandberg@ARM.com return drained; 11309444SAndreas.Sandberg@ARM.com} 11319444SAndreas.Sandberg@ARM.com 11329444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11339444SAndreas.Sandberg@ARM.comvoid 11349444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::commitDrained(ThreadID tid) 11359444SAndreas.Sandberg@ARM.com{ 11369444SAndreas.Sandberg@ARM.com fetch.drainStall(tid); 11379444SAndreas.Sandberg@ARM.com} 11389444SAndreas.Sandberg@ARM.com 11399444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11402316SN/Avoid 11419342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drainResume() 11422316SN/A{ 11439444SAndreas.Sandberg@ARM.com if (switchedOut()) 11449444SAndreas.Sandberg@ARM.com return; 11452316SN/A 11469444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Resuming...\n"); 11479523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 11483319Shsul@eecs.umich.edu 11499444SAndreas.Sandberg@ARM.com fetch.drainResume(); 11509444SAndreas.Sandberg@ARM.com commit.drainResume(); 11512316SN/A 11529444SAndreas.Sandberg@ARM.com _status = Idle; 11539444SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); i++) { 11549444SAndreas.Sandberg@ARM.com if (thread[i]->status() == ThreadContext::Active) { 11559444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Activating thread: %i\n", i); 11569444SAndreas.Sandberg@ARM.com activateThread(i); 11579444SAndreas.Sandberg@ARM.com _status = Running; 11582863Sktlim@umich.edu } 11592310SN/A } 11609444SAndreas.Sandberg@ARM.com 11619444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 11629444SAndreas.Sandberg@ARM.com if (_status == Running) 11639444SAndreas.Sandberg@ARM.com schedule(tickEvent, nextCycle()); 116412276Sanouk.vanlaer@arm.com 116512276Sanouk.vanlaer@arm.com // Reschedule any power gating event (if any) 116612276Sanouk.vanlaer@arm.com schedulePowerGatingEvent(); 11672843Sktlim@umich.edu} 11682843Sktlim@umich.edu 11692843Sktlim@umich.edutemplate <class Impl> 11702843Sktlim@umich.eduvoid 11712843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11722843Sktlim@umich.edu{ 11739444SAndreas.Sandberg@ARM.com DPRINTF(O3CPU, "Switching out\n"); 11749429SAndreas.Sandberg@ARM.com BaseCPU::switchOut(); 11759429SAndreas.Sandberg@ARM.com 11769444SAndreas.Sandberg@ARM.com activityRec.reset(); 11772843Sktlim@umich.edu 11782843Sktlim@umich.edu _status = SwitchedOut; 11798887Sgeoffrey.blake@arm.com 11802843Sktlim@umich.edu if (checker) 11812843Sktlim@umich.edu checker->switchOut(); 11821060SN/A} 11831060SN/A 11841060SN/Atemplate <class Impl> 11851060SN/Avoid 11861755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 11871060SN/A{ 11888737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 11891060SN/A 11902307SN/A fetch.takeOverFrom(); 11912307SN/A decode.takeOverFrom(); 11922307SN/A rename.takeOverFrom(); 11932307SN/A iew.takeOverFrom(); 11942307SN/A commit.takeOverFrom(); 11952307SN/A 11969444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 11971060SN/A 11989152Satgutier@umich.edu FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 11999152Satgutier@umich.edu if (oldO3CPU) 12009152Satgutier@umich.edu globalSeqNum = oldO3CPU->globalSeqNum; 12019152Satgutier@umich.edu 12029179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 12039444SAndreas.Sandberg@ARM.com _status = Idle; 12041060SN/A} 12051060SN/A 12061060SN/Atemplate <class Impl> 12079523SAndreas.Sandberg@ARM.comvoid 12089523SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::verifyMemoryMode() const 12099523SAndreas.Sandberg@ARM.com{ 12109524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 12119523SAndreas.Sandberg@ARM.com fatal("The O3 CPU requires the memory system to be in " 12129523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 12139523SAndreas.Sandberg@ARM.com } 12149523SAndreas.Sandberg@ARM.com} 12159523SAndreas.Sandberg@ARM.com 12169523SAndreas.Sandberg@ARM.comtemplate <class Impl> 121713557Sgabeblack@google.comRegVal 121810698Sandreas.hansson@arm.comFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const 12195595Sgblack@eecs.umich.edu{ 12209384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscRegNoEffect(misc_reg); 12215595Sgblack@eecs.umich.edu} 12225595Sgblack@eecs.umich.edu 12235595Sgblack@eecs.umich.edutemplate <class Impl> 122413557Sgabeblack@google.comRegVal 12256221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 12265595Sgblack@eecs.umich.edu{ 12277897Shestness@cs.utexas.edu miscRegfileReads++; 12289384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 12295595Sgblack@eecs.umich.edu} 12305595Sgblack@eecs.umich.edu 12315595Sgblack@eecs.umich.edutemplate <class Impl> 12325595Sgblack@eecs.umich.eduvoid 123313582Sgabeblack@google.comFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) 12345595Sgblack@eecs.umich.edu{ 12359384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 12365595Sgblack@eecs.umich.edu} 12375595Sgblack@eecs.umich.edu 12385595Sgblack@eecs.umich.edutemplate <class Impl> 12395595Sgblack@eecs.umich.eduvoid 124013582Sgabeblack@google.comFullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid) 12415595Sgblack@eecs.umich.edu{ 12427897Shestness@cs.utexas.edu miscRegfileWrites++; 12439384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 12445595Sgblack@eecs.umich.edu} 12455595Sgblack@eecs.umich.edu 12465595Sgblack@eecs.umich.edutemplate <class Impl> 124713557Sgabeblack@google.comRegVal 124812105Snathanael.premillieu@arm.comFullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg) 12491060SN/A{ 12507897Shestness@cs.utexas.edu intRegfileReads++; 125112105Snathanael.premillieu@arm.com return regFile.readIntReg(phys_reg); 12521060SN/A} 12531060SN/A 12541060SN/Atemplate <class Impl> 125513557Sgabeblack@google.comRegVal 125613611Sgabeblack@google.comFullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg) 12572455SN/A{ 12587897Shestness@cs.utexas.edu fpRegfileReads++; 125913611Sgabeblack@google.com return regFile.readFloatReg(phys_reg); 12601060SN/A} 12611060SN/A 12621060SN/Atemplate <class Impl> 126312109SRekai.GonzalezAlberquilla@arm.comauto 126412109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readVecReg(PhysRegIdPtr phys_reg) const 126512109SRekai.GonzalezAlberquilla@arm.com -> const VecRegContainer& 126612109SRekai.GonzalezAlberquilla@arm.com{ 126712109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads++; 126812109SRekai.GonzalezAlberquilla@arm.com return regFile.readVecReg(phys_reg); 126912109SRekai.GonzalezAlberquilla@arm.com} 127012109SRekai.GonzalezAlberquilla@arm.com 127112109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 127212109SRekai.GonzalezAlberquilla@arm.comauto 127312109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::getWritableVecReg(PhysRegIdPtr phys_reg) 127412109SRekai.GonzalezAlberquilla@arm.com -> VecRegContainer& 127512109SRekai.GonzalezAlberquilla@arm.com{ 127612109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 127712109SRekai.GonzalezAlberquilla@arm.com return regFile.getWritableVecReg(phys_reg); 127812109SRekai.GonzalezAlberquilla@arm.com} 127912109SRekai.GonzalezAlberquilla@arm.com 128012109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 128112109SRekai.GonzalezAlberquilla@arm.comauto 128212109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem& 128312109SRekai.GonzalezAlberquilla@arm.com{ 128412109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads++; 128512109SRekai.GonzalezAlberquilla@arm.com return regFile.readVecElem(phys_reg); 128612109SRekai.GonzalezAlberquilla@arm.com} 128712109SRekai.GonzalezAlberquilla@arm.com 128812109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 128913610Sgiacomo.gabrielli@arm.comauto 129013610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::readVecPredReg(PhysRegIdPtr phys_reg) const 129113610Sgiacomo.gabrielli@arm.com -> const VecPredRegContainer& 129213610Sgiacomo.gabrielli@arm.com{ 129313610Sgiacomo.gabrielli@arm.com vecPredRegfileReads++; 129413610Sgiacomo.gabrielli@arm.com return regFile.readVecPredReg(phys_reg); 129513610Sgiacomo.gabrielli@arm.com} 129613610Sgiacomo.gabrielli@arm.com 129713610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 129813610Sgiacomo.gabrielli@arm.comauto 129913610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::getWritableVecPredReg(PhysRegIdPtr phys_reg) 130013610Sgiacomo.gabrielli@arm.com -> VecPredRegContainer& 130113610Sgiacomo.gabrielli@arm.com{ 130213610Sgiacomo.gabrielli@arm.com vecPredRegfileWrites++; 130313610Sgiacomo.gabrielli@arm.com return regFile.getWritableVecPredReg(phys_reg); 130413610Sgiacomo.gabrielli@arm.com} 130513610Sgiacomo.gabrielli@arm.com 130613610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 130713622Sgabeblack@google.comRegVal 130812105Snathanael.premillieu@arm.comFullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg) 13099920Syasuko.eckert@amd.com{ 13109920Syasuko.eckert@amd.com ccRegfileReads++; 131112105Snathanael.premillieu@arm.com return regFile.readCCReg(phys_reg); 13129920Syasuko.eckert@amd.com} 13139920Syasuko.eckert@amd.com 13149920Syasuko.eckert@amd.comtemplate <class Impl> 13151060SN/Avoid 131613557Sgabeblack@google.comFullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val) 13171060SN/A{ 13187897Shestness@cs.utexas.edu intRegfileWrites++; 131912105Snathanael.premillieu@arm.com regFile.setIntReg(phys_reg, val); 13201060SN/A} 13211060SN/A 13221060SN/Atemplate <class Impl> 13231060SN/Avoid 132413611Sgabeblack@google.comFullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, RegVal val) 13252455SN/A{ 13267897Shestness@cs.utexas.edu fpRegfileWrites++; 132713611Sgabeblack@google.com regFile.setFloatReg(phys_reg, val); 13281060SN/A} 13291060SN/A 13301060SN/Atemplate <class Impl> 13319920Syasuko.eckert@amd.comvoid 133212109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) 133312109SRekai.GonzalezAlberquilla@arm.com{ 133412109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 133512109SRekai.GonzalezAlberquilla@arm.com regFile.setVecReg(phys_reg, val); 133612109SRekai.GonzalezAlberquilla@arm.com} 133712109SRekai.GonzalezAlberquilla@arm.com 133812109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 133912109SRekai.GonzalezAlberquilla@arm.comvoid 134012109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val) 134112109SRekai.GonzalezAlberquilla@arm.com{ 134212109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 134312109SRekai.GonzalezAlberquilla@arm.com regFile.setVecElem(phys_reg, val); 134412109SRekai.GonzalezAlberquilla@arm.com} 134512109SRekai.GonzalezAlberquilla@arm.com 134612109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 134712109SRekai.GonzalezAlberquilla@arm.comvoid 134813610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::setVecPredReg(PhysRegIdPtr phys_reg, 134913610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& val) 135013610Sgiacomo.gabrielli@arm.com{ 135113610Sgiacomo.gabrielli@arm.com vecPredRegfileWrites++; 135213610Sgiacomo.gabrielli@arm.com regFile.setVecPredReg(phys_reg, val); 135313610Sgiacomo.gabrielli@arm.com} 135413610Sgiacomo.gabrielli@arm.com 135513610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 135613610Sgiacomo.gabrielli@arm.comvoid 135713622Sgabeblack@google.comFullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, RegVal val) 13589920Syasuko.eckert@amd.com{ 13599920Syasuko.eckert@amd.com ccRegfileWrites++; 136012105Snathanael.premillieu@arm.com regFile.setCCReg(phys_reg, val); 13619920Syasuko.eckert@amd.com} 13629920Syasuko.eckert@amd.com 13639920Syasuko.eckert@amd.comtemplate <class Impl> 136413557Sgabeblack@google.comRegVal 13656221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 13661060SN/A{ 13677897Shestness@cs.utexas.edu intRegfileReads++; 136812106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 136912106SRekai.GonzalezAlberquilla@arm.com RegId(IntRegClass, reg_idx)); 13702292SN/A 13712292SN/A return regFile.readIntReg(phys_reg); 13722292SN/A} 13732292SN/A 13742292SN/Atemplate <class Impl> 137513557Sgabeblack@google.comRegVal 137613611Sgabeblack@google.comFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 13772292SN/A{ 13787897Shestness@cs.utexas.edu fpRegfileReads++; 137912106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 138012106SRekai.GonzalezAlberquilla@arm.com RegId(FloatRegClass, reg_idx)); 13812292SN/A 138213611Sgabeblack@google.com return regFile.readFloatReg(phys_reg); 13831060SN/A} 13841060SN/A 13851060SN/Atemplate <class Impl> 138612109SRekai.GonzalezAlberquilla@arm.comauto 138712109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const 138812109SRekai.GonzalezAlberquilla@arm.com -> const VecRegContainer& 138912109SRekai.GonzalezAlberquilla@arm.com{ 139012109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 139112109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 139212109SRekai.GonzalezAlberquilla@arm.com return readVecReg(phys_reg); 139312109SRekai.GonzalezAlberquilla@arm.com} 139412109SRekai.GonzalezAlberquilla@arm.com 139512109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 139612109SRekai.GonzalezAlberquilla@arm.comauto 139712109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid) 139812109SRekai.GonzalezAlberquilla@arm.com -> VecRegContainer& 139912109SRekai.GonzalezAlberquilla@arm.com{ 140012109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 140112109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 140212109SRekai.GonzalezAlberquilla@arm.com return getWritableVecReg(phys_reg); 140312109SRekai.GonzalezAlberquilla@arm.com} 140412109SRekai.GonzalezAlberquilla@arm.com 140512109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 140612109SRekai.GonzalezAlberquilla@arm.comauto 140712109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 140812109SRekai.GonzalezAlberquilla@arm.com ThreadID tid) const -> const VecElem& 140912109SRekai.GonzalezAlberquilla@arm.com{ 141012109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 141113598Sgiacomo.travaglini@arm.com RegId(VecElemClass, reg_idx, ldx)); 141212109SRekai.GonzalezAlberquilla@arm.com return readVecElem(phys_reg); 141312109SRekai.GonzalezAlberquilla@arm.com} 141412109SRekai.GonzalezAlberquilla@arm.com 141512109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 141613610Sgiacomo.gabrielli@arm.comauto 141713610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::readArchVecPredReg(int reg_idx, ThreadID tid) const 141813610Sgiacomo.gabrielli@arm.com -> const VecPredRegContainer& 141913610Sgiacomo.gabrielli@arm.com{ 142013610Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 142113610Sgiacomo.gabrielli@arm.com RegId(VecPredRegClass, reg_idx)); 142213610Sgiacomo.gabrielli@arm.com return readVecPredReg(phys_reg); 142313610Sgiacomo.gabrielli@arm.com} 142413610Sgiacomo.gabrielli@arm.com 142513610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 142613610Sgiacomo.gabrielli@arm.comauto 142713610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::getWritableArchVecPredReg(int reg_idx, ThreadID tid) 142813610Sgiacomo.gabrielli@arm.com -> VecPredRegContainer& 142913610Sgiacomo.gabrielli@arm.com{ 143013610Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 143113610Sgiacomo.gabrielli@arm.com RegId(VecPredRegClass, reg_idx)); 143213610Sgiacomo.gabrielli@arm.com return getWritableVecPredReg(phys_reg); 143313610Sgiacomo.gabrielli@arm.com} 143413610Sgiacomo.gabrielli@arm.com 143513610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 143613622Sgabeblack@google.comRegVal 14379920Syasuko.eckert@amd.comFullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid) 14389920Syasuko.eckert@amd.com{ 14399920Syasuko.eckert@amd.com ccRegfileReads++; 144012106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 144112106SRekai.GonzalezAlberquilla@arm.com RegId(CCRegClass, reg_idx)); 14429920Syasuko.eckert@amd.com 14439920Syasuko.eckert@amd.com return regFile.readCCReg(phys_reg); 14449920Syasuko.eckert@amd.com} 14459920Syasuko.eckert@amd.com 14469920Syasuko.eckert@amd.comtemplate <class Impl> 14471060SN/Avoid 144813557Sgabeblack@google.comFullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid) 14491060SN/A{ 14507897Shestness@cs.utexas.edu intRegfileWrites++; 145112106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 145212106SRekai.GonzalezAlberquilla@arm.com RegId(IntRegClass, reg_idx)); 14532292SN/A 14542292SN/A regFile.setIntReg(phys_reg, val); 14551060SN/A} 14561060SN/A 14571060SN/Atemplate <class Impl> 14581060SN/Avoid 145913611Sgabeblack@google.comFullO3CPU<Impl>::setArchFloatReg(int reg_idx, RegVal val, ThreadID tid) 14601060SN/A{ 14617897Shestness@cs.utexas.edu fpRegfileWrites++; 146212106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 146312106SRekai.GonzalezAlberquilla@arm.com RegId(FloatRegClass, reg_idx)); 14641060SN/A 146513611Sgabeblack@google.com regFile.setFloatReg(phys_reg, val); 14662292SN/A} 14672292SN/A 14682292SN/Atemplate <class Impl> 14699920Syasuko.eckert@amd.comvoid 147012109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setArchVecReg(int reg_idx, const VecRegContainer& val, 147112109SRekai.GonzalezAlberquilla@arm.com ThreadID tid) 147212109SRekai.GonzalezAlberquilla@arm.com{ 147312109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 147412109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 147512109SRekai.GonzalezAlberquilla@arm.com setVecReg(phys_reg, val); 147612109SRekai.GonzalezAlberquilla@arm.com} 147712109SRekai.GonzalezAlberquilla@arm.com 147812109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 147912109SRekai.GonzalezAlberquilla@arm.comvoid 148012109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 148112109SRekai.GonzalezAlberquilla@arm.com const VecElem& val, ThreadID tid) 148212109SRekai.GonzalezAlberquilla@arm.com{ 148312109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 148413546Sgiacomo.travaglini@arm.com RegId(VecElemClass, reg_idx, ldx)); 148512109SRekai.GonzalezAlberquilla@arm.com setVecElem(phys_reg, val); 148612109SRekai.GonzalezAlberquilla@arm.com} 148712109SRekai.GonzalezAlberquilla@arm.com 148812109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 148912109SRekai.GonzalezAlberquilla@arm.comvoid 149013610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, 149113610Sgiacomo.gabrielli@arm.com ThreadID tid) 149213610Sgiacomo.gabrielli@arm.com{ 149313610Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 149413610Sgiacomo.gabrielli@arm.com RegId(VecPredRegClass, reg_idx)); 149513610Sgiacomo.gabrielli@arm.com setVecPredReg(phys_reg, val); 149613610Sgiacomo.gabrielli@arm.com} 149713610Sgiacomo.gabrielli@arm.com 149813610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 149913610Sgiacomo.gabrielli@arm.comvoid 150013622Sgabeblack@google.comFullO3CPU<Impl>::setArchCCReg(int reg_idx, RegVal val, ThreadID tid) 15019920Syasuko.eckert@amd.com{ 15029920Syasuko.eckert@amd.com ccRegfileWrites++; 150312106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 150412106SRekai.GonzalezAlberquilla@arm.com RegId(CCRegClass, reg_idx)); 15059920Syasuko.eckert@amd.com 15069920Syasuko.eckert@amd.com regFile.setCCReg(phys_reg, val); 15079920Syasuko.eckert@amd.com} 15089920Syasuko.eckert@amd.com 15099920Syasuko.eckert@amd.comtemplate <class Impl> 15107720Sgblack@eecs.umich.eduTheISA::PCState 15117720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 15122292SN/A{ 15137720Sgblack@eecs.umich.edu return commit.pcState(tid); 15141060SN/A} 15151060SN/A 15161060SN/Atemplate <class Impl> 15171060SN/Avoid 15187720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 15191060SN/A{ 15207720Sgblack@eecs.umich.edu commit.pcState(val, tid); 15212292SN/A} 15221060SN/A 15232292SN/Atemplate <class Impl> 15247720Sgblack@eecs.umich.eduAddr 15257720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 15264636Sgblack@eecs.umich.edu{ 15277720Sgblack@eecs.umich.edu return commit.instAddr(tid); 15284636Sgblack@eecs.umich.edu} 15294636Sgblack@eecs.umich.edu 15304636Sgblack@eecs.umich.edutemplate <class Impl> 15317720Sgblack@eecs.umich.eduAddr 15327720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 15334636Sgblack@eecs.umich.edu{ 15347720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 15354636Sgblack@eecs.umich.edu} 15364636Sgblack@eecs.umich.edu 15374636Sgblack@eecs.umich.edutemplate <class Impl> 15387720Sgblack@eecs.umich.eduMicroPC 15397720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 15402292SN/A{ 15417720Sgblack@eecs.umich.edu return commit.microPC(tid); 15424636Sgblack@eecs.umich.edu} 15434636Sgblack@eecs.umich.edu 15444636Sgblack@eecs.umich.edutemplate <class Impl> 15455595Sgblack@eecs.umich.eduvoid 15466221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 15475595Sgblack@eecs.umich.edu{ 15489382SAli.Saidi@ARM.com this->thread[tid]->noSquashFromTC = true; 15495595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 15505595Sgblack@eecs.umich.edu} 15515595Sgblack@eecs.umich.edu 15525595Sgblack@eecs.umich.edutemplate <class Impl> 15532292SN/Atypename FullO3CPU<Impl>::ListIt 155413429Srekai.gonzalezalberquilla@arm.comFullO3CPU<Impl>::addInst(const DynInstPtr &inst) 15552292SN/A{ 15562292SN/A instList.push_back(inst); 15571060SN/A 15582292SN/A return --(instList.end()); 15592292SN/A} 15601060SN/A 15612292SN/Atemplate <class Impl> 15622292SN/Avoid 156313429Srekai.gonzalezalberquilla@arm.comFullO3CPU<Impl>::instDone(ThreadID tid, const DynInstPtr &inst) 15642292SN/A{ 15652292SN/A // Keep an instruction count. 15668834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 15678834Satgutier@umich.edu thread[tid]->numInst++; 15688834Satgutier@umich.edu thread[tid]->numInsts++; 15698834Satgutier@umich.edu committedInsts[tid]++; 157010774Snikos.nikoleris@gmail.com system->totalNumInsts++; 157110774Snikos.nikoleris@gmail.com 157210774Snikos.nikoleris@gmail.com // Check for instruction-count-based events. 157310774Snikos.nikoleris@gmail.com comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 157410774Snikos.nikoleris@gmail.com system->instEventQueue.serviceEvents(system->totalNumInsts); 15758834Satgutier@umich.edu } 15768834Satgutier@umich.edu thread[tid]->numOp++; 15778834Satgutier@umich.edu thread[tid]->numOps++; 15788834Satgutier@umich.edu committedOps[tid]++; 15798834Satgutier@umich.edu 158013818Sjavier.bueno@metempsy.com probeInstCommit(inst->staticInst, inst->instAddr()); 15812292SN/A} 15822292SN/A 15832292SN/Atemplate <class Impl> 15842292SN/Avoid 158513429Srekai.gonzalezalberquilla@arm.comFullO3CPU<Impl>::removeFrontInst(const DynInstPtr &inst) 15861060SN/A{ 15877720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 15882292SN/A "[sn:%lli]\n", 15897720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 15901060SN/A 15912292SN/A removeInstsThisCycle = true; 15921060SN/A 15931060SN/A // Remove the front instruction. 15942292SN/A removeList.push(inst->getInstListIt()); 15951060SN/A} 15961060SN/A 15971060SN/Atemplate <class Impl> 15981060SN/Avoid 15996221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 16001060SN/A{ 16012733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 16022292SN/A " list.\n", tid); 16031060SN/A 16042292SN/A ListIt end_it; 16051060SN/A 16062292SN/A bool rob_empty = false; 16072292SN/A 16082292SN/A if (instList.empty()) { 16092292SN/A return; 161010164Ssleimanf@umich.edu } else if (rob.isEmpty(tid)) { 16112733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 16122292SN/A end_it = instList.begin(); 16132292SN/A rob_empty = true; 16142292SN/A } else { 16152292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 16162733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 16172292SN/A } 16182292SN/A 16192292SN/A removeInstsThisCycle = true; 16202292SN/A 16212292SN/A ListIt inst_it = instList.end(); 16222292SN/A 16232292SN/A inst_it--; 16242292SN/A 16252292SN/A // Walk through the instruction list, removing any instructions 16262292SN/A // that were inserted after the given instruction iterator, end_it. 16272292SN/A while (inst_it != end_it) { 16282292SN/A assert(!instList.empty()); 16292292SN/A 16302292SN/A squashInstIt(inst_it, tid); 16312292SN/A 16322292SN/A inst_it--; 16332292SN/A } 16342292SN/A 16352292SN/A // If the ROB was empty, then we actually need to remove the first 16362292SN/A // instruction as well. 16372292SN/A if (rob_empty) { 16382292SN/A squashInstIt(inst_it, tid); 16392292SN/A } 16401060SN/A} 16411060SN/A 16421060SN/Atemplate <class Impl> 16431060SN/Avoid 16446221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 16451062SN/A{ 16462292SN/A assert(!instList.empty()); 16472292SN/A 16482292SN/A removeInstsThisCycle = true; 16492292SN/A 16502292SN/A ListIt inst_iter = instList.end(); 16512292SN/A 16522292SN/A inst_iter--; 16532292SN/A 16542733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 16552292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 16562292SN/A tid, seq_num, (*inst_iter)->seqNum); 16571062SN/A 16582292SN/A while ((*inst_iter)->seqNum > seq_num) { 16591062SN/A 16602292SN/A bool break_loop = (inst_iter == instList.begin()); 16611062SN/A 16622292SN/A squashInstIt(inst_iter, tid); 16631062SN/A 16642292SN/A inst_iter--; 16651062SN/A 16662292SN/A if (break_loop) 16672292SN/A break; 16682292SN/A } 16692292SN/A} 16702292SN/A 16712292SN/Atemplate <class Impl> 16722292SN/Ainline void 16736221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 16742292SN/A{ 16752292SN/A if ((*instIt)->threadNumber == tid) { 16762733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 16777720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 16782292SN/A (*instIt)->threadNumber, 16792292SN/A (*instIt)->seqNum, 16807720Sgblack@eecs.umich.edu (*instIt)->pcState()); 16811062SN/A 16821062SN/A // Mark it as squashed. 16832292SN/A (*instIt)->setSquashed(); 16842292SN/A 16852325SN/A // @todo: Formulate a consistent method for deleting 16862325SN/A // instructions from the instruction list 16872292SN/A // Remove the instruction from the list. 16882292SN/A removeList.push(instIt); 16892292SN/A } 16902292SN/A} 16912292SN/A 16922292SN/Atemplate <class Impl> 16932292SN/Avoid 16942292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 16952292SN/A{ 16962292SN/A while (!removeList.empty()) { 16972733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 16987720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 16992292SN/A (*removeList.front())->threadNumber, 17002292SN/A (*removeList.front())->seqNum, 17017720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 17022292SN/A 17032292SN/A instList.erase(removeList.front()); 17042292SN/A 17052292SN/A removeList.pop(); 17061062SN/A } 17071062SN/A 17082292SN/A removeInstsThisCycle = false; 17091062SN/A} 17102325SN/A/* 17111062SN/Atemplate <class Impl> 17121062SN/Avoid 17131755SN/AFullO3CPU<Impl>::removeAllInsts() 17141060SN/A{ 17151060SN/A instList.clear(); 17161060SN/A} 17172325SN/A*/ 17181060SN/Atemplate <class Impl> 17191060SN/Avoid 17201755SN/AFullO3CPU<Impl>::dumpInsts() 17211060SN/A{ 17221060SN/A int num = 0; 17231060SN/A 17242292SN/A ListIt inst_list_it = instList.begin(); 17252292SN/A 17262292SN/A cprintf("Dumping Instruction List\n"); 17272292SN/A 17282292SN/A while (inst_list_it != instList.end()) { 17292292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 17302292SN/A "Squashed:%i\n\n", 17317720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 17322292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 17332292SN/A (*inst_list_it)->isSquashed()); 17341060SN/A inst_list_it++; 17351060SN/A ++num; 17361060SN/A } 17371060SN/A} 17382325SN/A/* 17391060SN/Atemplate <class Impl> 17401060SN/Avoid 174113429Srekai.gonzalezalberquilla@arm.comFullO3CPU<Impl>::wakeDependents(const DynInstPtr &inst) 17421060SN/A{ 17431060SN/A iew.wakeDependents(inst); 17441060SN/A} 17452325SN/A*/ 17462292SN/Atemplate <class Impl> 17472292SN/Avoid 17482292SN/AFullO3CPU<Impl>::wakeCPU() 17492292SN/A{ 17502325SN/A if (activityRec.active() || tickEvent.scheduled()) { 17512325SN/A DPRINTF(Activity, "CPU already running.\n"); 17522292SN/A return; 17532292SN/A } 17542292SN/A 17552325SN/A DPRINTF(Activity, "Waking up CPU\n"); 17562325SN/A 17579180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 17589180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 175910464SAndreas.Sandberg@ARM.com if (cycles > 1) { 17609179Sandreas.hansson@arm.com --cycles; 176110464SAndreas.Sandberg@ARM.com idleCycles += cycles; 176210464SAndreas.Sandberg@ARM.com numCycles += cycles; 176310464SAndreas.Sandberg@ARM.com } 17642292SN/A 17659648Sdam.sunwoo@arm.com schedule(tickEvent, clockEdge()); 17662292SN/A} 17672292SN/A 17685807Snate@binkert.orgtemplate <class Impl> 17695807Snate@binkert.orgvoid 177011151Smitch.hayenga@arm.comFullO3CPU<Impl>::wakeup(ThreadID tid) 17715807Snate@binkert.org{ 177211151Smitch.hayenga@arm.com if (this->thread[tid]->status() != ThreadContext::Suspended) 17735807Snate@binkert.org return; 17745807Snate@binkert.org 17755807Snate@binkert.org this->wakeCPU(); 17765807Snate@binkert.org 17775807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 177811151Smitch.hayenga@arm.com this->threadContexts[tid]->activate(); 17795807Snate@binkert.org} 17805807Snate@binkert.org 17812292SN/Atemplate <class Impl> 17826221Snate@binkert.orgThreadID 17832292SN/AFullO3CPU<Impl>::getFreeTid() 17842292SN/A{ 17856221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 17866221Snate@binkert.org if (!tids[tid]) { 17876221Snate@binkert.org tids[tid] = true; 17886221Snate@binkert.org return tid; 17892292SN/A } 17902292SN/A } 17912292SN/A 17926221Snate@binkert.org return InvalidThreadID; 17932292SN/A} 17942292SN/A 17952292SN/Atemplate <class Impl> 17962292SN/Avoid 17972292SN/AFullO3CPU<Impl>::updateThreadPriority() 17982292SN/A{ 17996221Snate@binkert.org if (activeThreads.size() > 1) { 18002292SN/A //DEFAULT TO ROUND ROBIN SCHEME 18012292SN/A //e.g. Move highest priority to end of thread list 18026221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 18032292SN/A 18042292SN/A unsigned high_thread = *list_begin; 18052292SN/A 18062292SN/A activeThreads.erase(list_begin); 18072292SN/A 18082292SN/A activeThreads.push_back(high_thread); 18092292SN/A } 18102292SN/A} 18111060SN/A 181213641Sqtt2@cornell.edutemplate <class Impl> 181313641Sqtt2@cornell.eduvoid 181413641Sqtt2@cornell.eduFullO3CPU<Impl>::addThreadToExitingList(ThreadID tid) 181513641Sqtt2@cornell.edu{ 181613641Sqtt2@cornell.edu DPRINTF(O3CPU, "Thread %d is inserted to exitingThreads list\n", tid); 181713641Sqtt2@cornell.edu 181813644Sqtt2@cornell.edu // the thread trying to exit can't be already halted 181913644Sqtt2@cornell.edu assert(tcBase(tid)->status() != ThreadContext::Halted); 182013641Sqtt2@cornell.edu 182113641Sqtt2@cornell.edu // make sure the thread has not been added to the list yet 182213641Sqtt2@cornell.edu assert(exitingThreads.count(tid) == 0); 182313641Sqtt2@cornell.edu 182413641Sqtt2@cornell.edu // add the thread to exitingThreads list to mark that this thread is 182513641Sqtt2@cornell.edu // trying to exit. The boolean value in the pair denotes if a thread is 182613641Sqtt2@cornell.edu // ready to exit. The thread is not ready to exit until the corresponding 182713641Sqtt2@cornell.edu // exit trap event is processed in the future. Until then, it'll be still 182813641Sqtt2@cornell.edu // an active thread that is trying to exit. 182913641Sqtt2@cornell.edu exitingThreads.emplace(std::make_pair(tid, false)); 183013641Sqtt2@cornell.edu} 183113641Sqtt2@cornell.edu 183213641Sqtt2@cornell.edutemplate <class Impl> 183313641Sqtt2@cornell.edubool 183413641Sqtt2@cornell.eduFullO3CPU<Impl>::isThreadExiting(ThreadID tid) const 183513641Sqtt2@cornell.edu{ 183613641Sqtt2@cornell.edu return exitingThreads.count(tid) == 1; 183713641Sqtt2@cornell.edu} 183813641Sqtt2@cornell.edu 183913641Sqtt2@cornell.edutemplate <class Impl> 184013641Sqtt2@cornell.eduvoid 184113641Sqtt2@cornell.eduFullO3CPU<Impl>::scheduleThreadExitEvent(ThreadID tid) 184213641Sqtt2@cornell.edu{ 184313641Sqtt2@cornell.edu assert(exitingThreads.count(tid) == 1); 184413641Sqtt2@cornell.edu 184513641Sqtt2@cornell.edu // exit trap event has been processed. Now, the thread is ready to exit 184613641Sqtt2@cornell.edu // and be removed from the CPU. 184713641Sqtt2@cornell.edu exitingThreads[tid] = true; 184813641Sqtt2@cornell.edu 184913641Sqtt2@cornell.edu // we schedule a threadExitEvent in the next cycle to properly clean 185013641Sqtt2@cornell.edu // up the thread's states in the pipeline. threadExitEvent has lower 185113641Sqtt2@cornell.edu // priority than tickEvent, so the cleanup will happen at the very end 185213641Sqtt2@cornell.edu // of the next cycle after all pipeline stages complete their operations. 185313641Sqtt2@cornell.edu // We want all stages to complete squashing instructions before doing 185413641Sqtt2@cornell.edu // the cleanup. 185513641Sqtt2@cornell.edu if (!threadExitEvent.scheduled()) { 185613641Sqtt2@cornell.edu schedule(threadExitEvent, nextCycle()); 185713641Sqtt2@cornell.edu } 185813641Sqtt2@cornell.edu} 185913641Sqtt2@cornell.edu 186013641Sqtt2@cornell.edutemplate <class Impl> 186113641Sqtt2@cornell.eduvoid 186213641Sqtt2@cornell.eduFullO3CPU<Impl>::exitThreads() 186313641Sqtt2@cornell.edu{ 186413641Sqtt2@cornell.edu // there must be at least one thread trying to exit 186513641Sqtt2@cornell.edu assert(exitingThreads.size() > 0); 186613641Sqtt2@cornell.edu 186713641Sqtt2@cornell.edu // terminate all threads that are ready to exit 186813641Sqtt2@cornell.edu auto it = exitingThreads.begin(); 186913641Sqtt2@cornell.edu while (it != exitingThreads.end()) { 187013641Sqtt2@cornell.edu ThreadID thread_id = it->first; 187113641Sqtt2@cornell.edu bool readyToExit = it->second; 187213641Sqtt2@cornell.edu 187313641Sqtt2@cornell.edu if (readyToExit) { 187413641Sqtt2@cornell.edu DPRINTF(O3CPU, "Exiting thread %d\n", thread_id); 187513641Sqtt2@cornell.edu haltContext(thread_id); 187613641Sqtt2@cornell.edu tcBase(thread_id)->setStatus(ThreadContext::Halted); 187713641Sqtt2@cornell.edu it = exitingThreads.erase(it); 187813641Sqtt2@cornell.edu } else { 187913641Sqtt2@cornell.edu it++; 188013641Sqtt2@cornell.edu } 188113641Sqtt2@cornell.edu } 188213641Sqtt2@cornell.edu} 188313641Sqtt2@cornell.edu 18841755SN/A// Forward declaration of FullO3CPU. 18852818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1886