cpu.cc revision 13610
11689SN/A/* 213601Sgiacomo.travaglini@arm.com * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019 ARM Limited 39916Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 152325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 167897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432756Sksewell@umich.edu * Korey Sewell 447897Shestness@cs.utexas.edu * Rick Strong 451689SN/A */ 461689SN/A 4711793Sbrandon.potter@amd.com#include "cpu/o3/cpu.hh" 4811793Sbrandon.potter@amd.com 4912109SRekai.GonzalezAlberquilla@arm.com#include "arch/generic/traits.hh" 508779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 516658Snate@binkert.org#include "config/the_isa.hh" 5211793Sbrandon.potter@amd.com#include "cpu/activity.hh" 538887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 548887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 558229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 568229Snate@binkert.org#include "cpu/o3/thread_context.hh" 578779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 584762Snate@binkert.org#include "cpu/simple_thread.hh" 594762Snate@binkert.org#include "cpu/thread_context.hh" 608232Snate@binkert.org#include "debug/Activity.hh" 619152Satgutier@umich.edu#include "debug/Drain.hh" 628232Snate@binkert.org#include "debug/O3CPU.hh" 638232Snate@binkert.org#include "debug/Quiesce.hh" 644762Snate@binkert.org#include "enums/MemoryMode.hh" 654762Snate@binkert.org#include "sim/core.hh" 668793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 678779Sgblack@eecs.umich.edu#include "sim/process.hh" 684762Snate@binkert.org#include "sim/stat_control.hh" 698460SAli.Saidi@ARM.com#include "sim/system.hh" 704762Snate@binkert.org 715702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 725702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 738232Snate@binkert.org#include "debug/Activity.hh" 7411793Sbrandon.potter@amd.com 755702Ssaidi@eecs.umich.edu#endif 765702Ssaidi@eecs.umich.edu 778737Skoansin.tan@gmail.comstruct BaseCPUParams; 785529Snate@binkert.org 792669Sktlim@umich.eduusing namespace TheISA; 806221Snate@binkert.orgusing namespace std; 811060SN/A 825529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 835712Shsul@eecs.umich.edu : BaseCPU(params) 841060SN/A{ 851060SN/A} 861060SN/A 872292SN/Avoid 882733Sktlim@umich.eduBaseO3CPU::regStats() 892292SN/A{ 902292SN/A BaseCPU::regStats(); 912292SN/A} 922292SN/A 938707Sandreas.hansson@arm.comtemplate<class Impl> 948707Sandreas.hansson@arm.combool 958975Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 968707Sandreas.hansson@arm.com{ 978707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 9811284Sandreas.hansson@arm.com // We shouldn't ever get a cacheable block in Modified state 9910821Sandreas.hansson@arm.com assert(pkt->req->isUncacheable() || 10011284Sandreas.hansson@arm.com !(pkt->cacheResponding() && !pkt->hasSharers())); 1018948Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 1028707Sandreas.hansson@arm.com 1038707Sandreas.hansson@arm.com return true; 1048707Sandreas.hansson@arm.com} 1058707Sandreas.hansson@arm.com 1068707Sandreas.hansson@arm.comtemplate<class Impl> 1078707Sandreas.hansson@arm.comvoid 10810713Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvReqRetry() 1098707Sandreas.hansson@arm.com{ 11010713Sandreas.hansson@arm.com fetch->recvReqRetry(); 1118707Sandreas.hansson@arm.com} 1128707Sandreas.hansson@arm.com 1138707Sandreas.hansson@arm.comtemplate <class Impl> 1148707Sandreas.hansson@arm.combool 1158975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 1168707Sandreas.hansson@arm.com{ 1178975Sandreas.hansson@arm.com return lsq->recvTimingResp(pkt); 1188707Sandreas.hansson@arm.com} 1198707Sandreas.hansson@arm.com 1208707Sandreas.hansson@arm.comtemplate <class Impl> 1218975Sandreas.hansson@arm.comvoid 1228975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 1238948Sandreas.hansson@arm.com{ 12411148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 12511148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 12611151Smitch.hayenga@arm.com cpu->wakeup(tid); 12711148Smitch.hayenga@arm.com } 12810529Smorr@cs.wisc.edu } 1298975Sandreas.hansson@arm.com lsq->recvTimingSnoopReq(pkt); 1308948Sandreas.hansson@arm.com} 1318948Sandreas.hansson@arm.com 1328948Sandreas.hansson@arm.comtemplate <class Impl> 1338707Sandreas.hansson@arm.comvoid 13410713Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvReqRetry() 1358707Sandreas.hansson@arm.com{ 13610713Sandreas.hansson@arm.com lsq->recvReqRetry(); 1378707Sandreas.hansson@arm.com} 1388707Sandreas.hansson@arm.com 1391060SN/Atemplate <class Impl> 1405595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1412733Sktlim@umich.edu : BaseO3CPU(params), 1423781Sgblack@eecs.umich.edu itb(params->itb), 1433781Sgblack@eecs.umich.edu dtb(params->dtb), 14412127Sspwilson2@wisc.edu tickEvent([this]{ tick(); }, "FullO3CPU tick", 14512127Sspwilson2@wisc.edu false, Event::CPU_Tick_Pri), 1465737Scws3k@cs.virginia.edu#ifndef NDEBUG 1475737Scws3k@cs.virginia.edu instcount(0), 1485737Scws3k@cs.virginia.edu#endif 1492292SN/A removeInstsThisCycle(false), 1505595Sgblack@eecs.umich.edu fetch(this, params), 1515595Sgblack@eecs.umich.edu decode(this, params), 1525595Sgblack@eecs.umich.edu rename(this, params), 1535595Sgblack@eecs.umich.edu iew(this, params), 1545595Sgblack@eecs.umich.edu commit(this, params), 1551060SN/A 15612109SRekai.GonzalezAlberquilla@arm.com /* It is mandatory that all SMT threads use the same renaming mode as 15712109SRekai.GonzalezAlberquilla@arm.com * they are sharing registers and rename */ 15813601Sgiacomo.travaglini@arm.com vecMode(RenameMode<TheISA::ISA>::init(params->isa[0])), 1599915Ssteve.reinhardt@amd.com regFile(params->numPhysIntRegs, 1609920Syasuko.eckert@amd.com params->numPhysFloatRegs, 16112109SRekai.GonzalezAlberquilla@arm.com params->numPhysVecRegs, 16213610Sgiacomo.gabrielli@arm.com params->numPhysVecPredRegs, 16312109SRekai.GonzalezAlberquilla@arm.com params->numPhysCCRegs, 16412109SRekai.GonzalezAlberquilla@arm.com vecMode), 1651060SN/A 1669919Ssteve.reinhardt@amd.com freeList(name() + ".freelist", ®File), 1671060SN/A 1689954SFaissal.Sleiman@arm.com rob(this, params), 1691060SN/A 1709916Ssteve.reinhardt@amd.com scoreboard(name() + ".scoreboard", 17112105Snathanael.premillieu@arm.com regFile.totalNumPhysRegs()), 1721060SN/A 1739384SAndreas.Sandberg@arm.com isa(numThreads, NULL), 1749384SAndreas.Sandberg@arm.com 1758707Sandreas.hansson@arm.com icachePort(&fetch, this), 1768707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 1778707Sandreas.hansson@arm.com 1782873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1792873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1802873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1812873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1822873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1835804Snate@binkert.org activityRec(name(), NumStages, 1842873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1852873Sktlim@umich.edu params->activity), 1861060SN/A 1871060SN/A globalSeqNum(1), 1882292SN/A system(params->system), 1899180Sandreas.hansson@arm.com lastRunningCycle(curCycle()) 1901060SN/A{ 1919433SAndreas.Sandberg@ARM.com if (!params->switched_out) { 1923221Sktlim@umich.edu _status = Running; 1933221Sktlim@umich.edu } else { 1949152Satgutier@umich.edu _status = SwitchedOut; 1953221Sktlim@umich.edu } 1961681SN/A 1972794Sktlim@umich.edu if (params->checker) { 1982316SN/A BaseCPU *temp_checker = params->checker; 1998733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 2008707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2012316SN/A checker->setSystem(params->system); 2024598Sbinkertn@umich.edu } else { 2034598Sbinkertn@umich.edu checker = NULL; 2044598Sbinkertn@umich.edu } 2052316SN/A 2068793Sgblack@eecs.umich.edu if (!FullSystem) { 2078793Sgblack@eecs.umich.edu thread.resize(numThreads); 2088793Sgblack@eecs.umich.edu tids.resize(numThreads); 2098793Sgblack@eecs.umich.edu } 2101681SN/A 2112325SN/A // The stages also need their CPU pointer setup. However this 2122325SN/A // must be done at the upper level CPU because they have pointers 2132325SN/A // to the upper level CPU, and not this FullO3CPU. 2141060SN/A 2152292SN/A // Set up Pointers to the activeThreads list for each stage 2162292SN/A fetch.setActiveThreads(&activeThreads); 2172292SN/A decode.setActiveThreads(&activeThreads); 2182292SN/A rename.setActiveThreads(&activeThreads); 2192292SN/A iew.setActiveThreads(&activeThreads); 2202292SN/A commit.setActiveThreads(&activeThreads); 2211060SN/A 2221060SN/A // Give each of the stages the time buffer they will use. 2231060SN/A fetch.setTimeBuffer(&timeBuffer); 2241060SN/A decode.setTimeBuffer(&timeBuffer); 2251060SN/A rename.setTimeBuffer(&timeBuffer); 2261060SN/A iew.setTimeBuffer(&timeBuffer); 2271060SN/A commit.setTimeBuffer(&timeBuffer); 2281060SN/A 2291060SN/A // Also setup each of the stages' queues. 2301060SN/A fetch.setFetchQueue(&fetchQueue); 2311060SN/A decode.setFetchQueue(&fetchQueue); 2322292SN/A commit.setFetchQueue(&fetchQueue); 2331060SN/A decode.setDecodeQueue(&decodeQueue); 2341060SN/A rename.setDecodeQueue(&decodeQueue); 2351060SN/A rename.setRenameQueue(&renameQueue); 2361060SN/A iew.setRenameQueue(&renameQueue); 2371060SN/A iew.setIEWQueue(&iewQueue); 2381060SN/A commit.setIEWQueue(&iewQueue); 2391060SN/A commit.setRenameQueue(&renameQueue); 2401060SN/A 2412292SN/A commit.setIEWStage(&iew); 2422292SN/A rename.setIEWStage(&iew); 2432292SN/A rename.setCommitStage(&commit); 2442292SN/A 2458793Sgblack@eecs.umich.edu ThreadID active_threads; 2468793Sgblack@eecs.umich.edu if (FullSystem) { 2478793Sgblack@eecs.umich.edu active_threads = 1; 2488793Sgblack@eecs.umich.edu } else { 2498793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 2502831Sksewell@umich.edu 2518793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 2528793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 2538793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 2548793Sgblack@eecs.umich.edu "or edit your workload size."); 2558793Sgblack@eecs.umich.edu } 2562831Sksewell@umich.edu } 2572292SN/A 2582316SN/A //Make Sure That this a Valid Architeture 2592292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2602292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 26112109SRekai.GonzalezAlberquilla@arm.com assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs); 26213610Sgiacomo.gabrielli@arm.com assert(params->numPhysVecPredRegs >= numThreads * TheISA::NumVecPredRegs); 2639920Syasuko.eckert@amd.com assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs); 2642292SN/A 2652292SN/A rename.setScoreboard(&scoreboard); 2662292SN/A iew.setScoreboard(&scoreboard); 2672292SN/A 2681060SN/A // Setup the rename map for whichever stages need it. 2696221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2709384SAndreas.Sandberg@arm.com isa[tid] = params->isa[tid]; 27113601Sgiacomo.travaglini@arm.com assert(RenameMode<TheISA::ISA>::equalsInit(isa[tid], isa[0])); 2729384SAndreas.Sandberg@arm.com 2739919Ssteve.reinhardt@amd.com // Only Alpha has an FP zero register, so for other ISAs we 2749919Ssteve.reinhardt@amd.com // use an invalid FP register index to avoid special treatment 2759919Ssteve.reinhardt@amd.com // of any valid FP reg. 2769919Ssteve.reinhardt@amd.com RegIndex invalidFPReg = TheISA::NumFloatRegs + 1; 2779919Ssteve.reinhardt@amd.com RegIndex fpZeroReg = 2789919Ssteve.reinhardt@amd.com (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg; 2792292SN/A 2809919Ssteve.reinhardt@amd.com commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 28112109SRekai.GonzalezAlberquilla@arm.com &freeList, 28212109SRekai.GonzalezAlberquilla@arm.com vecMode); 2832292SN/A 2849919Ssteve.reinhardt@amd.com renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 28512109SRekai.GonzalezAlberquilla@arm.com &freeList, vecMode); 2862292SN/A } 2872292SN/A 2889919Ssteve.reinhardt@amd.com // Initialize rename map to assign physical registers to the 2899919Ssteve.reinhardt@amd.com // architectural registers for active threads only. 2909919Ssteve.reinhardt@amd.com for (ThreadID tid = 0; tid < active_threads; tid++) { 2919919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) { 2929919Ssteve.reinhardt@amd.com // Note that we can't use the rename() method because we don't 2939919Ssteve.reinhardt@amd.com // want special treatment for the zero register at this point 29412105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getIntReg(); 29512106SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg); 29612106SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg); 2979919Ssteve.reinhardt@amd.com } 2989919Ssteve.reinhardt@amd.com 2999919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) { 30012105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getFloatReg(); 30112106SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg); 30212106SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry( 30312106SRekai.GonzalezAlberquilla@arm.com RegId(FloatRegClass, ridx), phys_reg); 3049919Ssteve.reinhardt@amd.com } 3059920Syasuko.eckert@amd.com 30612109SRekai.GonzalezAlberquilla@arm.com /* Here we need two 'interfaces' the 'whole register' and the 30712109SRekai.GonzalezAlberquilla@arm.com * 'register element'. At any point only one of them will be 30812109SRekai.GonzalezAlberquilla@arm.com * active. */ 30912109SRekai.GonzalezAlberquilla@arm.com if (vecMode == Enums::Full) { 31012109SRekai.GonzalezAlberquilla@arm.com /* Initialize the full-vector interface */ 31112109SRekai.GonzalezAlberquilla@arm.com for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) { 31212109SRekai.GonzalezAlberquilla@arm.com RegId rid = RegId(VecRegClass, ridx); 31312109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = freeList.getVecReg(); 31412109SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(rid, phys_reg); 31512109SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(rid, phys_reg); 31612109SRekai.GonzalezAlberquilla@arm.com } 31712109SRekai.GonzalezAlberquilla@arm.com } else { 31812109SRekai.GonzalezAlberquilla@arm.com /* Initialize the vector-element interface */ 31912109SRekai.GonzalezAlberquilla@arm.com for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) { 32012109SRekai.GonzalezAlberquilla@arm.com for (ElemIndex ldx = 0; ldx < TheISA::NumVecElemPerVecReg; 32112109SRekai.GonzalezAlberquilla@arm.com ++ldx) { 32212109SRekai.GonzalezAlberquilla@arm.com RegId lrid = RegId(VecElemClass, ridx, ldx); 32312109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_elem = freeList.getVecElem(); 32412109SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(lrid, phys_elem); 32512109SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(lrid, phys_elem); 32612109SRekai.GonzalezAlberquilla@arm.com } 32712109SRekai.GonzalezAlberquilla@arm.com } 32812109SRekai.GonzalezAlberquilla@arm.com } 32912109SRekai.GonzalezAlberquilla@arm.com 33013610Sgiacomo.gabrielli@arm.com for (RegIndex ridx = 0; ridx < TheISA::NumVecPredRegs; ++ridx) { 33113610Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_reg = freeList.getVecPredReg(); 33213610Sgiacomo.gabrielli@arm.com renameMap[tid].setEntry(RegId(VecPredRegClass, ridx), phys_reg); 33313610Sgiacomo.gabrielli@arm.com commitRenameMap[tid].setEntry( 33413610Sgiacomo.gabrielli@arm.com RegId(VecPredRegClass, ridx), phys_reg); 33513610Sgiacomo.gabrielli@arm.com } 33613610Sgiacomo.gabrielli@arm.com 3379920Syasuko.eckert@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) { 33812105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getCCReg(); 33912106SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg); 34012106SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg); 3419920Syasuko.eckert@amd.com } 3429919Ssteve.reinhardt@amd.com } 3439919Ssteve.reinhardt@amd.com 3442292SN/A rename.setRenameMap(renameMap); 3452292SN/A commit.setRenameMap(commitRenameMap); 3461060SN/A rename.setFreeList(&freeList); 3472292SN/A 3481060SN/A // Setup the ROB for whichever stages need it. 3491060SN/A commit.setROB(&rob); 3502292SN/A 3519158Sandreas.hansson@arm.com lastActivatedCycle = 0; 3526221Snate@binkert.org#if 0 3533093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3546221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3556221Snate@binkert.org globalSeqNum[tid] = 1; 3566221Snate@binkert.org#endif 3573093Sksewell@umich.edu 3585595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3595595Sgblack@eecs.umich.edu 3605595Sgblack@eecs.umich.edu // Setup any thread state. 3615595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3625595Sgblack@eecs.umich.edu 3636221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 3648793Sgblack@eecs.umich.edu if (FullSystem) { 3658793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3668793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3678793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 3688793Sgblack@eecs.umich.edu } else { 3698793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 3708793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3718793Sgblack@eecs.umich.edu tid, this->thread[tid]); 3728793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3738793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3748793Sgblack@eecs.umich.edu tid, params->workload[tid]); 3755595Sgblack@eecs.umich.edu 3768793Sgblack@eecs.umich.edu //usedTids[tid] = true; 3778793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 3788793Sgblack@eecs.umich.edu } else { 3798793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3808793Sgblack@eecs.umich.edu //when scheduling threads to CPU 3818793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3825595Sgblack@eecs.umich.edu 3838793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3848793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3858793Sgblack@eecs.umich.edu tid, dummy_proc); 3868793Sgblack@eecs.umich.edu //usedTids[tid] = false; 3878793Sgblack@eecs.umich.edu } 3885595Sgblack@eecs.umich.edu } 3895595Sgblack@eecs.umich.edu 3905595Sgblack@eecs.umich.edu ThreadContext *tc; 3915595Sgblack@eecs.umich.edu 3925595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3935595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3945595Sgblack@eecs.umich.edu 3955595Sgblack@eecs.umich.edu tc = o3_tc; 3965595Sgblack@eecs.umich.edu 3975595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3985595Sgblack@eecs.umich.edu // CheckerThreadContext. 3995595Sgblack@eecs.umich.edu if (params->checker) { 4005595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 4015595Sgblack@eecs.umich.edu o3_tc, this->checker); 4025595Sgblack@eecs.umich.edu } 4035595Sgblack@eecs.umich.edu 4045595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 4055595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 4066221Snate@binkert.org o3_tc->thread = this->thread[tid]; 4075595Sgblack@eecs.umich.edu 40811627Smichael.lebeane@amd.com // Setup quiesce event. 40911627Smichael.lebeane@amd.com this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 41011627Smichael.lebeane@amd.com 4115595Sgblack@eecs.umich.edu // Give the thread the TC. 4126221Snate@binkert.org this->thread[tid]->tc = tc; 4135595Sgblack@eecs.umich.edu 4145595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4155595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4165595Sgblack@eecs.umich.edu } 4175595Sgblack@eecs.umich.edu 4188876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 41911150Smitch.hayenga@arm.com if (!params->switched_out && interrupts.empty()) { 4208876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 4218876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 4228876Sandreas.hansson@arm.com } 4238876Sandreas.hansson@arm.com 4246221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4256221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4261060SN/A} 4271060SN/A 4281060SN/Atemplate <class Impl> 4291755SN/AFullO3CPU<Impl>::~FullO3CPU() 4301060SN/A{ 4311060SN/A} 4321060SN/A 4331060SN/Atemplate <class Impl> 4341060SN/Avoid 43510023Smatt.horsnell@ARM.comFullO3CPU<Impl>::regProbePoints() 43610023Smatt.horsnell@ARM.com{ 43710464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 43810464SAndreas.Sandberg@ARM.com 43910023Smatt.horsnell@ARM.com ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete"); 44010023Smatt.horsnell@ARM.com ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete"); 44110464SAndreas.Sandberg@ARM.com 44210023Smatt.horsnell@ARM.com fetch.regProbePoints(); 44311246Sradhika.jagtap@ARM.com rename.regProbePoints(); 44410023Smatt.horsnell@ARM.com iew.regProbePoints(); 44510023Smatt.horsnell@ARM.com commit.regProbePoints(); 44610023Smatt.horsnell@ARM.com} 44710023Smatt.horsnell@ARM.com 44810023Smatt.horsnell@ARM.comtemplate <class Impl> 44910023Smatt.horsnell@ARM.comvoid 4505595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4511062SN/A{ 4522733Sktlim@umich.edu BaseO3CPU::regStats(); 4532292SN/A 4542733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4552292SN/A timesIdled 4562292SN/A .name(name() + ".timesIdled") 4572292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4582292SN/A " unscheduled itself") 4592292SN/A .prereq(timesIdled); 4602292SN/A 4612292SN/A idleCycles 4622292SN/A .name(name() + ".idleCycles") 4632292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4642292SN/A "to idling") 4652292SN/A .prereq(idleCycles); 4662292SN/A 4678627SAli.Saidi@ARM.com quiesceCycles 4688627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 4698627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 4708627SAli.Saidi@ARM.com "for an interrupt") 4718627SAli.Saidi@ARM.com .prereq(quiesceCycles); 4728627SAli.Saidi@ARM.com 4732292SN/A // Number of Instructions simulated 4742292SN/A // -------------------------------- 4752292SN/A // Should probably be in Base CPU but need templated 4762292SN/A // MaxThreads so put in here instead 4772292SN/A committedInsts 4782292SN/A .init(numThreads) 4792292SN/A .name(name() + ".committedInsts") 48010225Snilay@cs.wisc.edu .desc("Number of Instructions Simulated") 48110225Snilay@cs.wisc.edu .flags(Stats::total); 4822292SN/A 4838834Satgutier@umich.edu committedOps 4848834Satgutier@umich.edu .init(numThreads) 4858834Satgutier@umich.edu .name(name() + ".committedOps") 48610225Snilay@cs.wisc.edu .desc("Number of Ops (including micro ops) Simulated") 48710225Snilay@cs.wisc.edu .flags(Stats::total); 4882292SN/A 4892292SN/A cpi 4902292SN/A .name(name() + ".cpi") 4912292SN/A .desc("CPI: Cycles Per Instruction") 4922292SN/A .precision(6); 4934392Sktlim@umich.edu cpi = numCycles / committedInsts; 4942292SN/A 4952292SN/A totalCpi 4962292SN/A .name(name() + ".cpi_total") 4972292SN/A .desc("CPI: Total CPI of All Threads") 4982292SN/A .precision(6); 49910225Snilay@cs.wisc.edu totalCpi = numCycles / sum(committedInsts); 5002292SN/A 5012292SN/A ipc 5022292SN/A .name(name() + ".ipc") 5032292SN/A .desc("IPC: Instructions Per Cycle") 5042292SN/A .precision(6); 5054392Sktlim@umich.edu ipc = committedInsts / numCycles; 5062292SN/A 5072292SN/A totalIpc 5082292SN/A .name(name() + ".ipc_total") 5092292SN/A .desc("IPC: Total IPC of All Threads") 5102292SN/A .precision(6); 51110225Snilay@cs.wisc.edu totalIpc = sum(committedInsts) / numCycles; 5122292SN/A 5135595Sgblack@eecs.umich.edu this->fetch.regStats(); 5145595Sgblack@eecs.umich.edu this->decode.regStats(); 5155595Sgblack@eecs.umich.edu this->rename.regStats(); 5165595Sgblack@eecs.umich.edu this->iew.regStats(); 5175595Sgblack@eecs.umich.edu this->commit.regStats(); 5187897Shestness@cs.utexas.edu this->rob.regStats(); 5197897Shestness@cs.utexas.edu 5207897Shestness@cs.utexas.edu intRegfileReads 5217897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 5227897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 5237897Shestness@cs.utexas.edu .prereq(intRegfileReads); 5247897Shestness@cs.utexas.edu 5257897Shestness@cs.utexas.edu intRegfileWrites 5267897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 5277897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 5287897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 5297897Shestness@cs.utexas.edu 5307897Shestness@cs.utexas.edu fpRegfileReads 5317897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 5327897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5337897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5347897Shestness@cs.utexas.edu 5357897Shestness@cs.utexas.edu fpRegfileWrites 5367897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5377897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5387897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5397897Shestness@cs.utexas.edu 54012109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads 54112109SRekai.GonzalezAlberquilla@arm.com .name(name() + ".vec_regfile_reads") 54212109SRekai.GonzalezAlberquilla@arm.com .desc("number of vector regfile reads") 54312109SRekai.GonzalezAlberquilla@arm.com .prereq(vecRegfileReads); 54412109SRekai.GonzalezAlberquilla@arm.com 54512109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites 54612109SRekai.GonzalezAlberquilla@arm.com .name(name() + ".vec_regfile_writes") 54712109SRekai.GonzalezAlberquilla@arm.com .desc("number of vector regfile writes") 54812109SRekai.GonzalezAlberquilla@arm.com .prereq(vecRegfileWrites); 54912109SRekai.GonzalezAlberquilla@arm.com 55013610Sgiacomo.gabrielli@arm.com vecPredRegfileReads 55113610Sgiacomo.gabrielli@arm.com .name(name() + ".pred_regfile_reads") 55213610Sgiacomo.gabrielli@arm.com .desc("number of predicate regfile reads") 55313610Sgiacomo.gabrielli@arm.com .prereq(vecPredRegfileReads); 55413610Sgiacomo.gabrielli@arm.com 55513610Sgiacomo.gabrielli@arm.com vecPredRegfileWrites 55613610Sgiacomo.gabrielli@arm.com .name(name() + ".pred_regfile_writes") 55713610Sgiacomo.gabrielli@arm.com .desc("number of predicate regfile writes") 55813610Sgiacomo.gabrielli@arm.com .prereq(vecPredRegfileWrites); 55913610Sgiacomo.gabrielli@arm.com 5609920Syasuko.eckert@amd.com ccRegfileReads 5619920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_reads") 5629920Syasuko.eckert@amd.com .desc("number of cc regfile reads") 5639920Syasuko.eckert@amd.com .prereq(ccRegfileReads); 5649920Syasuko.eckert@amd.com 5659920Syasuko.eckert@amd.com ccRegfileWrites 5669920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_writes") 5679920Syasuko.eckert@amd.com .desc("number of cc regfile writes") 5689920Syasuko.eckert@amd.com .prereq(ccRegfileWrites); 5699920Syasuko.eckert@amd.com 5707897Shestness@cs.utexas.edu miscRegfileReads 5717897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5727897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5737897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5747897Shestness@cs.utexas.edu 5757897Shestness@cs.utexas.edu miscRegfileWrites 5767897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5777897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5787897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5791062SN/A} 5801062SN/A 5811062SN/Atemplate <class Impl> 5821062SN/Avoid 5831755SN/AFullO3CPU<Impl>::tick() 5841060SN/A{ 5852733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5869444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 58710913Sandreas.sandberg@arm.com assert(drainState() != DrainState::Drained); 5881060SN/A 5892292SN/A ++numCycles; 59012284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 5912292SN/A 5922325SN/A// activity = false; 5932292SN/A 5942292SN/A //Tick each of the stages 5951060SN/A fetch.tick(); 5961060SN/A 5971060SN/A decode.tick(); 5981060SN/A 5991060SN/A rename.tick(); 6001060SN/A 6011060SN/A iew.tick(); 6021060SN/A 6031060SN/A commit.tick(); 6041060SN/A 6052292SN/A // Now advance the time buffers 6061060SN/A timeBuffer.advance(); 6071060SN/A 6081060SN/A fetchQueue.advance(); 6091060SN/A decodeQueue.advance(); 6101060SN/A renameQueue.advance(); 6111060SN/A iewQueue.advance(); 6121060SN/A 6132325SN/A activityRec.advance(); 6142292SN/A 6152292SN/A if (removeInstsThisCycle) { 6162292SN/A cleanUpRemovedInsts(); 6172292SN/A } 6182292SN/A 6192325SN/A if (!tickEvent.scheduled()) { 6209444SAndreas.Sandberg@ARM.com if (_status == SwitchedOut) { 6213226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 6222325SN/A // increment stat 6239179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6243221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 6253226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 6269179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6272325SN/A timesIdled++; 6282325SN/A } else { 6299180Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(Cycles(1))); 6303226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 6312325SN/A } 6322292SN/A } 6332292SN/A 6348793Sgblack@eecs.umich.edu if (!FullSystem) 6358793Sgblack@eecs.umich.edu updateThreadPriority(); 6369444SAndreas.Sandberg@ARM.com 6379444SAndreas.Sandberg@ARM.com tryDrain(); 6381060SN/A} 6391060SN/A 6401060SN/Atemplate <class Impl> 6411060SN/Avoid 6421755SN/AFullO3CPU<Impl>::init() 6431060SN/A{ 6445714Shsul@eecs.umich.edu BaseCPU::init(); 6451060SN/A 6468921Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 6479382SAli.Saidi@ARM.com // Set noSquashFromTC so that the CPU doesn't squash when initially 6488921Sandreas.hansson@arm.com // setting up registers. 6499382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 6508921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 6518921Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 6528921Sandreas.hansson@arm.com } 6532292SN/A 6549433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 6558793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6568793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6578793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6588793Sgblack@eecs.umich.edu } 6596034Ssteve.reinhardt@amd.com } 6602292SN/A 6619382SAli.Saidi@ARM.com // Clear noSquashFromTC. 6626221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6639382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6642292SN/A 6659427SAndreas.Sandberg@ARM.com commit.setThreads(thread); 6669427SAndreas.Sandberg@ARM.com} 6672292SN/A 6689427SAndreas.Sandberg@ARM.comtemplate <class Impl> 6699427SAndreas.Sandberg@ARM.comvoid 6709427SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::startup() 6719427SAndreas.Sandberg@ARM.com{ 6729992Snilay@cs.wisc.edu BaseCPU::startup(); 6739461Snilay@cs.wisc.edu for (int tid = 0; tid < numThreads; ++tid) 6749461Snilay@cs.wisc.edu isa[tid]->startup(threadContexts[tid]); 6759461Snilay@cs.wisc.edu 6769427SAndreas.Sandberg@ARM.com fetch.startupStage(); 6779444SAndreas.Sandberg@ARM.com decode.startupStage(); 6789427SAndreas.Sandberg@ARM.com iew.startupStage(); 6799427SAndreas.Sandberg@ARM.com rename.startupStage(); 6809427SAndreas.Sandberg@ARM.com commit.startupStage(); 6812292SN/A} 6822292SN/A 6832292SN/Atemplate <class Impl> 6842292SN/Avoid 6856221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6862875Sksewell@umich.edu{ 6876221Snate@binkert.org list<ThreadID>::iterator isActive = 6885314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6892875Sksewell@umich.edu 6903226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6919444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6923226Sktlim@umich.edu 6932875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6942875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6952875Sksewell@umich.edu tid); 6962875Sksewell@umich.edu 6972875Sksewell@umich.edu activeThreads.push_back(tid); 6982875Sksewell@umich.edu } 6992875Sksewell@umich.edu} 7002875Sksewell@umich.edu 7012875Sksewell@umich.edutemplate <class Impl> 7022875Sksewell@umich.eduvoid 7036221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 7042875Sksewell@umich.edu{ 7052875Sksewell@umich.edu //Remove From Active List, if Active 7066221Snate@binkert.org list<ThreadID>::iterator thread_it = 7075314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 7082875Sksewell@umich.edu 7093226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 7109444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7113226Sktlim@umich.edu 7122875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 7132875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 7142875Sksewell@umich.edu tid); 7152875Sksewell@umich.edu activeThreads.erase(thread_it); 7162875Sksewell@umich.edu } 71710331Smitch.hayenga@arm.com 71810331Smitch.hayenga@arm.com fetch.deactivateThread(tid); 71910331Smitch.hayenga@arm.com commit.deactivateThread(tid); 7202875Sksewell@umich.edu} 7212875Sksewell@umich.edu 7222875Sksewell@umich.edutemplate <class Impl> 7236221Snate@binkert.orgCounter 7248834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 7256221Snate@binkert.org{ 7266221Snate@binkert.org Counter total(0); 7276221Snate@binkert.org 7286221Snate@binkert.org ThreadID size = thread.size(); 7296221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 7306221Snate@binkert.org total += thread[i]->numInst; 7316221Snate@binkert.org 7326221Snate@binkert.org return total; 7336221Snate@binkert.org} 7346221Snate@binkert.org 7356221Snate@binkert.orgtemplate <class Impl> 7368834Satgutier@umich.eduCounter 7378834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 7388834Satgutier@umich.edu{ 7398834Satgutier@umich.edu Counter total(0); 7408834Satgutier@umich.edu 7418834Satgutier@umich.edu ThreadID size = thread.size(); 7428834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 7438834Satgutier@umich.edu total += thread[i]->numOp; 7448834Satgutier@umich.edu 7458834Satgutier@umich.edu return total; 7468834Satgutier@umich.edu} 7478834Satgutier@umich.edu 7488834Satgutier@umich.edutemplate <class Impl> 7492875Sksewell@umich.eduvoid 75010407Smitch.hayenga@arm.comFullO3CPU<Impl>::activateContext(ThreadID tid) 7512875Sksewell@umich.edu{ 7529444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7539444SAndreas.Sandberg@ARM.com 7542875Sksewell@umich.edu // Needs to set each stage to running as well. 75510407Smitch.hayenga@arm.com activateThread(tid); 7562875Sksewell@umich.edu 7579444SAndreas.Sandberg@ARM.com // We don't want to wake the CPU if it is drained. In that case, 7589444SAndreas.Sandberg@ARM.com // we just want to flag the thread as active and schedule the tick 7599444SAndreas.Sandberg@ARM.com // event from drainResume() instead. 76010913Sandreas.sandberg@arm.com if (drainState() == DrainState::Drained) 7619444SAndreas.Sandberg@ARM.com return; 7629444SAndreas.Sandberg@ARM.com 7639158Sandreas.hansson@arm.com // If we are time 0 or if the last activation time is in the past, 7649158Sandreas.hansson@arm.com // schedule the next tick and wake up the fetch unit 7659158Sandreas.hansson@arm.com if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 76610407Smitch.hayenga@arm.com scheduleTickEvent(Cycles(0)); 7672875Sksewell@umich.edu 7682875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7692875Sksewell@umich.edu // deschedule itself. 7702875Sksewell@umich.edu activityRec.activity(); 7712875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7722875Sksewell@umich.edu 7739180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 7749180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 7759179Sandreas.hansson@arm.com if (cycles != 0) 7769179Sandreas.hansson@arm.com --cycles; 7779179Sandreas.hansson@arm.com quiesceCycles += cycles; 7788627SAli.Saidi@ARM.com 7797823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7802875Sksewell@umich.edu 7812875Sksewell@umich.edu _status = Running; 78211526Sdavid.guillen@arm.com 78311526Sdavid.guillen@arm.com BaseCPU::activateContext(tid); 7842875Sksewell@umich.edu } 7852875Sksewell@umich.edu} 7862875Sksewell@umich.edu 7872875Sksewell@umich.edutemplate <class Impl> 78810407Smitch.hayenga@arm.comvoid 7896221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 7902875Sksewell@umich.edu{ 7912875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7929444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 79310408Smitch.hayenga@arm.com 79410408Smitch.hayenga@arm.com deactivateThread(tid); 79510407Smitch.hayenga@arm.com 7963221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 79710683Salexandru.dutu@amd.com if (activeThreads.size() == 0) { 7982910Sksewell@umich.edu unscheduleTickEvent(); 79910683Salexandru.dutu@amd.com lastRunningCycle = curCycle(); 80010683Salexandru.dutu@amd.com _status = Idle; 80110683Salexandru.dutu@amd.com } 8028627SAli.Saidi@ARM.com 8038627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 80411526Sdavid.guillen@arm.com 80511526Sdavid.guillen@arm.com BaseCPU::suspendContext(tid); 8062875Sksewell@umich.edu} 8072875Sksewell@umich.edu 8082875Sksewell@umich.edutemplate <class Impl> 8092875Sksewell@umich.eduvoid 8106221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 8112875Sksewell@umich.edu{ 8122910Sksewell@umich.edu //For now, this is the same as deallocate 8132910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 8149444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 81510408Smitch.hayenga@arm.com 81610408Smitch.hayenga@arm.com deactivateThread(tid); 81710408Smitch.hayenga@arm.com removeThread(tid); 81812284Sjose.marinho@arm.com 81912284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_SLEEP); 8202875Sksewell@umich.edu} 8212875Sksewell@umich.edu 8222875Sksewell@umich.edutemplate <class Impl> 8232875Sksewell@umich.eduvoid 8246221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 8252292SN/A{ 8262847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 8272292SN/A // Will change now that the PC and thread state is internal to the CPU 8282683Sktlim@umich.edu // and not in the ThreadContext. 8298793Sgblack@eecs.umich.edu ThreadContext *src_tc; 8308793Sgblack@eecs.umich.edu if (FullSystem) 8318793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 8328793Sgblack@eecs.umich.edu else 8338793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 8342292SN/A 8352292SN/A //Bind Int Regs to Rename Map 83612104Snathanael.premillieu@arm.com 83712106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs; 83812106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 83912105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getIntReg(); 84012104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 8412292SN/A scoreboard.setReg(phys_reg); 8422292SN/A } 8432292SN/A 8442292SN/A //Bind Float Regs to Rename Map 84512106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs; 84612106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 84712105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getFloatReg(); 84812104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 8492292SN/A scoreboard.setReg(phys_reg); 8502292SN/A } 8512292SN/A 8529920Syasuko.eckert@amd.com //Bind condition-code Regs to Rename Map 85312106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs; 85412106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 85512105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getCCReg(); 85612104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 8579920Syasuko.eckert@amd.com scoreboard.setReg(phys_reg); 8589920Syasuko.eckert@amd.com } 8599920Syasuko.eckert@amd.com 8602292SN/A //Copy Thread Data Into RegFile 8612847Sksewell@umich.edu //this->copyFromTC(tid); 8622292SN/A 8632847Sksewell@umich.edu //Set PC/NPC/NNPC 8647720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8652292SN/A 8662680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8672292SN/A 86810407Smitch.hayenga@arm.com activateContext(tid); 8692292SN/A 8702292SN/A //Reset ROB/IQ/LSQ Entries 8712292SN/A commit.rob->resetEntries(); 8722292SN/A} 8732292SN/A 8742292SN/Atemplate <class Impl> 8752292SN/Avoid 8766221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8772292SN/A{ 8782877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 8792847Sksewell@umich.edu 8802847Sksewell@umich.edu // Copy Thread Data From RegFile 8812847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 8825364Sksewell@umich.edu // this->copyToTC(tid); 8835364Sksewell@umich.edu 8845364Sksewell@umich.edu 8855364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 8865364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 8875364Sksewell@umich.edu // in SMT workloads. 8882847Sksewell@umich.edu 8892847Sksewell@umich.edu // Unbind Int Regs from Rename Map 89012106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs; 89112106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 89212105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id); 8932292SN/A scoreboard.unsetReg(phys_reg); 8942292SN/A freeList.addReg(phys_reg); 8952292SN/A } 8962292SN/A 8972847Sksewell@umich.edu // Unbind Float Regs from Rename Map 89812106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs; 89912106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 90012105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id); 9012292SN/A scoreboard.unsetReg(phys_reg); 9022292SN/A freeList.addReg(phys_reg); 9032292SN/A } 9042292SN/A 90513610Sgiacomo.gabrielli@arm.com // Unbind Float Regs from Rename Map 90613610Sgiacomo.gabrielli@arm.com for (unsigned preg = 0; preg < TheISA::NumVecPredRegs; preg++) { 90713610Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_reg = renameMap[tid].lookup( 90813610Sgiacomo.gabrielli@arm.com RegId(VecPredRegClass, preg)); 90913610Sgiacomo.gabrielli@arm.com scoreboard.unsetReg(phys_reg); 91013610Sgiacomo.gabrielli@arm.com freeList.addReg(phys_reg); 91113610Sgiacomo.gabrielli@arm.com } 91213610Sgiacomo.gabrielli@arm.com 9139920Syasuko.eckert@amd.com // Unbind condition-code Regs from Rename Map 91412106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs; 91512106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 91612105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id); 9179920Syasuko.eckert@amd.com scoreboard.unsetReg(phys_reg); 9189920Syasuko.eckert@amd.com freeList.addReg(phys_reg); 9199920Syasuko.eckert@amd.com } 9209920Syasuko.eckert@amd.com 9212847Sksewell@umich.edu // Squash Throughout Pipeline 9228138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 9238138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 9248138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 9252292SN/A decode.squash(tid); 9262935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 9272875Sksewell@umich.edu iew.squash(tid); 9285363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 9292935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 9302292SN/A 9315362Sksewell@umich.edu 9325362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 9332292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 9342292SN/A 9352847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 9363229Sktlim@umich.edu 9373229Sktlim@umich.edu // Commented out for now. This should be possible to do by 9383229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 9393229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 9403229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 9413229Sktlim@umich.edu/* 9422292SN/A if (activeThreads.size() >= 1) { 9432292SN/A commit.rob->resetEntries(); 9442292SN/A iew.resetEntries(); 9452292SN/A } 9463229Sktlim@umich.edu*/ 9472292SN/A} 9482292SN/A 9494192Sktlim@umich.edutemplate <class Impl> 9505595Sgblack@eecs.umich.eduFault 9516221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 9525702Ssaidi@eecs.umich.edu{ 9535702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9545702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 9555702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 9565702Ssaidi@eecs.umich.edu 9575702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 9585702Ssaidi@eecs.umich.edu 9595702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9605702Ssaidi@eecs.umich.edu#endif 9615702Ssaidi@eecs.umich.edu return NoFault; 9625702Ssaidi@eecs.umich.edu} 9635702Ssaidi@eecs.umich.edu 9645702Ssaidi@eecs.umich.edutemplate <class Impl> 9655702Ssaidi@eecs.umich.edubool 9666221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 9675702Ssaidi@eecs.umich.edu{ 9685702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9695702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 9705702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 9715702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 9725702Ssaidi@eecs.umich.edu 9735702Ssaidi@eecs.umich.edu switch (palFunc) { 9745702Ssaidi@eecs.umich.edu case PAL::halt: 9755702Ssaidi@eecs.umich.edu halt(); 9765702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 9775702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 9785702Ssaidi@eecs.umich.edu break; 9795702Ssaidi@eecs.umich.edu 9805702Ssaidi@eecs.umich.edu case PAL::bpt: 9815702Ssaidi@eecs.umich.edu case PAL::bugchk: 9825702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 9835702Ssaidi@eecs.umich.edu return false; 9845702Ssaidi@eecs.umich.edu break; 9855702Ssaidi@eecs.umich.edu } 9865702Ssaidi@eecs.umich.edu#endif 9875702Ssaidi@eecs.umich.edu return true; 9885702Ssaidi@eecs.umich.edu} 9895702Ssaidi@eecs.umich.edu 9905702Ssaidi@eecs.umich.edutemplate <class Impl> 99113601Sgiacomo.travaglini@arm.comvoid 99213601Sgiacomo.travaglini@arm.comFullO3CPU<Impl>::switchRenameMode(ThreadID tid, UnifiedFreeList* freelist) 99313601Sgiacomo.travaglini@arm.com{ 99413601Sgiacomo.travaglini@arm.com auto pc = this->pcState(tid); 99513601Sgiacomo.travaglini@arm.com 99613601Sgiacomo.travaglini@arm.com // new_mode is the new vector renaming mode 99713601Sgiacomo.travaglini@arm.com auto new_mode = RenameMode<TheISA::ISA>::mode(pc); 99813601Sgiacomo.travaglini@arm.com 99913601Sgiacomo.travaglini@arm.com // We update vecMode only if there has been a change 100013601Sgiacomo.travaglini@arm.com if (new_mode != vecMode) { 100113601Sgiacomo.travaglini@arm.com vecMode = new_mode; 100213601Sgiacomo.travaglini@arm.com 100313601Sgiacomo.travaglini@arm.com renameMap[tid].switchMode(vecMode); 100413601Sgiacomo.travaglini@arm.com commitRenameMap[tid].switchMode(vecMode); 100513601Sgiacomo.travaglini@arm.com renameMap[tid].switchFreeList(freelist); 100613601Sgiacomo.travaglini@arm.com } 100713601Sgiacomo.travaglini@arm.com} 100813601Sgiacomo.travaglini@arm.com 100913601Sgiacomo.travaglini@arm.comtemplate <class Impl> 10105702Ssaidi@eecs.umich.eduFault 10115595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 10125595Sgblack@eecs.umich.edu{ 10135595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 101411150Smitch.hayenga@arm.com return this->interrupts[0]->getInterrupt(this->threadContexts[0]); 10155595Sgblack@eecs.umich.edu} 10165595Sgblack@eecs.umich.edu 10175595Sgblack@eecs.umich.edutemplate <class Impl> 10185595Sgblack@eecs.umich.eduvoid 101910379Sandreas.hansson@arm.comFullO3CPU<Impl>::processInterrupts(const Fault &interrupt) 10205595Sgblack@eecs.umich.edu{ 10215595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 10225595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 10235595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 10245595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 10255595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 10265595Sgblack@eecs.umich.edu 10275595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 102811150Smitch.hayenga@arm.com this->interrupts[0]->updateIntrInfo(this->threadContexts[0]); 10295595Sgblack@eecs.umich.edu 10305595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 103110417Sandreas.hansson@arm.com this->trap(interrupt, 0, nullptr); 10325595Sgblack@eecs.umich.edu} 10335595Sgblack@eecs.umich.edu 10341060SN/Atemplate <class Impl> 10352852Sktlim@umich.eduvoid 103610417Sandreas.hansson@arm.comFullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid, 103710417Sandreas.hansson@arm.com const StaticInstPtr &inst) 10385595Sgblack@eecs.umich.edu{ 10395595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 10407684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 10415595Sgblack@eecs.umich.edu} 10425595Sgblack@eecs.umich.edu 10435595Sgblack@eecs.umich.edutemplate <class Impl> 10445595Sgblack@eecs.umich.eduvoid 104511877Sbrandon.potter@amd.comFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault) 10465595Sgblack@eecs.umich.edu{ 10475595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 10485595Sgblack@eecs.umich.edu 10495595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 10505595Sgblack@eecs.umich.edu 10515595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 10525595Sgblack@eecs.umich.edu // instruction. 10535595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 10545595Sgblack@eecs.umich.edu 10555595Sgblack@eecs.umich.edu // Execute the actual syscall. 105611877Sbrandon.potter@amd.com this->thread[tid]->syscall(callnum, fault); 10575595Sgblack@eecs.umich.edu 10585595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 10595595Sgblack@eecs.umich.edu // incrementing it. 10605595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 10615595Sgblack@eecs.umich.edu} 10625595Sgblack@eecs.umich.edu 10635595Sgblack@eecs.umich.edutemplate <class Impl> 10645595Sgblack@eecs.umich.eduvoid 106510905Sandreas.sandberg@arm.comFullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const 10662864Sktlim@umich.edu{ 106710905Sandreas.sandberg@arm.com thread[tid]->serialize(cp); 10682864Sktlim@umich.edu} 10692864Sktlim@umich.edu 10702864Sktlim@umich.edutemplate <class Impl> 10712864Sktlim@umich.eduvoid 107210905Sandreas.sandberg@arm.comFullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid) 10732864Sktlim@umich.edu{ 107410905Sandreas.sandberg@arm.com thread[tid]->unserialize(cp); 10752864Sktlim@umich.edu} 10762864Sktlim@umich.edu 10772864Sktlim@umich.edutemplate <class Impl> 107810913Sandreas.sandberg@arm.comDrainState 107910913Sandreas.sandberg@arm.comFullO3CPU<Impl>::drain() 10801060SN/A{ 108112276Sanouk.vanlaer@arm.com // Deschedule any power gating event (if any) 108212276Sanouk.vanlaer@arm.com deschedulePowerGatingEvent(); 108312276Sanouk.vanlaer@arm.com 10849444SAndreas.Sandberg@ARM.com // If the CPU isn't doing anything, then return immediately. 108510913Sandreas.sandberg@arm.com if (switchedOut()) 108610913Sandreas.sandberg@arm.com return DrainState::Drained; 10873512Sktlim@umich.edu 10889444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Draining...\n"); 10893512Sktlim@umich.edu 10909444SAndreas.Sandberg@ARM.com // We only need to signal a drain to the commit stage as this 10919444SAndreas.Sandberg@ARM.com // initiates squashing controls the draining. Once the commit 10929444SAndreas.Sandberg@ARM.com // stage commits an instruction where it is safe to stop, it'll 10939444SAndreas.Sandberg@ARM.com // squash the rest of the instructions in the pipeline and force 10949444SAndreas.Sandberg@ARM.com // the fetch stage to stall. The pipeline will be drained once all 10959444SAndreas.Sandberg@ARM.com // in-flight instructions have retired. 10962843Sktlim@umich.edu commit.drain(); 10972325SN/A 10982325SN/A // Wake the CPU and record activity so everything can drain out if 10992863Sktlim@umich.edu // the CPU was not able to immediately drain. 11009444SAndreas.Sandberg@ARM.com if (!isDrained()) { 110112143Sanouk.vanlaer@arm.com // If a thread is suspended, wake it up so it can be drained 110212143Sanouk.vanlaer@arm.com for (auto t : threadContexts) { 110312143Sanouk.vanlaer@arm.com if (t->status() == ThreadContext::Suspended){ 110412143Sanouk.vanlaer@arm.com DPRINTF(Drain, "Currently suspended so activate %i \n", 110512143Sanouk.vanlaer@arm.com t->threadId()); 110612143Sanouk.vanlaer@arm.com t->activate(); 110712143Sanouk.vanlaer@arm.com // As the thread is now active, change the power state as well 110812143Sanouk.vanlaer@arm.com activateContext(t->threadId()); 110912143Sanouk.vanlaer@arm.com } 111012143Sanouk.vanlaer@arm.com } 111112143Sanouk.vanlaer@arm.com 11122863Sktlim@umich.edu wakeCPU(); 11132863Sktlim@umich.edu activityRec.activity(); 11142852Sktlim@umich.edu 11159152Satgutier@umich.edu DPRINTF(Drain, "CPU not drained\n"); 11169152Satgutier@umich.edu 111710913Sandreas.sandberg@arm.com return DrainState::Draining; 11182863Sktlim@umich.edu } else { 11199444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU is already drained\n"); 11209444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 11219444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 11229444SAndreas.Sandberg@ARM.com 11239444SAndreas.Sandberg@ARM.com // Flush out any old data from the time buffers. In 11249444SAndreas.Sandberg@ARM.com // particular, there might be some data in flight from the 11259444SAndreas.Sandberg@ARM.com // fetch stage that isn't visible in any of the CPU buffers we 11269444SAndreas.Sandberg@ARM.com // test in isDrained(). 11279444SAndreas.Sandberg@ARM.com for (int i = 0; i < timeBuffer.getSize(); ++i) { 11289444SAndreas.Sandberg@ARM.com timeBuffer.advance(); 11299444SAndreas.Sandberg@ARM.com fetchQueue.advance(); 11309444SAndreas.Sandberg@ARM.com decodeQueue.advance(); 11319444SAndreas.Sandberg@ARM.com renameQueue.advance(); 11329444SAndreas.Sandberg@ARM.com iewQueue.advance(); 11339444SAndreas.Sandberg@ARM.com } 11349444SAndreas.Sandberg@ARM.com 11359444SAndreas.Sandberg@ARM.com drainSanityCheck(); 113610913Sandreas.sandberg@arm.com return DrainState::Drained; 11372863Sktlim@umich.edu } 11382316SN/A} 11392310SN/A 11402316SN/Atemplate <class Impl> 11419444SAndreas.Sandberg@ARM.combool 11429444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::tryDrain() 11439444SAndreas.Sandberg@ARM.com{ 114410913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining || !isDrained()) 11459444SAndreas.Sandberg@ARM.com return false; 11469444SAndreas.Sandberg@ARM.com 11479444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 11489444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 11499444SAndreas.Sandberg@ARM.com 11509444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 115110913Sandreas.sandberg@arm.com signalDrainDone(); 11529444SAndreas.Sandberg@ARM.com 11539444SAndreas.Sandberg@ARM.com return true; 11549444SAndreas.Sandberg@ARM.com} 11559444SAndreas.Sandberg@ARM.com 11569444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11579444SAndreas.Sandberg@ARM.comvoid 11589444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::drainSanityCheck() const 11599444SAndreas.Sandberg@ARM.com{ 11609444SAndreas.Sandberg@ARM.com assert(isDrained()); 11619444SAndreas.Sandberg@ARM.com fetch.drainSanityCheck(); 11629444SAndreas.Sandberg@ARM.com decode.drainSanityCheck(); 11639444SAndreas.Sandberg@ARM.com rename.drainSanityCheck(); 11649444SAndreas.Sandberg@ARM.com iew.drainSanityCheck(); 11659444SAndreas.Sandberg@ARM.com commit.drainSanityCheck(); 11669444SAndreas.Sandberg@ARM.com} 11679444SAndreas.Sandberg@ARM.com 11689444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11699444SAndreas.Sandberg@ARM.combool 11709444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::isDrained() const 11719444SAndreas.Sandberg@ARM.com{ 11729444SAndreas.Sandberg@ARM.com bool drained(true); 11739444SAndreas.Sandberg@ARM.com 11749444SAndreas.Sandberg@ARM.com if (!instList.empty() || !removeList.empty()) { 11759444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Main CPU structures not drained.\n"); 11769444SAndreas.Sandberg@ARM.com drained = false; 11779444SAndreas.Sandberg@ARM.com } 11789444SAndreas.Sandberg@ARM.com 11799444SAndreas.Sandberg@ARM.com if (!fetch.isDrained()) { 11809444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Fetch not drained.\n"); 11819444SAndreas.Sandberg@ARM.com drained = false; 11829444SAndreas.Sandberg@ARM.com } 11839444SAndreas.Sandberg@ARM.com 11849444SAndreas.Sandberg@ARM.com if (!decode.isDrained()) { 11859444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Decode not drained.\n"); 11869444SAndreas.Sandberg@ARM.com drained = false; 11879444SAndreas.Sandberg@ARM.com } 11889444SAndreas.Sandberg@ARM.com 11899444SAndreas.Sandberg@ARM.com if (!rename.isDrained()) { 11909444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Rename not drained.\n"); 11919444SAndreas.Sandberg@ARM.com drained = false; 11929444SAndreas.Sandberg@ARM.com } 11939444SAndreas.Sandberg@ARM.com 11949444SAndreas.Sandberg@ARM.com if (!iew.isDrained()) { 11959444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "IEW not drained.\n"); 11969444SAndreas.Sandberg@ARM.com drained = false; 11979444SAndreas.Sandberg@ARM.com } 11989444SAndreas.Sandberg@ARM.com 11999444SAndreas.Sandberg@ARM.com if (!commit.isDrained()) { 12009444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Commit not drained.\n"); 12019444SAndreas.Sandberg@ARM.com drained = false; 12029444SAndreas.Sandberg@ARM.com } 12039444SAndreas.Sandberg@ARM.com 12049444SAndreas.Sandberg@ARM.com return drained; 12059444SAndreas.Sandberg@ARM.com} 12069444SAndreas.Sandberg@ARM.com 12079444SAndreas.Sandberg@ARM.comtemplate <class Impl> 12089444SAndreas.Sandberg@ARM.comvoid 12099444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::commitDrained(ThreadID tid) 12109444SAndreas.Sandberg@ARM.com{ 12119444SAndreas.Sandberg@ARM.com fetch.drainStall(tid); 12129444SAndreas.Sandberg@ARM.com} 12139444SAndreas.Sandberg@ARM.com 12149444SAndreas.Sandberg@ARM.comtemplate <class Impl> 12152316SN/Avoid 12169342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drainResume() 12172316SN/A{ 12189444SAndreas.Sandberg@ARM.com if (switchedOut()) 12199444SAndreas.Sandberg@ARM.com return; 12202316SN/A 12219444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Resuming...\n"); 12229523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 12233319Shsul@eecs.umich.edu 12249444SAndreas.Sandberg@ARM.com fetch.drainResume(); 12259444SAndreas.Sandberg@ARM.com commit.drainResume(); 12262316SN/A 12279444SAndreas.Sandberg@ARM.com _status = Idle; 12289444SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); i++) { 12299444SAndreas.Sandberg@ARM.com if (thread[i]->status() == ThreadContext::Active) { 12309444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Activating thread: %i\n", i); 12319444SAndreas.Sandberg@ARM.com activateThread(i); 12329444SAndreas.Sandberg@ARM.com _status = Running; 12332863Sktlim@umich.edu } 12342310SN/A } 12359444SAndreas.Sandberg@ARM.com 12369444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 12379444SAndreas.Sandberg@ARM.com if (_status == Running) 12389444SAndreas.Sandberg@ARM.com schedule(tickEvent, nextCycle()); 123912276Sanouk.vanlaer@arm.com 124012276Sanouk.vanlaer@arm.com // Reschedule any power gating event (if any) 124112276Sanouk.vanlaer@arm.com schedulePowerGatingEvent(); 12422843Sktlim@umich.edu} 12432843Sktlim@umich.edu 12442843Sktlim@umich.edutemplate <class Impl> 12452843Sktlim@umich.eduvoid 12462843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 12472843Sktlim@umich.edu{ 12489444SAndreas.Sandberg@ARM.com DPRINTF(O3CPU, "Switching out\n"); 12499429SAndreas.Sandberg@ARM.com BaseCPU::switchOut(); 12509429SAndreas.Sandberg@ARM.com 12519444SAndreas.Sandberg@ARM.com activityRec.reset(); 12522843Sktlim@umich.edu 12532843Sktlim@umich.edu _status = SwitchedOut; 12548887Sgeoffrey.blake@arm.com 12552843Sktlim@umich.edu if (checker) 12562843Sktlim@umich.edu checker->switchOut(); 12571060SN/A} 12581060SN/A 12591060SN/Atemplate <class Impl> 12601060SN/Avoid 12611755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 12621060SN/A{ 12638737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 12641060SN/A 12652307SN/A fetch.takeOverFrom(); 12662307SN/A decode.takeOverFrom(); 12672307SN/A rename.takeOverFrom(); 12682307SN/A iew.takeOverFrom(); 12692307SN/A commit.takeOverFrom(); 12702307SN/A 12719444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 12721060SN/A 12739152Satgutier@umich.edu FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 12749152Satgutier@umich.edu if (oldO3CPU) 12759152Satgutier@umich.edu globalSeqNum = oldO3CPU->globalSeqNum; 12769152Satgutier@umich.edu 12779179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 12789444SAndreas.Sandberg@ARM.com _status = Idle; 12791060SN/A} 12801060SN/A 12811060SN/Atemplate <class Impl> 12829523SAndreas.Sandberg@ARM.comvoid 12839523SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::verifyMemoryMode() const 12849523SAndreas.Sandberg@ARM.com{ 12859524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 12869523SAndreas.Sandberg@ARM.com fatal("The O3 CPU requires the memory system to be in " 12879523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 12889523SAndreas.Sandberg@ARM.com } 12899523SAndreas.Sandberg@ARM.com} 12909523SAndreas.Sandberg@ARM.com 12919523SAndreas.Sandberg@ARM.comtemplate <class Impl> 129213557Sgabeblack@google.comRegVal 129310698Sandreas.hansson@arm.comFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const 12945595Sgblack@eecs.umich.edu{ 12959384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscRegNoEffect(misc_reg); 12965595Sgblack@eecs.umich.edu} 12975595Sgblack@eecs.umich.edu 12985595Sgblack@eecs.umich.edutemplate <class Impl> 129913557Sgabeblack@google.comRegVal 13006221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 13015595Sgblack@eecs.umich.edu{ 13027897Shestness@cs.utexas.edu miscRegfileReads++; 13039384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 13045595Sgblack@eecs.umich.edu} 13055595Sgblack@eecs.umich.edu 13065595Sgblack@eecs.umich.edutemplate <class Impl> 13075595Sgblack@eecs.umich.eduvoid 130813582Sgabeblack@google.comFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) 13095595Sgblack@eecs.umich.edu{ 13109384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 13115595Sgblack@eecs.umich.edu} 13125595Sgblack@eecs.umich.edu 13135595Sgblack@eecs.umich.edutemplate <class Impl> 13145595Sgblack@eecs.umich.eduvoid 131513582Sgabeblack@google.comFullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid) 13165595Sgblack@eecs.umich.edu{ 13177897Shestness@cs.utexas.edu miscRegfileWrites++; 13189384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 13195595Sgblack@eecs.umich.edu} 13205595Sgblack@eecs.umich.edu 13215595Sgblack@eecs.umich.edutemplate <class Impl> 132213557Sgabeblack@google.comRegVal 132312105Snathanael.premillieu@arm.comFullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg) 13241060SN/A{ 13257897Shestness@cs.utexas.edu intRegfileReads++; 132612105Snathanael.premillieu@arm.com return regFile.readIntReg(phys_reg); 13271060SN/A} 13281060SN/A 13291060SN/Atemplate <class Impl> 133013557Sgabeblack@google.comRegVal 133112105Snathanael.premillieu@arm.comFullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg) 13322455SN/A{ 13337897Shestness@cs.utexas.edu fpRegfileReads++; 133412105Snathanael.premillieu@arm.com return regFile.readFloatRegBits(phys_reg); 13351060SN/A} 13361060SN/A 13371060SN/Atemplate <class Impl> 133812109SRekai.GonzalezAlberquilla@arm.comauto 133912109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readVecReg(PhysRegIdPtr phys_reg) const 134012109SRekai.GonzalezAlberquilla@arm.com -> const VecRegContainer& 134112109SRekai.GonzalezAlberquilla@arm.com{ 134212109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads++; 134312109SRekai.GonzalezAlberquilla@arm.com return regFile.readVecReg(phys_reg); 134412109SRekai.GonzalezAlberquilla@arm.com} 134512109SRekai.GonzalezAlberquilla@arm.com 134612109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 134712109SRekai.GonzalezAlberquilla@arm.comauto 134812109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::getWritableVecReg(PhysRegIdPtr phys_reg) 134912109SRekai.GonzalezAlberquilla@arm.com -> VecRegContainer& 135012109SRekai.GonzalezAlberquilla@arm.com{ 135112109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 135212109SRekai.GonzalezAlberquilla@arm.com return regFile.getWritableVecReg(phys_reg); 135312109SRekai.GonzalezAlberquilla@arm.com} 135412109SRekai.GonzalezAlberquilla@arm.com 135512109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 135612109SRekai.GonzalezAlberquilla@arm.comauto 135712109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem& 135812109SRekai.GonzalezAlberquilla@arm.com{ 135912109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads++; 136012109SRekai.GonzalezAlberquilla@arm.com return regFile.readVecElem(phys_reg); 136112109SRekai.GonzalezAlberquilla@arm.com} 136212109SRekai.GonzalezAlberquilla@arm.com 136312109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 136413610Sgiacomo.gabrielli@arm.comauto 136513610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::readVecPredReg(PhysRegIdPtr phys_reg) const 136613610Sgiacomo.gabrielli@arm.com -> const VecPredRegContainer& 136713610Sgiacomo.gabrielli@arm.com{ 136813610Sgiacomo.gabrielli@arm.com vecPredRegfileReads++; 136913610Sgiacomo.gabrielli@arm.com return regFile.readVecPredReg(phys_reg); 137013610Sgiacomo.gabrielli@arm.com} 137113610Sgiacomo.gabrielli@arm.com 137213610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 137313610Sgiacomo.gabrielli@arm.comauto 137413610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::getWritableVecPredReg(PhysRegIdPtr phys_reg) 137513610Sgiacomo.gabrielli@arm.com -> VecPredRegContainer& 137613610Sgiacomo.gabrielli@arm.com{ 137713610Sgiacomo.gabrielli@arm.com vecPredRegfileWrites++; 137813610Sgiacomo.gabrielli@arm.com return regFile.getWritableVecPredReg(phys_reg); 137913610Sgiacomo.gabrielli@arm.com} 138013610Sgiacomo.gabrielli@arm.com 138113610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 13829920Syasuko.eckert@amd.comCCReg 138312105Snathanael.premillieu@arm.comFullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg) 13849920Syasuko.eckert@amd.com{ 13859920Syasuko.eckert@amd.com ccRegfileReads++; 138612105Snathanael.premillieu@arm.com return regFile.readCCReg(phys_reg); 13879920Syasuko.eckert@amd.com} 13889920Syasuko.eckert@amd.com 13899920Syasuko.eckert@amd.comtemplate <class Impl> 13901060SN/Avoid 139113557Sgabeblack@google.comFullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val) 13921060SN/A{ 13937897Shestness@cs.utexas.edu intRegfileWrites++; 139412105Snathanael.premillieu@arm.com regFile.setIntReg(phys_reg, val); 13951060SN/A} 13961060SN/A 13971060SN/Atemplate <class Impl> 13981060SN/Avoid 139913557Sgabeblack@google.comFullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val) 14002455SN/A{ 14017897Shestness@cs.utexas.edu fpRegfileWrites++; 140212105Snathanael.premillieu@arm.com regFile.setFloatRegBits(phys_reg, val); 14031060SN/A} 14041060SN/A 14051060SN/Atemplate <class Impl> 14069920Syasuko.eckert@amd.comvoid 140712109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) 140812109SRekai.GonzalezAlberquilla@arm.com{ 140912109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 141012109SRekai.GonzalezAlberquilla@arm.com regFile.setVecReg(phys_reg, val); 141112109SRekai.GonzalezAlberquilla@arm.com} 141212109SRekai.GonzalezAlberquilla@arm.com 141312109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 141412109SRekai.GonzalezAlberquilla@arm.comvoid 141512109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val) 141612109SRekai.GonzalezAlberquilla@arm.com{ 141712109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 141812109SRekai.GonzalezAlberquilla@arm.com regFile.setVecElem(phys_reg, val); 141912109SRekai.GonzalezAlberquilla@arm.com} 142012109SRekai.GonzalezAlberquilla@arm.com 142112109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 142212109SRekai.GonzalezAlberquilla@arm.comvoid 142313610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::setVecPredReg(PhysRegIdPtr phys_reg, 142413610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& val) 142513610Sgiacomo.gabrielli@arm.com{ 142613610Sgiacomo.gabrielli@arm.com vecPredRegfileWrites++; 142713610Sgiacomo.gabrielli@arm.com regFile.setVecPredReg(phys_reg, val); 142813610Sgiacomo.gabrielli@arm.com} 142913610Sgiacomo.gabrielli@arm.com 143013610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 143113610Sgiacomo.gabrielli@arm.comvoid 143212105Snathanael.premillieu@arm.comFullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val) 14339920Syasuko.eckert@amd.com{ 14349920Syasuko.eckert@amd.com ccRegfileWrites++; 143512105Snathanael.premillieu@arm.com regFile.setCCReg(phys_reg, val); 14369920Syasuko.eckert@amd.com} 14379920Syasuko.eckert@amd.com 14389920Syasuko.eckert@amd.comtemplate <class Impl> 143913557Sgabeblack@google.comRegVal 14406221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 14411060SN/A{ 14427897Shestness@cs.utexas.edu intRegfileReads++; 144312106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 144412106SRekai.GonzalezAlberquilla@arm.com RegId(IntRegClass, reg_idx)); 14452292SN/A 14462292SN/A return regFile.readIntReg(phys_reg); 14472292SN/A} 14482292SN/A 14492292SN/Atemplate <class Impl> 145013557Sgabeblack@google.comRegVal 145113500Sgabeblack@google.comFullO3CPU<Impl>::readArchFloatRegBits(int reg_idx, ThreadID tid) 14522292SN/A{ 14537897Shestness@cs.utexas.edu fpRegfileReads++; 145412106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 145512106SRekai.GonzalezAlberquilla@arm.com RegId(FloatRegClass, reg_idx)); 14562292SN/A 14572669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 14581060SN/A} 14591060SN/A 14601060SN/Atemplate <class Impl> 146112109SRekai.GonzalezAlberquilla@arm.comauto 146212109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const 146312109SRekai.GonzalezAlberquilla@arm.com -> const VecRegContainer& 146412109SRekai.GonzalezAlberquilla@arm.com{ 146512109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 146612109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 146712109SRekai.GonzalezAlberquilla@arm.com return readVecReg(phys_reg); 146812109SRekai.GonzalezAlberquilla@arm.com} 146912109SRekai.GonzalezAlberquilla@arm.com 147012109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 147112109SRekai.GonzalezAlberquilla@arm.comauto 147212109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid) 147312109SRekai.GonzalezAlberquilla@arm.com -> VecRegContainer& 147412109SRekai.GonzalezAlberquilla@arm.com{ 147512109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 147612109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 147712109SRekai.GonzalezAlberquilla@arm.com return getWritableVecReg(phys_reg); 147812109SRekai.GonzalezAlberquilla@arm.com} 147912109SRekai.GonzalezAlberquilla@arm.com 148012109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 148112109SRekai.GonzalezAlberquilla@arm.comauto 148212109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 148312109SRekai.GonzalezAlberquilla@arm.com ThreadID tid) const -> const VecElem& 148412109SRekai.GonzalezAlberquilla@arm.com{ 148512109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 148613598Sgiacomo.travaglini@arm.com RegId(VecElemClass, reg_idx, ldx)); 148712109SRekai.GonzalezAlberquilla@arm.com return readVecElem(phys_reg); 148812109SRekai.GonzalezAlberquilla@arm.com} 148912109SRekai.GonzalezAlberquilla@arm.com 149012109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 149113610Sgiacomo.gabrielli@arm.comauto 149213610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::readArchVecPredReg(int reg_idx, ThreadID tid) const 149313610Sgiacomo.gabrielli@arm.com -> const VecPredRegContainer& 149413610Sgiacomo.gabrielli@arm.com{ 149513610Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 149613610Sgiacomo.gabrielli@arm.com RegId(VecPredRegClass, reg_idx)); 149713610Sgiacomo.gabrielli@arm.com return readVecPredReg(phys_reg); 149813610Sgiacomo.gabrielli@arm.com} 149913610Sgiacomo.gabrielli@arm.com 150013610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 150113610Sgiacomo.gabrielli@arm.comauto 150213610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::getWritableArchVecPredReg(int reg_idx, ThreadID tid) 150313610Sgiacomo.gabrielli@arm.com -> VecPredRegContainer& 150413610Sgiacomo.gabrielli@arm.com{ 150513610Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 150613610Sgiacomo.gabrielli@arm.com RegId(VecPredRegClass, reg_idx)); 150713610Sgiacomo.gabrielli@arm.com return getWritableVecPredReg(phys_reg); 150813610Sgiacomo.gabrielli@arm.com} 150913610Sgiacomo.gabrielli@arm.com 151013610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 15119920Syasuko.eckert@amd.comCCReg 15129920Syasuko.eckert@amd.comFullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid) 15139920Syasuko.eckert@amd.com{ 15149920Syasuko.eckert@amd.com ccRegfileReads++; 151512106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 151612106SRekai.GonzalezAlberquilla@arm.com RegId(CCRegClass, reg_idx)); 15179920Syasuko.eckert@amd.com 15189920Syasuko.eckert@amd.com return regFile.readCCReg(phys_reg); 15199920Syasuko.eckert@amd.com} 15209920Syasuko.eckert@amd.com 15219920Syasuko.eckert@amd.comtemplate <class Impl> 15221060SN/Avoid 152313557Sgabeblack@google.comFullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid) 15241060SN/A{ 15257897Shestness@cs.utexas.edu intRegfileWrites++; 152612106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 152712106SRekai.GonzalezAlberquilla@arm.com RegId(IntRegClass, reg_idx)); 15282292SN/A 15292292SN/A regFile.setIntReg(phys_reg, val); 15301060SN/A} 15311060SN/A 15321060SN/Atemplate <class Impl> 15331060SN/Avoid 153413557Sgabeblack@google.comFullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid) 15351060SN/A{ 15367897Shestness@cs.utexas.edu fpRegfileWrites++; 153712106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 153812106SRekai.GonzalezAlberquilla@arm.com RegId(FloatRegClass, reg_idx)); 15391060SN/A 15402669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 15412292SN/A} 15422292SN/A 15432292SN/Atemplate <class Impl> 15449920Syasuko.eckert@amd.comvoid 154512109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setArchVecReg(int reg_idx, const VecRegContainer& val, 154612109SRekai.GonzalezAlberquilla@arm.com ThreadID tid) 154712109SRekai.GonzalezAlberquilla@arm.com{ 154812109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 154912109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 155012109SRekai.GonzalezAlberquilla@arm.com setVecReg(phys_reg, val); 155112109SRekai.GonzalezAlberquilla@arm.com} 155212109SRekai.GonzalezAlberquilla@arm.com 155312109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 155412109SRekai.GonzalezAlberquilla@arm.comvoid 155512109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 155612109SRekai.GonzalezAlberquilla@arm.com const VecElem& val, ThreadID tid) 155712109SRekai.GonzalezAlberquilla@arm.com{ 155812109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 155913546Sgiacomo.travaglini@arm.com RegId(VecElemClass, reg_idx, ldx)); 156012109SRekai.GonzalezAlberquilla@arm.com setVecElem(phys_reg, val); 156112109SRekai.GonzalezAlberquilla@arm.com} 156212109SRekai.GonzalezAlberquilla@arm.com 156312109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 156412109SRekai.GonzalezAlberquilla@arm.comvoid 156513610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, 156613610Sgiacomo.gabrielli@arm.com ThreadID tid) 156713610Sgiacomo.gabrielli@arm.com{ 156813610Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 156913610Sgiacomo.gabrielli@arm.com RegId(VecPredRegClass, reg_idx)); 157013610Sgiacomo.gabrielli@arm.com setVecPredReg(phys_reg, val); 157113610Sgiacomo.gabrielli@arm.com} 157213610Sgiacomo.gabrielli@arm.com 157313610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 157413610Sgiacomo.gabrielli@arm.comvoid 15759920Syasuko.eckert@amd.comFullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid) 15769920Syasuko.eckert@amd.com{ 15779920Syasuko.eckert@amd.com ccRegfileWrites++; 157812106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 157912106SRekai.GonzalezAlberquilla@arm.com RegId(CCRegClass, reg_idx)); 15809920Syasuko.eckert@amd.com 15819920Syasuko.eckert@amd.com regFile.setCCReg(phys_reg, val); 15829920Syasuko.eckert@amd.com} 15839920Syasuko.eckert@amd.com 15849920Syasuko.eckert@amd.comtemplate <class Impl> 15857720Sgblack@eecs.umich.eduTheISA::PCState 15867720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 15872292SN/A{ 15887720Sgblack@eecs.umich.edu return commit.pcState(tid); 15891060SN/A} 15901060SN/A 15911060SN/Atemplate <class Impl> 15921060SN/Avoid 15937720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 15941060SN/A{ 15957720Sgblack@eecs.umich.edu commit.pcState(val, tid); 15962292SN/A} 15971060SN/A 15982292SN/Atemplate <class Impl> 15997720Sgblack@eecs.umich.eduAddr 16007720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 16014636Sgblack@eecs.umich.edu{ 16027720Sgblack@eecs.umich.edu return commit.instAddr(tid); 16034636Sgblack@eecs.umich.edu} 16044636Sgblack@eecs.umich.edu 16054636Sgblack@eecs.umich.edutemplate <class Impl> 16067720Sgblack@eecs.umich.eduAddr 16077720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 16084636Sgblack@eecs.umich.edu{ 16097720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 16104636Sgblack@eecs.umich.edu} 16114636Sgblack@eecs.umich.edu 16124636Sgblack@eecs.umich.edutemplate <class Impl> 16137720Sgblack@eecs.umich.eduMicroPC 16147720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 16152292SN/A{ 16167720Sgblack@eecs.umich.edu return commit.microPC(tid); 16174636Sgblack@eecs.umich.edu} 16184636Sgblack@eecs.umich.edu 16194636Sgblack@eecs.umich.edutemplate <class Impl> 16205595Sgblack@eecs.umich.eduvoid 16216221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 16225595Sgblack@eecs.umich.edu{ 16239382SAli.Saidi@ARM.com this->thread[tid]->noSquashFromTC = true; 16245595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 16255595Sgblack@eecs.umich.edu} 16265595Sgblack@eecs.umich.edu 16275595Sgblack@eecs.umich.edutemplate <class Impl> 16282292SN/Atypename FullO3CPU<Impl>::ListIt 162913429Srekai.gonzalezalberquilla@arm.comFullO3CPU<Impl>::addInst(const DynInstPtr &inst) 16302292SN/A{ 16312292SN/A instList.push_back(inst); 16321060SN/A 16332292SN/A return --(instList.end()); 16342292SN/A} 16351060SN/A 16362292SN/Atemplate <class Impl> 16372292SN/Avoid 163813429Srekai.gonzalezalberquilla@arm.comFullO3CPU<Impl>::instDone(ThreadID tid, const DynInstPtr &inst) 16392292SN/A{ 16402292SN/A // Keep an instruction count. 16418834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 16428834Satgutier@umich.edu thread[tid]->numInst++; 16438834Satgutier@umich.edu thread[tid]->numInsts++; 16448834Satgutier@umich.edu committedInsts[tid]++; 164510774Snikos.nikoleris@gmail.com system->totalNumInsts++; 164610774Snikos.nikoleris@gmail.com 164710774Snikos.nikoleris@gmail.com // Check for instruction-count-based events. 164810774Snikos.nikoleris@gmail.com comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 164910774Snikos.nikoleris@gmail.com system->instEventQueue.serviceEvents(system->totalNumInsts); 16508834Satgutier@umich.edu } 16518834Satgutier@umich.edu thread[tid]->numOp++; 16528834Satgutier@umich.edu thread[tid]->numOps++; 16538834Satgutier@umich.edu committedOps[tid]++; 16548834Satgutier@umich.edu 165510464SAndreas.Sandberg@ARM.com probeInstCommit(inst->staticInst); 16562292SN/A} 16572292SN/A 16582292SN/Atemplate <class Impl> 16592292SN/Avoid 166013429Srekai.gonzalezalberquilla@arm.comFullO3CPU<Impl>::removeFrontInst(const DynInstPtr &inst) 16611060SN/A{ 16627720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 16632292SN/A "[sn:%lli]\n", 16647720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 16651060SN/A 16662292SN/A removeInstsThisCycle = true; 16671060SN/A 16681060SN/A // Remove the front instruction. 16692292SN/A removeList.push(inst->getInstListIt()); 16701060SN/A} 16711060SN/A 16721060SN/Atemplate <class Impl> 16731060SN/Avoid 16746221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 16751060SN/A{ 16762733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 16772292SN/A " list.\n", tid); 16781060SN/A 16792292SN/A ListIt end_it; 16801060SN/A 16812292SN/A bool rob_empty = false; 16822292SN/A 16832292SN/A if (instList.empty()) { 16842292SN/A return; 168510164Ssleimanf@umich.edu } else if (rob.isEmpty(tid)) { 16862733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 16872292SN/A end_it = instList.begin(); 16882292SN/A rob_empty = true; 16892292SN/A } else { 16902292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 16912733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 16922292SN/A } 16932292SN/A 16942292SN/A removeInstsThisCycle = true; 16952292SN/A 16962292SN/A ListIt inst_it = instList.end(); 16972292SN/A 16982292SN/A inst_it--; 16992292SN/A 17002292SN/A // Walk through the instruction list, removing any instructions 17012292SN/A // that were inserted after the given instruction iterator, end_it. 17022292SN/A while (inst_it != end_it) { 17032292SN/A assert(!instList.empty()); 17042292SN/A 17052292SN/A squashInstIt(inst_it, tid); 17062292SN/A 17072292SN/A inst_it--; 17082292SN/A } 17092292SN/A 17102292SN/A // If the ROB was empty, then we actually need to remove the first 17112292SN/A // instruction as well. 17122292SN/A if (rob_empty) { 17132292SN/A squashInstIt(inst_it, tid); 17142292SN/A } 17151060SN/A} 17161060SN/A 17171060SN/Atemplate <class Impl> 17181060SN/Avoid 17196221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 17201062SN/A{ 17212292SN/A assert(!instList.empty()); 17222292SN/A 17232292SN/A removeInstsThisCycle = true; 17242292SN/A 17252292SN/A ListIt inst_iter = instList.end(); 17262292SN/A 17272292SN/A inst_iter--; 17282292SN/A 17292733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 17302292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 17312292SN/A tid, seq_num, (*inst_iter)->seqNum); 17321062SN/A 17332292SN/A while ((*inst_iter)->seqNum > seq_num) { 17341062SN/A 17352292SN/A bool break_loop = (inst_iter == instList.begin()); 17361062SN/A 17372292SN/A squashInstIt(inst_iter, tid); 17381062SN/A 17392292SN/A inst_iter--; 17401062SN/A 17412292SN/A if (break_loop) 17422292SN/A break; 17432292SN/A } 17442292SN/A} 17452292SN/A 17462292SN/Atemplate <class Impl> 17472292SN/Ainline void 17486221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 17492292SN/A{ 17502292SN/A if ((*instIt)->threadNumber == tid) { 17512733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 17527720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 17532292SN/A (*instIt)->threadNumber, 17542292SN/A (*instIt)->seqNum, 17557720Sgblack@eecs.umich.edu (*instIt)->pcState()); 17561062SN/A 17571062SN/A // Mark it as squashed. 17582292SN/A (*instIt)->setSquashed(); 17592292SN/A 17602325SN/A // @todo: Formulate a consistent method for deleting 17612325SN/A // instructions from the instruction list 17622292SN/A // Remove the instruction from the list. 17632292SN/A removeList.push(instIt); 17642292SN/A } 17652292SN/A} 17662292SN/A 17672292SN/Atemplate <class Impl> 17682292SN/Avoid 17692292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 17702292SN/A{ 17712292SN/A while (!removeList.empty()) { 17722733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 17737720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 17742292SN/A (*removeList.front())->threadNumber, 17752292SN/A (*removeList.front())->seqNum, 17767720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 17772292SN/A 17782292SN/A instList.erase(removeList.front()); 17792292SN/A 17802292SN/A removeList.pop(); 17811062SN/A } 17821062SN/A 17832292SN/A removeInstsThisCycle = false; 17841062SN/A} 17852325SN/A/* 17861062SN/Atemplate <class Impl> 17871062SN/Avoid 17881755SN/AFullO3CPU<Impl>::removeAllInsts() 17891060SN/A{ 17901060SN/A instList.clear(); 17911060SN/A} 17922325SN/A*/ 17931060SN/Atemplate <class Impl> 17941060SN/Avoid 17951755SN/AFullO3CPU<Impl>::dumpInsts() 17961060SN/A{ 17971060SN/A int num = 0; 17981060SN/A 17992292SN/A ListIt inst_list_it = instList.begin(); 18002292SN/A 18012292SN/A cprintf("Dumping Instruction List\n"); 18022292SN/A 18032292SN/A while (inst_list_it != instList.end()) { 18042292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 18052292SN/A "Squashed:%i\n\n", 18067720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 18072292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 18082292SN/A (*inst_list_it)->isSquashed()); 18091060SN/A inst_list_it++; 18101060SN/A ++num; 18111060SN/A } 18121060SN/A} 18132325SN/A/* 18141060SN/Atemplate <class Impl> 18151060SN/Avoid 181613429Srekai.gonzalezalberquilla@arm.comFullO3CPU<Impl>::wakeDependents(const DynInstPtr &inst) 18171060SN/A{ 18181060SN/A iew.wakeDependents(inst); 18191060SN/A} 18202325SN/A*/ 18212292SN/Atemplate <class Impl> 18222292SN/Avoid 18232292SN/AFullO3CPU<Impl>::wakeCPU() 18242292SN/A{ 18252325SN/A if (activityRec.active() || tickEvent.scheduled()) { 18262325SN/A DPRINTF(Activity, "CPU already running.\n"); 18272292SN/A return; 18282292SN/A } 18292292SN/A 18302325SN/A DPRINTF(Activity, "Waking up CPU\n"); 18312325SN/A 18329180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 18339180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 183410464SAndreas.Sandberg@ARM.com if (cycles > 1) { 18359179Sandreas.hansson@arm.com --cycles; 183610464SAndreas.Sandberg@ARM.com idleCycles += cycles; 183710464SAndreas.Sandberg@ARM.com numCycles += cycles; 183810464SAndreas.Sandberg@ARM.com } 18392292SN/A 18409648Sdam.sunwoo@arm.com schedule(tickEvent, clockEdge()); 18412292SN/A} 18422292SN/A 18435807Snate@binkert.orgtemplate <class Impl> 18445807Snate@binkert.orgvoid 184511151Smitch.hayenga@arm.comFullO3CPU<Impl>::wakeup(ThreadID tid) 18465807Snate@binkert.org{ 184711151Smitch.hayenga@arm.com if (this->thread[tid]->status() != ThreadContext::Suspended) 18485807Snate@binkert.org return; 18495807Snate@binkert.org 18505807Snate@binkert.org this->wakeCPU(); 18515807Snate@binkert.org 18525807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 185311151Smitch.hayenga@arm.com this->threadContexts[tid]->activate(); 18545807Snate@binkert.org} 18555807Snate@binkert.org 18562292SN/Atemplate <class Impl> 18576221Snate@binkert.orgThreadID 18582292SN/AFullO3CPU<Impl>::getFreeTid() 18592292SN/A{ 18606221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 18616221Snate@binkert.org if (!tids[tid]) { 18626221Snate@binkert.org tids[tid] = true; 18636221Snate@binkert.org return tid; 18642292SN/A } 18652292SN/A } 18662292SN/A 18676221Snate@binkert.org return InvalidThreadID; 18682292SN/A} 18692292SN/A 18702292SN/Atemplate <class Impl> 18712292SN/Avoid 18722292SN/AFullO3CPU<Impl>::updateThreadPriority() 18732292SN/A{ 18746221Snate@binkert.org if (activeThreads.size() > 1) { 18752292SN/A //DEFAULT TO ROUND ROBIN SCHEME 18762292SN/A //e.g. Move highest priority to end of thread list 18776221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 18782292SN/A 18792292SN/A unsigned high_thread = *list_begin; 18802292SN/A 18812292SN/A activeThreads.erase(list_begin); 18822292SN/A 18832292SN/A activeThreads.push_back(high_thread); 18842292SN/A } 18852292SN/A} 18861060SN/A 18871755SN/A// Forward declaration of FullO3CPU. 18882818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1889