cpu.cc revision 12276
11689SN/A/* 212143Sanouk.vanlaer@arm.com * Copyright (c) 2011-2012, 2014, 2016, 2017 ARM Limited 39916Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 152325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 167897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432756Sksewell@umich.edu * Korey Sewell 447897Shestness@cs.utexas.edu * Rick Strong 451689SN/A */ 461689SN/A 4711793Sbrandon.potter@amd.com#include "cpu/o3/cpu.hh" 4811793Sbrandon.potter@amd.com 4912109SRekai.GonzalezAlberquilla@arm.com#include "arch/generic/traits.hh" 508779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 516658Snate@binkert.org#include "config/the_isa.hh" 5211793Sbrandon.potter@amd.com#include "cpu/activity.hh" 538887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 548887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 558229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 568229Snate@binkert.org#include "cpu/o3/thread_context.hh" 578779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 584762Snate@binkert.org#include "cpu/simple_thread.hh" 594762Snate@binkert.org#include "cpu/thread_context.hh" 608232Snate@binkert.org#include "debug/Activity.hh" 619152Satgutier@umich.edu#include "debug/Drain.hh" 628232Snate@binkert.org#include "debug/O3CPU.hh" 638232Snate@binkert.org#include "debug/Quiesce.hh" 644762Snate@binkert.org#include "enums/MemoryMode.hh" 654762Snate@binkert.org#include "sim/core.hh" 668793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 678779Sgblack@eecs.umich.edu#include "sim/process.hh" 684762Snate@binkert.org#include "sim/stat_control.hh" 698460SAli.Saidi@ARM.com#include "sim/system.hh" 704762Snate@binkert.org 715702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 725702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 738232Snate@binkert.org#include "debug/Activity.hh" 7411793Sbrandon.potter@amd.com 755702Ssaidi@eecs.umich.edu#endif 765702Ssaidi@eecs.umich.edu 778737Skoansin.tan@gmail.comstruct BaseCPUParams; 785529Snate@binkert.org 792669Sktlim@umich.eduusing namespace TheISA; 806221Snate@binkert.orgusing namespace std; 811060SN/A 825529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 835712Shsul@eecs.umich.edu : BaseCPU(params) 841060SN/A{ 851060SN/A} 861060SN/A 872292SN/Avoid 882733Sktlim@umich.eduBaseO3CPU::regStats() 892292SN/A{ 902292SN/A BaseCPU::regStats(); 912292SN/A} 922292SN/A 938707Sandreas.hansson@arm.comtemplate<class Impl> 948707Sandreas.hansson@arm.combool 958975Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 968707Sandreas.hansson@arm.com{ 978707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 9811284Sandreas.hansson@arm.com // We shouldn't ever get a cacheable block in Modified state 9910821Sandreas.hansson@arm.com assert(pkt->req->isUncacheable() || 10011284Sandreas.hansson@arm.com !(pkt->cacheResponding() && !pkt->hasSharers())); 1018948Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 1028707Sandreas.hansson@arm.com 1038707Sandreas.hansson@arm.com return true; 1048707Sandreas.hansson@arm.com} 1058707Sandreas.hansson@arm.com 1068707Sandreas.hansson@arm.comtemplate<class Impl> 1078707Sandreas.hansson@arm.comvoid 10810713Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvReqRetry() 1098707Sandreas.hansson@arm.com{ 11010713Sandreas.hansson@arm.com fetch->recvReqRetry(); 1118707Sandreas.hansson@arm.com} 1128707Sandreas.hansson@arm.com 1138707Sandreas.hansson@arm.comtemplate <class Impl> 1148707Sandreas.hansson@arm.combool 1158975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 1168707Sandreas.hansson@arm.com{ 1178975Sandreas.hansson@arm.com return lsq->recvTimingResp(pkt); 1188707Sandreas.hansson@arm.com} 1198707Sandreas.hansson@arm.com 1208707Sandreas.hansson@arm.comtemplate <class Impl> 1218975Sandreas.hansson@arm.comvoid 1228975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 1238948Sandreas.hansson@arm.com{ 12411148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 12511148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 12611151Smitch.hayenga@arm.com cpu->wakeup(tid); 12711148Smitch.hayenga@arm.com } 12810529Smorr@cs.wisc.edu } 1298975Sandreas.hansson@arm.com lsq->recvTimingSnoopReq(pkt); 1308948Sandreas.hansson@arm.com} 1318948Sandreas.hansson@arm.com 1328948Sandreas.hansson@arm.comtemplate <class Impl> 1338707Sandreas.hansson@arm.comvoid 13410713Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvReqRetry() 1358707Sandreas.hansson@arm.com{ 13610713Sandreas.hansson@arm.com lsq->recvReqRetry(); 1378707Sandreas.hansson@arm.com} 1388707Sandreas.hansson@arm.com 1391060SN/Atemplate <class Impl> 1405595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1412733Sktlim@umich.edu : BaseO3CPU(params), 1423781Sgblack@eecs.umich.edu itb(params->itb), 1433781Sgblack@eecs.umich.edu dtb(params->dtb), 14412127Sspwilson2@wisc.edu tickEvent([this]{ tick(); }, "FullO3CPU tick", 14512127Sspwilson2@wisc.edu false, Event::CPU_Tick_Pri), 1465737Scws3k@cs.virginia.edu#ifndef NDEBUG 1475737Scws3k@cs.virginia.edu instcount(0), 1485737Scws3k@cs.virginia.edu#endif 1492292SN/A removeInstsThisCycle(false), 1505595Sgblack@eecs.umich.edu fetch(this, params), 1515595Sgblack@eecs.umich.edu decode(this, params), 1525595Sgblack@eecs.umich.edu rename(this, params), 1535595Sgblack@eecs.umich.edu iew(this, params), 1545595Sgblack@eecs.umich.edu commit(this, params), 1551060SN/A 15612109SRekai.GonzalezAlberquilla@arm.com /* It is mandatory that all SMT threads use the same renaming mode as 15712109SRekai.GonzalezAlberquilla@arm.com * they are sharing registers and rename */ 15812109SRekai.GonzalezAlberquilla@arm.com vecMode(initRenameMode<TheISA::ISA>::mode(params->isa[0])), 1599915Ssteve.reinhardt@amd.com regFile(params->numPhysIntRegs, 1609920Syasuko.eckert@amd.com params->numPhysFloatRegs, 16112109SRekai.GonzalezAlberquilla@arm.com params->numPhysVecRegs, 16212109SRekai.GonzalezAlberquilla@arm.com params->numPhysCCRegs, 16312109SRekai.GonzalezAlberquilla@arm.com vecMode), 1641060SN/A 1659919Ssteve.reinhardt@amd.com freeList(name() + ".freelist", ®File), 1661060SN/A 1679954SFaissal.Sleiman@arm.com rob(this, params), 1681060SN/A 1699916Ssteve.reinhardt@amd.com scoreboard(name() + ".scoreboard", 17012105Snathanael.premillieu@arm.com regFile.totalNumPhysRegs()), 1711060SN/A 1729384SAndreas.Sandberg@arm.com isa(numThreads, NULL), 1739384SAndreas.Sandberg@arm.com 1748707Sandreas.hansson@arm.com icachePort(&fetch, this), 1758707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 1768707Sandreas.hansson@arm.com 1772873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1782873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1792873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1802873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1812873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1825804Snate@binkert.org activityRec(name(), NumStages, 1832873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1842873Sktlim@umich.edu params->activity), 1851060SN/A 1861060SN/A globalSeqNum(1), 1872292SN/A system(params->system), 1889180Sandreas.hansson@arm.com lastRunningCycle(curCycle()) 1891060SN/A{ 1909433SAndreas.Sandberg@ARM.com if (!params->switched_out) { 1913221Sktlim@umich.edu _status = Running; 1923221Sktlim@umich.edu } else { 1939152Satgutier@umich.edu _status = SwitchedOut; 1943221Sktlim@umich.edu } 1951681SN/A 1962794Sktlim@umich.edu if (params->checker) { 1972316SN/A BaseCPU *temp_checker = params->checker; 1988733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 1998707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2002316SN/A checker->setSystem(params->system); 2014598Sbinkertn@umich.edu } else { 2024598Sbinkertn@umich.edu checker = NULL; 2034598Sbinkertn@umich.edu } 2042316SN/A 2058793Sgblack@eecs.umich.edu if (!FullSystem) { 2068793Sgblack@eecs.umich.edu thread.resize(numThreads); 2078793Sgblack@eecs.umich.edu tids.resize(numThreads); 2088793Sgblack@eecs.umich.edu } 2091681SN/A 2102325SN/A // The stages also need their CPU pointer setup. However this 2112325SN/A // must be done at the upper level CPU because they have pointers 2122325SN/A // to the upper level CPU, and not this FullO3CPU. 2131060SN/A 2142292SN/A // Set up Pointers to the activeThreads list for each stage 2152292SN/A fetch.setActiveThreads(&activeThreads); 2162292SN/A decode.setActiveThreads(&activeThreads); 2172292SN/A rename.setActiveThreads(&activeThreads); 2182292SN/A iew.setActiveThreads(&activeThreads); 2192292SN/A commit.setActiveThreads(&activeThreads); 2201060SN/A 2211060SN/A // Give each of the stages the time buffer they will use. 2221060SN/A fetch.setTimeBuffer(&timeBuffer); 2231060SN/A decode.setTimeBuffer(&timeBuffer); 2241060SN/A rename.setTimeBuffer(&timeBuffer); 2251060SN/A iew.setTimeBuffer(&timeBuffer); 2261060SN/A commit.setTimeBuffer(&timeBuffer); 2271060SN/A 2281060SN/A // Also setup each of the stages' queues. 2291060SN/A fetch.setFetchQueue(&fetchQueue); 2301060SN/A decode.setFetchQueue(&fetchQueue); 2312292SN/A commit.setFetchQueue(&fetchQueue); 2321060SN/A decode.setDecodeQueue(&decodeQueue); 2331060SN/A rename.setDecodeQueue(&decodeQueue); 2341060SN/A rename.setRenameQueue(&renameQueue); 2351060SN/A iew.setRenameQueue(&renameQueue); 2361060SN/A iew.setIEWQueue(&iewQueue); 2371060SN/A commit.setIEWQueue(&iewQueue); 2381060SN/A commit.setRenameQueue(&renameQueue); 2391060SN/A 2402292SN/A commit.setIEWStage(&iew); 2412292SN/A rename.setIEWStage(&iew); 2422292SN/A rename.setCommitStage(&commit); 2432292SN/A 2448793Sgblack@eecs.umich.edu ThreadID active_threads; 2458793Sgblack@eecs.umich.edu if (FullSystem) { 2468793Sgblack@eecs.umich.edu active_threads = 1; 2478793Sgblack@eecs.umich.edu } else { 2488793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 2492831Sksewell@umich.edu 2508793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 2518793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 2528793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 2538793Sgblack@eecs.umich.edu "or edit your workload size."); 2548793Sgblack@eecs.umich.edu } 2552831Sksewell@umich.edu } 2562292SN/A 2572316SN/A //Make Sure That this a Valid Architeture 2582292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2592292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 26012109SRekai.GonzalezAlberquilla@arm.com assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs); 2619920Syasuko.eckert@amd.com assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs); 2622292SN/A 2632292SN/A rename.setScoreboard(&scoreboard); 2642292SN/A iew.setScoreboard(&scoreboard); 2652292SN/A 2661060SN/A // Setup the rename map for whichever stages need it. 2676221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2689384SAndreas.Sandberg@arm.com isa[tid] = params->isa[tid]; 26912109SRekai.GonzalezAlberquilla@arm.com assert(initRenameMode<TheISA::ISA>::equals(isa[tid], isa[0])); 2709384SAndreas.Sandberg@arm.com 2719919Ssteve.reinhardt@amd.com // Only Alpha has an FP zero register, so for other ISAs we 2729919Ssteve.reinhardt@amd.com // use an invalid FP register index to avoid special treatment 2739919Ssteve.reinhardt@amd.com // of any valid FP reg. 2749919Ssteve.reinhardt@amd.com RegIndex invalidFPReg = TheISA::NumFloatRegs + 1; 2759919Ssteve.reinhardt@amd.com RegIndex fpZeroReg = 2769919Ssteve.reinhardt@amd.com (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg; 2772292SN/A 2789919Ssteve.reinhardt@amd.com commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 27912109SRekai.GonzalezAlberquilla@arm.com &freeList, 28012109SRekai.GonzalezAlberquilla@arm.com vecMode); 2812292SN/A 2829919Ssteve.reinhardt@amd.com renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 28312109SRekai.GonzalezAlberquilla@arm.com &freeList, vecMode); 2842292SN/A } 2852292SN/A 2869919Ssteve.reinhardt@amd.com // Initialize rename map to assign physical registers to the 2879919Ssteve.reinhardt@amd.com // architectural registers for active threads only. 2889919Ssteve.reinhardt@amd.com for (ThreadID tid = 0; tid < active_threads; tid++) { 2899919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) { 2909919Ssteve.reinhardt@amd.com // Note that we can't use the rename() method because we don't 2919919Ssteve.reinhardt@amd.com // want special treatment for the zero register at this point 29212105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getIntReg(); 29312106SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg); 29412106SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg); 2959919Ssteve.reinhardt@amd.com } 2969919Ssteve.reinhardt@amd.com 2979919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) { 29812105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getFloatReg(); 29912106SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg); 30012106SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry( 30112106SRekai.GonzalezAlberquilla@arm.com RegId(FloatRegClass, ridx), phys_reg); 3029919Ssteve.reinhardt@amd.com } 3039920Syasuko.eckert@amd.com 30412109SRekai.GonzalezAlberquilla@arm.com /* Here we need two 'interfaces' the 'whole register' and the 30512109SRekai.GonzalezAlberquilla@arm.com * 'register element'. At any point only one of them will be 30612109SRekai.GonzalezAlberquilla@arm.com * active. */ 30712109SRekai.GonzalezAlberquilla@arm.com if (vecMode == Enums::Full) { 30812109SRekai.GonzalezAlberquilla@arm.com /* Initialize the full-vector interface */ 30912109SRekai.GonzalezAlberquilla@arm.com for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) { 31012109SRekai.GonzalezAlberquilla@arm.com RegId rid = RegId(VecRegClass, ridx); 31112109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = freeList.getVecReg(); 31212109SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(rid, phys_reg); 31312109SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(rid, phys_reg); 31412109SRekai.GonzalezAlberquilla@arm.com } 31512109SRekai.GonzalezAlberquilla@arm.com } else { 31612109SRekai.GonzalezAlberquilla@arm.com /* Initialize the vector-element interface */ 31712109SRekai.GonzalezAlberquilla@arm.com for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) { 31812109SRekai.GonzalezAlberquilla@arm.com for (ElemIndex ldx = 0; ldx < TheISA::NumVecElemPerVecReg; 31912109SRekai.GonzalezAlberquilla@arm.com ++ldx) { 32012109SRekai.GonzalezAlberquilla@arm.com RegId lrid = RegId(VecElemClass, ridx, ldx); 32112109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_elem = freeList.getVecElem(); 32212109SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(lrid, phys_elem); 32312109SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(lrid, phys_elem); 32412109SRekai.GonzalezAlberquilla@arm.com } 32512109SRekai.GonzalezAlberquilla@arm.com } 32612109SRekai.GonzalezAlberquilla@arm.com } 32712109SRekai.GonzalezAlberquilla@arm.com 3289920Syasuko.eckert@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) { 32912105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getCCReg(); 33012106SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg); 33112106SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg); 3329920Syasuko.eckert@amd.com } 3339919Ssteve.reinhardt@amd.com } 3349919Ssteve.reinhardt@amd.com 3352292SN/A rename.setRenameMap(renameMap); 3362292SN/A commit.setRenameMap(commitRenameMap); 3371060SN/A rename.setFreeList(&freeList); 3382292SN/A 3391060SN/A // Setup the ROB for whichever stages need it. 3401060SN/A commit.setROB(&rob); 3412292SN/A 3429158Sandreas.hansson@arm.com lastActivatedCycle = 0; 3436221Snate@binkert.org#if 0 3443093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3456221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3466221Snate@binkert.org globalSeqNum[tid] = 1; 3476221Snate@binkert.org#endif 3483093Sksewell@umich.edu 3495595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3505595Sgblack@eecs.umich.edu 3515595Sgblack@eecs.umich.edu // Setup any thread state. 3525595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3535595Sgblack@eecs.umich.edu 3546221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 3558793Sgblack@eecs.umich.edu if (FullSystem) { 3568793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3578793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3588793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 3598793Sgblack@eecs.umich.edu } else { 3608793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 3618793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3628793Sgblack@eecs.umich.edu tid, this->thread[tid]); 3638793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3648793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3658793Sgblack@eecs.umich.edu tid, params->workload[tid]); 3665595Sgblack@eecs.umich.edu 3678793Sgblack@eecs.umich.edu //usedTids[tid] = true; 3688793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 3698793Sgblack@eecs.umich.edu } else { 3708793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3718793Sgblack@eecs.umich.edu //when scheduling threads to CPU 3728793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3735595Sgblack@eecs.umich.edu 3748793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3758793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3768793Sgblack@eecs.umich.edu tid, dummy_proc); 3778793Sgblack@eecs.umich.edu //usedTids[tid] = false; 3788793Sgblack@eecs.umich.edu } 3795595Sgblack@eecs.umich.edu } 3805595Sgblack@eecs.umich.edu 3815595Sgblack@eecs.umich.edu ThreadContext *tc; 3825595Sgblack@eecs.umich.edu 3835595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3845595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3855595Sgblack@eecs.umich.edu 3865595Sgblack@eecs.umich.edu tc = o3_tc; 3875595Sgblack@eecs.umich.edu 3885595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3895595Sgblack@eecs.umich.edu // CheckerThreadContext. 3905595Sgblack@eecs.umich.edu if (params->checker) { 3915595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3925595Sgblack@eecs.umich.edu o3_tc, this->checker); 3935595Sgblack@eecs.umich.edu } 3945595Sgblack@eecs.umich.edu 3955595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 3965595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 3976221Snate@binkert.org o3_tc->thread = this->thread[tid]; 3985595Sgblack@eecs.umich.edu 39911627Smichael.lebeane@amd.com // Setup quiesce event. 40011627Smichael.lebeane@amd.com this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 40111627Smichael.lebeane@amd.com 4025595Sgblack@eecs.umich.edu // Give the thread the TC. 4036221Snate@binkert.org this->thread[tid]->tc = tc; 4045595Sgblack@eecs.umich.edu 4055595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4065595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4075595Sgblack@eecs.umich.edu } 4085595Sgblack@eecs.umich.edu 4098876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 41011150Smitch.hayenga@arm.com if (!params->switched_out && interrupts.empty()) { 4118876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 4128876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 4138876Sandreas.hansson@arm.com } 4148876Sandreas.hansson@arm.com 4156221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4166221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4171060SN/A} 4181060SN/A 4191060SN/Atemplate <class Impl> 4201755SN/AFullO3CPU<Impl>::~FullO3CPU() 4211060SN/A{ 4221060SN/A} 4231060SN/A 4241060SN/Atemplate <class Impl> 4251060SN/Avoid 42610023Smatt.horsnell@ARM.comFullO3CPU<Impl>::regProbePoints() 42710023Smatt.horsnell@ARM.com{ 42810464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 42910464SAndreas.Sandberg@ARM.com 43010023Smatt.horsnell@ARM.com ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete"); 43110023Smatt.horsnell@ARM.com ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete"); 43210464SAndreas.Sandberg@ARM.com 43310023Smatt.horsnell@ARM.com fetch.regProbePoints(); 43411246Sradhika.jagtap@ARM.com rename.regProbePoints(); 43510023Smatt.horsnell@ARM.com iew.regProbePoints(); 43610023Smatt.horsnell@ARM.com commit.regProbePoints(); 43710023Smatt.horsnell@ARM.com} 43810023Smatt.horsnell@ARM.com 43910023Smatt.horsnell@ARM.comtemplate <class Impl> 44010023Smatt.horsnell@ARM.comvoid 4415595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4421062SN/A{ 4432733Sktlim@umich.edu BaseO3CPU::regStats(); 4442292SN/A 4452733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4462292SN/A timesIdled 4472292SN/A .name(name() + ".timesIdled") 4482292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4492292SN/A " unscheduled itself") 4502292SN/A .prereq(timesIdled); 4512292SN/A 4522292SN/A idleCycles 4532292SN/A .name(name() + ".idleCycles") 4542292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4552292SN/A "to idling") 4562292SN/A .prereq(idleCycles); 4572292SN/A 4588627SAli.Saidi@ARM.com quiesceCycles 4598627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 4608627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 4618627SAli.Saidi@ARM.com "for an interrupt") 4628627SAli.Saidi@ARM.com .prereq(quiesceCycles); 4638627SAli.Saidi@ARM.com 4642292SN/A // Number of Instructions simulated 4652292SN/A // -------------------------------- 4662292SN/A // Should probably be in Base CPU but need templated 4672292SN/A // MaxThreads so put in here instead 4682292SN/A committedInsts 4692292SN/A .init(numThreads) 4702292SN/A .name(name() + ".committedInsts") 47110225Snilay@cs.wisc.edu .desc("Number of Instructions Simulated") 47210225Snilay@cs.wisc.edu .flags(Stats::total); 4732292SN/A 4748834Satgutier@umich.edu committedOps 4758834Satgutier@umich.edu .init(numThreads) 4768834Satgutier@umich.edu .name(name() + ".committedOps") 47710225Snilay@cs.wisc.edu .desc("Number of Ops (including micro ops) Simulated") 47810225Snilay@cs.wisc.edu .flags(Stats::total); 4792292SN/A 4802292SN/A cpi 4812292SN/A .name(name() + ".cpi") 4822292SN/A .desc("CPI: Cycles Per Instruction") 4832292SN/A .precision(6); 4844392Sktlim@umich.edu cpi = numCycles / committedInsts; 4852292SN/A 4862292SN/A totalCpi 4872292SN/A .name(name() + ".cpi_total") 4882292SN/A .desc("CPI: Total CPI of All Threads") 4892292SN/A .precision(6); 49010225Snilay@cs.wisc.edu totalCpi = numCycles / sum(committedInsts); 4912292SN/A 4922292SN/A ipc 4932292SN/A .name(name() + ".ipc") 4942292SN/A .desc("IPC: Instructions Per Cycle") 4952292SN/A .precision(6); 4964392Sktlim@umich.edu ipc = committedInsts / numCycles; 4972292SN/A 4982292SN/A totalIpc 4992292SN/A .name(name() + ".ipc_total") 5002292SN/A .desc("IPC: Total IPC of All Threads") 5012292SN/A .precision(6); 50210225Snilay@cs.wisc.edu totalIpc = sum(committedInsts) / numCycles; 5032292SN/A 5045595Sgblack@eecs.umich.edu this->fetch.regStats(); 5055595Sgblack@eecs.umich.edu this->decode.regStats(); 5065595Sgblack@eecs.umich.edu this->rename.regStats(); 5075595Sgblack@eecs.umich.edu this->iew.regStats(); 5085595Sgblack@eecs.umich.edu this->commit.regStats(); 5097897Shestness@cs.utexas.edu this->rob.regStats(); 5107897Shestness@cs.utexas.edu 5117897Shestness@cs.utexas.edu intRegfileReads 5127897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 5137897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 5147897Shestness@cs.utexas.edu .prereq(intRegfileReads); 5157897Shestness@cs.utexas.edu 5167897Shestness@cs.utexas.edu intRegfileWrites 5177897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 5187897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 5197897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 5207897Shestness@cs.utexas.edu 5217897Shestness@cs.utexas.edu fpRegfileReads 5227897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 5237897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5247897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5257897Shestness@cs.utexas.edu 5267897Shestness@cs.utexas.edu fpRegfileWrites 5277897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5287897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5297897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5307897Shestness@cs.utexas.edu 53112109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads 53212109SRekai.GonzalezAlberquilla@arm.com .name(name() + ".vec_regfile_reads") 53312109SRekai.GonzalezAlberquilla@arm.com .desc("number of vector regfile reads") 53412109SRekai.GonzalezAlberquilla@arm.com .prereq(vecRegfileReads); 53512109SRekai.GonzalezAlberquilla@arm.com 53612109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites 53712109SRekai.GonzalezAlberquilla@arm.com .name(name() + ".vec_regfile_writes") 53812109SRekai.GonzalezAlberquilla@arm.com .desc("number of vector regfile writes") 53912109SRekai.GonzalezAlberquilla@arm.com .prereq(vecRegfileWrites); 54012109SRekai.GonzalezAlberquilla@arm.com 5419920Syasuko.eckert@amd.com ccRegfileReads 5429920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_reads") 5439920Syasuko.eckert@amd.com .desc("number of cc regfile reads") 5449920Syasuko.eckert@amd.com .prereq(ccRegfileReads); 5459920Syasuko.eckert@amd.com 5469920Syasuko.eckert@amd.com ccRegfileWrites 5479920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_writes") 5489920Syasuko.eckert@amd.com .desc("number of cc regfile writes") 5499920Syasuko.eckert@amd.com .prereq(ccRegfileWrites); 5509920Syasuko.eckert@amd.com 5517897Shestness@cs.utexas.edu miscRegfileReads 5527897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5537897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5547897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5557897Shestness@cs.utexas.edu 5567897Shestness@cs.utexas.edu miscRegfileWrites 5577897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5587897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5597897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5601062SN/A} 5611062SN/A 5621062SN/Atemplate <class Impl> 5631062SN/Avoid 5641755SN/AFullO3CPU<Impl>::tick() 5651060SN/A{ 5662733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5679444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 56810913Sandreas.sandberg@arm.com assert(drainState() != DrainState::Drained); 5691060SN/A 5702292SN/A ++numCycles; 57110464SAndreas.Sandberg@ARM.com ppCycles->notify(1); 5722292SN/A 5732325SN/A// activity = false; 5742292SN/A 5752292SN/A //Tick each of the stages 5761060SN/A fetch.tick(); 5771060SN/A 5781060SN/A decode.tick(); 5791060SN/A 5801060SN/A rename.tick(); 5811060SN/A 5821060SN/A iew.tick(); 5831060SN/A 5841060SN/A commit.tick(); 5851060SN/A 5862292SN/A // Now advance the time buffers 5871060SN/A timeBuffer.advance(); 5881060SN/A 5891060SN/A fetchQueue.advance(); 5901060SN/A decodeQueue.advance(); 5911060SN/A renameQueue.advance(); 5921060SN/A iewQueue.advance(); 5931060SN/A 5942325SN/A activityRec.advance(); 5952292SN/A 5962292SN/A if (removeInstsThisCycle) { 5972292SN/A cleanUpRemovedInsts(); 5982292SN/A } 5992292SN/A 6002325SN/A if (!tickEvent.scheduled()) { 6019444SAndreas.Sandberg@ARM.com if (_status == SwitchedOut) { 6023226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 6032325SN/A // increment stat 6049179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6053221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 6063226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 6079179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6082325SN/A timesIdled++; 6092325SN/A } else { 6109180Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(Cycles(1))); 6113226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 6122325SN/A } 6132292SN/A } 6142292SN/A 6158793Sgblack@eecs.umich.edu if (!FullSystem) 6168793Sgblack@eecs.umich.edu updateThreadPriority(); 6179444SAndreas.Sandberg@ARM.com 6189444SAndreas.Sandberg@ARM.com tryDrain(); 6191060SN/A} 6201060SN/A 6211060SN/Atemplate <class Impl> 6221060SN/Avoid 6231755SN/AFullO3CPU<Impl>::init() 6241060SN/A{ 6255714Shsul@eecs.umich.edu BaseCPU::init(); 6261060SN/A 6278921Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 6289382SAli.Saidi@ARM.com // Set noSquashFromTC so that the CPU doesn't squash when initially 6298921Sandreas.hansson@arm.com // setting up registers. 6309382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 6318921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 6328921Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 6338921Sandreas.hansson@arm.com } 6342292SN/A 6359433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 6368793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6378793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6388793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6398793Sgblack@eecs.umich.edu } 6406034Ssteve.reinhardt@amd.com } 6412292SN/A 6429382SAli.Saidi@ARM.com // Clear noSquashFromTC. 6436221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6449382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6452292SN/A 6469427SAndreas.Sandberg@ARM.com commit.setThreads(thread); 6479427SAndreas.Sandberg@ARM.com} 6482292SN/A 6499427SAndreas.Sandberg@ARM.comtemplate <class Impl> 6509427SAndreas.Sandberg@ARM.comvoid 6519427SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::startup() 6529427SAndreas.Sandberg@ARM.com{ 6539992Snilay@cs.wisc.edu BaseCPU::startup(); 6549461Snilay@cs.wisc.edu for (int tid = 0; tid < numThreads; ++tid) 6559461Snilay@cs.wisc.edu isa[tid]->startup(threadContexts[tid]); 6569461Snilay@cs.wisc.edu 6579427SAndreas.Sandberg@ARM.com fetch.startupStage(); 6589444SAndreas.Sandberg@ARM.com decode.startupStage(); 6599427SAndreas.Sandberg@ARM.com iew.startupStage(); 6609427SAndreas.Sandberg@ARM.com rename.startupStage(); 6619427SAndreas.Sandberg@ARM.com commit.startupStage(); 6622292SN/A} 6632292SN/A 6642292SN/Atemplate <class Impl> 6652292SN/Avoid 6666221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6672875Sksewell@umich.edu{ 6686221Snate@binkert.org list<ThreadID>::iterator isActive = 6695314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6702875Sksewell@umich.edu 6713226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6729444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6733226Sktlim@umich.edu 6742875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6752875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6762875Sksewell@umich.edu tid); 6772875Sksewell@umich.edu 6782875Sksewell@umich.edu activeThreads.push_back(tid); 6792875Sksewell@umich.edu } 6802875Sksewell@umich.edu} 6812875Sksewell@umich.edu 6822875Sksewell@umich.edutemplate <class Impl> 6832875Sksewell@umich.eduvoid 6846221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 6852875Sksewell@umich.edu{ 6862875Sksewell@umich.edu //Remove From Active List, if Active 6876221Snate@binkert.org list<ThreadID>::iterator thread_it = 6885314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6892875Sksewell@umich.edu 6903226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 6919444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6923226Sktlim@umich.edu 6932875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6942875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6952875Sksewell@umich.edu tid); 6962875Sksewell@umich.edu activeThreads.erase(thread_it); 6972875Sksewell@umich.edu } 69810331Smitch.hayenga@arm.com 69910331Smitch.hayenga@arm.com fetch.deactivateThread(tid); 70010331Smitch.hayenga@arm.com commit.deactivateThread(tid); 7012875Sksewell@umich.edu} 7022875Sksewell@umich.edu 7032875Sksewell@umich.edutemplate <class Impl> 7046221Snate@binkert.orgCounter 7058834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 7066221Snate@binkert.org{ 7076221Snate@binkert.org Counter total(0); 7086221Snate@binkert.org 7096221Snate@binkert.org ThreadID size = thread.size(); 7106221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 7116221Snate@binkert.org total += thread[i]->numInst; 7126221Snate@binkert.org 7136221Snate@binkert.org return total; 7146221Snate@binkert.org} 7156221Snate@binkert.org 7166221Snate@binkert.orgtemplate <class Impl> 7178834Satgutier@umich.eduCounter 7188834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 7198834Satgutier@umich.edu{ 7208834Satgutier@umich.edu Counter total(0); 7218834Satgutier@umich.edu 7228834Satgutier@umich.edu ThreadID size = thread.size(); 7238834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 7248834Satgutier@umich.edu total += thread[i]->numOp; 7258834Satgutier@umich.edu 7268834Satgutier@umich.edu return total; 7278834Satgutier@umich.edu} 7288834Satgutier@umich.edu 7298834Satgutier@umich.edutemplate <class Impl> 7302875Sksewell@umich.eduvoid 73110407Smitch.hayenga@arm.comFullO3CPU<Impl>::activateContext(ThreadID tid) 7322875Sksewell@umich.edu{ 7339444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7349444SAndreas.Sandberg@ARM.com 7352875Sksewell@umich.edu // Needs to set each stage to running as well. 73610407Smitch.hayenga@arm.com activateThread(tid); 7372875Sksewell@umich.edu 7389444SAndreas.Sandberg@ARM.com // We don't want to wake the CPU if it is drained. In that case, 7399444SAndreas.Sandberg@ARM.com // we just want to flag the thread as active and schedule the tick 7409444SAndreas.Sandberg@ARM.com // event from drainResume() instead. 74110913Sandreas.sandberg@arm.com if (drainState() == DrainState::Drained) 7429444SAndreas.Sandberg@ARM.com return; 7439444SAndreas.Sandberg@ARM.com 7449158Sandreas.hansson@arm.com // If we are time 0 or if the last activation time is in the past, 7459158Sandreas.hansson@arm.com // schedule the next tick and wake up the fetch unit 7469158Sandreas.hansson@arm.com if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 74710407Smitch.hayenga@arm.com scheduleTickEvent(Cycles(0)); 7482875Sksewell@umich.edu 7492875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7502875Sksewell@umich.edu // deschedule itself. 7512875Sksewell@umich.edu activityRec.activity(); 7522875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7532875Sksewell@umich.edu 7549180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 7559180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 7569179Sandreas.hansson@arm.com if (cycles != 0) 7579179Sandreas.hansson@arm.com --cycles; 7589179Sandreas.hansson@arm.com quiesceCycles += cycles; 7598627SAli.Saidi@ARM.com 7607823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7612875Sksewell@umich.edu 7622875Sksewell@umich.edu _status = Running; 76311526Sdavid.guillen@arm.com 76411526Sdavid.guillen@arm.com BaseCPU::activateContext(tid); 7652875Sksewell@umich.edu } 7662875Sksewell@umich.edu} 7672875Sksewell@umich.edu 7682875Sksewell@umich.edutemplate <class Impl> 76910407Smitch.hayenga@arm.comvoid 7706221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 7712875Sksewell@umich.edu{ 7722875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7739444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 77410408Smitch.hayenga@arm.com 77510408Smitch.hayenga@arm.com deactivateThread(tid); 77610407Smitch.hayenga@arm.com 7773221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 77810683Salexandru.dutu@amd.com if (activeThreads.size() == 0) { 7792910Sksewell@umich.edu unscheduleTickEvent(); 78010683Salexandru.dutu@amd.com lastRunningCycle = curCycle(); 78110683Salexandru.dutu@amd.com _status = Idle; 78210683Salexandru.dutu@amd.com } 7838627SAli.Saidi@ARM.com 7848627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 78511526Sdavid.guillen@arm.com 78611526Sdavid.guillen@arm.com BaseCPU::suspendContext(tid); 7872875Sksewell@umich.edu} 7882875Sksewell@umich.edu 7892875Sksewell@umich.edutemplate <class Impl> 7902875Sksewell@umich.eduvoid 7916221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 7922875Sksewell@umich.edu{ 7932910Sksewell@umich.edu //For now, this is the same as deallocate 7942910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 7959444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 79610408Smitch.hayenga@arm.com 79710408Smitch.hayenga@arm.com deactivateThread(tid); 79810408Smitch.hayenga@arm.com removeThread(tid); 7992875Sksewell@umich.edu} 8002875Sksewell@umich.edu 8012875Sksewell@umich.edutemplate <class Impl> 8022875Sksewell@umich.eduvoid 8036221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 8042292SN/A{ 8052847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 8062292SN/A // Will change now that the PC and thread state is internal to the CPU 8072683Sktlim@umich.edu // and not in the ThreadContext. 8088793Sgblack@eecs.umich.edu ThreadContext *src_tc; 8098793Sgblack@eecs.umich.edu if (FullSystem) 8108793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 8118793Sgblack@eecs.umich.edu else 8128793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 8132292SN/A 8142292SN/A //Bind Int Regs to Rename Map 81512104Snathanael.premillieu@arm.com 81612106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs; 81712106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 81812105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getIntReg(); 81912104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 8202292SN/A scoreboard.setReg(phys_reg); 8212292SN/A } 8222292SN/A 8232292SN/A //Bind Float Regs to Rename Map 82412106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs; 82512106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 82612105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getFloatReg(); 82712104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 8282292SN/A scoreboard.setReg(phys_reg); 8292292SN/A } 8302292SN/A 8319920Syasuko.eckert@amd.com //Bind condition-code Regs to Rename Map 83212106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs; 83312106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 83412105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getCCReg(); 83512104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 8369920Syasuko.eckert@amd.com scoreboard.setReg(phys_reg); 8379920Syasuko.eckert@amd.com } 8389920Syasuko.eckert@amd.com 8392292SN/A //Copy Thread Data Into RegFile 8402847Sksewell@umich.edu //this->copyFromTC(tid); 8412292SN/A 8422847Sksewell@umich.edu //Set PC/NPC/NNPC 8437720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8442292SN/A 8452680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8462292SN/A 84710407Smitch.hayenga@arm.com activateContext(tid); 8482292SN/A 8492292SN/A //Reset ROB/IQ/LSQ Entries 8502292SN/A commit.rob->resetEntries(); 8512292SN/A iew.resetEntries(); 8522292SN/A} 8532292SN/A 8542292SN/Atemplate <class Impl> 8552292SN/Avoid 8566221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8572292SN/A{ 8582877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 8592847Sksewell@umich.edu 8602847Sksewell@umich.edu // Copy Thread Data From RegFile 8612847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 8625364Sksewell@umich.edu // this->copyToTC(tid); 8635364Sksewell@umich.edu 8645364Sksewell@umich.edu 8655364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 8665364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 8675364Sksewell@umich.edu // in SMT workloads. 8682847Sksewell@umich.edu 8692847Sksewell@umich.edu // Unbind Int Regs from Rename Map 87012106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs; 87112106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 87212105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id); 8732292SN/A scoreboard.unsetReg(phys_reg); 8742292SN/A freeList.addReg(phys_reg); 8752292SN/A } 8762292SN/A 8772847Sksewell@umich.edu // Unbind Float Regs from Rename Map 87812106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs; 87912106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 88012105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id); 8812292SN/A scoreboard.unsetReg(phys_reg); 8822292SN/A freeList.addReg(phys_reg); 8832292SN/A } 8842292SN/A 8859920Syasuko.eckert@amd.com // Unbind condition-code Regs from Rename Map 88612106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs; 88712106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 88812105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id); 8899920Syasuko.eckert@amd.com scoreboard.unsetReg(phys_reg); 8909920Syasuko.eckert@amd.com freeList.addReg(phys_reg); 8919920Syasuko.eckert@amd.com } 8929920Syasuko.eckert@amd.com 8932847Sksewell@umich.edu // Squash Throughout Pipeline 8948138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 8958138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 8968138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 8972292SN/A decode.squash(tid); 8982935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 8992875Sksewell@umich.edu iew.squash(tid); 9005363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 9012935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 9022292SN/A 9035362Sksewell@umich.edu 9045362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 9052292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 9062292SN/A 9072847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 9083229Sktlim@umich.edu 9093229Sktlim@umich.edu // Commented out for now. This should be possible to do by 9103229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 9113229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 9123229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 9133229Sktlim@umich.edu/* 9142292SN/A if (activeThreads.size() >= 1) { 9152292SN/A commit.rob->resetEntries(); 9162292SN/A iew.resetEntries(); 9172292SN/A } 9183229Sktlim@umich.edu*/ 9192292SN/A} 9202292SN/A 9214192Sktlim@umich.edutemplate <class Impl> 9225595Sgblack@eecs.umich.eduFault 9236221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 9245702Ssaidi@eecs.umich.edu{ 9255702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9265702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 9275702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 9285702Ssaidi@eecs.umich.edu 9295702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 9305702Ssaidi@eecs.umich.edu 9315702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9325702Ssaidi@eecs.umich.edu#endif 9335702Ssaidi@eecs.umich.edu return NoFault; 9345702Ssaidi@eecs.umich.edu} 9355702Ssaidi@eecs.umich.edu 9365702Ssaidi@eecs.umich.edutemplate <class Impl> 9375702Ssaidi@eecs.umich.edubool 9386221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 9395702Ssaidi@eecs.umich.edu{ 9405702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9415702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 9425702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 9435702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 9445702Ssaidi@eecs.umich.edu 9455702Ssaidi@eecs.umich.edu switch (palFunc) { 9465702Ssaidi@eecs.umich.edu case PAL::halt: 9475702Ssaidi@eecs.umich.edu halt(); 9485702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 9495702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 9505702Ssaidi@eecs.umich.edu break; 9515702Ssaidi@eecs.umich.edu 9525702Ssaidi@eecs.umich.edu case PAL::bpt: 9535702Ssaidi@eecs.umich.edu case PAL::bugchk: 9545702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 9555702Ssaidi@eecs.umich.edu return false; 9565702Ssaidi@eecs.umich.edu break; 9575702Ssaidi@eecs.umich.edu } 9585702Ssaidi@eecs.umich.edu#endif 9595702Ssaidi@eecs.umich.edu return true; 9605702Ssaidi@eecs.umich.edu} 9615702Ssaidi@eecs.umich.edu 9625702Ssaidi@eecs.umich.edutemplate <class Impl> 9635702Ssaidi@eecs.umich.eduFault 9645595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 9655595Sgblack@eecs.umich.edu{ 9665595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 96711150Smitch.hayenga@arm.com return this->interrupts[0]->getInterrupt(this->threadContexts[0]); 9685595Sgblack@eecs.umich.edu} 9695595Sgblack@eecs.umich.edu 9705595Sgblack@eecs.umich.edutemplate <class Impl> 9715595Sgblack@eecs.umich.eduvoid 97210379Sandreas.hansson@arm.comFullO3CPU<Impl>::processInterrupts(const Fault &interrupt) 9735595Sgblack@eecs.umich.edu{ 9745595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 9755595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 9765595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9775595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9785595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9795595Sgblack@eecs.umich.edu 9805595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 98111150Smitch.hayenga@arm.com this->interrupts[0]->updateIntrInfo(this->threadContexts[0]); 9825595Sgblack@eecs.umich.edu 9835595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 98410417Sandreas.hansson@arm.com this->trap(interrupt, 0, nullptr); 9855595Sgblack@eecs.umich.edu} 9865595Sgblack@eecs.umich.edu 9871060SN/Atemplate <class Impl> 9882852Sktlim@umich.eduvoid 98910417Sandreas.hansson@arm.comFullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid, 99010417Sandreas.hansson@arm.com const StaticInstPtr &inst) 9915595Sgblack@eecs.umich.edu{ 9925595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 9937684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 9945595Sgblack@eecs.umich.edu} 9955595Sgblack@eecs.umich.edu 9965595Sgblack@eecs.umich.edutemplate <class Impl> 9975595Sgblack@eecs.umich.eduvoid 99811877Sbrandon.potter@amd.comFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault) 9995595Sgblack@eecs.umich.edu{ 10005595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 10015595Sgblack@eecs.umich.edu 10025595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 10035595Sgblack@eecs.umich.edu 10045595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 10055595Sgblack@eecs.umich.edu // instruction. 10065595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 10075595Sgblack@eecs.umich.edu 10085595Sgblack@eecs.umich.edu // Execute the actual syscall. 100911877Sbrandon.potter@amd.com this->thread[tid]->syscall(callnum, fault); 10105595Sgblack@eecs.umich.edu 10115595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 10125595Sgblack@eecs.umich.edu // incrementing it. 10135595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 10145595Sgblack@eecs.umich.edu} 10155595Sgblack@eecs.umich.edu 10165595Sgblack@eecs.umich.edutemplate <class Impl> 10175595Sgblack@eecs.umich.eduvoid 101810905Sandreas.sandberg@arm.comFullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const 10192864Sktlim@umich.edu{ 102010905Sandreas.sandberg@arm.com thread[tid]->serialize(cp); 10212864Sktlim@umich.edu} 10222864Sktlim@umich.edu 10232864Sktlim@umich.edutemplate <class Impl> 10242864Sktlim@umich.eduvoid 102510905Sandreas.sandberg@arm.comFullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid) 10262864Sktlim@umich.edu{ 102710905Sandreas.sandberg@arm.com thread[tid]->unserialize(cp); 10282864Sktlim@umich.edu} 10292864Sktlim@umich.edu 10302864Sktlim@umich.edutemplate <class Impl> 103110913Sandreas.sandberg@arm.comDrainState 103210913Sandreas.sandberg@arm.comFullO3CPU<Impl>::drain() 10331060SN/A{ 103412276Sanouk.vanlaer@arm.com // Deschedule any power gating event (if any) 103512276Sanouk.vanlaer@arm.com deschedulePowerGatingEvent(); 103612276Sanouk.vanlaer@arm.com 10379444SAndreas.Sandberg@ARM.com // If the CPU isn't doing anything, then return immediately. 103810913Sandreas.sandberg@arm.com if (switchedOut()) 103910913Sandreas.sandberg@arm.com return DrainState::Drained; 10403512Sktlim@umich.edu 10419444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Draining...\n"); 10423512Sktlim@umich.edu 10439444SAndreas.Sandberg@ARM.com // We only need to signal a drain to the commit stage as this 10449444SAndreas.Sandberg@ARM.com // initiates squashing controls the draining. Once the commit 10459444SAndreas.Sandberg@ARM.com // stage commits an instruction where it is safe to stop, it'll 10469444SAndreas.Sandberg@ARM.com // squash the rest of the instructions in the pipeline and force 10479444SAndreas.Sandberg@ARM.com // the fetch stage to stall. The pipeline will be drained once all 10489444SAndreas.Sandberg@ARM.com // in-flight instructions have retired. 10492843Sktlim@umich.edu commit.drain(); 10502325SN/A 10512325SN/A // Wake the CPU and record activity so everything can drain out if 10522863Sktlim@umich.edu // the CPU was not able to immediately drain. 10539444SAndreas.Sandberg@ARM.com if (!isDrained()) { 105412143Sanouk.vanlaer@arm.com // If a thread is suspended, wake it up so it can be drained 105512143Sanouk.vanlaer@arm.com for (auto t : threadContexts) { 105612143Sanouk.vanlaer@arm.com if (t->status() == ThreadContext::Suspended){ 105712143Sanouk.vanlaer@arm.com DPRINTF(Drain, "Currently suspended so activate %i \n", 105812143Sanouk.vanlaer@arm.com t->threadId()); 105912143Sanouk.vanlaer@arm.com t->activate(); 106012143Sanouk.vanlaer@arm.com // As the thread is now active, change the power state as well 106112143Sanouk.vanlaer@arm.com activateContext(t->threadId()); 106212143Sanouk.vanlaer@arm.com } 106312143Sanouk.vanlaer@arm.com } 106412143Sanouk.vanlaer@arm.com 10652863Sktlim@umich.edu wakeCPU(); 10662863Sktlim@umich.edu activityRec.activity(); 10672852Sktlim@umich.edu 10689152Satgutier@umich.edu DPRINTF(Drain, "CPU not drained\n"); 10699152Satgutier@umich.edu 107010913Sandreas.sandberg@arm.com return DrainState::Draining; 10712863Sktlim@umich.edu } else { 10729444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU is already drained\n"); 10739444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 10749444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 10759444SAndreas.Sandberg@ARM.com 10769444SAndreas.Sandberg@ARM.com // Flush out any old data from the time buffers. In 10779444SAndreas.Sandberg@ARM.com // particular, there might be some data in flight from the 10789444SAndreas.Sandberg@ARM.com // fetch stage that isn't visible in any of the CPU buffers we 10799444SAndreas.Sandberg@ARM.com // test in isDrained(). 10809444SAndreas.Sandberg@ARM.com for (int i = 0; i < timeBuffer.getSize(); ++i) { 10819444SAndreas.Sandberg@ARM.com timeBuffer.advance(); 10829444SAndreas.Sandberg@ARM.com fetchQueue.advance(); 10839444SAndreas.Sandberg@ARM.com decodeQueue.advance(); 10849444SAndreas.Sandberg@ARM.com renameQueue.advance(); 10859444SAndreas.Sandberg@ARM.com iewQueue.advance(); 10869444SAndreas.Sandberg@ARM.com } 10879444SAndreas.Sandberg@ARM.com 10889444SAndreas.Sandberg@ARM.com drainSanityCheck(); 108910913Sandreas.sandberg@arm.com return DrainState::Drained; 10902863Sktlim@umich.edu } 10912316SN/A} 10922310SN/A 10932316SN/Atemplate <class Impl> 10949444SAndreas.Sandberg@ARM.combool 10959444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::tryDrain() 10969444SAndreas.Sandberg@ARM.com{ 109710913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining || !isDrained()) 10989444SAndreas.Sandberg@ARM.com return false; 10999444SAndreas.Sandberg@ARM.com 11009444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 11019444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 11029444SAndreas.Sandberg@ARM.com 11039444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 110410913Sandreas.sandberg@arm.com signalDrainDone(); 11059444SAndreas.Sandberg@ARM.com 11069444SAndreas.Sandberg@ARM.com return true; 11079444SAndreas.Sandberg@ARM.com} 11089444SAndreas.Sandberg@ARM.com 11099444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11109444SAndreas.Sandberg@ARM.comvoid 11119444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::drainSanityCheck() const 11129444SAndreas.Sandberg@ARM.com{ 11139444SAndreas.Sandberg@ARM.com assert(isDrained()); 11149444SAndreas.Sandberg@ARM.com fetch.drainSanityCheck(); 11159444SAndreas.Sandberg@ARM.com decode.drainSanityCheck(); 11169444SAndreas.Sandberg@ARM.com rename.drainSanityCheck(); 11179444SAndreas.Sandberg@ARM.com iew.drainSanityCheck(); 11189444SAndreas.Sandberg@ARM.com commit.drainSanityCheck(); 11199444SAndreas.Sandberg@ARM.com} 11209444SAndreas.Sandberg@ARM.com 11219444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11229444SAndreas.Sandberg@ARM.combool 11239444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::isDrained() const 11249444SAndreas.Sandberg@ARM.com{ 11259444SAndreas.Sandberg@ARM.com bool drained(true); 11269444SAndreas.Sandberg@ARM.com 11279444SAndreas.Sandberg@ARM.com if (!instList.empty() || !removeList.empty()) { 11289444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Main CPU structures not drained.\n"); 11299444SAndreas.Sandberg@ARM.com drained = false; 11309444SAndreas.Sandberg@ARM.com } 11319444SAndreas.Sandberg@ARM.com 11329444SAndreas.Sandberg@ARM.com if (!fetch.isDrained()) { 11339444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Fetch not drained.\n"); 11349444SAndreas.Sandberg@ARM.com drained = false; 11359444SAndreas.Sandberg@ARM.com } 11369444SAndreas.Sandberg@ARM.com 11379444SAndreas.Sandberg@ARM.com if (!decode.isDrained()) { 11389444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Decode not drained.\n"); 11399444SAndreas.Sandberg@ARM.com drained = false; 11409444SAndreas.Sandberg@ARM.com } 11419444SAndreas.Sandberg@ARM.com 11429444SAndreas.Sandberg@ARM.com if (!rename.isDrained()) { 11439444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Rename not drained.\n"); 11449444SAndreas.Sandberg@ARM.com drained = false; 11459444SAndreas.Sandberg@ARM.com } 11469444SAndreas.Sandberg@ARM.com 11479444SAndreas.Sandberg@ARM.com if (!iew.isDrained()) { 11489444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "IEW not drained.\n"); 11499444SAndreas.Sandberg@ARM.com drained = false; 11509444SAndreas.Sandberg@ARM.com } 11519444SAndreas.Sandberg@ARM.com 11529444SAndreas.Sandberg@ARM.com if (!commit.isDrained()) { 11539444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Commit not drained.\n"); 11549444SAndreas.Sandberg@ARM.com drained = false; 11559444SAndreas.Sandberg@ARM.com } 11569444SAndreas.Sandberg@ARM.com 11579444SAndreas.Sandberg@ARM.com return drained; 11589444SAndreas.Sandberg@ARM.com} 11599444SAndreas.Sandberg@ARM.com 11609444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11619444SAndreas.Sandberg@ARM.comvoid 11629444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::commitDrained(ThreadID tid) 11639444SAndreas.Sandberg@ARM.com{ 11649444SAndreas.Sandberg@ARM.com fetch.drainStall(tid); 11659444SAndreas.Sandberg@ARM.com} 11669444SAndreas.Sandberg@ARM.com 11679444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11682316SN/Avoid 11699342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drainResume() 11702316SN/A{ 11719444SAndreas.Sandberg@ARM.com if (switchedOut()) 11729444SAndreas.Sandberg@ARM.com return; 11732316SN/A 11749444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Resuming...\n"); 11759523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 11763319Shsul@eecs.umich.edu 11779444SAndreas.Sandberg@ARM.com fetch.drainResume(); 11789444SAndreas.Sandberg@ARM.com commit.drainResume(); 11792316SN/A 11809444SAndreas.Sandberg@ARM.com _status = Idle; 11819444SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); i++) { 11829444SAndreas.Sandberg@ARM.com if (thread[i]->status() == ThreadContext::Active) { 11839444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Activating thread: %i\n", i); 11849444SAndreas.Sandberg@ARM.com activateThread(i); 11859444SAndreas.Sandberg@ARM.com _status = Running; 11862863Sktlim@umich.edu } 11872310SN/A } 11889444SAndreas.Sandberg@ARM.com 11899444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 11909444SAndreas.Sandberg@ARM.com if (_status == Running) 11919444SAndreas.Sandberg@ARM.com schedule(tickEvent, nextCycle()); 119212276Sanouk.vanlaer@arm.com 119312276Sanouk.vanlaer@arm.com // Reschedule any power gating event (if any) 119412276Sanouk.vanlaer@arm.com schedulePowerGatingEvent(); 11952843Sktlim@umich.edu} 11962843Sktlim@umich.edu 11972843Sktlim@umich.edutemplate <class Impl> 11982843Sktlim@umich.eduvoid 11992843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 12002843Sktlim@umich.edu{ 12019444SAndreas.Sandberg@ARM.com DPRINTF(O3CPU, "Switching out\n"); 12029429SAndreas.Sandberg@ARM.com BaseCPU::switchOut(); 12039429SAndreas.Sandberg@ARM.com 12049444SAndreas.Sandberg@ARM.com activityRec.reset(); 12052843Sktlim@umich.edu 12062843Sktlim@umich.edu _status = SwitchedOut; 12078887Sgeoffrey.blake@arm.com 12082843Sktlim@umich.edu if (checker) 12092843Sktlim@umich.edu checker->switchOut(); 12101060SN/A} 12111060SN/A 12121060SN/Atemplate <class Impl> 12131060SN/Avoid 12141755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 12151060SN/A{ 12168737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 12171060SN/A 12182307SN/A fetch.takeOverFrom(); 12192307SN/A decode.takeOverFrom(); 12202307SN/A rename.takeOverFrom(); 12212307SN/A iew.takeOverFrom(); 12222307SN/A commit.takeOverFrom(); 12232307SN/A 12249444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 12251060SN/A 12269152Satgutier@umich.edu FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 12279152Satgutier@umich.edu if (oldO3CPU) 12289152Satgutier@umich.edu globalSeqNum = oldO3CPU->globalSeqNum; 12299152Satgutier@umich.edu 12309179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 12319444SAndreas.Sandberg@ARM.com _status = Idle; 12321060SN/A} 12331060SN/A 12341060SN/Atemplate <class Impl> 12359523SAndreas.Sandberg@ARM.comvoid 12369523SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::verifyMemoryMode() const 12379523SAndreas.Sandberg@ARM.com{ 12389524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 12399523SAndreas.Sandberg@ARM.com fatal("The O3 CPU requires the memory system to be in " 12409523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 12419523SAndreas.Sandberg@ARM.com } 12429523SAndreas.Sandberg@ARM.com} 12439523SAndreas.Sandberg@ARM.com 12449523SAndreas.Sandberg@ARM.comtemplate <class Impl> 12455595Sgblack@eecs.umich.eduTheISA::MiscReg 124610698Sandreas.hansson@arm.comFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const 12475595Sgblack@eecs.umich.edu{ 12489384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscRegNoEffect(misc_reg); 12495595Sgblack@eecs.umich.edu} 12505595Sgblack@eecs.umich.edu 12515595Sgblack@eecs.umich.edutemplate <class Impl> 12525595Sgblack@eecs.umich.eduTheISA::MiscReg 12536221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 12545595Sgblack@eecs.umich.edu{ 12557897Shestness@cs.utexas.edu miscRegfileReads++; 12569384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 12575595Sgblack@eecs.umich.edu} 12585595Sgblack@eecs.umich.edu 12595595Sgblack@eecs.umich.edutemplate <class Impl> 12605595Sgblack@eecs.umich.eduvoid 12615595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 12626221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12635595Sgblack@eecs.umich.edu{ 12649384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 12655595Sgblack@eecs.umich.edu} 12665595Sgblack@eecs.umich.edu 12675595Sgblack@eecs.umich.edutemplate <class Impl> 12685595Sgblack@eecs.umich.eduvoid 12695595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 12706221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12715595Sgblack@eecs.umich.edu{ 12727897Shestness@cs.utexas.edu miscRegfileWrites++; 12739384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 12745595Sgblack@eecs.umich.edu} 12755595Sgblack@eecs.umich.edu 12765595Sgblack@eecs.umich.edutemplate <class Impl> 12771060SN/Auint64_t 127812105Snathanael.premillieu@arm.comFullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg) 12791060SN/A{ 12807897Shestness@cs.utexas.edu intRegfileReads++; 128112105Snathanael.premillieu@arm.com return regFile.readIntReg(phys_reg); 12821060SN/A} 12831060SN/A 12841060SN/Atemplate <class Impl> 12852455SN/AFloatReg 128612105Snathanael.premillieu@arm.comFullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg) 12871060SN/A{ 12887897Shestness@cs.utexas.edu fpRegfileReads++; 128912105Snathanael.premillieu@arm.com return regFile.readFloatReg(phys_reg); 12901060SN/A} 12911060SN/A 12921060SN/Atemplate <class Impl> 12932455SN/AFloatRegBits 129412105Snathanael.premillieu@arm.comFullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg) 12952455SN/A{ 12967897Shestness@cs.utexas.edu fpRegfileReads++; 129712105Snathanael.premillieu@arm.com return regFile.readFloatRegBits(phys_reg); 12981060SN/A} 12991060SN/A 13001060SN/Atemplate <class Impl> 130112109SRekai.GonzalezAlberquilla@arm.comauto 130212109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readVecReg(PhysRegIdPtr phys_reg) const 130312109SRekai.GonzalezAlberquilla@arm.com -> const VecRegContainer& 130412109SRekai.GonzalezAlberquilla@arm.com{ 130512109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads++; 130612109SRekai.GonzalezAlberquilla@arm.com return regFile.readVecReg(phys_reg); 130712109SRekai.GonzalezAlberquilla@arm.com} 130812109SRekai.GonzalezAlberquilla@arm.com 130912109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 131012109SRekai.GonzalezAlberquilla@arm.comauto 131112109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::getWritableVecReg(PhysRegIdPtr phys_reg) 131212109SRekai.GonzalezAlberquilla@arm.com -> VecRegContainer& 131312109SRekai.GonzalezAlberquilla@arm.com{ 131412109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 131512109SRekai.GonzalezAlberquilla@arm.com return regFile.getWritableVecReg(phys_reg); 131612109SRekai.GonzalezAlberquilla@arm.com} 131712109SRekai.GonzalezAlberquilla@arm.com 131812109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 131912109SRekai.GonzalezAlberquilla@arm.comauto 132012109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem& 132112109SRekai.GonzalezAlberquilla@arm.com{ 132212109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads++; 132312109SRekai.GonzalezAlberquilla@arm.com return regFile.readVecElem(phys_reg); 132412109SRekai.GonzalezAlberquilla@arm.com} 132512109SRekai.GonzalezAlberquilla@arm.com 132612109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 13279920Syasuko.eckert@amd.comCCReg 132812105Snathanael.premillieu@arm.comFullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg) 13299920Syasuko.eckert@amd.com{ 13309920Syasuko.eckert@amd.com ccRegfileReads++; 133112105Snathanael.premillieu@arm.com return regFile.readCCReg(phys_reg); 13329920Syasuko.eckert@amd.com} 13339920Syasuko.eckert@amd.com 13349920Syasuko.eckert@amd.comtemplate <class Impl> 13351060SN/Avoid 133612105Snathanael.premillieu@arm.comFullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val) 13371060SN/A{ 13387897Shestness@cs.utexas.edu intRegfileWrites++; 133912105Snathanael.premillieu@arm.com regFile.setIntReg(phys_reg, val); 13401060SN/A} 13411060SN/A 13421060SN/Atemplate <class Impl> 13431060SN/Avoid 134412105Snathanael.premillieu@arm.comFullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, FloatReg val) 13451060SN/A{ 13467897Shestness@cs.utexas.edu fpRegfileWrites++; 134712105Snathanael.premillieu@arm.com regFile.setFloatReg(phys_reg, val); 13481060SN/A} 13491060SN/A 13501060SN/Atemplate <class Impl> 13511060SN/Avoid 135212105Snathanael.premillieu@arm.comFullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val) 13532455SN/A{ 13547897Shestness@cs.utexas.edu fpRegfileWrites++; 135512105Snathanael.premillieu@arm.com regFile.setFloatRegBits(phys_reg, val); 13561060SN/A} 13571060SN/A 13581060SN/Atemplate <class Impl> 13599920Syasuko.eckert@amd.comvoid 136012109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) 136112109SRekai.GonzalezAlberquilla@arm.com{ 136212109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 136312109SRekai.GonzalezAlberquilla@arm.com regFile.setVecReg(phys_reg, val); 136412109SRekai.GonzalezAlberquilla@arm.com} 136512109SRekai.GonzalezAlberquilla@arm.com 136612109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 136712109SRekai.GonzalezAlberquilla@arm.comvoid 136812109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val) 136912109SRekai.GonzalezAlberquilla@arm.com{ 137012109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 137112109SRekai.GonzalezAlberquilla@arm.com regFile.setVecElem(phys_reg, val); 137212109SRekai.GonzalezAlberquilla@arm.com} 137312109SRekai.GonzalezAlberquilla@arm.com 137412109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 137512109SRekai.GonzalezAlberquilla@arm.comvoid 137612105Snathanael.premillieu@arm.comFullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val) 13779920Syasuko.eckert@amd.com{ 13789920Syasuko.eckert@amd.com ccRegfileWrites++; 137912105Snathanael.premillieu@arm.com regFile.setCCReg(phys_reg, val); 13809920Syasuko.eckert@amd.com} 13819920Syasuko.eckert@amd.com 13829920Syasuko.eckert@amd.comtemplate <class Impl> 13831060SN/Auint64_t 13846221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 13851060SN/A{ 13867897Shestness@cs.utexas.edu intRegfileReads++; 138712106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 138812106SRekai.GonzalezAlberquilla@arm.com RegId(IntRegClass, reg_idx)); 13892292SN/A 13902292SN/A return regFile.readIntReg(phys_reg); 13912292SN/A} 13922292SN/A 13932292SN/Atemplate <class Impl> 13942292SN/Afloat 13956314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 13962292SN/A{ 13977897Shestness@cs.utexas.edu fpRegfileReads++; 139812106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 139912106SRekai.GonzalezAlberquilla@arm.com RegId(FloatRegClass, reg_idx)); 14002292SN/A 14012669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 14022292SN/A} 14032292SN/A 14042292SN/Atemplate <class Impl> 14052292SN/Auint64_t 14066221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 14072292SN/A{ 14087897Shestness@cs.utexas.edu fpRegfileReads++; 140912106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 141012106SRekai.GonzalezAlberquilla@arm.com RegId(FloatRegClass, reg_idx)); 14112292SN/A 14122669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 14131060SN/A} 14141060SN/A 14151060SN/Atemplate <class Impl> 141612109SRekai.GonzalezAlberquilla@arm.comauto 141712109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const 141812109SRekai.GonzalezAlberquilla@arm.com -> const VecRegContainer& 141912109SRekai.GonzalezAlberquilla@arm.com{ 142012109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 142112109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 142212109SRekai.GonzalezAlberquilla@arm.com return readVecReg(phys_reg); 142312109SRekai.GonzalezAlberquilla@arm.com} 142412109SRekai.GonzalezAlberquilla@arm.com 142512109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 142612109SRekai.GonzalezAlberquilla@arm.comauto 142712109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid) 142812109SRekai.GonzalezAlberquilla@arm.com -> VecRegContainer& 142912109SRekai.GonzalezAlberquilla@arm.com{ 143012109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 143112109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 143212109SRekai.GonzalezAlberquilla@arm.com return getWritableVecReg(phys_reg); 143312109SRekai.GonzalezAlberquilla@arm.com} 143412109SRekai.GonzalezAlberquilla@arm.com 143512109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 143612109SRekai.GonzalezAlberquilla@arm.comauto 143712109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 143812109SRekai.GonzalezAlberquilla@arm.com ThreadID tid) const -> const VecElem& 143912109SRekai.GonzalezAlberquilla@arm.com{ 144012109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 144112109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx, ldx)); 144212109SRekai.GonzalezAlberquilla@arm.com return readVecElem(phys_reg); 144312109SRekai.GonzalezAlberquilla@arm.com} 144412109SRekai.GonzalezAlberquilla@arm.com 144512109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 14469920Syasuko.eckert@amd.comCCReg 14479920Syasuko.eckert@amd.comFullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid) 14489920Syasuko.eckert@amd.com{ 14499920Syasuko.eckert@amd.com ccRegfileReads++; 145012106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 145112106SRekai.GonzalezAlberquilla@arm.com RegId(CCRegClass, reg_idx)); 14529920Syasuko.eckert@amd.com 14539920Syasuko.eckert@amd.com return regFile.readCCReg(phys_reg); 14549920Syasuko.eckert@amd.com} 14559920Syasuko.eckert@amd.com 14569920Syasuko.eckert@amd.comtemplate <class Impl> 14571060SN/Avoid 14586221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 14591060SN/A{ 14607897Shestness@cs.utexas.edu intRegfileWrites++; 146112106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 146212106SRekai.GonzalezAlberquilla@arm.com RegId(IntRegClass, reg_idx)); 14632292SN/A 14642292SN/A regFile.setIntReg(phys_reg, val); 14651060SN/A} 14661060SN/A 14671060SN/Atemplate <class Impl> 14681060SN/Avoid 14696314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 14701060SN/A{ 14717897Shestness@cs.utexas.edu fpRegfileWrites++; 147212106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 147312106SRekai.GonzalezAlberquilla@arm.com RegId(FloatRegClass, reg_idx)); 14742292SN/A 14752669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 14761060SN/A} 14771060SN/A 14781060SN/Atemplate <class Impl> 14791060SN/Avoid 14806221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 14811060SN/A{ 14827897Shestness@cs.utexas.edu fpRegfileWrites++; 148312106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 148412106SRekai.GonzalezAlberquilla@arm.com RegId(FloatRegClass, reg_idx)); 14851060SN/A 14862669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 14872292SN/A} 14882292SN/A 14892292SN/Atemplate <class Impl> 14909920Syasuko.eckert@amd.comvoid 149112109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setArchVecReg(int reg_idx, const VecRegContainer& val, 149212109SRekai.GonzalezAlberquilla@arm.com ThreadID tid) 149312109SRekai.GonzalezAlberquilla@arm.com{ 149412109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 149512109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 149612109SRekai.GonzalezAlberquilla@arm.com setVecReg(phys_reg, val); 149712109SRekai.GonzalezAlberquilla@arm.com} 149812109SRekai.GonzalezAlberquilla@arm.com 149912109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 150012109SRekai.GonzalezAlberquilla@arm.comvoid 150112109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 150212109SRekai.GonzalezAlberquilla@arm.com const VecElem& val, ThreadID tid) 150312109SRekai.GonzalezAlberquilla@arm.com{ 150412109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 150512109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx, ldx)); 150612109SRekai.GonzalezAlberquilla@arm.com setVecElem(phys_reg, val); 150712109SRekai.GonzalezAlberquilla@arm.com} 150812109SRekai.GonzalezAlberquilla@arm.com 150912109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 151012109SRekai.GonzalezAlberquilla@arm.comvoid 15119920Syasuko.eckert@amd.comFullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid) 15129920Syasuko.eckert@amd.com{ 15139920Syasuko.eckert@amd.com ccRegfileWrites++; 151412106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 151512106SRekai.GonzalezAlberquilla@arm.com RegId(CCRegClass, reg_idx)); 15169920Syasuko.eckert@amd.com 15179920Syasuko.eckert@amd.com regFile.setCCReg(phys_reg, val); 15189920Syasuko.eckert@amd.com} 15199920Syasuko.eckert@amd.com 15209920Syasuko.eckert@amd.comtemplate <class Impl> 15217720Sgblack@eecs.umich.eduTheISA::PCState 15227720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 15232292SN/A{ 15247720Sgblack@eecs.umich.edu return commit.pcState(tid); 15251060SN/A} 15261060SN/A 15271060SN/Atemplate <class Impl> 15281060SN/Avoid 15297720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 15301060SN/A{ 15317720Sgblack@eecs.umich.edu commit.pcState(val, tid); 15322292SN/A} 15331060SN/A 15342292SN/Atemplate <class Impl> 15357720Sgblack@eecs.umich.eduAddr 15367720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 15374636Sgblack@eecs.umich.edu{ 15387720Sgblack@eecs.umich.edu return commit.instAddr(tid); 15394636Sgblack@eecs.umich.edu} 15404636Sgblack@eecs.umich.edu 15414636Sgblack@eecs.umich.edutemplate <class Impl> 15427720Sgblack@eecs.umich.eduAddr 15437720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 15444636Sgblack@eecs.umich.edu{ 15457720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 15464636Sgblack@eecs.umich.edu} 15474636Sgblack@eecs.umich.edu 15484636Sgblack@eecs.umich.edutemplate <class Impl> 15497720Sgblack@eecs.umich.eduMicroPC 15507720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 15512292SN/A{ 15527720Sgblack@eecs.umich.edu return commit.microPC(tid); 15534636Sgblack@eecs.umich.edu} 15544636Sgblack@eecs.umich.edu 15554636Sgblack@eecs.umich.edutemplate <class Impl> 15565595Sgblack@eecs.umich.eduvoid 15576221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 15585595Sgblack@eecs.umich.edu{ 15599382SAli.Saidi@ARM.com this->thread[tid]->noSquashFromTC = true; 15605595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 15615595Sgblack@eecs.umich.edu} 15625595Sgblack@eecs.umich.edu 15635595Sgblack@eecs.umich.edutemplate <class Impl> 15642292SN/Atypename FullO3CPU<Impl>::ListIt 15652292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 15662292SN/A{ 15672292SN/A instList.push_back(inst); 15681060SN/A 15692292SN/A return --(instList.end()); 15702292SN/A} 15711060SN/A 15722292SN/Atemplate <class Impl> 15732292SN/Avoid 15748834Satgutier@umich.eduFullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 15752292SN/A{ 15762292SN/A // Keep an instruction count. 15778834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 15788834Satgutier@umich.edu thread[tid]->numInst++; 15798834Satgutier@umich.edu thread[tid]->numInsts++; 15808834Satgutier@umich.edu committedInsts[tid]++; 158110774Snikos.nikoleris@gmail.com system->totalNumInsts++; 158210774Snikos.nikoleris@gmail.com 158310774Snikos.nikoleris@gmail.com // Check for instruction-count-based events. 158410774Snikos.nikoleris@gmail.com comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 158510774Snikos.nikoleris@gmail.com system->instEventQueue.serviceEvents(system->totalNumInsts); 15868834Satgutier@umich.edu } 15878834Satgutier@umich.edu thread[tid]->numOp++; 15888834Satgutier@umich.edu thread[tid]->numOps++; 15898834Satgutier@umich.edu committedOps[tid]++; 15908834Satgutier@umich.edu 159110464SAndreas.Sandberg@ARM.com probeInstCommit(inst->staticInst); 15922292SN/A} 15932292SN/A 15942292SN/Atemplate <class Impl> 15952292SN/Avoid 15961755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 15971060SN/A{ 15987720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 15992292SN/A "[sn:%lli]\n", 16007720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 16011060SN/A 16022292SN/A removeInstsThisCycle = true; 16031060SN/A 16041060SN/A // Remove the front instruction. 16052292SN/A removeList.push(inst->getInstListIt()); 16061060SN/A} 16071060SN/A 16081060SN/Atemplate <class Impl> 16091060SN/Avoid 16106221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 16111060SN/A{ 16122733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 16132292SN/A " list.\n", tid); 16141060SN/A 16152292SN/A ListIt end_it; 16161060SN/A 16172292SN/A bool rob_empty = false; 16182292SN/A 16192292SN/A if (instList.empty()) { 16202292SN/A return; 162110164Ssleimanf@umich.edu } else if (rob.isEmpty(tid)) { 16222733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 16232292SN/A end_it = instList.begin(); 16242292SN/A rob_empty = true; 16252292SN/A } else { 16262292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 16272733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 16282292SN/A } 16292292SN/A 16302292SN/A removeInstsThisCycle = true; 16312292SN/A 16322292SN/A ListIt inst_it = instList.end(); 16332292SN/A 16342292SN/A inst_it--; 16352292SN/A 16362292SN/A // Walk through the instruction list, removing any instructions 16372292SN/A // that were inserted after the given instruction iterator, end_it. 16382292SN/A while (inst_it != end_it) { 16392292SN/A assert(!instList.empty()); 16402292SN/A 16412292SN/A squashInstIt(inst_it, tid); 16422292SN/A 16432292SN/A inst_it--; 16442292SN/A } 16452292SN/A 16462292SN/A // If the ROB was empty, then we actually need to remove the first 16472292SN/A // instruction as well. 16482292SN/A if (rob_empty) { 16492292SN/A squashInstIt(inst_it, tid); 16502292SN/A } 16511060SN/A} 16521060SN/A 16531060SN/Atemplate <class Impl> 16541060SN/Avoid 16556221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 16561062SN/A{ 16572292SN/A assert(!instList.empty()); 16582292SN/A 16592292SN/A removeInstsThisCycle = true; 16602292SN/A 16612292SN/A ListIt inst_iter = instList.end(); 16622292SN/A 16632292SN/A inst_iter--; 16642292SN/A 16652733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 16662292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 16672292SN/A tid, seq_num, (*inst_iter)->seqNum); 16681062SN/A 16692292SN/A while ((*inst_iter)->seqNum > seq_num) { 16701062SN/A 16712292SN/A bool break_loop = (inst_iter == instList.begin()); 16721062SN/A 16732292SN/A squashInstIt(inst_iter, tid); 16741062SN/A 16752292SN/A inst_iter--; 16761062SN/A 16772292SN/A if (break_loop) 16782292SN/A break; 16792292SN/A } 16802292SN/A} 16812292SN/A 16822292SN/Atemplate <class Impl> 16832292SN/Ainline void 16846221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 16852292SN/A{ 16862292SN/A if ((*instIt)->threadNumber == tid) { 16872733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 16887720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 16892292SN/A (*instIt)->threadNumber, 16902292SN/A (*instIt)->seqNum, 16917720Sgblack@eecs.umich.edu (*instIt)->pcState()); 16921062SN/A 16931062SN/A // Mark it as squashed. 16942292SN/A (*instIt)->setSquashed(); 16952292SN/A 16962325SN/A // @todo: Formulate a consistent method for deleting 16972325SN/A // instructions from the instruction list 16982292SN/A // Remove the instruction from the list. 16992292SN/A removeList.push(instIt); 17002292SN/A } 17012292SN/A} 17022292SN/A 17032292SN/Atemplate <class Impl> 17042292SN/Avoid 17052292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 17062292SN/A{ 17072292SN/A while (!removeList.empty()) { 17082733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 17097720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 17102292SN/A (*removeList.front())->threadNumber, 17112292SN/A (*removeList.front())->seqNum, 17127720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 17132292SN/A 17142292SN/A instList.erase(removeList.front()); 17152292SN/A 17162292SN/A removeList.pop(); 17171062SN/A } 17181062SN/A 17192292SN/A removeInstsThisCycle = false; 17201062SN/A} 17212325SN/A/* 17221062SN/Atemplate <class Impl> 17231062SN/Avoid 17241755SN/AFullO3CPU<Impl>::removeAllInsts() 17251060SN/A{ 17261060SN/A instList.clear(); 17271060SN/A} 17282325SN/A*/ 17291060SN/Atemplate <class Impl> 17301060SN/Avoid 17311755SN/AFullO3CPU<Impl>::dumpInsts() 17321060SN/A{ 17331060SN/A int num = 0; 17341060SN/A 17352292SN/A ListIt inst_list_it = instList.begin(); 17362292SN/A 17372292SN/A cprintf("Dumping Instruction List\n"); 17382292SN/A 17392292SN/A while (inst_list_it != instList.end()) { 17402292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 17412292SN/A "Squashed:%i\n\n", 17427720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 17432292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 17442292SN/A (*inst_list_it)->isSquashed()); 17451060SN/A inst_list_it++; 17461060SN/A ++num; 17471060SN/A } 17481060SN/A} 17492325SN/A/* 17501060SN/Atemplate <class Impl> 17511060SN/Avoid 17521755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 17531060SN/A{ 17541060SN/A iew.wakeDependents(inst); 17551060SN/A} 17562325SN/A*/ 17572292SN/Atemplate <class Impl> 17582292SN/Avoid 17592292SN/AFullO3CPU<Impl>::wakeCPU() 17602292SN/A{ 17612325SN/A if (activityRec.active() || tickEvent.scheduled()) { 17622325SN/A DPRINTF(Activity, "CPU already running.\n"); 17632292SN/A return; 17642292SN/A } 17652292SN/A 17662325SN/A DPRINTF(Activity, "Waking up CPU\n"); 17672325SN/A 17689180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 17699180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 177010464SAndreas.Sandberg@ARM.com if (cycles > 1) { 17719179Sandreas.hansson@arm.com --cycles; 177210464SAndreas.Sandberg@ARM.com idleCycles += cycles; 177310464SAndreas.Sandberg@ARM.com numCycles += cycles; 177410464SAndreas.Sandberg@ARM.com ppCycles->notify(cycles); 177510464SAndreas.Sandberg@ARM.com } 17762292SN/A 17779648Sdam.sunwoo@arm.com schedule(tickEvent, clockEdge()); 17782292SN/A} 17792292SN/A 17805807Snate@binkert.orgtemplate <class Impl> 17815807Snate@binkert.orgvoid 178211151Smitch.hayenga@arm.comFullO3CPU<Impl>::wakeup(ThreadID tid) 17835807Snate@binkert.org{ 178411151Smitch.hayenga@arm.com if (this->thread[tid]->status() != ThreadContext::Suspended) 17855807Snate@binkert.org return; 17865807Snate@binkert.org 17875807Snate@binkert.org this->wakeCPU(); 17885807Snate@binkert.org 17895807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 179011151Smitch.hayenga@arm.com this->threadContexts[tid]->activate(); 17915807Snate@binkert.org} 17925807Snate@binkert.org 17932292SN/Atemplate <class Impl> 17946221Snate@binkert.orgThreadID 17952292SN/AFullO3CPU<Impl>::getFreeTid() 17962292SN/A{ 17976221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 17986221Snate@binkert.org if (!tids[tid]) { 17996221Snate@binkert.org tids[tid] = true; 18006221Snate@binkert.org return tid; 18012292SN/A } 18022292SN/A } 18032292SN/A 18046221Snate@binkert.org return InvalidThreadID; 18052292SN/A} 18062292SN/A 18072292SN/Atemplate <class Impl> 18082292SN/Avoid 18092292SN/AFullO3CPU<Impl>::updateThreadPriority() 18102292SN/A{ 18116221Snate@binkert.org if (activeThreads.size() > 1) { 18122292SN/A //DEFAULT TO ROUND ROBIN SCHEME 18132292SN/A //e.g. Move highest priority to end of thread list 18146221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 18152292SN/A 18162292SN/A unsigned high_thread = *list_begin; 18172292SN/A 18182292SN/A activeThreads.erase(list_begin); 18192292SN/A 18202292SN/A activeThreads.push_back(high_thread); 18212292SN/A } 18222292SN/A} 18231060SN/A 18241755SN/A// Forward declaration of FullO3CPU. 18252818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1826