cpu.cc revision 12104
11689SN/A/* 210331Smitch.hayenga@arm.com * Copyright (c) 2011-2012, 2014 ARM Limited 39916Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 152325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 167897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432756Sksewell@umich.edu * Korey Sewell 447897Shestness@cs.utexas.edu * Rick Strong 451689SN/A */ 461689SN/A 4711793Sbrandon.potter@amd.com#include "cpu/o3/cpu.hh" 4811793Sbrandon.potter@amd.com 498779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 5111793Sbrandon.potter@amd.com#include "cpu/activity.hh" 528887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 538887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 548229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 558229Snate@binkert.org#include "cpu/o3/thread_context.hh" 568779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 574762Snate@binkert.org#include "cpu/simple_thread.hh" 584762Snate@binkert.org#include "cpu/thread_context.hh" 598232Snate@binkert.org#include "debug/Activity.hh" 609152Satgutier@umich.edu#include "debug/Drain.hh" 618232Snate@binkert.org#include "debug/O3CPU.hh" 628232Snate@binkert.org#include "debug/Quiesce.hh" 634762Snate@binkert.org#include "enums/MemoryMode.hh" 644762Snate@binkert.org#include "sim/core.hh" 658793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 668779Sgblack@eecs.umich.edu#include "sim/process.hh" 674762Snate@binkert.org#include "sim/stat_control.hh" 688460SAli.Saidi@ARM.com#include "sim/system.hh" 694762Snate@binkert.org 705702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 715702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 728232Snate@binkert.org#include "debug/Activity.hh" 7311793Sbrandon.potter@amd.com 745702Ssaidi@eecs.umich.edu#endif 755702Ssaidi@eecs.umich.edu 768737Skoansin.tan@gmail.comstruct BaseCPUParams; 775529Snate@binkert.org 782669Sktlim@umich.eduusing namespace TheISA; 796221Snate@binkert.orgusing namespace std; 801060SN/A 815529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 825712Shsul@eecs.umich.edu : BaseCPU(params) 831060SN/A{ 841060SN/A} 851060SN/A 862292SN/Avoid 872733Sktlim@umich.eduBaseO3CPU::regStats() 882292SN/A{ 892292SN/A BaseCPU::regStats(); 902292SN/A} 912292SN/A 928707Sandreas.hansson@arm.comtemplate<class Impl> 938707Sandreas.hansson@arm.combool 948975Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 958707Sandreas.hansson@arm.com{ 968707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 9711284Sandreas.hansson@arm.com // We shouldn't ever get a cacheable block in Modified state 9810821Sandreas.hansson@arm.com assert(pkt->req->isUncacheable() || 9911284Sandreas.hansson@arm.com !(pkt->cacheResponding() && !pkt->hasSharers())); 1008948Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 1018707Sandreas.hansson@arm.com 1028707Sandreas.hansson@arm.com return true; 1038707Sandreas.hansson@arm.com} 1048707Sandreas.hansson@arm.com 1058707Sandreas.hansson@arm.comtemplate<class Impl> 1068707Sandreas.hansson@arm.comvoid 10710713Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvReqRetry() 1088707Sandreas.hansson@arm.com{ 10910713Sandreas.hansson@arm.com fetch->recvReqRetry(); 1108707Sandreas.hansson@arm.com} 1118707Sandreas.hansson@arm.com 1128707Sandreas.hansson@arm.comtemplate <class Impl> 1138707Sandreas.hansson@arm.combool 1148975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 1158707Sandreas.hansson@arm.com{ 1168975Sandreas.hansson@arm.com return lsq->recvTimingResp(pkt); 1178707Sandreas.hansson@arm.com} 1188707Sandreas.hansson@arm.com 1198707Sandreas.hansson@arm.comtemplate <class Impl> 1208975Sandreas.hansson@arm.comvoid 1218975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 1228948Sandreas.hansson@arm.com{ 12311148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 12411148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 12511151Smitch.hayenga@arm.com cpu->wakeup(tid); 12611148Smitch.hayenga@arm.com } 12710529Smorr@cs.wisc.edu } 1288975Sandreas.hansson@arm.com lsq->recvTimingSnoopReq(pkt); 1298948Sandreas.hansson@arm.com} 1308948Sandreas.hansson@arm.com 1318948Sandreas.hansson@arm.comtemplate <class Impl> 1328707Sandreas.hansson@arm.comvoid 13310713Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvReqRetry() 1348707Sandreas.hansson@arm.com{ 13510713Sandreas.hansson@arm.com lsq->recvReqRetry(); 1368707Sandreas.hansson@arm.com} 1378707Sandreas.hansson@arm.com 1381060SN/Atemplate <class Impl> 1391755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 1405606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 1411060SN/A{ 1421060SN/A} 1431060SN/A 1441060SN/Atemplate <class Impl> 1451060SN/Avoid 1461755SN/AFullO3CPU<Impl>::TickEvent::process() 1471060SN/A{ 1481060SN/A cpu->tick(); 1491060SN/A} 1501060SN/A 1511060SN/Atemplate <class Impl> 1521060SN/Aconst char * 1535336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 1541060SN/A{ 1554873Sstever@eecs.umich.edu return "FullO3CPU tick"; 1561060SN/A} 1571060SN/A 1581060SN/Atemplate <class Impl> 1595595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1602733Sktlim@umich.edu : BaseO3CPU(params), 1613781Sgblack@eecs.umich.edu itb(params->itb), 1623781Sgblack@eecs.umich.edu dtb(params->dtb), 1631060SN/A tickEvent(this), 1645737Scws3k@cs.virginia.edu#ifndef NDEBUG 1655737Scws3k@cs.virginia.edu instcount(0), 1665737Scws3k@cs.virginia.edu#endif 1672292SN/A removeInstsThisCycle(false), 1685595Sgblack@eecs.umich.edu fetch(this, params), 1695595Sgblack@eecs.umich.edu decode(this, params), 1705595Sgblack@eecs.umich.edu rename(this, params), 1715595Sgblack@eecs.umich.edu iew(this, params), 1725595Sgblack@eecs.umich.edu commit(this, params), 1731060SN/A 1749915Ssteve.reinhardt@amd.com regFile(params->numPhysIntRegs, 1759920Syasuko.eckert@amd.com params->numPhysFloatRegs, 17610935Snilay@cs.wisc.edu params->numPhysCCRegs), 1771060SN/A 1789919Ssteve.reinhardt@amd.com freeList(name() + ".freelist", ®File), 1791060SN/A 1809954SFaissal.Sleiman@arm.com rob(this, params), 1811060SN/A 1829916Ssteve.reinhardt@amd.com scoreboard(name() + ".scoreboard", 1839916Ssteve.reinhardt@amd.com regFile.totalNumPhysRegs(), TheISA::NumMiscRegs, 1849916Ssteve.reinhardt@amd.com TheISA::ZeroReg, TheISA::ZeroReg), 1851060SN/A 1869384SAndreas.Sandberg@arm.com isa(numThreads, NULL), 1879384SAndreas.Sandberg@arm.com 1888707Sandreas.hansson@arm.com icachePort(&fetch, this), 1898707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 1908707Sandreas.hansson@arm.com 1912873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1922873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1932873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1942873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1952873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1965804Snate@binkert.org activityRec(name(), NumStages, 1972873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1982873Sktlim@umich.edu params->activity), 1991060SN/A 2001060SN/A globalSeqNum(1), 2012292SN/A system(params->system), 2029180Sandreas.hansson@arm.com lastRunningCycle(curCycle()) 2031060SN/A{ 2049433SAndreas.Sandberg@ARM.com if (!params->switched_out) { 2053221Sktlim@umich.edu _status = Running; 2063221Sktlim@umich.edu } else { 2079152Satgutier@umich.edu _status = SwitchedOut; 2083221Sktlim@umich.edu } 2091681SN/A 2102794Sktlim@umich.edu if (params->checker) { 2112316SN/A BaseCPU *temp_checker = params->checker; 2128733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 2138707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2142316SN/A checker->setSystem(params->system); 2154598Sbinkertn@umich.edu } else { 2164598Sbinkertn@umich.edu checker = NULL; 2174598Sbinkertn@umich.edu } 2182316SN/A 2198793Sgblack@eecs.umich.edu if (!FullSystem) { 2208793Sgblack@eecs.umich.edu thread.resize(numThreads); 2218793Sgblack@eecs.umich.edu tids.resize(numThreads); 2228793Sgblack@eecs.umich.edu } 2231681SN/A 2242325SN/A // The stages also need their CPU pointer setup. However this 2252325SN/A // must be done at the upper level CPU because they have pointers 2262325SN/A // to the upper level CPU, and not this FullO3CPU. 2271060SN/A 2282292SN/A // Set up Pointers to the activeThreads list for each stage 2292292SN/A fetch.setActiveThreads(&activeThreads); 2302292SN/A decode.setActiveThreads(&activeThreads); 2312292SN/A rename.setActiveThreads(&activeThreads); 2322292SN/A iew.setActiveThreads(&activeThreads); 2332292SN/A commit.setActiveThreads(&activeThreads); 2341060SN/A 2351060SN/A // Give each of the stages the time buffer they will use. 2361060SN/A fetch.setTimeBuffer(&timeBuffer); 2371060SN/A decode.setTimeBuffer(&timeBuffer); 2381060SN/A rename.setTimeBuffer(&timeBuffer); 2391060SN/A iew.setTimeBuffer(&timeBuffer); 2401060SN/A commit.setTimeBuffer(&timeBuffer); 2411060SN/A 2421060SN/A // Also setup each of the stages' queues. 2431060SN/A fetch.setFetchQueue(&fetchQueue); 2441060SN/A decode.setFetchQueue(&fetchQueue); 2452292SN/A commit.setFetchQueue(&fetchQueue); 2461060SN/A decode.setDecodeQueue(&decodeQueue); 2471060SN/A rename.setDecodeQueue(&decodeQueue); 2481060SN/A rename.setRenameQueue(&renameQueue); 2491060SN/A iew.setRenameQueue(&renameQueue); 2501060SN/A iew.setIEWQueue(&iewQueue); 2511060SN/A commit.setIEWQueue(&iewQueue); 2521060SN/A commit.setRenameQueue(&renameQueue); 2531060SN/A 2542292SN/A commit.setIEWStage(&iew); 2552292SN/A rename.setIEWStage(&iew); 2562292SN/A rename.setCommitStage(&commit); 2572292SN/A 2588793Sgblack@eecs.umich.edu ThreadID active_threads; 2598793Sgblack@eecs.umich.edu if (FullSystem) { 2608793Sgblack@eecs.umich.edu active_threads = 1; 2618793Sgblack@eecs.umich.edu } else { 2628793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 2632831Sksewell@umich.edu 2648793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 2658793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 2668793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 2678793Sgblack@eecs.umich.edu "or edit your workload size."); 2688793Sgblack@eecs.umich.edu } 2692831Sksewell@umich.edu } 2702292SN/A 2712316SN/A //Make Sure That this a Valid Architeture 2722292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2732292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2749920Syasuko.eckert@amd.com assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs); 2752292SN/A 2762292SN/A rename.setScoreboard(&scoreboard); 2772292SN/A iew.setScoreboard(&scoreboard); 2782292SN/A 2791060SN/A // Setup the rename map for whichever stages need it. 2806221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2819384SAndreas.Sandberg@arm.com isa[tid] = params->isa[tid]; 2829384SAndreas.Sandberg@arm.com 2839919Ssteve.reinhardt@amd.com // Only Alpha has an FP zero register, so for other ISAs we 2849919Ssteve.reinhardt@amd.com // use an invalid FP register index to avoid special treatment 2859919Ssteve.reinhardt@amd.com // of any valid FP reg. 2869919Ssteve.reinhardt@amd.com RegIndex invalidFPReg = TheISA::NumFloatRegs + 1; 2879919Ssteve.reinhardt@amd.com RegIndex fpZeroReg = 2889919Ssteve.reinhardt@amd.com (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg; 2892292SN/A 2909919Ssteve.reinhardt@amd.com commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 2919919Ssteve.reinhardt@amd.com &freeList); 2922292SN/A 2939919Ssteve.reinhardt@amd.com renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 2949919Ssteve.reinhardt@amd.com &freeList); 2952292SN/A } 2962292SN/A 2979919Ssteve.reinhardt@amd.com // Initialize rename map to assign physical registers to the 2989919Ssteve.reinhardt@amd.com // architectural registers for active threads only. 2999919Ssteve.reinhardt@amd.com for (ThreadID tid = 0; tid < active_threads; tid++) { 3009919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) { 3019919Ssteve.reinhardt@amd.com // Note that we can't use the rename() method because we don't 3029919Ssteve.reinhardt@amd.com // want special treatment for the zero register at this point 3039919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = freeList.getIntReg(); 3049919Ssteve.reinhardt@amd.com renameMap[tid].setIntEntry(ridx, phys_reg); 3059919Ssteve.reinhardt@amd.com commitRenameMap[tid].setIntEntry(ridx, phys_reg); 3069919Ssteve.reinhardt@amd.com } 3079919Ssteve.reinhardt@amd.com 3089919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) { 3099919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = freeList.getFloatReg(); 3109919Ssteve.reinhardt@amd.com renameMap[tid].setFloatEntry(ridx, phys_reg); 3119919Ssteve.reinhardt@amd.com commitRenameMap[tid].setFloatEntry(ridx, phys_reg); 3129919Ssteve.reinhardt@amd.com } 3139920Syasuko.eckert@amd.com 3149920Syasuko.eckert@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) { 3159920Syasuko.eckert@amd.com PhysRegIndex phys_reg = freeList.getCCReg(); 3169920Syasuko.eckert@amd.com renameMap[tid].setCCEntry(ridx, phys_reg); 3179920Syasuko.eckert@amd.com commitRenameMap[tid].setCCEntry(ridx, phys_reg); 3189920Syasuko.eckert@amd.com } 3199919Ssteve.reinhardt@amd.com } 3209919Ssteve.reinhardt@amd.com 3212292SN/A rename.setRenameMap(renameMap); 3222292SN/A commit.setRenameMap(commitRenameMap); 3231060SN/A rename.setFreeList(&freeList); 3242292SN/A 3251060SN/A // Setup the ROB for whichever stages need it. 3261060SN/A commit.setROB(&rob); 3272292SN/A 3289158Sandreas.hansson@arm.com lastActivatedCycle = 0; 3296221Snate@binkert.org#if 0 3303093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3316221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3326221Snate@binkert.org globalSeqNum[tid] = 1; 3336221Snate@binkert.org#endif 3343093Sksewell@umich.edu 3355595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3365595Sgblack@eecs.umich.edu 3375595Sgblack@eecs.umich.edu // Setup any thread state. 3385595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3395595Sgblack@eecs.umich.edu 3406221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 3418793Sgblack@eecs.umich.edu if (FullSystem) { 3428793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3438793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3448793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 3458793Sgblack@eecs.umich.edu } else { 3468793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 3478793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3488793Sgblack@eecs.umich.edu tid, this->thread[tid]); 3498793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3508793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3518793Sgblack@eecs.umich.edu tid, params->workload[tid]); 3525595Sgblack@eecs.umich.edu 3538793Sgblack@eecs.umich.edu //usedTids[tid] = true; 3548793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 3558793Sgblack@eecs.umich.edu } else { 3568793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3578793Sgblack@eecs.umich.edu //when scheduling threads to CPU 3588793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3595595Sgblack@eecs.umich.edu 3608793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3618793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3628793Sgblack@eecs.umich.edu tid, dummy_proc); 3638793Sgblack@eecs.umich.edu //usedTids[tid] = false; 3648793Sgblack@eecs.umich.edu } 3655595Sgblack@eecs.umich.edu } 3665595Sgblack@eecs.umich.edu 3675595Sgblack@eecs.umich.edu ThreadContext *tc; 3685595Sgblack@eecs.umich.edu 3695595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3705595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3715595Sgblack@eecs.umich.edu 3725595Sgblack@eecs.umich.edu tc = o3_tc; 3735595Sgblack@eecs.umich.edu 3745595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3755595Sgblack@eecs.umich.edu // CheckerThreadContext. 3765595Sgblack@eecs.umich.edu if (params->checker) { 3775595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3785595Sgblack@eecs.umich.edu o3_tc, this->checker); 3795595Sgblack@eecs.umich.edu } 3805595Sgblack@eecs.umich.edu 3815595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 3825595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 3836221Snate@binkert.org o3_tc->thread = this->thread[tid]; 3845595Sgblack@eecs.umich.edu 38511627Smichael.lebeane@amd.com // Setup quiesce event. 38611627Smichael.lebeane@amd.com this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 38711627Smichael.lebeane@amd.com 3885595Sgblack@eecs.umich.edu // Give the thread the TC. 3896221Snate@binkert.org this->thread[tid]->tc = tc; 3905595Sgblack@eecs.umich.edu 3915595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 3925595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 3935595Sgblack@eecs.umich.edu } 3945595Sgblack@eecs.umich.edu 3958876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 39611150Smitch.hayenga@arm.com if (!params->switched_out && interrupts.empty()) { 3978876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 3988876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 3998876Sandreas.hansson@arm.com } 4008876Sandreas.hansson@arm.com 4016221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4026221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4031060SN/A} 4041060SN/A 4051060SN/Atemplate <class Impl> 4061755SN/AFullO3CPU<Impl>::~FullO3CPU() 4071060SN/A{ 4081060SN/A} 4091060SN/A 4101060SN/Atemplate <class Impl> 4111060SN/Avoid 41210023Smatt.horsnell@ARM.comFullO3CPU<Impl>::regProbePoints() 41310023Smatt.horsnell@ARM.com{ 41410464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 41510464SAndreas.Sandberg@ARM.com 41610023Smatt.horsnell@ARM.com ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete"); 41710023Smatt.horsnell@ARM.com ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete"); 41810464SAndreas.Sandberg@ARM.com 41910023Smatt.horsnell@ARM.com fetch.regProbePoints(); 42011246Sradhika.jagtap@ARM.com rename.regProbePoints(); 42110023Smatt.horsnell@ARM.com iew.regProbePoints(); 42210023Smatt.horsnell@ARM.com commit.regProbePoints(); 42310023Smatt.horsnell@ARM.com} 42410023Smatt.horsnell@ARM.com 42510023Smatt.horsnell@ARM.comtemplate <class Impl> 42610023Smatt.horsnell@ARM.comvoid 4275595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4281062SN/A{ 4292733Sktlim@umich.edu BaseO3CPU::regStats(); 4302292SN/A 4312733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4322292SN/A timesIdled 4332292SN/A .name(name() + ".timesIdled") 4342292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4352292SN/A " unscheduled itself") 4362292SN/A .prereq(timesIdled); 4372292SN/A 4382292SN/A idleCycles 4392292SN/A .name(name() + ".idleCycles") 4402292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4412292SN/A "to idling") 4422292SN/A .prereq(idleCycles); 4432292SN/A 4448627SAli.Saidi@ARM.com quiesceCycles 4458627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 4468627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 4478627SAli.Saidi@ARM.com "for an interrupt") 4488627SAli.Saidi@ARM.com .prereq(quiesceCycles); 4498627SAli.Saidi@ARM.com 4502292SN/A // Number of Instructions simulated 4512292SN/A // -------------------------------- 4522292SN/A // Should probably be in Base CPU but need templated 4532292SN/A // MaxThreads so put in here instead 4542292SN/A committedInsts 4552292SN/A .init(numThreads) 4562292SN/A .name(name() + ".committedInsts") 45710225Snilay@cs.wisc.edu .desc("Number of Instructions Simulated") 45810225Snilay@cs.wisc.edu .flags(Stats::total); 4592292SN/A 4608834Satgutier@umich.edu committedOps 4618834Satgutier@umich.edu .init(numThreads) 4628834Satgutier@umich.edu .name(name() + ".committedOps") 46310225Snilay@cs.wisc.edu .desc("Number of Ops (including micro ops) Simulated") 46410225Snilay@cs.wisc.edu .flags(Stats::total); 4652292SN/A 4662292SN/A cpi 4672292SN/A .name(name() + ".cpi") 4682292SN/A .desc("CPI: Cycles Per Instruction") 4692292SN/A .precision(6); 4704392Sktlim@umich.edu cpi = numCycles / committedInsts; 4712292SN/A 4722292SN/A totalCpi 4732292SN/A .name(name() + ".cpi_total") 4742292SN/A .desc("CPI: Total CPI of All Threads") 4752292SN/A .precision(6); 47610225Snilay@cs.wisc.edu totalCpi = numCycles / sum(committedInsts); 4772292SN/A 4782292SN/A ipc 4792292SN/A .name(name() + ".ipc") 4802292SN/A .desc("IPC: Instructions Per Cycle") 4812292SN/A .precision(6); 4824392Sktlim@umich.edu ipc = committedInsts / numCycles; 4832292SN/A 4842292SN/A totalIpc 4852292SN/A .name(name() + ".ipc_total") 4862292SN/A .desc("IPC: Total IPC of All Threads") 4872292SN/A .precision(6); 48810225Snilay@cs.wisc.edu totalIpc = sum(committedInsts) / numCycles; 4892292SN/A 4905595Sgblack@eecs.umich.edu this->fetch.regStats(); 4915595Sgblack@eecs.umich.edu this->decode.regStats(); 4925595Sgblack@eecs.umich.edu this->rename.regStats(); 4935595Sgblack@eecs.umich.edu this->iew.regStats(); 4945595Sgblack@eecs.umich.edu this->commit.regStats(); 4957897Shestness@cs.utexas.edu this->rob.regStats(); 4967897Shestness@cs.utexas.edu 4977897Shestness@cs.utexas.edu intRegfileReads 4987897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 4997897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 5007897Shestness@cs.utexas.edu .prereq(intRegfileReads); 5017897Shestness@cs.utexas.edu 5027897Shestness@cs.utexas.edu intRegfileWrites 5037897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 5047897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 5057897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 5067897Shestness@cs.utexas.edu 5077897Shestness@cs.utexas.edu fpRegfileReads 5087897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 5097897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5107897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5117897Shestness@cs.utexas.edu 5127897Shestness@cs.utexas.edu fpRegfileWrites 5137897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5147897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5157897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5167897Shestness@cs.utexas.edu 5179920Syasuko.eckert@amd.com ccRegfileReads 5189920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_reads") 5199920Syasuko.eckert@amd.com .desc("number of cc regfile reads") 5209920Syasuko.eckert@amd.com .prereq(ccRegfileReads); 5219920Syasuko.eckert@amd.com 5229920Syasuko.eckert@amd.com ccRegfileWrites 5239920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_writes") 5249920Syasuko.eckert@amd.com .desc("number of cc regfile writes") 5259920Syasuko.eckert@amd.com .prereq(ccRegfileWrites); 5269920Syasuko.eckert@amd.com 5277897Shestness@cs.utexas.edu miscRegfileReads 5287897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5297897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5307897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5317897Shestness@cs.utexas.edu 5327897Shestness@cs.utexas.edu miscRegfileWrites 5337897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5347897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5357897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5361062SN/A} 5371062SN/A 5381062SN/Atemplate <class Impl> 5391062SN/Avoid 5401755SN/AFullO3CPU<Impl>::tick() 5411060SN/A{ 5422733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5439444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 54410913Sandreas.sandberg@arm.com assert(drainState() != DrainState::Drained); 5451060SN/A 5462292SN/A ++numCycles; 54710464SAndreas.Sandberg@ARM.com ppCycles->notify(1); 5482292SN/A 5492325SN/A// activity = false; 5502292SN/A 5512292SN/A //Tick each of the stages 5521060SN/A fetch.tick(); 5531060SN/A 5541060SN/A decode.tick(); 5551060SN/A 5561060SN/A rename.tick(); 5571060SN/A 5581060SN/A iew.tick(); 5591060SN/A 5601060SN/A commit.tick(); 5611060SN/A 5622292SN/A // Now advance the time buffers 5631060SN/A timeBuffer.advance(); 5641060SN/A 5651060SN/A fetchQueue.advance(); 5661060SN/A decodeQueue.advance(); 5671060SN/A renameQueue.advance(); 5681060SN/A iewQueue.advance(); 5691060SN/A 5702325SN/A activityRec.advance(); 5712292SN/A 5722292SN/A if (removeInstsThisCycle) { 5732292SN/A cleanUpRemovedInsts(); 5742292SN/A } 5752292SN/A 5762325SN/A if (!tickEvent.scheduled()) { 5779444SAndreas.Sandberg@ARM.com if (_status == SwitchedOut) { 5783226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 5792325SN/A // increment stat 5809179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 5813221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 5823226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 5839179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 5842325SN/A timesIdled++; 5852325SN/A } else { 5869180Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(Cycles(1))); 5873226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 5882325SN/A } 5892292SN/A } 5902292SN/A 5918793Sgblack@eecs.umich.edu if (!FullSystem) 5928793Sgblack@eecs.umich.edu updateThreadPriority(); 5939444SAndreas.Sandberg@ARM.com 5949444SAndreas.Sandberg@ARM.com tryDrain(); 5951060SN/A} 5961060SN/A 5971060SN/Atemplate <class Impl> 5981060SN/Avoid 5991755SN/AFullO3CPU<Impl>::init() 6001060SN/A{ 6015714Shsul@eecs.umich.edu BaseCPU::init(); 6021060SN/A 6038921Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 6049382SAli.Saidi@ARM.com // Set noSquashFromTC so that the CPU doesn't squash when initially 6058921Sandreas.hansson@arm.com // setting up registers. 6069382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 6078921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 6088921Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 6098921Sandreas.hansson@arm.com } 6102292SN/A 6119433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 6128793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6138793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6148793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6158793Sgblack@eecs.umich.edu } 6166034Ssteve.reinhardt@amd.com } 6172292SN/A 6189382SAli.Saidi@ARM.com // Clear noSquashFromTC. 6196221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6209382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6212292SN/A 6229427SAndreas.Sandberg@ARM.com commit.setThreads(thread); 6239427SAndreas.Sandberg@ARM.com} 6242292SN/A 6259427SAndreas.Sandberg@ARM.comtemplate <class Impl> 6269427SAndreas.Sandberg@ARM.comvoid 6279427SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::startup() 6289427SAndreas.Sandberg@ARM.com{ 6299992Snilay@cs.wisc.edu BaseCPU::startup(); 6309461Snilay@cs.wisc.edu for (int tid = 0; tid < numThreads; ++tid) 6319461Snilay@cs.wisc.edu isa[tid]->startup(threadContexts[tid]); 6329461Snilay@cs.wisc.edu 6339427SAndreas.Sandberg@ARM.com fetch.startupStage(); 6349444SAndreas.Sandberg@ARM.com decode.startupStage(); 6359427SAndreas.Sandberg@ARM.com iew.startupStage(); 6369427SAndreas.Sandberg@ARM.com rename.startupStage(); 6379427SAndreas.Sandberg@ARM.com commit.startupStage(); 6382292SN/A} 6392292SN/A 6402292SN/Atemplate <class Impl> 6412292SN/Avoid 6426221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6432875Sksewell@umich.edu{ 6446221Snate@binkert.org list<ThreadID>::iterator isActive = 6455314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6462875Sksewell@umich.edu 6473226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6489444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6493226Sktlim@umich.edu 6502875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6512875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6522875Sksewell@umich.edu tid); 6532875Sksewell@umich.edu 6542875Sksewell@umich.edu activeThreads.push_back(tid); 6552875Sksewell@umich.edu } 6562875Sksewell@umich.edu} 6572875Sksewell@umich.edu 6582875Sksewell@umich.edutemplate <class Impl> 6592875Sksewell@umich.eduvoid 6606221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 6612875Sksewell@umich.edu{ 6622875Sksewell@umich.edu //Remove From Active List, if Active 6636221Snate@binkert.org list<ThreadID>::iterator thread_it = 6645314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6652875Sksewell@umich.edu 6663226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 6679444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6683226Sktlim@umich.edu 6692875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6702875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6712875Sksewell@umich.edu tid); 6722875Sksewell@umich.edu activeThreads.erase(thread_it); 6732875Sksewell@umich.edu } 67410331Smitch.hayenga@arm.com 67510331Smitch.hayenga@arm.com fetch.deactivateThread(tid); 67610331Smitch.hayenga@arm.com commit.deactivateThread(tid); 6772875Sksewell@umich.edu} 6782875Sksewell@umich.edu 6792875Sksewell@umich.edutemplate <class Impl> 6806221Snate@binkert.orgCounter 6818834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 6826221Snate@binkert.org{ 6836221Snate@binkert.org Counter total(0); 6846221Snate@binkert.org 6856221Snate@binkert.org ThreadID size = thread.size(); 6866221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 6876221Snate@binkert.org total += thread[i]->numInst; 6886221Snate@binkert.org 6896221Snate@binkert.org return total; 6906221Snate@binkert.org} 6916221Snate@binkert.org 6926221Snate@binkert.orgtemplate <class Impl> 6938834Satgutier@umich.eduCounter 6948834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 6958834Satgutier@umich.edu{ 6968834Satgutier@umich.edu Counter total(0); 6978834Satgutier@umich.edu 6988834Satgutier@umich.edu ThreadID size = thread.size(); 6998834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 7008834Satgutier@umich.edu total += thread[i]->numOp; 7018834Satgutier@umich.edu 7028834Satgutier@umich.edu return total; 7038834Satgutier@umich.edu} 7048834Satgutier@umich.edu 7058834Satgutier@umich.edutemplate <class Impl> 7062875Sksewell@umich.eduvoid 70710407Smitch.hayenga@arm.comFullO3CPU<Impl>::activateContext(ThreadID tid) 7082875Sksewell@umich.edu{ 7099444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7109444SAndreas.Sandberg@ARM.com 7112875Sksewell@umich.edu // Needs to set each stage to running as well. 71210407Smitch.hayenga@arm.com activateThread(tid); 7132875Sksewell@umich.edu 7149444SAndreas.Sandberg@ARM.com // We don't want to wake the CPU if it is drained. In that case, 7159444SAndreas.Sandberg@ARM.com // we just want to flag the thread as active and schedule the tick 7169444SAndreas.Sandberg@ARM.com // event from drainResume() instead. 71710913Sandreas.sandberg@arm.com if (drainState() == DrainState::Drained) 7189444SAndreas.Sandberg@ARM.com return; 7199444SAndreas.Sandberg@ARM.com 7209158Sandreas.hansson@arm.com // If we are time 0 or if the last activation time is in the past, 7219158Sandreas.hansson@arm.com // schedule the next tick and wake up the fetch unit 7229158Sandreas.hansson@arm.com if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 72310407Smitch.hayenga@arm.com scheduleTickEvent(Cycles(0)); 7242875Sksewell@umich.edu 7252875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7262875Sksewell@umich.edu // deschedule itself. 7272875Sksewell@umich.edu activityRec.activity(); 7282875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7292875Sksewell@umich.edu 7309180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 7319180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 7329179Sandreas.hansson@arm.com if (cycles != 0) 7339179Sandreas.hansson@arm.com --cycles; 7349179Sandreas.hansson@arm.com quiesceCycles += cycles; 7358627SAli.Saidi@ARM.com 7367823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7372875Sksewell@umich.edu 7382875Sksewell@umich.edu _status = Running; 73911526Sdavid.guillen@arm.com 74011526Sdavid.guillen@arm.com BaseCPU::activateContext(tid); 7412875Sksewell@umich.edu } 7422875Sksewell@umich.edu} 7432875Sksewell@umich.edu 7442875Sksewell@umich.edutemplate <class Impl> 74510407Smitch.hayenga@arm.comvoid 7466221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 7472875Sksewell@umich.edu{ 7482875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7499444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 75010408Smitch.hayenga@arm.com 75110408Smitch.hayenga@arm.com deactivateThread(tid); 75210407Smitch.hayenga@arm.com 7533221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 75410683Salexandru.dutu@amd.com if (activeThreads.size() == 0) { 7552910Sksewell@umich.edu unscheduleTickEvent(); 75610683Salexandru.dutu@amd.com lastRunningCycle = curCycle(); 75710683Salexandru.dutu@amd.com _status = Idle; 75810683Salexandru.dutu@amd.com } 7598627SAli.Saidi@ARM.com 7608627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 76111526Sdavid.guillen@arm.com 76211526Sdavid.guillen@arm.com BaseCPU::suspendContext(tid); 7632875Sksewell@umich.edu} 7642875Sksewell@umich.edu 7652875Sksewell@umich.edutemplate <class Impl> 7662875Sksewell@umich.eduvoid 7676221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 7682875Sksewell@umich.edu{ 7692910Sksewell@umich.edu //For now, this is the same as deallocate 7702910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 7719444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 77210408Smitch.hayenga@arm.com 77310408Smitch.hayenga@arm.com deactivateThread(tid); 77410408Smitch.hayenga@arm.com removeThread(tid); 7752875Sksewell@umich.edu} 7762875Sksewell@umich.edu 7772875Sksewell@umich.edutemplate <class Impl> 7782875Sksewell@umich.eduvoid 7796221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 7802292SN/A{ 7812847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 7822292SN/A // Will change now that the PC and thread state is internal to the CPU 7832683Sktlim@umich.edu // and not in the ThreadContext. 7848793Sgblack@eecs.umich.edu ThreadContext *src_tc; 7858793Sgblack@eecs.umich.edu if (FullSystem) 7868793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 7878793Sgblack@eecs.umich.edu else 7888793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 7892292SN/A 7902292SN/A //Bind Int Regs to Rename Map 79112104Snathanael.premillieu@arm.com 79212104Snathanael.premillieu@arm.com for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs; 79312104Snathanael.premillieu@arm.com reg_id.regIdx++) { 7942292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 79512104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 7962292SN/A scoreboard.setReg(phys_reg); 7972292SN/A } 7982292SN/A 7992292SN/A //Bind Float Regs to Rename Map 80012104Snathanael.premillieu@arm.com for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs; 80112104Snathanael.premillieu@arm.com reg_id.regIdx++) { 8022292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 80312104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 8042292SN/A scoreboard.setReg(phys_reg); 8052292SN/A } 8062292SN/A 8079920Syasuko.eckert@amd.com //Bind condition-code Regs to Rename Map 80812104Snathanael.premillieu@arm.com for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs; 80912104Snathanael.premillieu@arm.com reg_id.regIdx++) { 8109920Syasuko.eckert@amd.com PhysRegIndex phys_reg = freeList.getCCReg(); 81112104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 8129920Syasuko.eckert@amd.com scoreboard.setReg(phys_reg); 8139920Syasuko.eckert@amd.com } 8149920Syasuko.eckert@amd.com 8152292SN/A //Copy Thread Data Into RegFile 8162847Sksewell@umich.edu //this->copyFromTC(tid); 8172292SN/A 8182847Sksewell@umich.edu //Set PC/NPC/NNPC 8197720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8202292SN/A 8212680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8222292SN/A 82310407Smitch.hayenga@arm.com activateContext(tid); 8242292SN/A 8252292SN/A //Reset ROB/IQ/LSQ Entries 8262292SN/A commit.rob->resetEntries(); 8272292SN/A iew.resetEntries(); 8282292SN/A} 8292292SN/A 8302292SN/Atemplate <class Impl> 8312292SN/Avoid 8326221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8332292SN/A{ 8342877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 8352847Sksewell@umich.edu 8362847Sksewell@umich.edu // Copy Thread Data From RegFile 8372847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 8385364Sksewell@umich.edu // this->copyToTC(tid); 8395364Sksewell@umich.edu 8405364Sksewell@umich.edu 8415364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 8425364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 8435364Sksewell@umich.edu // in SMT workloads. 8442847Sksewell@umich.edu 8452847Sksewell@umich.edu // Unbind Int Regs from Rename Map 84612104Snathanael.premillieu@arm.com for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs; 84712104Snathanael.premillieu@arm.com reg_id.regIdx++) { 84812104Snathanael.premillieu@arm.com PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id); 8492292SN/A scoreboard.unsetReg(phys_reg); 8502292SN/A freeList.addReg(phys_reg); 8512292SN/A } 8522292SN/A 8532847Sksewell@umich.edu // Unbind Float Regs from Rename Map 85412104Snathanael.premillieu@arm.com for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs; 85512104Snathanael.premillieu@arm.com reg_id.regIdx++) { 85612104Snathanael.premillieu@arm.com PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id); 8572292SN/A scoreboard.unsetReg(phys_reg); 8582292SN/A freeList.addReg(phys_reg); 8592292SN/A } 8602292SN/A 8619920Syasuko.eckert@amd.com // Unbind condition-code Regs from Rename Map 86212104Snathanael.premillieu@arm.com for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs; 86312104Snathanael.premillieu@arm.com reg_id.regIdx++) { 86412104Snathanael.premillieu@arm.com PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id); 8659920Syasuko.eckert@amd.com scoreboard.unsetReg(phys_reg); 8669920Syasuko.eckert@amd.com freeList.addReg(phys_reg); 8679920Syasuko.eckert@amd.com } 8689920Syasuko.eckert@amd.com 8692847Sksewell@umich.edu // Squash Throughout Pipeline 8708138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 8718138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 8728138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 8732292SN/A decode.squash(tid); 8742935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 8752875Sksewell@umich.edu iew.squash(tid); 8765363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 8772935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 8782292SN/A 8795362Sksewell@umich.edu 8805362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 8812292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 8822292SN/A 8832847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 8843229Sktlim@umich.edu 8853229Sktlim@umich.edu // Commented out for now. This should be possible to do by 8863229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 8873229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 8883229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 8893229Sktlim@umich.edu/* 8902292SN/A if (activeThreads.size() >= 1) { 8912292SN/A commit.rob->resetEntries(); 8922292SN/A iew.resetEntries(); 8932292SN/A } 8943229Sktlim@umich.edu*/ 8952292SN/A} 8962292SN/A 8974192Sktlim@umich.edutemplate <class Impl> 8985595Sgblack@eecs.umich.eduFault 8996221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 9005702Ssaidi@eecs.umich.edu{ 9015702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9025702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 9035702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 9045702Ssaidi@eecs.umich.edu 9055702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 9065702Ssaidi@eecs.umich.edu 9075702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9085702Ssaidi@eecs.umich.edu#endif 9095702Ssaidi@eecs.umich.edu return NoFault; 9105702Ssaidi@eecs.umich.edu} 9115702Ssaidi@eecs.umich.edu 9125702Ssaidi@eecs.umich.edutemplate <class Impl> 9135702Ssaidi@eecs.umich.edubool 9146221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 9155702Ssaidi@eecs.umich.edu{ 9165702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9175702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 9185702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 9195702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 9205702Ssaidi@eecs.umich.edu 9215702Ssaidi@eecs.umich.edu switch (palFunc) { 9225702Ssaidi@eecs.umich.edu case PAL::halt: 9235702Ssaidi@eecs.umich.edu halt(); 9245702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 9255702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 9265702Ssaidi@eecs.umich.edu break; 9275702Ssaidi@eecs.umich.edu 9285702Ssaidi@eecs.umich.edu case PAL::bpt: 9295702Ssaidi@eecs.umich.edu case PAL::bugchk: 9305702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 9315702Ssaidi@eecs.umich.edu return false; 9325702Ssaidi@eecs.umich.edu break; 9335702Ssaidi@eecs.umich.edu } 9345702Ssaidi@eecs.umich.edu#endif 9355702Ssaidi@eecs.umich.edu return true; 9365702Ssaidi@eecs.umich.edu} 9375702Ssaidi@eecs.umich.edu 9385702Ssaidi@eecs.umich.edutemplate <class Impl> 9395702Ssaidi@eecs.umich.eduFault 9405595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 9415595Sgblack@eecs.umich.edu{ 9425595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 94311150Smitch.hayenga@arm.com return this->interrupts[0]->getInterrupt(this->threadContexts[0]); 9445595Sgblack@eecs.umich.edu} 9455595Sgblack@eecs.umich.edu 9465595Sgblack@eecs.umich.edutemplate <class Impl> 9475595Sgblack@eecs.umich.eduvoid 94810379Sandreas.hansson@arm.comFullO3CPU<Impl>::processInterrupts(const Fault &interrupt) 9495595Sgblack@eecs.umich.edu{ 9505595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 9515595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 9525595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9535595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9545595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9555595Sgblack@eecs.umich.edu 9565595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 95711150Smitch.hayenga@arm.com this->interrupts[0]->updateIntrInfo(this->threadContexts[0]); 9585595Sgblack@eecs.umich.edu 9595595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 96010417Sandreas.hansson@arm.com this->trap(interrupt, 0, nullptr); 9615595Sgblack@eecs.umich.edu} 9625595Sgblack@eecs.umich.edu 9631060SN/Atemplate <class Impl> 9642852Sktlim@umich.eduvoid 96510417Sandreas.hansson@arm.comFullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid, 96610417Sandreas.hansson@arm.com const StaticInstPtr &inst) 9675595Sgblack@eecs.umich.edu{ 9685595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 9697684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 9705595Sgblack@eecs.umich.edu} 9715595Sgblack@eecs.umich.edu 9725595Sgblack@eecs.umich.edutemplate <class Impl> 9735595Sgblack@eecs.umich.eduvoid 97411877Sbrandon.potter@amd.comFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault) 9755595Sgblack@eecs.umich.edu{ 9765595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 9775595Sgblack@eecs.umich.edu 9785595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 9795595Sgblack@eecs.umich.edu 9805595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 9815595Sgblack@eecs.umich.edu // instruction. 9825595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 9835595Sgblack@eecs.umich.edu 9845595Sgblack@eecs.umich.edu // Execute the actual syscall. 98511877Sbrandon.potter@amd.com this->thread[tid]->syscall(callnum, fault); 9865595Sgblack@eecs.umich.edu 9875595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 9885595Sgblack@eecs.umich.edu // incrementing it. 9895595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 9905595Sgblack@eecs.umich.edu} 9915595Sgblack@eecs.umich.edu 9925595Sgblack@eecs.umich.edutemplate <class Impl> 9935595Sgblack@eecs.umich.eduvoid 99410905Sandreas.sandberg@arm.comFullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const 9952864Sktlim@umich.edu{ 99610905Sandreas.sandberg@arm.com thread[tid]->serialize(cp); 9972864Sktlim@umich.edu} 9982864Sktlim@umich.edu 9992864Sktlim@umich.edutemplate <class Impl> 10002864Sktlim@umich.eduvoid 100110905Sandreas.sandberg@arm.comFullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid) 10022864Sktlim@umich.edu{ 100310905Sandreas.sandberg@arm.com thread[tid]->unserialize(cp); 10042864Sktlim@umich.edu} 10052864Sktlim@umich.edu 10062864Sktlim@umich.edutemplate <class Impl> 100710913Sandreas.sandberg@arm.comDrainState 100810913Sandreas.sandberg@arm.comFullO3CPU<Impl>::drain() 10091060SN/A{ 10109444SAndreas.Sandberg@ARM.com // If the CPU isn't doing anything, then return immediately. 101110913Sandreas.sandberg@arm.com if (switchedOut()) 101210913Sandreas.sandberg@arm.com return DrainState::Drained; 10133512Sktlim@umich.edu 10149444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Draining...\n"); 10153512Sktlim@umich.edu 10169444SAndreas.Sandberg@ARM.com // We only need to signal a drain to the commit stage as this 10179444SAndreas.Sandberg@ARM.com // initiates squashing controls the draining. Once the commit 10189444SAndreas.Sandberg@ARM.com // stage commits an instruction where it is safe to stop, it'll 10199444SAndreas.Sandberg@ARM.com // squash the rest of the instructions in the pipeline and force 10209444SAndreas.Sandberg@ARM.com // the fetch stage to stall. The pipeline will be drained once all 10219444SAndreas.Sandberg@ARM.com // in-flight instructions have retired. 10222843Sktlim@umich.edu commit.drain(); 10232325SN/A 10242325SN/A // Wake the CPU and record activity so everything can drain out if 10252863Sktlim@umich.edu // the CPU was not able to immediately drain. 10269444SAndreas.Sandberg@ARM.com if (!isDrained()) { 10272863Sktlim@umich.edu wakeCPU(); 10282863Sktlim@umich.edu activityRec.activity(); 10292852Sktlim@umich.edu 10309152Satgutier@umich.edu DPRINTF(Drain, "CPU not drained\n"); 10319152Satgutier@umich.edu 103210913Sandreas.sandberg@arm.com return DrainState::Draining; 10332863Sktlim@umich.edu } else { 10349444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU is already drained\n"); 10359444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 10369444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 10379444SAndreas.Sandberg@ARM.com 10389444SAndreas.Sandberg@ARM.com // Flush out any old data from the time buffers. In 10399444SAndreas.Sandberg@ARM.com // particular, there might be some data in flight from the 10409444SAndreas.Sandberg@ARM.com // fetch stage that isn't visible in any of the CPU buffers we 10419444SAndreas.Sandberg@ARM.com // test in isDrained(). 10429444SAndreas.Sandberg@ARM.com for (int i = 0; i < timeBuffer.getSize(); ++i) { 10439444SAndreas.Sandberg@ARM.com timeBuffer.advance(); 10449444SAndreas.Sandberg@ARM.com fetchQueue.advance(); 10459444SAndreas.Sandberg@ARM.com decodeQueue.advance(); 10469444SAndreas.Sandberg@ARM.com renameQueue.advance(); 10479444SAndreas.Sandberg@ARM.com iewQueue.advance(); 10489444SAndreas.Sandberg@ARM.com } 10499444SAndreas.Sandberg@ARM.com 10509444SAndreas.Sandberg@ARM.com drainSanityCheck(); 105110913Sandreas.sandberg@arm.com return DrainState::Drained; 10522863Sktlim@umich.edu } 10532316SN/A} 10542310SN/A 10552316SN/Atemplate <class Impl> 10569444SAndreas.Sandberg@ARM.combool 10579444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::tryDrain() 10589444SAndreas.Sandberg@ARM.com{ 105910913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining || !isDrained()) 10609444SAndreas.Sandberg@ARM.com return false; 10619444SAndreas.Sandberg@ARM.com 10629444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 10639444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 10649444SAndreas.Sandberg@ARM.com 10659444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 106610913Sandreas.sandberg@arm.com signalDrainDone(); 10679444SAndreas.Sandberg@ARM.com 10689444SAndreas.Sandberg@ARM.com return true; 10699444SAndreas.Sandberg@ARM.com} 10709444SAndreas.Sandberg@ARM.com 10719444SAndreas.Sandberg@ARM.comtemplate <class Impl> 10729444SAndreas.Sandberg@ARM.comvoid 10739444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::drainSanityCheck() const 10749444SAndreas.Sandberg@ARM.com{ 10759444SAndreas.Sandberg@ARM.com assert(isDrained()); 10769444SAndreas.Sandberg@ARM.com fetch.drainSanityCheck(); 10779444SAndreas.Sandberg@ARM.com decode.drainSanityCheck(); 10789444SAndreas.Sandberg@ARM.com rename.drainSanityCheck(); 10799444SAndreas.Sandberg@ARM.com iew.drainSanityCheck(); 10809444SAndreas.Sandberg@ARM.com commit.drainSanityCheck(); 10819444SAndreas.Sandberg@ARM.com} 10829444SAndreas.Sandberg@ARM.com 10839444SAndreas.Sandberg@ARM.comtemplate <class Impl> 10849444SAndreas.Sandberg@ARM.combool 10859444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::isDrained() const 10869444SAndreas.Sandberg@ARM.com{ 10879444SAndreas.Sandberg@ARM.com bool drained(true); 10889444SAndreas.Sandberg@ARM.com 10899444SAndreas.Sandberg@ARM.com if (!instList.empty() || !removeList.empty()) { 10909444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Main CPU structures not drained.\n"); 10919444SAndreas.Sandberg@ARM.com drained = false; 10929444SAndreas.Sandberg@ARM.com } 10939444SAndreas.Sandberg@ARM.com 10949444SAndreas.Sandberg@ARM.com if (!fetch.isDrained()) { 10959444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Fetch not drained.\n"); 10969444SAndreas.Sandberg@ARM.com drained = false; 10979444SAndreas.Sandberg@ARM.com } 10989444SAndreas.Sandberg@ARM.com 10999444SAndreas.Sandberg@ARM.com if (!decode.isDrained()) { 11009444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Decode not drained.\n"); 11019444SAndreas.Sandberg@ARM.com drained = false; 11029444SAndreas.Sandberg@ARM.com } 11039444SAndreas.Sandberg@ARM.com 11049444SAndreas.Sandberg@ARM.com if (!rename.isDrained()) { 11059444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Rename not drained.\n"); 11069444SAndreas.Sandberg@ARM.com drained = false; 11079444SAndreas.Sandberg@ARM.com } 11089444SAndreas.Sandberg@ARM.com 11099444SAndreas.Sandberg@ARM.com if (!iew.isDrained()) { 11109444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "IEW not drained.\n"); 11119444SAndreas.Sandberg@ARM.com drained = false; 11129444SAndreas.Sandberg@ARM.com } 11139444SAndreas.Sandberg@ARM.com 11149444SAndreas.Sandberg@ARM.com if (!commit.isDrained()) { 11159444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Commit not drained.\n"); 11169444SAndreas.Sandberg@ARM.com drained = false; 11179444SAndreas.Sandberg@ARM.com } 11189444SAndreas.Sandberg@ARM.com 11199444SAndreas.Sandberg@ARM.com return drained; 11209444SAndreas.Sandberg@ARM.com} 11219444SAndreas.Sandberg@ARM.com 11229444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11239444SAndreas.Sandberg@ARM.comvoid 11249444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::commitDrained(ThreadID tid) 11259444SAndreas.Sandberg@ARM.com{ 11269444SAndreas.Sandberg@ARM.com fetch.drainStall(tid); 11279444SAndreas.Sandberg@ARM.com} 11289444SAndreas.Sandberg@ARM.com 11299444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11302316SN/Avoid 11319342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drainResume() 11322316SN/A{ 11339444SAndreas.Sandberg@ARM.com if (switchedOut()) 11349444SAndreas.Sandberg@ARM.com return; 11352316SN/A 11369444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Resuming...\n"); 11379523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 11383319Shsul@eecs.umich.edu 11399444SAndreas.Sandberg@ARM.com fetch.drainResume(); 11409444SAndreas.Sandberg@ARM.com commit.drainResume(); 11412316SN/A 11429444SAndreas.Sandberg@ARM.com _status = Idle; 11439444SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); i++) { 11449444SAndreas.Sandberg@ARM.com if (thread[i]->status() == ThreadContext::Active) { 11459444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Activating thread: %i\n", i); 11469444SAndreas.Sandberg@ARM.com activateThread(i); 11479444SAndreas.Sandberg@ARM.com _status = Running; 11482863Sktlim@umich.edu } 11492310SN/A } 11509444SAndreas.Sandberg@ARM.com 11519444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 11529444SAndreas.Sandberg@ARM.com if (_status == Running) 11539444SAndreas.Sandberg@ARM.com schedule(tickEvent, nextCycle()); 11542843Sktlim@umich.edu} 11552843Sktlim@umich.edu 11562843Sktlim@umich.edutemplate <class Impl> 11572843Sktlim@umich.eduvoid 11582843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11592843Sktlim@umich.edu{ 11609444SAndreas.Sandberg@ARM.com DPRINTF(O3CPU, "Switching out\n"); 11619429SAndreas.Sandberg@ARM.com BaseCPU::switchOut(); 11629429SAndreas.Sandberg@ARM.com 11639444SAndreas.Sandberg@ARM.com activityRec.reset(); 11642843Sktlim@umich.edu 11652843Sktlim@umich.edu _status = SwitchedOut; 11668887Sgeoffrey.blake@arm.com 11672843Sktlim@umich.edu if (checker) 11682843Sktlim@umich.edu checker->switchOut(); 11691060SN/A} 11701060SN/A 11711060SN/Atemplate <class Impl> 11721060SN/Avoid 11731755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 11741060SN/A{ 11758737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 11761060SN/A 11772307SN/A fetch.takeOverFrom(); 11782307SN/A decode.takeOverFrom(); 11792307SN/A rename.takeOverFrom(); 11802307SN/A iew.takeOverFrom(); 11812307SN/A commit.takeOverFrom(); 11822307SN/A 11839444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 11841060SN/A 11859152Satgutier@umich.edu FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 11869152Satgutier@umich.edu if (oldO3CPU) 11879152Satgutier@umich.edu globalSeqNum = oldO3CPU->globalSeqNum; 11889152Satgutier@umich.edu 11899179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 11909444SAndreas.Sandberg@ARM.com _status = Idle; 11911060SN/A} 11921060SN/A 11931060SN/Atemplate <class Impl> 11949523SAndreas.Sandberg@ARM.comvoid 11959523SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::verifyMemoryMode() const 11969523SAndreas.Sandberg@ARM.com{ 11979524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 11989523SAndreas.Sandberg@ARM.com fatal("The O3 CPU requires the memory system to be in " 11999523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 12009523SAndreas.Sandberg@ARM.com } 12019523SAndreas.Sandberg@ARM.com} 12029523SAndreas.Sandberg@ARM.com 12039523SAndreas.Sandberg@ARM.comtemplate <class Impl> 12045595Sgblack@eecs.umich.eduTheISA::MiscReg 120510698Sandreas.hansson@arm.comFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const 12065595Sgblack@eecs.umich.edu{ 12079384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscRegNoEffect(misc_reg); 12085595Sgblack@eecs.umich.edu} 12095595Sgblack@eecs.umich.edu 12105595Sgblack@eecs.umich.edutemplate <class Impl> 12115595Sgblack@eecs.umich.eduTheISA::MiscReg 12126221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 12135595Sgblack@eecs.umich.edu{ 12147897Shestness@cs.utexas.edu miscRegfileReads++; 12159384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 12165595Sgblack@eecs.umich.edu} 12175595Sgblack@eecs.umich.edu 12185595Sgblack@eecs.umich.edutemplate <class Impl> 12195595Sgblack@eecs.umich.eduvoid 12205595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 12216221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12225595Sgblack@eecs.umich.edu{ 12239384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 12245595Sgblack@eecs.umich.edu} 12255595Sgblack@eecs.umich.edu 12265595Sgblack@eecs.umich.edutemplate <class Impl> 12275595Sgblack@eecs.umich.eduvoid 12285595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 12296221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12305595Sgblack@eecs.umich.edu{ 12317897Shestness@cs.utexas.edu miscRegfileWrites++; 12329384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 12335595Sgblack@eecs.umich.edu} 12345595Sgblack@eecs.umich.edu 12355595Sgblack@eecs.umich.edutemplate <class Impl> 12361060SN/Auint64_t 12371755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 12381060SN/A{ 12397897Shestness@cs.utexas.edu intRegfileReads++; 12401060SN/A return regFile.readIntReg(reg_idx); 12411060SN/A} 12421060SN/A 12431060SN/Atemplate <class Impl> 12442455SN/AFloatReg 12452455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 12461060SN/A{ 12477897Shestness@cs.utexas.edu fpRegfileReads++; 12482455SN/A return regFile.readFloatReg(reg_idx); 12491060SN/A} 12501060SN/A 12511060SN/Atemplate <class Impl> 12522455SN/AFloatRegBits 12532455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 12542455SN/A{ 12557897Shestness@cs.utexas.edu fpRegfileReads++; 12562455SN/A return regFile.readFloatRegBits(reg_idx); 12571060SN/A} 12581060SN/A 12591060SN/Atemplate <class Impl> 12609920Syasuko.eckert@amd.comCCReg 12619920Syasuko.eckert@amd.comFullO3CPU<Impl>::readCCReg(int reg_idx) 12629920Syasuko.eckert@amd.com{ 12639920Syasuko.eckert@amd.com ccRegfileReads++; 12649920Syasuko.eckert@amd.com return regFile.readCCReg(reg_idx); 12659920Syasuko.eckert@amd.com} 12669920Syasuko.eckert@amd.com 12679920Syasuko.eckert@amd.comtemplate <class Impl> 12681060SN/Avoid 12691755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 12701060SN/A{ 12717897Shestness@cs.utexas.edu intRegfileWrites++; 12721060SN/A regFile.setIntReg(reg_idx, val); 12731060SN/A} 12741060SN/A 12751060SN/Atemplate <class Impl> 12761060SN/Avoid 12772455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 12781060SN/A{ 12797897Shestness@cs.utexas.edu fpRegfileWrites++; 12802455SN/A regFile.setFloatReg(reg_idx, val); 12811060SN/A} 12821060SN/A 12831060SN/Atemplate <class Impl> 12841060SN/Avoid 12852455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 12862455SN/A{ 12877897Shestness@cs.utexas.edu fpRegfileWrites++; 12882455SN/A regFile.setFloatRegBits(reg_idx, val); 12891060SN/A} 12901060SN/A 12911060SN/Atemplate <class Impl> 12929920Syasuko.eckert@amd.comvoid 12939920Syasuko.eckert@amd.comFullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val) 12949920Syasuko.eckert@amd.com{ 12959920Syasuko.eckert@amd.com ccRegfileWrites++; 12969920Syasuko.eckert@amd.com regFile.setCCReg(reg_idx, val); 12979920Syasuko.eckert@amd.com} 12989920Syasuko.eckert@amd.com 12999920Syasuko.eckert@amd.comtemplate <class Impl> 13001060SN/Auint64_t 13016221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 13021060SN/A{ 13037897Shestness@cs.utexas.edu intRegfileReads++; 13049919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 13052292SN/A 13062292SN/A return regFile.readIntReg(phys_reg); 13072292SN/A} 13082292SN/A 13092292SN/Atemplate <class Impl> 13102292SN/Afloat 13116314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 13122292SN/A{ 13137897Shestness@cs.utexas.edu fpRegfileReads++; 13149919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 13152292SN/A 13162669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 13172292SN/A} 13182292SN/A 13192292SN/Atemplate <class Impl> 13202292SN/Auint64_t 13216221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 13222292SN/A{ 13237897Shestness@cs.utexas.edu fpRegfileReads++; 13249919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 13252292SN/A 13262669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13271060SN/A} 13281060SN/A 13291060SN/Atemplate <class Impl> 13309920Syasuko.eckert@amd.comCCReg 13319920Syasuko.eckert@amd.comFullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid) 13329920Syasuko.eckert@amd.com{ 13339920Syasuko.eckert@amd.com ccRegfileReads++; 13349920Syasuko.eckert@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 13359920Syasuko.eckert@amd.com 13369920Syasuko.eckert@amd.com return regFile.readCCReg(phys_reg); 13379920Syasuko.eckert@amd.com} 13389920Syasuko.eckert@amd.com 13399920Syasuko.eckert@amd.comtemplate <class Impl> 13401060SN/Avoid 13416221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 13421060SN/A{ 13437897Shestness@cs.utexas.edu intRegfileWrites++; 13449919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 13452292SN/A 13462292SN/A regFile.setIntReg(phys_reg, val); 13471060SN/A} 13481060SN/A 13491060SN/Atemplate <class Impl> 13501060SN/Avoid 13516314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 13521060SN/A{ 13537897Shestness@cs.utexas.edu fpRegfileWrites++; 13549919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 13552292SN/A 13562669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 13571060SN/A} 13581060SN/A 13591060SN/Atemplate <class Impl> 13601060SN/Avoid 13616221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 13621060SN/A{ 13637897Shestness@cs.utexas.edu fpRegfileWrites++; 13649919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 13651060SN/A 13662669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 13672292SN/A} 13682292SN/A 13692292SN/Atemplate <class Impl> 13709920Syasuko.eckert@amd.comvoid 13719920Syasuko.eckert@amd.comFullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid) 13729920Syasuko.eckert@amd.com{ 13739920Syasuko.eckert@amd.com ccRegfileWrites++; 13749920Syasuko.eckert@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 13759920Syasuko.eckert@amd.com 13769920Syasuko.eckert@amd.com regFile.setCCReg(phys_reg, val); 13779920Syasuko.eckert@amd.com} 13789920Syasuko.eckert@amd.com 13799920Syasuko.eckert@amd.comtemplate <class Impl> 13807720Sgblack@eecs.umich.eduTheISA::PCState 13817720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 13822292SN/A{ 13837720Sgblack@eecs.umich.edu return commit.pcState(tid); 13841060SN/A} 13851060SN/A 13861060SN/Atemplate <class Impl> 13871060SN/Avoid 13887720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 13891060SN/A{ 13907720Sgblack@eecs.umich.edu commit.pcState(val, tid); 13912292SN/A} 13921060SN/A 13932292SN/Atemplate <class Impl> 13947720Sgblack@eecs.umich.eduAddr 13957720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 13964636Sgblack@eecs.umich.edu{ 13977720Sgblack@eecs.umich.edu return commit.instAddr(tid); 13984636Sgblack@eecs.umich.edu} 13994636Sgblack@eecs.umich.edu 14004636Sgblack@eecs.umich.edutemplate <class Impl> 14017720Sgblack@eecs.umich.eduAddr 14027720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 14034636Sgblack@eecs.umich.edu{ 14047720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 14054636Sgblack@eecs.umich.edu} 14064636Sgblack@eecs.umich.edu 14074636Sgblack@eecs.umich.edutemplate <class Impl> 14087720Sgblack@eecs.umich.eduMicroPC 14097720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 14102292SN/A{ 14117720Sgblack@eecs.umich.edu return commit.microPC(tid); 14124636Sgblack@eecs.umich.edu} 14134636Sgblack@eecs.umich.edu 14144636Sgblack@eecs.umich.edutemplate <class Impl> 14155595Sgblack@eecs.umich.eduvoid 14166221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 14175595Sgblack@eecs.umich.edu{ 14189382SAli.Saidi@ARM.com this->thread[tid]->noSquashFromTC = true; 14195595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 14205595Sgblack@eecs.umich.edu} 14215595Sgblack@eecs.umich.edu 14225595Sgblack@eecs.umich.edutemplate <class Impl> 14232292SN/Atypename FullO3CPU<Impl>::ListIt 14242292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14252292SN/A{ 14262292SN/A instList.push_back(inst); 14271060SN/A 14282292SN/A return --(instList.end()); 14292292SN/A} 14301060SN/A 14312292SN/Atemplate <class Impl> 14322292SN/Avoid 14338834Satgutier@umich.eduFullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 14342292SN/A{ 14352292SN/A // Keep an instruction count. 14368834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 14378834Satgutier@umich.edu thread[tid]->numInst++; 14388834Satgutier@umich.edu thread[tid]->numInsts++; 14398834Satgutier@umich.edu committedInsts[tid]++; 144010774Snikos.nikoleris@gmail.com system->totalNumInsts++; 144110774Snikos.nikoleris@gmail.com 144210774Snikos.nikoleris@gmail.com // Check for instruction-count-based events. 144310774Snikos.nikoleris@gmail.com comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 144410774Snikos.nikoleris@gmail.com system->instEventQueue.serviceEvents(system->totalNumInsts); 14458834Satgutier@umich.edu } 14468834Satgutier@umich.edu thread[tid]->numOp++; 14478834Satgutier@umich.edu thread[tid]->numOps++; 14488834Satgutier@umich.edu committedOps[tid]++; 14498834Satgutier@umich.edu 145010464SAndreas.Sandberg@ARM.com probeInstCommit(inst->staticInst); 14512292SN/A} 14522292SN/A 14532292SN/Atemplate <class Impl> 14542292SN/Avoid 14551755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 14561060SN/A{ 14577720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 14582292SN/A "[sn:%lli]\n", 14597720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 14601060SN/A 14612292SN/A removeInstsThisCycle = true; 14621060SN/A 14631060SN/A // Remove the front instruction. 14642292SN/A removeList.push(inst->getInstListIt()); 14651060SN/A} 14661060SN/A 14671060SN/Atemplate <class Impl> 14681060SN/Avoid 14696221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 14701060SN/A{ 14712733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 14722292SN/A " list.\n", tid); 14731060SN/A 14742292SN/A ListIt end_it; 14751060SN/A 14762292SN/A bool rob_empty = false; 14772292SN/A 14782292SN/A if (instList.empty()) { 14792292SN/A return; 148010164Ssleimanf@umich.edu } else if (rob.isEmpty(tid)) { 14812733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 14822292SN/A end_it = instList.begin(); 14832292SN/A rob_empty = true; 14842292SN/A } else { 14852292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 14862733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 14872292SN/A } 14882292SN/A 14892292SN/A removeInstsThisCycle = true; 14902292SN/A 14912292SN/A ListIt inst_it = instList.end(); 14922292SN/A 14932292SN/A inst_it--; 14942292SN/A 14952292SN/A // Walk through the instruction list, removing any instructions 14962292SN/A // that were inserted after the given instruction iterator, end_it. 14972292SN/A while (inst_it != end_it) { 14982292SN/A assert(!instList.empty()); 14992292SN/A 15002292SN/A squashInstIt(inst_it, tid); 15012292SN/A 15022292SN/A inst_it--; 15032292SN/A } 15042292SN/A 15052292SN/A // If the ROB was empty, then we actually need to remove the first 15062292SN/A // instruction as well. 15072292SN/A if (rob_empty) { 15082292SN/A squashInstIt(inst_it, tid); 15092292SN/A } 15101060SN/A} 15111060SN/A 15121060SN/Atemplate <class Impl> 15131060SN/Avoid 15146221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 15151062SN/A{ 15162292SN/A assert(!instList.empty()); 15172292SN/A 15182292SN/A removeInstsThisCycle = true; 15192292SN/A 15202292SN/A ListIt inst_iter = instList.end(); 15212292SN/A 15222292SN/A inst_iter--; 15232292SN/A 15242733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 15252292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15262292SN/A tid, seq_num, (*inst_iter)->seqNum); 15271062SN/A 15282292SN/A while ((*inst_iter)->seqNum > seq_num) { 15291062SN/A 15302292SN/A bool break_loop = (inst_iter == instList.begin()); 15311062SN/A 15322292SN/A squashInstIt(inst_iter, tid); 15331062SN/A 15342292SN/A inst_iter--; 15351062SN/A 15362292SN/A if (break_loop) 15372292SN/A break; 15382292SN/A } 15392292SN/A} 15402292SN/A 15412292SN/Atemplate <class Impl> 15422292SN/Ainline void 15436221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 15442292SN/A{ 15452292SN/A if ((*instIt)->threadNumber == tid) { 15462733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 15477720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15482292SN/A (*instIt)->threadNumber, 15492292SN/A (*instIt)->seqNum, 15507720Sgblack@eecs.umich.edu (*instIt)->pcState()); 15511062SN/A 15521062SN/A // Mark it as squashed. 15532292SN/A (*instIt)->setSquashed(); 15542292SN/A 15552325SN/A // @todo: Formulate a consistent method for deleting 15562325SN/A // instructions from the instruction list 15572292SN/A // Remove the instruction from the list. 15582292SN/A removeList.push(instIt); 15592292SN/A } 15602292SN/A} 15612292SN/A 15622292SN/Atemplate <class Impl> 15632292SN/Avoid 15642292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 15652292SN/A{ 15662292SN/A while (!removeList.empty()) { 15672733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 15687720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15692292SN/A (*removeList.front())->threadNumber, 15702292SN/A (*removeList.front())->seqNum, 15717720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 15722292SN/A 15732292SN/A instList.erase(removeList.front()); 15742292SN/A 15752292SN/A removeList.pop(); 15761062SN/A } 15771062SN/A 15782292SN/A removeInstsThisCycle = false; 15791062SN/A} 15802325SN/A/* 15811062SN/Atemplate <class Impl> 15821062SN/Avoid 15831755SN/AFullO3CPU<Impl>::removeAllInsts() 15841060SN/A{ 15851060SN/A instList.clear(); 15861060SN/A} 15872325SN/A*/ 15881060SN/Atemplate <class Impl> 15891060SN/Avoid 15901755SN/AFullO3CPU<Impl>::dumpInsts() 15911060SN/A{ 15921060SN/A int num = 0; 15931060SN/A 15942292SN/A ListIt inst_list_it = instList.begin(); 15952292SN/A 15962292SN/A cprintf("Dumping Instruction List\n"); 15972292SN/A 15982292SN/A while (inst_list_it != instList.end()) { 15992292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 16002292SN/A "Squashed:%i\n\n", 16017720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 16022292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16032292SN/A (*inst_list_it)->isSquashed()); 16041060SN/A inst_list_it++; 16051060SN/A ++num; 16061060SN/A } 16071060SN/A} 16082325SN/A/* 16091060SN/Atemplate <class Impl> 16101060SN/Avoid 16111755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 16121060SN/A{ 16131060SN/A iew.wakeDependents(inst); 16141060SN/A} 16152325SN/A*/ 16162292SN/Atemplate <class Impl> 16172292SN/Avoid 16182292SN/AFullO3CPU<Impl>::wakeCPU() 16192292SN/A{ 16202325SN/A if (activityRec.active() || tickEvent.scheduled()) { 16212325SN/A DPRINTF(Activity, "CPU already running.\n"); 16222292SN/A return; 16232292SN/A } 16242292SN/A 16252325SN/A DPRINTF(Activity, "Waking up CPU\n"); 16262325SN/A 16279180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 16289180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 162910464SAndreas.Sandberg@ARM.com if (cycles > 1) { 16309179Sandreas.hansson@arm.com --cycles; 163110464SAndreas.Sandberg@ARM.com idleCycles += cycles; 163210464SAndreas.Sandberg@ARM.com numCycles += cycles; 163310464SAndreas.Sandberg@ARM.com ppCycles->notify(cycles); 163410464SAndreas.Sandberg@ARM.com } 16352292SN/A 16369648Sdam.sunwoo@arm.com schedule(tickEvent, clockEdge()); 16372292SN/A} 16382292SN/A 16395807Snate@binkert.orgtemplate <class Impl> 16405807Snate@binkert.orgvoid 164111151Smitch.hayenga@arm.comFullO3CPU<Impl>::wakeup(ThreadID tid) 16425807Snate@binkert.org{ 164311151Smitch.hayenga@arm.com if (this->thread[tid]->status() != ThreadContext::Suspended) 16445807Snate@binkert.org return; 16455807Snate@binkert.org 16465807Snate@binkert.org this->wakeCPU(); 16475807Snate@binkert.org 16485807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 164911151Smitch.hayenga@arm.com this->threadContexts[tid]->activate(); 16505807Snate@binkert.org} 16515807Snate@binkert.org 16522292SN/Atemplate <class Impl> 16536221Snate@binkert.orgThreadID 16542292SN/AFullO3CPU<Impl>::getFreeTid() 16552292SN/A{ 16566221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 16576221Snate@binkert.org if (!tids[tid]) { 16586221Snate@binkert.org tids[tid] = true; 16596221Snate@binkert.org return tid; 16602292SN/A } 16612292SN/A } 16622292SN/A 16636221Snate@binkert.org return InvalidThreadID; 16642292SN/A} 16652292SN/A 16662292SN/Atemplate <class Impl> 16672292SN/Avoid 16682292SN/AFullO3CPU<Impl>::updateThreadPriority() 16692292SN/A{ 16706221Snate@binkert.org if (activeThreads.size() > 1) { 16712292SN/A //DEFAULT TO ROUND ROBIN SCHEME 16722292SN/A //e.g. Move highest priority to end of thread list 16736221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 16742292SN/A 16752292SN/A unsigned high_thread = *list_begin; 16762292SN/A 16772292SN/A activeThreads.erase(list_begin); 16782292SN/A 16792292SN/A activeThreads.push_back(high_thread); 16802292SN/A } 16812292SN/A} 16821060SN/A 16831755SN/A// Forward declaration of FullO3CPU. 16842818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1685