cpu.cc revision 11627
11689SN/A/* 210331Smitch.hayenga@arm.com * Copyright (c) 2011-2012, 2014 ARM Limited 39916Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 152325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 167897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432756Sksewell@umich.edu * Korey Sewell 447897Shestness@cs.utexas.edu * Rick Strong 451689SN/A */ 461689SN/A 478779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 498887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 508887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 518229Snate@binkert.org#include "cpu/o3/cpu.hh" 528229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 538229Snate@binkert.org#include "cpu/o3/thread_context.hh" 544762Snate@binkert.org#include "cpu/activity.hh" 558779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 564762Snate@binkert.org#include "cpu/simple_thread.hh" 574762Snate@binkert.org#include "cpu/thread_context.hh" 588232Snate@binkert.org#include "debug/Activity.hh" 599152Satgutier@umich.edu#include "debug/Drain.hh" 608232Snate@binkert.org#include "debug/O3CPU.hh" 618232Snate@binkert.org#include "debug/Quiesce.hh" 624762Snate@binkert.org#include "enums/MemoryMode.hh" 634762Snate@binkert.org#include "sim/core.hh" 648793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 658779Sgblack@eecs.umich.edu#include "sim/process.hh" 664762Snate@binkert.org#include "sim/stat_control.hh" 678460SAli.Saidi@ARM.com#include "sim/system.hh" 684762Snate@binkert.org 695702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 705702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 718232Snate@binkert.org#include "debug/Activity.hh" 725702Ssaidi@eecs.umich.edu#endif 735702Ssaidi@eecs.umich.edu 748737Skoansin.tan@gmail.comstruct BaseCPUParams; 755529Snate@binkert.org 762669Sktlim@umich.eduusing namespace TheISA; 776221Snate@binkert.orgusing namespace std; 781060SN/A 795529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 805712Shsul@eecs.umich.edu : BaseCPU(params) 811060SN/A{ 821060SN/A} 831060SN/A 842292SN/Avoid 852733Sktlim@umich.eduBaseO3CPU::regStats() 862292SN/A{ 872292SN/A BaseCPU::regStats(); 882292SN/A} 892292SN/A 908707Sandreas.hansson@arm.comtemplate<class Impl> 918707Sandreas.hansson@arm.combool 928975Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 938707Sandreas.hansson@arm.com{ 948707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 9511284Sandreas.hansson@arm.com // We shouldn't ever get a cacheable block in Modified state 9610821Sandreas.hansson@arm.com assert(pkt->req->isUncacheable() || 9711284Sandreas.hansson@arm.com !(pkt->cacheResponding() && !pkt->hasSharers())); 988948Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 998707Sandreas.hansson@arm.com 1008707Sandreas.hansson@arm.com return true; 1018707Sandreas.hansson@arm.com} 1028707Sandreas.hansson@arm.com 1038707Sandreas.hansson@arm.comtemplate<class Impl> 1048707Sandreas.hansson@arm.comvoid 10510713Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvReqRetry() 1068707Sandreas.hansson@arm.com{ 10710713Sandreas.hansson@arm.com fetch->recvReqRetry(); 1088707Sandreas.hansson@arm.com} 1098707Sandreas.hansson@arm.com 1108707Sandreas.hansson@arm.comtemplate <class Impl> 1118707Sandreas.hansson@arm.combool 1128975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 1138707Sandreas.hansson@arm.com{ 1148975Sandreas.hansson@arm.com return lsq->recvTimingResp(pkt); 1158707Sandreas.hansson@arm.com} 1168707Sandreas.hansson@arm.com 1178707Sandreas.hansson@arm.comtemplate <class Impl> 1188975Sandreas.hansson@arm.comvoid 1198975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 1208948Sandreas.hansson@arm.com{ 12111148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 12211148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 12311151Smitch.hayenga@arm.com cpu->wakeup(tid); 12411148Smitch.hayenga@arm.com } 12510529Smorr@cs.wisc.edu } 1268975Sandreas.hansson@arm.com lsq->recvTimingSnoopReq(pkt); 1278948Sandreas.hansson@arm.com} 1288948Sandreas.hansson@arm.com 1298948Sandreas.hansson@arm.comtemplate <class Impl> 1308707Sandreas.hansson@arm.comvoid 13110713Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvReqRetry() 1328707Sandreas.hansson@arm.com{ 13310713Sandreas.hansson@arm.com lsq->recvReqRetry(); 1348707Sandreas.hansson@arm.com} 1358707Sandreas.hansson@arm.com 1361060SN/Atemplate <class Impl> 1371755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 1385606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 1391060SN/A{ 1401060SN/A} 1411060SN/A 1421060SN/Atemplate <class Impl> 1431060SN/Avoid 1441755SN/AFullO3CPU<Impl>::TickEvent::process() 1451060SN/A{ 1461060SN/A cpu->tick(); 1471060SN/A} 1481060SN/A 1491060SN/Atemplate <class Impl> 1501060SN/Aconst char * 1515336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 1521060SN/A{ 1534873Sstever@eecs.umich.edu return "FullO3CPU tick"; 1541060SN/A} 1551060SN/A 1561060SN/Atemplate <class Impl> 1575595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1582733Sktlim@umich.edu : BaseO3CPU(params), 1593781Sgblack@eecs.umich.edu itb(params->itb), 1603781Sgblack@eecs.umich.edu dtb(params->dtb), 1611060SN/A tickEvent(this), 1625737Scws3k@cs.virginia.edu#ifndef NDEBUG 1635737Scws3k@cs.virginia.edu instcount(0), 1645737Scws3k@cs.virginia.edu#endif 1652292SN/A removeInstsThisCycle(false), 1665595Sgblack@eecs.umich.edu fetch(this, params), 1675595Sgblack@eecs.umich.edu decode(this, params), 1685595Sgblack@eecs.umich.edu rename(this, params), 1695595Sgblack@eecs.umich.edu iew(this, params), 1705595Sgblack@eecs.umich.edu commit(this, params), 1711060SN/A 1729915Ssteve.reinhardt@amd.com regFile(params->numPhysIntRegs, 1739920Syasuko.eckert@amd.com params->numPhysFloatRegs, 17410935Snilay@cs.wisc.edu params->numPhysCCRegs), 1751060SN/A 1769919Ssteve.reinhardt@amd.com freeList(name() + ".freelist", ®File), 1771060SN/A 1789954SFaissal.Sleiman@arm.com rob(this, params), 1791060SN/A 1809916Ssteve.reinhardt@amd.com scoreboard(name() + ".scoreboard", 1819916Ssteve.reinhardt@amd.com regFile.totalNumPhysRegs(), TheISA::NumMiscRegs, 1829916Ssteve.reinhardt@amd.com TheISA::ZeroReg, TheISA::ZeroReg), 1831060SN/A 1849384SAndreas.Sandberg@arm.com isa(numThreads, NULL), 1859384SAndreas.Sandberg@arm.com 1868707Sandreas.hansson@arm.com icachePort(&fetch, this), 1878707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 1888707Sandreas.hansson@arm.com 1892873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1902873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1912873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1922873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1932873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1945804Snate@binkert.org activityRec(name(), NumStages, 1952873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1962873Sktlim@umich.edu params->activity), 1971060SN/A 1981060SN/A globalSeqNum(1), 1992292SN/A system(params->system), 2009180Sandreas.hansson@arm.com lastRunningCycle(curCycle()) 2011060SN/A{ 2029433SAndreas.Sandberg@ARM.com if (!params->switched_out) { 2033221Sktlim@umich.edu _status = Running; 2043221Sktlim@umich.edu } else { 2059152Satgutier@umich.edu _status = SwitchedOut; 2063221Sktlim@umich.edu } 2071681SN/A 2082794Sktlim@umich.edu if (params->checker) { 2092316SN/A BaseCPU *temp_checker = params->checker; 2108733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 2118707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2122316SN/A checker->setSystem(params->system); 2134598Sbinkertn@umich.edu } else { 2144598Sbinkertn@umich.edu checker = NULL; 2154598Sbinkertn@umich.edu } 2162316SN/A 2178793Sgblack@eecs.umich.edu if (!FullSystem) { 2188793Sgblack@eecs.umich.edu thread.resize(numThreads); 2198793Sgblack@eecs.umich.edu tids.resize(numThreads); 2208793Sgblack@eecs.umich.edu } 2211681SN/A 2222325SN/A // The stages also need their CPU pointer setup. However this 2232325SN/A // must be done at the upper level CPU because they have pointers 2242325SN/A // to the upper level CPU, and not this FullO3CPU. 2251060SN/A 2262292SN/A // Set up Pointers to the activeThreads list for each stage 2272292SN/A fetch.setActiveThreads(&activeThreads); 2282292SN/A decode.setActiveThreads(&activeThreads); 2292292SN/A rename.setActiveThreads(&activeThreads); 2302292SN/A iew.setActiveThreads(&activeThreads); 2312292SN/A commit.setActiveThreads(&activeThreads); 2321060SN/A 2331060SN/A // Give each of the stages the time buffer they will use. 2341060SN/A fetch.setTimeBuffer(&timeBuffer); 2351060SN/A decode.setTimeBuffer(&timeBuffer); 2361060SN/A rename.setTimeBuffer(&timeBuffer); 2371060SN/A iew.setTimeBuffer(&timeBuffer); 2381060SN/A commit.setTimeBuffer(&timeBuffer); 2391060SN/A 2401060SN/A // Also setup each of the stages' queues. 2411060SN/A fetch.setFetchQueue(&fetchQueue); 2421060SN/A decode.setFetchQueue(&fetchQueue); 2432292SN/A commit.setFetchQueue(&fetchQueue); 2441060SN/A decode.setDecodeQueue(&decodeQueue); 2451060SN/A rename.setDecodeQueue(&decodeQueue); 2461060SN/A rename.setRenameQueue(&renameQueue); 2471060SN/A iew.setRenameQueue(&renameQueue); 2481060SN/A iew.setIEWQueue(&iewQueue); 2491060SN/A commit.setIEWQueue(&iewQueue); 2501060SN/A commit.setRenameQueue(&renameQueue); 2511060SN/A 2522292SN/A commit.setIEWStage(&iew); 2532292SN/A rename.setIEWStage(&iew); 2542292SN/A rename.setCommitStage(&commit); 2552292SN/A 2568793Sgblack@eecs.umich.edu ThreadID active_threads; 2578793Sgblack@eecs.umich.edu if (FullSystem) { 2588793Sgblack@eecs.umich.edu active_threads = 1; 2598793Sgblack@eecs.umich.edu } else { 2608793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 2612831Sksewell@umich.edu 2628793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 2638793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 2648793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 2658793Sgblack@eecs.umich.edu "or edit your workload size."); 2668793Sgblack@eecs.umich.edu } 2672831Sksewell@umich.edu } 2682292SN/A 2692316SN/A //Make Sure That this a Valid Architeture 2702292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2712292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2729920Syasuko.eckert@amd.com assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs); 2732292SN/A 2742292SN/A rename.setScoreboard(&scoreboard); 2752292SN/A iew.setScoreboard(&scoreboard); 2762292SN/A 2771060SN/A // Setup the rename map for whichever stages need it. 2786221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2799384SAndreas.Sandberg@arm.com isa[tid] = params->isa[tid]; 2809384SAndreas.Sandberg@arm.com 2819919Ssteve.reinhardt@amd.com // Only Alpha has an FP zero register, so for other ISAs we 2829919Ssteve.reinhardt@amd.com // use an invalid FP register index to avoid special treatment 2839919Ssteve.reinhardt@amd.com // of any valid FP reg. 2849919Ssteve.reinhardt@amd.com RegIndex invalidFPReg = TheISA::NumFloatRegs + 1; 2859919Ssteve.reinhardt@amd.com RegIndex fpZeroReg = 2869919Ssteve.reinhardt@amd.com (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg; 2872292SN/A 2889919Ssteve.reinhardt@amd.com commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 2899919Ssteve.reinhardt@amd.com &freeList); 2902292SN/A 2919919Ssteve.reinhardt@amd.com renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 2929919Ssteve.reinhardt@amd.com &freeList); 2932292SN/A } 2942292SN/A 2959919Ssteve.reinhardt@amd.com // Initialize rename map to assign physical registers to the 2969919Ssteve.reinhardt@amd.com // architectural registers for active threads only. 2979919Ssteve.reinhardt@amd.com for (ThreadID tid = 0; tid < active_threads; tid++) { 2989919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) { 2999919Ssteve.reinhardt@amd.com // Note that we can't use the rename() method because we don't 3009919Ssteve.reinhardt@amd.com // want special treatment for the zero register at this point 3019919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = freeList.getIntReg(); 3029919Ssteve.reinhardt@amd.com renameMap[tid].setIntEntry(ridx, phys_reg); 3039919Ssteve.reinhardt@amd.com commitRenameMap[tid].setIntEntry(ridx, phys_reg); 3049919Ssteve.reinhardt@amd.com } 3059919Ssteve.reinhardt@amd.com 3069919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) { 3079919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = freeList.getFloatReg(); 3089919Ssteve.reinhardt@amd.com renameMap[tid].setFloatEntry(ridx, phys_reg); 3099919Ssteve.reinhardt@amd.com commitRenameMap[tid].setFloatEntry(ridx, phys_reg); 3109919Ssteve.reinhardt@amd.com } 3119920Syasuko.eckert@amd.com 3129920Syasuko.eckert@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) { 3139920Syasuko.eckert@amd.com PhysRegIndex phys_reg = freeList.getCCReg(); 3149920Syasuko.eckert@amd.com renameMap[tid].setCCEntry(ridx, phys_reg); 3159920Syasuko.eckert@amd.com commitRenameMap[tid].setCCEntry(ridx, phys_reg); 3169920Syasuko.eckert@amd.com } 3179919Ssteve.reinhardt@amd.com } 3189919Ssteve.reinhardt@amd.com 3192292SN/A rename.setRenameMap(renameMap); 3202292SN/A commit.setRenameMap(commitRenameMap); 3211060SN/A rename.setFreeList(&freeList); 3222292SN/A 3231060SN/A // Setup the ROB for whichever stages need it. 3241060SN/A commit.setROB(&rob); 3252292SN/A 3269158Sandreas.hansson@arm.com lastActivatedCycle = 0; 3276221Snate@binkert.org#if 0 3283093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3296221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3306221Snate@binkert.org globalSeqNum[tid] = 1; 3316221Snate@binkert.org#endif 3323093Sksewell@umich.edu 3335595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3345595Sgblack@eecs.umich.edu 3355595Sgblack@eecs.umich.edu // Setup any thread state. 3365595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3375595Sgblack@eecs.umich.edu 3386221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 3398793Sgblack@eecs.umich.edu if (FullSystem) { 3408793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3418793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3428793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 3438793Sgblack@eecs.umich.edu } else { 3448793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 3458793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3468793Sgblack@eecs.umich.edu tid, this->thread[tid]); 3478793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3488793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3498793Sgblack@eecs.umich.edu tid, params->workload[tid]); 3505595Sgblack@eecs.umich.edu 3518793Sgblack@eecs.umich.edu //usedTids[tid] = true; 3528793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 3538793Sgblack@eecs.umich.edu } else { 3548793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3558793Sgblack@eecs.umich.edu //when scheduling threads to CPU 3568793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3575595Sgblack@eecs.umich.edu 3588793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3598793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3608793Sgblack@eecs.umich.edu tid, dummy_proc); 3618793Sgblack@eecs.umich.edu //usedTids[tid] = false; 3628793Sgblack@eecs.umich.edu } 3635595Sgblack@eecs.umich.edu } 3645595Sgblack@eecs.umich.edu 3655595Sgblack@eecs.umich.edu ThreadContext *tc; 3665595Sgblack@eecs.umich.edu 3675595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3685595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3695595Sgblack@eecs.umich.edu 3705595Sgblack@eecs.umich.edu tc = o3_tc; 3715595Sgblack@eecs.umich.edu 3725595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3735595Sgblack@eecs.umich.edu // CheckerThreadContext. 3745595Sgblack@eecs.umich.edu if (params->checker) { 3755595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3765595Sgblack@eecs.umich.edu o3_tc, this->checker); 3775595Sgblack@eecs.umich.edu } 3785595Sgblack@eecs.umich.edu 3795595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 3805595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 3816221Snate@binkert.org o3_tc->thread = this->thread[tid]; 3825595Sgblack@eecs.umich.edu 38311627Smichael.lebeane@amd.com // Setup quiesce event. 38411627Smichael.lebeane@amd.com this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 38511627Smichael.lebeane@amd.com 3865595Sgblack@eecs.umich.edu // Give the thread the TC. 3876221Snate@binkert.org this->thread[tid]->tc = tc; 3885595Sgblack@eecs.umich.edu 3895595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 3905595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 3915595Sgblack@eecs.umich.edu } 3925595Sgblack@eecs.umich.edu 3938876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 39411150Smitch.hayenga@arm.com if (!params->switched_out && interrupts.empty()) { 3958876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 3968876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 3978876Sandreas.hansson@arm.com } 3988876Sandreas.hansson@arm.com 3996221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4006221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4011060SN/A} 4021060SN/A 4031060SN/Atemplate <class Impl> 4041755SN/AFullO3CPU<Impl>::~FullO3CPU() 4051060SN/A{ 4061060SN/A} 4071060SN/A 4081060SN/Atemplate <class Impl> 4091060SN/Avoid 41010023Smatt.horsnell@ARM.comFullO3CPU<Impl>::regProbePoints() 41110023Smatt.horsnell@ARM.com{ 41210464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 41310464SAndreas.Sandberg@ARM.com 41410023Smatt.horsnell@ARM.com ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete"); 41510023Smatt.horsnell@ARM.com ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete"); 41610464SAndreas.Sandberg@ARM.com 41710023Smatt.horsnell@ARM.com fetch.regProbePoints(); 41811246Sradhika.jagtap@ARM.com rename.regProbePoints(); 41910023Smatt.horsnell@ARM.com iew.regProbePoints(); 42010023Smatt.horsnell@ARM.com commit.regProbePoints(); 42110023Smatt.horsnell@ARM.com} 42210023Smatt.horsnell@ARM.com 42310023Smatt.horsnell@ARM.comtemplate <class Impl> 42410023Smatt.horsnell@ARM.comvoid 4255595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4261062SN/A{ 4272733Sktlim@umich.edu BaseO3CPU::regStats(); 4282292SN/A 4292733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4302292SN/A timesIdled 4312292SN/A .name(name() + ".timesIdled") 4322292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4332292SN/A " unscheduled itself") 4342292SN/A .prereq(timesIdled); 4352292SN/A 4362292SN/A idleCycles 4372292SN/A .name(name() + ".idleCycles") 4382292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4392292SN/A "to idling") 4402292SN/A .prereq(idleCycles); 4412292SN/A 4428627SAli.Saidi@ARM.com quiesceCycles 4438627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 4448627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 4458627SAli.Saidi@ARM.com "for an interrupt") 4468627SAli.Saidi@ARM.com .prereq(quiesceCycles); 4478627SAli.Saidi@ARM.com 4482292SN/A // Number of Instructions simulated 4492292SN/A // -------------------------------- 4502292SN/A // Should probably be in Base CPU but need templated 4512292SN/A // MaxThreads so put in here instead 4522292SN/A committedInsts 4532292SN/A .init(numThreads) 4542292SN/A .name(name() + ".committedInsts") 45510225Snilay@cs.wisc.edu .desc("Number of Instructions Simulated") 45610225Snilay@cs.wisc.edu .flags(Stats::total); 4572292SN/A 4588834Satgutier@umich.edu committedOps 4598834Satgutier@umich.edu .init(numThreads) 4608834Satgutier@umich.edu .name(name() + ".committedOps") 46110225Snilay@cs.wisc.edu .desc("Number of Ops (including micro ops) Simulated") 46210225Snilay@cs.wisc.edu .flags(Stats::total); 4632292SN/A 4642292SN/A cpi 4652292SN/A .name(name() + ".cpi") 4662292SN/A .desc("CPI: Cycles Per Instruction") 4672292SN/A .precision(6); 4684392Sktlim@umich.edu cpi = numCycles / committedInsts; 4692292SN/A 4702292SN/A totalCpi 4712292SN/A .name(name() + ".cpi_total") 4722292SN/A .desc("CPI: Total CPI of All Threads") 4732292SN/A .precision(6); 47410225Snilay@cs.wisc.edu totalCpi = numCycles / sum(committedInsts); 4752292SN/A 4762292SN/A ipc 4772292SN/A .name(name() + ".ipc") 4782292SN/A .desc("IPC: Instructions Per Cycle") 4792292SN/A .precision(6); 4804392Sktlim@umich.edu ipc = committedInsts / numCycles; 4812292SN/A 4822292SN/A totalIpc 4832292SN/A .name(name() + ".ipc_total") 4842292SN/A .desc("IPC: Total IPC of All Threads") 4852292SN/A .precision(6); 48610225Snilay@cs.wisc.edu totalIpc = sum(committedInsts) / numCycles; 4872292SN/A 4885595Sgblack@eecs.umich.edu this->fetch.regStats(); 4895595Sgblack@eecs.umich.edu this->decode.regStats(); 4905595Sgblack@eecs.umich.edu this->rename.regStats(); 4915595Sgblack@eecs.umich.edu this->iew.regStats(); 4925595Sgblack@eecs.umich.edu this->commit.regStats(); 4937897Shestness@cs.utexas.edu this->rob.regStats(); 4947897Shestness@cs.utexas.edu 4957897Shestness@cs.utexas.edu intRegfileReads 4967897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 4977897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 4987897Shestness@cs.utexas.edu .prereq(intRegfileReads); 4997897Shestness@cs.utexas.edu 5007897Shestness@cs.utexas.edu intRegfileWrites 5017897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 5027897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 5037897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 5047897Shestness@cs.utexas.edu 5057897Shestness@cs.utexas.edu fpRegfileReads 5067897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 5077897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5087897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5097897Shestness@cs.utexas.edu 5107897Shestness@cs.utexas.edu fpRegfileWrites 5117897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5127897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5137897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5147897Shestness@cs.utexas.edu 5159920Syasuko.eckert@amd.com ccRegfileReads 5169920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_reads") 5179920Syasuko.eckert@amd.com .desc("number of cc regfile reads") 5189920Syasuko.eckert@amd.com .prereq(ccRegfileReads); 5199920Syasuko.eckert@amd.com 5209920Syasuko.eckert@amd.com ccRegfileWrites 5219920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_writes") 5229920Syasuko.eckert@amd.com .desc("number of cc regfile writes") 5239920Syasuko.eckert@amd.com .prereq(ccRegfileWrites); 5249920Syasuko.eckert@amd.com 5257897Shestness@cs.utexas.edu miscRegfileReads 5267897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5277897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5287897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5297897Shestness@cs.utexas.edu 5307897Shestness@cs.utexas.edu miscRegfileWrites 5317897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5327897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5337897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5341062SN/A} 5351062SN/A 5361062SN/Atemplate <class Impl> 5371062SN/Avoid 5381755SN/AFullO3CPU<Impl>::tick() 5391060SN/A{ 5402733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5419444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 54210913Sandreas.sandberg@arm.com assert(drainState() != DrainState::Drained); 5431060SN/A 5442292SN/A ++numCycles; 54510464SAndreas.Sandberg@ARM.com ppCycles->notify(1); 5462292SN/A 5472325SN/A// activity = false; 5482292SN/A 5492292SN/A //Tick each of the stages 5501060SN/A fetch.tick(); 5511060SN/A 5521060SN/A decode.tick(); 5531060SN/A 5541060SN/A rename.tick(); 5551060SN/A 5561060SN/A iew.tick(); 5571060SN/A 5581060SN/A commit.tick(); 5591060SN/A 5602292SN/A // Now advance the time buffers 5611060SN/A timeBuffer.advance(); 5621060SN/A 5631060SN/A fetchQueue.advance(); 5641060SN/A decodeQueue.advance(); 5651060SN/A renameQueue.advance(); 5661060SN/A iewQueue.advance(); 5671060SN/A 5682325SN/A activityRec.advance(); 5692292SN/A 5702292SN/A if (removeInstsThisCycle) { 5712292SN/A cleanUpRemovedInsts(); 5722292SN/A } 5732292SN/A 5742325SN/A if (!tickEvent.scheduled()) { 5759444SAndreas.Sandberg@ARM.com if (_status == SwitchedOut) { 5763226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 5772325SN/A // increment stat 5789179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 5793221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 5803226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 5819179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 5822325SN/A timesIdled++; 5832325SN/A } else { 5849180Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(Cycles(1))); 5853226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 5862325SN/A } 5872292SN/A } 5882292SN/A 5898793Sgblack@eecs.umich.edu if (!FullSystem) 5908793Sgblack@eecs.umich.edu updateThreadPriority(); 5919444SAndreas.Sandberg@ARM.com 5929444SAndreas.Sandberg@ARM.com tryDrain(); 5931060SN/A} 5941060SN/A 5951060SN/Atemplate <class Impl> 5961060SN/Avoid 5971755SN/AFullO3CPU<Impl>::init() 5981060SN/A{ 5995714Shsul@eecs.umich.edu BaseCPU::init(); 6001060SN/A 6018921Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 6029382SAli.Saidi@ARM.com // Set noSquashFromTC so that the CPU doesn't squash when initially 6038921Sandreas.hansson@arm.com // setting up registers. 6049382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 6058921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 6068921Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 6078921Sandreas.hansson@arm.com } 6082292SN/A 6099433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 6108793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6118793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6128793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6138793Sgblack@eecs.umich.edu } 6146034Ssteve.reinhardt@amd.com } 6152292SN/A 6169382SAli.Saidi@ARM.com // Clear noSquashFromTC. 6176221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6189382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6192292SN/A 6209427SAndreas.Sandberg@ARM.com commit.setThreads(thread); 6219427SAndreas.Sandberg@ARM.com} 6222292SN/A 6239427SAndreas.Sandberg@ARM.comtemplate <class Impl> 6249427SAndreas.Sandberg@ARM.comvoid 6259427SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::startup() 6269427SAndreas.Sandberg@ARM.com{ 6279992Snilay@cs.wisc.edu BaseCPU::startup(); 6289461Snilay@cs.wisc.edu for (int tid = 0; tid < numThreads; ++tid) 6299461Snilay@cs.wisc.edu isa[tid]->startup(threadContexts[tid]); 6309461Snilay@cs.wisc.edu 6319427SAndreas.Sandberg@ARM.com fetch.startupStage(); 6329444SAndreas.Sandberg@ARM.com decode.startupStage(); 6339427SAndreas.Sandberg@ARM.com iew.startupStage(); 6349427SAndreas.Sandberg@ARM.com rename.startupStage(); 6359427SAndreas.Sandberg@ARM.com commit.startupStage(); 6362292SN/A} 6372292SN/A 6382292SN/Atemplate <class Impl> 6392292SN/Avoid 6406221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6412875Sksewell@umich.edu{ 6426221Snate@binkert.org list<ThreadID>::iterator isActive = 6435314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6442875Sksewell@umich.edu 6453226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6469444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6473226Sktlim@umich.edu 6482875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6492875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6502875Sksewell@umich.edu tid); 6512875Sksewell@umich.edu 6522875Sksewell@umich.edu activeThreads.push_back(tid); 6532875Sksewell@umich.edu } 6542875Sksewell@umich.edu} 6552875Sksewell@umich.edu 6562875Sksewell@umich.edutemplate <class Impl> 6572875Sksewell@umich.eduvoid 6586221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 6592875Sksewell@umich.edu{ 6602875Sksewell@umich.edu //Remove From Active List, if Active 6616221Snate@binkert.org list<ThreadID>::iterator thread_it = 6625314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6632875Sksewell@umich.edu 6643226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 6659444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6663226Sktlim@umich.edu 6672875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6682875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6692875Sksewell@umich.edu tid); 6702875Sksewell@umich.edu activeThreads.erase(thread_it); 6712875Sksewell@umich.edu } 67210331Smitch.hayenga@arm.com 67310331Smitch.hayenga@arm.com fetch.deactivateThread(tid); 67410331Smitch.hayenga@arm.com commit.deactivateThread(tid); 6752875Sksewell@umich.edu} 6762875Sksewell@umich.edu 6772875Sksewell@umich.edutemplate <class Impl> 6786221Snate@binkert.orgCounter 6798834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 6806221Snate@binkert.org{ 6816221Snate@binkert.org Counter total(0); 6826221Snate@binkert.org 6836221Snate@binkert.org ThreadID size = thread.size(); 6846221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 6856221Snate@binkert.org total += thread[i]->numInst; 6866221Snate@binkert.org 6876221Snate@binkert.org return total; 6886221Snate@binkert.org} 6896221Snate@binkert.org 6906221Snate@binkert.orgtemplate <class Impl> 6918834Satgutier@umich.eduCounter 6928834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 6938834Satgutier@umich.edu{ 6948834Satgutier@umich.edu Counter total(0); 6958834Satgutier@umich.edu 6968834Satgutier@umich.edu ThreadID size = thread.size(); 6978834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 6988834Satgutier@umich.edu total += thread[i]->numOp; 6998834Satgutier@umich.edu 7008834Satgutier@umich.edu return total; 7018834Satgutier@umich.edu} 7028834Satgutier@umich.edu 7038834Satgutier@umich.edutemplate <class Impl> 7042875Sksewell@umich.eduvoid 70510407Smitch.hayenga@arm.comFullO3CPU<Impl>::activateContext(ThreadID tid) 7062875Sksewell@umich.edu{ 7079444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7089444SAndreas.Sandberg@ARM.com 7092875Sksewell@umich.edu // Needs to set each stage to running as well. 71010407Smitch.hayenga@arm.com activateThread(tid); 7112875Sksewell@umich.edu 7129444SAndreas.Sandberg@ARM.com // We don't want to wake the CPU if it is drained. In that case, 7139444SAndreas.Sandberg@ARM.com // we just want to flag the thread as active and schedule the tick 7149444SAndreas.Sandberg@ARM.com // event from drainResume() instead. 71510913Sandreas.sandberg@arm.com if (drainState() == DrainState::Drained) 7169444SAndreas.Sandberg@ARM.com return; 7179444SAndreas.Sandberg@ARM.com 7189158Sandreas.hansson@arm.com // If we are time 0 or if the last activation time is in the past, 7199158Sandreas.hansson@arm.com // schedule the next tick and wake up the fetch unit 7209158Sandreas.hansson@arm.com if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 72110407Smitch.hayenga@arm.com scheduleTickEvent(Cycles(0)); 7222875Sksewell@umich.edu 7232875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7242875Sksewell@umich.edu // deschedule itself. 7252875Sksewell@umich.edu activityRec.activity(); 7262875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7272875Sksewell@umich.edu 7289180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 7299180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 7309179Sandreas.hansson@arm.com if (cycles != 0) 7319179Sandreas.hansson@arm.com --cycles; 7329179Sandreas.hansson@arm.com quiesceCycles += cycles; 7338627SAli.Saidi@ARM.com 7347823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7352875Sksewell@umich.edu 7362875Sksewell@umich.edu _status = Running; 73711526Sdavid.guillen@arm.com 73811526Sdavid.guillen@arm.com BaseCPU::activateContext(tid); 7392875Sksewell@umich.edu } 7402875Sksewell@umich.edu} 7412875Sksewell@umich.edu 7422875Sksewell@umich.edutemplate <class Impl> 74310407Smitch.hayenga@arm.comvoid 7446221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 7452875Sksewell@umich.edu{ 7462875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7479444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 74810408Smitch.hayenga@arm.com 74910408Smitch.hayenga@arm.com deactivateThread(tid); 75010407Smitch.hayenga@arm.com 7513221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 75210683Salexandru.dutu@amd.com if (activeThreads.size() == 0) { 7532910Sksewell@umich.edu unscheduleTickEvent(); 75410683Salexandru.dutu@amd.com lastRunningCycle = curCycle(); 75510683Salexandru.dutu@amd.com _status = Idle; 75610683Salexandru.dutu@amd.com } 7578627SAli.Saidi@ARM.com 7588627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 75911526Sdavid.guillen@arm.com 76011526Sdavid.guillen@arm.com BaseCPU::suspendContext(tid); 7612875Sksewell@umich.edu} 7622875Sksewell@umich.edu 7632875Sksewell@umich.edutemplate <class Impl> 7642875Sksewell@umich.eduvoid 7656221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 7662875Sksewell@umich.edu{ 7672910Sksewell@umich.edu //For now, this is the same as deallocate 7682910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 7699444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 77010408Smitch.hayenga@arm.com 77110408Smitch.hayenga@arm.com deactivateThread(tid); 77210408Smitch.hayenga@arm.com removeThread(tid); 7732875Sksewell@umich.edu} 7742875Sksewell@umich.edu 7752875Sksewell@umich.edutemplate <class Impl> 7762875Sksewell@umich.eduvoid 7776221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 7782292SN/A{ 7792847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 7802292SN/A // Will change now that the PC and thread state is internal to the CPU 7812683Sktlim@umich.edu // and not in the ThreadContext. 7828793Sgblack@eecs.umich.edu ThreadContext *src_tc; 7838793Sgblack@eecs.umich.edu if (FullSystem) 7848793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 7858793Sgblack@eecs.umich.edu else 7868793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 7872292SN/A 7882292SN/A //Bind Int Regs to Rename Map 7892292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7902292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 7912292SN/A 7922292SN/A renameMap[tid].setEntry(ireg,phys_reg); 7932292SN/A scoreboard.setReg(phys_reg); 7942292SN/A } 7952292SN/A 7962292SN/A //Bind Float Regs to Rename Map 79711225Snathananel.premillieu@arm.com int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs; 79811225Snathananel.premillieu@arm.com for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) { 7992292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 8002292SN/A 8012292SN/A renameMap[tid].setEntry(freg,phys_reg); 8022292SN/A scoreboard.setReg(phys_reg); 8032292SN/A } 8042292SN/A 8059920Syasuko.eckert@amd.com //Bind condition-code Regs to Rename Map 80611225Snathananel.premillieu@arm.com max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs; 80711225Snathananel.premillieu@arm.com for (int creg = TheISA::CC_Reg_Base; 8089920Syasuko.eckert@amd.com creg < max_reg; creg++) { 8099920Syasuko.eckert@amd.com PhysRegIndex phys_reg = freeList.getCCReg(); 8109920Syasuko.eckert@amd.com 8119920Syasuko.eckert@amd.com renameMap[tid].setEntry(creg,phys_reg); 8129920Syasuko.eckert@amd.com scoreboard.setReg(phys_reg); 8139920Syasuko.eckert@amd.com } 8149920Syasuko.eckert@amd.com 8152292SN/A //Copy Thread Data Into RegFile 8162847Sksewell@umich.edu //this->copyFromTC(tid); 8172292SN/A 8182847Sksewell@umich.edu //Set PC/NPC/NNPC 8197720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8202292SN/A 8212680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8222292SN/A 82310407Smitch.hayenga@arm.com activateContext(tid); 8242292SN/A 8252292SN/A //Reset ROB/IQ/LSQ Entries 8262292SN/A commit.rob->resetEntries(); 8272292SN/A iew.resetEntries(); 8282292SN/A} 8292292SN/A 8302292SN/Atemplate <class Impl> 8312292SN/Avoid 8326221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8332292SN/A{ 8342877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 8352847Sksewell@umich.edu 8362847Sksewell@umich.edu // Copy Thread Data From RegFile 8372847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 8385364Sksewell@umich.edu // this->copyToTC(tid); 8395364Sksewell@umich.edu 8405364Sksewell@umich.edu 8415364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 8425364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 8435364Sksewell@umich.edu // in SMT workloads. 8442847Sksewell@umich.edu 8452847Sksewell@umich.edu // Unbind Int Regs from Rename Map 8462292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8472292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 8482292SN/A scoreboard.unsetReg(phys_reg); 8492292SN/A freeList.addReg(phys_reg); 8502292SN/A } 8512292SN/A 8522847Sksewell@umich.edu // Unbind Float Regs from Rename Map 85310487Snilay@cs.wisc.edu int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs; 85410487Snilay@cs.wisc.edu for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) { 8552292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 8562292SN/A scoreboard.unsetReg(phys_reg); 8572292SN/A freeList.addReg(phys_reg); 8582292SN/A } 8592292SN/A 8609920Syasuko.eckert@amd.com // Unbind condition-code Regs from Rename Map 86110487Snilay@cs.wisc.edu max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs; 86210487Snilay@cs.wisc.edu for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) { 8639920Syasuko.eckert@amd.com PhysRegIndex phys_reg = renameMap[tid].lookup(creg); 8649920Syasuko.eckert@amd.com scoreboard.unsetReg(phys_reg); 8659920Syasuko.eckert@amd.com freeList.addReg(phys_reg); 8669920Syasuko.eckert@amd.com } 8679920Syasuko.eckert@amd.com 8682847Sksewell@umich.edu // Squash Throughout Pipeline 8698138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 8708138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 8718138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 8722292SN/A decode.squash(tid); 8732935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 8742875Sksewell@umich.edu iew.squash(tid); 8755363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 8762935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 8772292SN/A 8785362Sksewell@umich.edu 8795362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 8802292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 8812292SN/A 8822847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 8833229Sktlim@umich.edu 8843229Sktlim@umich.edu // Commented out for now. This should be possible to do by 8853229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 8863229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 8873229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 8883229Sktlim@umich.edu/* 8892292SN/A if (activeThreads.size() >= 1) { 8902292SN/A commit.rob->resetEntries(); 8912292SN/A iew.resetEntries(); 8922292SN/A } 8933229Sktlim@umich.edu*/ 8942292SN/A} 8952292SN/A 8964192Sktlim@umich.edutemplate <class Impl> 8975595Sgblack@eecs.umich.eduFault 8986221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 8995702Ssaidi@eecs.umich.edu{ 9005702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9015702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 9025702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 9035702Ssaidi@eecs.umich.edu 9045702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 9055702Ssaidi@eecs.umich.edu 9065702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9075702Ssaidi@eecs.umich.edu#endif 9085702Ssaidi@eecs.umich.edu return NoFault; 9095702Ssaidi@eecs.umich.edu} 9105702Ssaidi@eecs.umich.edu 9115702Ssaidi@eecs.umich.edutemplate <class Impl> 9125702Ssaidi@eecs.umich.edubool 9136221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 9145702Ssaidi@eecs.umich.edu{ 9155702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9165702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 9175702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 9185702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 9195702Ssaidi@eecs.umich.edu 9205702Ssaidi@eecs.umich.edu switch (palFunc) { 9215702Ssaidi@eecs.umich.edu case PAL::halt: 9225702Ssaidi@eecs.umich.edu halt(); 9235702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 9245702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 9255702Ssaidi@eecs.umich.edu break; 9265702Ssaidi@eecs.umich.edu 9275702Ssaidi@eecs.umich.edu case PAL::bpt: 9285702Ssaidi@eecs.umich.edu case PAL::bugchk: 9295702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 9305702Ssaidi@eecs.umich.edu return false; 9315702Ssaidi@eecs.umich.edu break; 9325702Ssaidi@eecs.umich.edu } 9335702Ssaidi@eecs.umich.edu#endif 9345702Ssaidi@eecs.umich.edu return true; 9355702Ssaidi@eecs.umich.edu} 9365702Ssaidi@eecs.umich.edu 9375702Ssaidi@eecs.umich.edutemplate <class Impl> 9385702Ssaidi@eecs.umich.eduFault 9395595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 9405595Sgblack@eecs.umich.edu{ 9415595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 94211150Smitch.hayenga@arm.com return this->interrupts[0]->getInterrupt(this->threadContexts[0]); 9435595Sgblack@eecs.umich.edu} 9445595Sgblack@eecs.umich.edu 9455595Sgblack@eecs.umich.edutemplate <class Impl> 9465595Sgblack@eecs.umich.eduvoid 94710379Sandreas.hansson@arm.comFullO3CPU<Impl>::processInterrupts(const Fault &interrupt) 9485595Sgblack@eecs.umich.edu{ 9495595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 9505595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 9515595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9525595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9535595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9545595Sgblack@eecs.umich.edu 9555595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 95611150Smitch.hayenga@arm.com this->interrupts[0]->updateIntrInfo(this->threadContexts[0]); 9575595Sgblack@eecs.umich.edu 9585595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 95910417Sandreas.hansson@arm.com this->trap(interrupt, 0, nullptr); 9605595Sgblack@eecs.umich.edu} 9615595Sgblack@eecs.umich.edu 9621060SN/Atemplate <class Impl> 9632852Sktlim@umich.eduvoid 96410417Sandreas.hansson@arm.comFullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid, 96510417Sandreas.hansson@arm.com const StaticInstPtr &inst) 9665595Sgblack@eecs.umich.edu{ 9675595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 9687684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 9695595Sgblack@eecs.umich.edu} 9705595Sgblack@eecs.umich.edu 9715595Sgblack@eecs.umich.edutemplate <class Impl> 9725595Sgblack@eecs.umich.eduvoid 9736221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 9745595Sgblack@eecs.umich.edu{ 9755595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 9765595Sgblack@eecs.umich.edu 9775595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 9785595Sgblack@eecs.umich.edu 9795595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 9805595Sgblack@eecs.umich.edu // instruction. 9815595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 9825595Sgblack@eecs.umich.edu 9835595Sgblack@eecs.umich.edu // Execute the actual syscall. 9845595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 9855595Sgblack@eecs.umich.edu 9865595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 9875595Sgblack@eecs.umich.edu // incrementing it. 9885595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 9895595Sgblack@eecs.umich.edu} 9905595Sgblack@eecs.umich.edu 9915595Sgblack@eecs.umich.edutemplate <class Impl> 9925595Sgblack@eecs.umich.eduvoid 99310905Sandreas.sandberg@arm.comFullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const 9942864Sktlim@umich.edu{ 99510905Sandreas.sandberg@arm.com thread[tid]->serialize(cp); 9962864Sktlim@umich.edu} 9972864Sktlim@umich.edu 9982864Sktlim@umich.edutemplate <class Impl> 9992864Sktlim@umich.eduvoid 100010905Sandreas.sandberg@arm.comFullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid) 10012864Sktlim@umich.edu{ 100210905Sandreas.sandberg@arm.com thread[tid]->unserialize(cp); 10032864Sktlim@umich.edu} 10042864Sktlim@umich.edu 10052864Sktlim@umich.edutemplate <class Impl> 100610913Sandreas.sandberg@arm.comDrainState 100710913Sandreas.sandberg@arm.comFullO3CPU<Impl>::drain() 10081060SN/A{ 10099444SAndreas.Sandberg@ARM.com // If the CPU isn't doing anything, then return immediately. 101010913Sandreas.sandberg@arm.com if (switchedOut()) 101110913Sandreas.sandberg@arm.com return DrainState::Drained; 10123512Sktlim@umich.edu 10139444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Draining...\n"); 10143512Sktlim@umich.edu 10159444SAndreas.Sandberg@ARM.com // We only need to signal a drain to the commit stage as this 10169444SAndreas.Sandberg@ARM.com // initiates squashing controls the draining. Once the commit 10179444SAndreas.Sandberg@ARM.com // stage commits an instruction where it is safe to stop, it'll 10189444SAndreas.Sandberg@ARM.com // squash the rest of the instructions in the pipeline and force 10199444SAndreas.Sandberg@ARM.com // the fetch stage to stall. The pipeline will be drained once all 10209444SAndreas.Sandberg@ARM.com // in-flight instructions have retired. 10212843Sktlim@umich.edu commit.drain(); 10222325SN/A 10232325SN/A // Wake the CPU and record activity so everything can drain out if 10242863Sktlim@umich.edu // the CPU was not able to immediately drain. 10259444SAndreas.Sandberg@ARM.com if (!isDrained()) { 10262863Sktlim@umich.edu wakeCPU(); 10272863Sktlim@umich.edu activityRec.activity(); 10282852Sktlim@umich.edu 10299152Satgutier@umich.edu DPRINTF(Drain, "CPU not drained\n"); 10309152Satgutier@umich.edu 103110913Sandreas.sandberg@arm.com return DrainState::Draining; 10322863Sktlim@umich.edu } else { 10339444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU is already drained\n"); 10349444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 10359444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 10369444SAndreas.Sandberg@ARM.com 10379444SAndreas.Sandberg@ARM.com // Flush out any old data from the time buffers. In 10389444SAndreas.Sandberg@ARM.com // particular, there might be some data in flight from the 10399444SAndreas.Sandberg@ARM.com // fetch stage that isn't visible in any of the CPU buffers we 10409444SAndreas.Sandberg@ARM.com // test in isDrained(). 10419444SAndreas.Sandberg@ARM.com for (int i = 0; i < timeBuffer.getSize(); ++i) { 10429444SAndreas.Sandberg@ARM.com timeBuffer.advance(); 10439444SAndreas.Sandberg@ARM.com fetchQueue.advance(); 10449444SAndreas.Sandberg@ARM.com decodeQueue.advance(); 10459444SAndreas.Sandberg@ARM.com renameQueue.advance(); 10469444SAndreas.Sandberg@ARM.com iewQueue.advance(); 10479444SAndreas.Sandberg@ARM.com } 10489444SAndreas.Sandberg@ARM.com 10499444SAndreas.Sandberg@ARM.com drainSanityCheck(); 105010913Sandreas.sandberg@arm.com return DrainState::Drained; 10512863Sktlim@umich.edu } 10522316SN/A} 10532310SN/A 10542316SN/Atemplate <class Impl> 10559444SAndreas.Sandberg@ARM.combool 10569444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::tryDrain() 10579444SAndreas.Sandberg@ARM.com{ 105810913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining || !isDrained()) 10599444SAndreas.Sandberg@ARM.com return false; 10609444SAndreas.Sandberg@ARM.com 10619444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 10629444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 10639444SAndreas.Sandberg@ARM.com 10649444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 106510913Sandreas.sandberg@arm.com signalDrainDone(); 10669444SAndreas.Sandberg@ARM.com 10679444SAndreas.Sandberg@ARM.com return true; 10689444SAndreas.Sandberg@ARM.com} 10699444SAndreas.Sandberg@ARM.com 10709444SAndreas.Sandberg@ARM.comtemplate <class Impl> 10719444SAndreas.Sandberg@ARM.comvoid 10729444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::drainSanityCheck() const 10739444SAndreas.Sandberg@ARM.com{ 10749444SAndreas.Sandberg@ARM.com assert(isDrained()); 10759444SAndreas.Sandberg@ARM.com fetch.drainSanityCheck(); 10769444SAndreas.Sandberg@ARM.com decode.drainSanityCheck(); 10779444SAndreas.Sandberg@ARM.com rename.drainSanityCheck(); 10789444SAndreas.Sandberg@ARM.com iew.drainSanityCheck(); 10799444SAndreas.Sandberg@ARM.com commit.drainSanityCheck(); 10809444SAndreas.Sandberg@ARM.com} 10819444SAndreas.Sandberg@ARM.com 10829444SAndreas.Sandberg@ARM.comtemplate <class Impl> 10839444SAndreas.Sandberg@ARM.combool 10849444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::isDrained() const 10859444SAndreas.Sandberg@ARM.com{ 10869444SAndreas.Sandberg@ARM.com bool drained(true); 10879444SAndreas.Sandberg@ARM.com 10889444SAndreas.Sandberg@ARM.com if (!instList.empty() || !removeList.empty()) { 10899444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Main CPU structures not drained.\n"); 10909444SAndreas.Sandberg@ARM.com drained = false; 10919444SAndreas.Sandberg@ARM.com } 10929444SAndreas.Sandberg@ARM.com 10939444SAndreas.Sandberg@ARM.com if (!fetch.isDrained()) { 10949444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Fetch not drained.\n"); 10959444SAndreas.Sandberg@ARM.com drained = false; 10969444SAndreas.Sandberg@ARM.com } 10979444SAndreas.Sandberg@ARM.com 10989444SAndreas.Sandberg@ARM.com if (!decode.isDrained()) { 10999444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Decode not drained.\n"); 11009444SAndreas.Sandberg@ARM.com drained = false; 11019444SAndreas.Sandberg@ARM.com } 11029444SAndreas.Sandberg@ARM.com 11039444SAndreas.Sandberg@ARM.com if (!rename.isDrained()) { 11049444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Rename not drained.\n"); 11059444SAndreas.Sandberg@ARM.com drained = false; 11069444SAndreas.Sandberg@ARM.com } 11079444SAndreas.Sandberg@ARM.com 11089444SAndreas.Sandberg@ARM.com if (!iew.isDrained()) { 11099444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "IEW not drained.\n"); 11109444SAndreas.Sandberg@ARM.com drained = false; 11119444SAndreas.Sandberg@ARM.com } 11129444SAndreas.Sandberg@ARM.com 11139444SAndreas.Sandberg@ARM.com if (!commit.isDrained()) { 11149444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Commit not drained.\n"); 11159444SAndreas.Sandberg@ARM.com drained = false; 11169444SAndreas.Sandberg@ARM.com } 11179444SAndreas.Sandberg@ARM.com 11189444SAndreas.Sandberg@ARM.com return drained; 11199444SAndreas.Sandberg@ARM.com} 11209444SAndreas.Sandberg@ARM.com 11219444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11229444SAndreas.Sandberg@ARM.comvoid 11239444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::commitDrained(ThreadID tid) 11249444SAndreas.Sandberg@ARM.com{ 11259444SAndreas.Sandberg@ARM.com fetch.drainStall(tid); 11269444SAndreas.Sandberg@ARM.com} 11279444SAndreas.Sandberg@ARM.com 11289444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11292316SN/Avoid 11309342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drainResume() 11312316SN/A{ 11329444SAndreas.Sandberg@ARM.com if (switchedOut()) 11339444SAndreas.Sandberg@ARM.com return; 11342316SN/A 11359444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Resuming...\n"); 11369523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 11373319Shsul@eecs.umich.edu 11389444SAndreas.Sandberg@ARM.com fetch.drainResume(); 11399444SAndreas.Sandberg@ARM.com commit.drainResume(); 11402316SN/A 11419444SAndreas.Sandberg@ARM.com _status = Idle; 11429444SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); i++) { 11439444SAndreas.Sandberg@ARM.com if (thread[i]->status() == ThreadContext::Active) { 11449444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Activating thread: %i\n", i); 11459444SAndreas.Sandberg@ARM.com activateThread(i); 11469444SAndreas.Sandberg@ARM.com _status = Running; 11472863Sktlim@umich.edu } 11482310SN/A } 11499444SAndreas.Sandberg@ARM.com 11509444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 11519444SAndreas.Sandberg@ARM.com if (_status == Running) 11529444SAndreas.Sandberg@ARM.com schedule(tickEvent, nextCycle()); 11532843Sktlim@umich.edu} 11542843Sktlim@umich.edu 11552843Sktlim@umich.edutemplate <class Impl> 11562843Sktlim@umich.eduvoid 11572843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11582843Sktlim@umich.edu{ 11599444SAndreas.Sandberg@ARM.com DPRINTF(O3CPU, "Switching out\n"); 11609429SAndreas.Sandberg@ARM.com BaseCPU::switchOut(); 11619429SAndreas.Sandberg@ARM.com 11629444SAndreas.Sandberg@ARM.com activityRec.reset(); 11632843Sktlim@umich.edu 11642843Sktlim@umich.edu _status = SwitchedOut; 11658887Sgeoffrey.blake@arm.com 11662843Sktlim@umich.edu if (checker) 11672843Sktlim@umich.edu checker->switchOut(); 11681060SN/A} 11691060SN/A 11701060SN/Atemplate <class Impl> 11711060SN/Avoid 11721755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 11731060SN/A{ 11748737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 11751060SN/A 11762307SN/A fetch.takeOverFrom(); 11772307SN/A decode.takeOverFrom(); 11782307SN/A rename.takeOverFrom(); 11792307SN/A iew.takeOverFrom(); 11802307SN/A commit.takeOverFrom(); 11812307SN/A 11829444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 11831060SN/A 11849152Satgutier@umich.edu FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 11859152Satgutier@umich.edu if (oldO3CPU) 11869152Satgutier@umich.edu globalSeqNum = oldO3CPU->globalSeqNum; 11879152Satgutier@umich.edu 11889179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 11899444SAndreas.Sandberg@ARM.com _status = Idle; 11901060SN/A} 11911060SN/A 11921060SN/Atemplate <class Impl> 11939523SAndreas.Sandberg@ARM.comvoid 11949523SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::verifyMemoryMode() const 11959523SAndreas.Sandberg@ARM.com{ 11969524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 11979523SAndreas.Sandberg@ARM.com fatal("The O3 CPU requires the memory system to be in " 11989523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 11999523SAndreas.Sandberg@ARM.com } 12009523SAndreas.Sandberg@ARM.com} 12019523SAndreas.Sandberg@ARM.com 12029523SAndreas.Sandberg@ARM.comtemplate <class Impl> 12035595Sgblack@eecs.umich.eduTheISA::MiscReg 120410698Sandreas.hansson@arm.comFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const 12055595Sgblack@eecs.umich.edu{ 12069384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscRegNoEffect(misc_reg); 12075595Sgblack@eecs.umich.edu} 12085595Sgblack@eecs.umich.edu 12095595Sgblack@eecs.umich.edutemplate <class Impl> 12105595Sgblack@eecs.umich.eduTheISA::MiscReg 12116221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 12125595Sgblack@eecs.umich.edu{ 12137897Shestness@cs.utexas.edu miscRegfileReads++; 12149384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 12155595Sgblack@eecs.umich.edu} 12165595Sgblack@eecs.umich.edu 12175595Sgblack@eecs.umich.edutemplate <class Impl> 12185595Sgblack@eecs.umich.eduvoid 12195595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 12206221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12215595Sgblack@eecs.umich.edu{ 12229384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 12235595Sgblack@eecs.umich.edu} 12245595Sgblack@eecs.umich.edu 12255595Sgblack@eecs.umich.edutemplate <class Impl> 12265595Sgblack@eecs.umich.eduvoid 12275595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 12286221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12295595Sgblack@eecs.umich.edu{ 12307897Shestness@cs.utexas.edu miscRegfileWrites++; 12319384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 12325595Sgblack@eecs.umich.edu} 12335595Sgblack@eecs.umich.edu 12345595Sgblack@eecs.umich.edutemplate <class Impl> 12351060SN/Auint64_t 12361755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 12371060SN/A{ 12387897Shestness@cs.utexas.edu intRegfileReads++; 12391060SN/A return regFile.readIntReg(reg_idx); 12401060SN/A} 12411060SN/A 12421060SN/Atemplate <class Impl> 12432455SN/AFloatReg 12442455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 12451060SN/A{ 12467897Shestness@cs.utexas.edu fpRegfileReads++; 12472455SN/A return regFile.readFloatReg(reg_idx); 12481060SN/A} 12491060SN/A 12501060SN/Atemplate <class Impl> 12512455SN/AFloatRegBits 12522455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 12532455SN/A{ 12547897Shestness@cs.utexas.edu fpRegfileReads++; 12552455SN/A return regFile.readFloatRegBits(reg_idx); 12561060SN/A} 12571060SN/A 12581060SN/Atemplate <class Impl> 12599920Syasuko.eckert@amd.comCCReg 12609920Syasuko.eckert@amd.comFullO3CPU<Impl>::readCCReg(int reg_idx) 12619920Syasuko.eckert@amd.com{ 12629920Syasuko.eckert@amd.com ccRegfileReads++; 12639920Syasuko.eckert@amd.com return regFile.readCCReg(reg_idx); 12649920Syasuko.eckert@amd.com} 12659920Syasuko.eckert@amd.com 12669920Syasuko.eckert@amd.comtemplate <class Impl> 12671060SN/Avoid 12681755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 12691060SN/A{ 12707897Shestness@cs.utexas.edu intRegfileWrites++; 12711060SN/A regFile.setIntReg(reg_idx, val); 12721060SN/A} 12731060SN/A 12741060SN/Atemplate <class Impl> 12751060SN/Avoid 12762455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 12771060SN/A{ 12787897Shestness@cs.utexas.edu fpRegfileWrites++; 12792455SN/A regFile.setFloatReg(reg_idx, val); 12801060SN/A} 12811060SN/A 12821060SN/Atemplate <class Impl> 12831060SN/Avoid 12842455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 12852455SN/A{ 12867897Shestness@cs.utexas.edu fpRegfileWrites++; 12872455SN/A regFile.setFloatRegBits(reg_idx, val); 12881060SN/A} 12891060SN/A 12901060SN/Atemplate <class Impl> 12919920Syasuko.eckert@amd.comvoid 12929920Syasuko.eckert@amd.comFullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val) 12939920Syasuko.eckert@amd.com{ 12949920Syasuko.eckert@amd.com ccRegfileWrites++; 12959920Syasuko.eckert@amd.com regFile.setCCReg(reg_idx, val); 12969920Syasuko.eckert@amd.com} 12979920Syasuko.eckert@amd.com 12989920Syasuko.eckert@amd.comtemplate <class Impl> 12991060SN/Auint64_t 13006221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 13011060SN/A{ 13027897Shestness@cs.utexas.edu intRegfileReads++; 13039919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 13042292SN/A 13052292SN/A return regFile.readIntReg(phys_reg); 13062292SN/A} 13072292SN/A 13082292SN/Atemplate <class Impl> 13092292SN/Afloat 13106314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 13112292SN/A{ 13127897Shestness@cs.utexas.edu fpRegfileReads++; 13139919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 13142292SN/A 13152669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 13162292SN/A} 13172292SN/A 13182292SN/Atemplate <class Impl> 13192292SN/Auint64_t 13206221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 13212292SN/A{ 13227897Shestness@cs.utexas.edu fpRegfileReads++; 13239919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 13242292SN/A 13252669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13261060SN/A} 13271060SN/A 13281060SN/Atemplate <class Impl> 13299920Syasuko.eckert@amd.comCCReg 13309920Syasuko.eckert@amd.comFullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid) 13319920Syasuko.eckert@amd.com{ 13329920Syasuko.eckert@amd.com ccRegfileReads++; 13339920Syasuko.eckert@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 13349920Syasuko.eckert@amd.com 13359920Syasuko.eckert@amd.com return regFile.readCCReg(phys_reg); 13369920Syasuko.eckert@amd.com} 13379920Syasuko.eckert@amd.com 13389920Syasuko.eckert@amd.comtemplate <class Impl> 13391060SN/Avoid 13406221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 13411060SN/A{ 13427897Shestness@cs.utexas.edu intRegfileWrites++; 13439919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 13442292SN/A 13452292SN/A regFile.setIntReg(phys_reg, val); 13461060SN/A} 13471060SN/A 13481060SN/Atemplate <class Impl> 13491060SN/Avoid 13506314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 13511060SN/A{ 13527897Shestness@cs.utexas.edu fpRegfileWrites++; 13539919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 13542292SN/A 13552669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 13561060SN/A} 13571060SN/A 13581060SN/Atemplate <class Impl> 13591060SN/Avoid 13606221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 13611060SN/A{ 13627897Shestness@cs.utexas.edu fpRegfileWrites++; 13639919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 13641060SN/A 13652669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 13662292SN/A} 13672292SN/A 13682292SN/Atemplate <class Impl> 13699920Syasuko.eckert@amd.comvoid 13709920Syasuko.eckert@amd.comFullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid) 13719920Syasuko.eckert@amd.com{ 13729920Syasuko.eckert@amd.com ccRegfileWrites++; 13739920Syasuko.eckert@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 13749920Syasuko.eckert@amd.com 13759920Syasuko.eckert@amd.com regFile.setCCReg(phys_reg, val); 13769920Syasuko.eckert@amd.com} 13779920Syasuko.eckert@amd.com 13789920Syasuko.eckert@amd.comtemplate <class Impl> 13797720Sgblack@eecs.umich.eduTheISA::PCState 13807720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 13812292SN/A{ 13827720Sgblack@eecs.umich.edu return commit.pcState(tid); 13831060SN/A} 13841060SN/A 13851060SN/Atemplate <class Impl> 13861060SN/Avoid 13877720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 13881060SN/A{ 13897720Sgblack@eecs.umich.edu commit.pcState(val, tid); 13902292SN/A} 13911060SN/A 13922292SN/Atemplate <class Impl> 13937720Sgblack@eecs.umich.eduAddr 13947720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 13954636Sgblack@eecs.umich.edu{ 13967720Sgblack@eecs.umich.edu return commit.instAddr(tid); 13974636Sgblack@eecs.umich.edu} 13984636Sgblack@eecs.umich.edu 13994636Sgblack@eecs.umich.edutemplate <class Impl> 14007720Sgblack@eecs.umich.eduAddr 14017720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 14024636Sgblack@eecs.umich.edu{ 14037720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 14044636Sgblack@eecs.umich.edu} 14054636Sgblack@eecs.umich.edu 14064636Sgblack@eecs.umich.edutemplate <class Impl> 14077720Sgblack@eecs.umich.eduMicroPC 14087720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 14092292SN/A{ 14107720Sgblack@eecs.umich.edu return commit.microPC(tid); 14114636Sgblack@eecs.umich.edu} 14124636Sgblack@eecs.umich.edu 14134636Sgblack@eecs.umich.edutemplate <class Impl> 14145595Sgblack@eecs.umich.eduvoid 14156221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 14165595Sgblack@eecs.umich.edu{ 14179382SAli.Saidi@ARM.com this->thread[tid]->noSquashFromTC = true; 14185595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 14195595Sgblack@eecs.umich.edu} 14205595Sgblack@eecs.umich.edu 14215595Sgblack@eecs.umich.edutemplate <class Impl> 14222292SN/Atypename FullO3CPU<Impl>::ListIt 14232292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14242292SN/A{ 14252292SN/A instList.push_back(inst); 14261060SN/A 14272292SN/A return --(instList.end()); 14282292SN/A} 14291060SN/A 14302292SN/Atemplate <class Impl> 14312292SN/Avoid 14328834Satgutier@umich.eduFullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 14332292SN/A{ 14342292SN/A // Keep an instruction count. 14358834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 14368834Satgutier@umich.edu thread[tid]->numInst++; 14378834Satgutier@umich.edu thread[tid]->numInsts++; 14388834Satgutier@umich.edu committedInsts[tid]++; 143910774Snikos.nikoleris@gmail.com system->totalNumInsts++; 144010774Snikos.nikoleris@gmail.com 144110774Snikos.nikoleris@gmail.com // Check for instruction-count-based events. 144210774Snikos.nikoleris@gmail.com comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 144310774Snikos.nikoleris@gmail.com system->instEventQueue.serviceEvents(system->totalNumInsts); 14448834Satgutier@umich.edu } 14458834Satgutier@umich.edu thread[tid]->numOp++; 14468834Satgutier@umich.edu thread[tid]->numOps++; 14478834Satgutier@umich.edu committedOps[tid]++; 14488834Satgutier@umich.edu 144910464SAndreas.Sandberg@ARM.com probeInstCommit(inst->staticInst); 14502292SN/A} 14512292SN/A 14522292SN/Atemplate <class Impl> 14532292SN/Avoid 14541755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 14551060SN/A{ 14567720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 14572292SN/A "[sn:%lli]\n", 14587720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 14591060SN/A 14602292SN/A removeInstsThisCycle = true; 14611060SN/A 14621060SN/A // Remove the front instruction. 14632292SN/A removeList.push(inst->getInstListIt()); 14641060SN/A} 14651060SN/A 14661060SN/Atemplate <class Impl> 14671060SN/Avoid 14686221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 14691060SN/A{ 14702733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 14712292SN/A " list.\n", tid); 14721060SN/A 14732292SN/A ListIt end_it; 14741060SN/A 14752292SN/A bool rob_empty = false; 14762292SN/A 14772292SN/A if (instList.empty()) { 14782292SN/A return; 147910164Ssleimanf@umich.edu } else if (rob.isEmpty(tid)) { 14802733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 14812292SN/A end_it = instList.begin(); 14822292SN/A rob_empty = true; 14832292SN/A } else { 14842292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 14852733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 14862292SN/A } 14872292SN/A 14882292SN/A removeInstsThisCycle = true; 14892292SN/A 14902292SN/A ListIt inst_it = instList.end(); 14912292SN/A 14922292SN/A inst_it--; 14932292SN/A 14942292SN/A // Walk through the instruction list, removing any instructions 14952292SN/A // that were inserted after the given instruction iterator, end_it. 14962292SN/A while (inst_it != end_it) { 14972292SN/A assert(!instList.empty()); 14982292SN/A 14992292SN/A squashInstIt(inst_it, tid); 15002292SN/A 15012292SN/A inst_it--; 15022292SN/A } 15032292SN/A 15042292SN/A // If the ROB was empty, then we actually need to remove the first 15052292SN/A // instruction as well. 15062292SN/A if (rob_empty) { 15072292SN/A squashInstIt(inst_it, tid); 15082292SN/A } 15091060SN/A} 15101060SN/A 15111060SN/Atemplate <class Impl> 15121060SN/Avoid 15136221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 15141062SN/A{ 15152292SN/A assert(!instList.empty()); 15162292SN/A 15172292SN/A removeInstsThisCycle = true; 15182292SN/A 15192292SN/A ListIt inst_iter = instList.end(); 15202292SN/A 15212292SN/A inst_iter--; 15222292SN/A 15232733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 15242292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15252292SN/A tid, seq_num, (*inst_iter)->seqNum); 15261062SN/A 15272292SN/A while ((*inst_iter)->seqNum > seq_num) { 15281062SN/A 15292292SN/A bool break_loop = (inst_iter == instList.begin()); 15301062SN/A 15312292SN/A squashInstIt(inst_iter, tid); 15321062SN/A 15332292SN/A inst_iter--; 15341062SN/A 15352292SN/A if (break_loop) 15362292SN/A break; 15372292SN/A } 15382292SN/A} 15392292SN/A 15402292SN/Atemplate <class Impl> 15412292SN/Ainline void 15426221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 15432292SN/A{ 15442292SN/A if ((*instIt)->threadNumber == tid) { 15452733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 15467720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15472292SN/A (*instIt)->threadNumber, 15482292SN/A (*instIt)->seqNum, 15497720Sgblack@eecs.umich.edu (*instIt)->pcState()); 15501062SN/A 15511062SN/A // Mark it as squashed. 15522292SN/A (*instIt)->setSquashed(); 15532292SN/A 15542325SN/A // @todo: Formulate a consistent method for deleting 15552325SN/A // instructions from the instruction list 15562292SN/A // Remove the instruction from the list. 15572292SN/A removeList.push(instIt); 15582292SN/A } 15592292SN/A} 15602292SN/A 15612292SN/Atemplate <class Impl> 15622292SN/Avoid 15632292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 15642292SN/A{ 15652292SN/A while (!removeList.empty()) { 15662733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 15677720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15682292SN/A (*removeList.front())->threadNumber, 15692292SN/A (*removeList.front())->seqNum, 15707720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 15712292SN/A 15722292SN/A instList.erase(removeList.front()); 15732292SN/A 15742292SN/A removeList.pop(); 15751062SN/A } 15761062SN/A 15772292SN/A removeInstsThisCycle = false; 15781062SN/A} 15792325SN/A/* 15801062SN/Atemplate <class Impl> 15811062SN/Avoid 15821755SN/AFullO3CPU<Impl>::removeAllInsts() 15831060SN/A{ 15841060SN/A instList.clear(); 15851060SN/A} 15862325SN/A*/ 15871060SN/Atemplate <class Impl> 15881060SN/Avoid 15891755SN/AFullO3CPU<Impl>::dumpInsts() 15901060SN/A{ 15911060SN/A int num = 0; 15921060SN/A 15932292SN/A ListIt inst_list_it = instList.begin(); 15942292SN/A 15952292SN/A cprintf("Dumping Instruction List\n"); 15962292SN/A 15972292SN/A while (inst_list_it != instList.end()) { 15982292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 15992292SN/A "Squashed:%i\n\n", 16007720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 16012292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16022292SN/A (*inst_list_it)->isSquashed()); 16031060SN/A inst_list_it++; 16041060SN/A ++num; 16051060SN/A } 16061060SN/A} 16072325SN/A/* 16081060SN/Atemplate <class Impl> 16091060SN/Avoid 16101755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 16111060SN/A{ 16121060SN/A iew.wakeDependents(inst); 16131060SN/A} 16142325SN/A*/ 16152292SN/Atemplate <class Impl> 16162292SN/Avoid 16172292SN/AFullO3CPU<Impl>::wakeCPU() 16182292SN/A{ 16192325SN/A if (activityRec.active() || tickEvent.scheduled()) { 16202325SN/A DPRINTF(Activity, "CPU already running.\n"); 16212292SN/A return; 16222292SN/A } 16232292SN/A 16242325SN/A DPRINTF(Activity, "Waking up CPU\n"); 16252325SN/A 16269180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 16279180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 162810464SAndreas.Sandberg@ARM.com if (cycles > 1) { 16299179Sandreas.hansson@arm.com --cycles; 163010464SAndreas.Sandberg@ARM.com idleCycles += cycles; 163110464SAndreas.Sandberg@ARM.com numCycles += cycles; 163210464SAndreas.Sandberg@ARM.com ppCycles->notify(cycles); 163310464SAndreas.Sandberg@ARM.com } 16342292SN/A 16359648Sdam.sunwoo@arm.com schedule(tickEvent, clockEdge()); 16362292SN/A} 16372292SN/A 16385807Snate@binkert.orgtemplate <class Impl> 16395807Snate@binkert.orgvoid 164011151Smitch.hayenga@arm.comFullO3CPU<Impl>::wakeup(ThreadID tid) 16415807Snate@binkert.org{ 164211151Smitch.hayenga@arm.com if (this->thread[tid]->status() != ThreadContext::Suspended) 16435807Snate@binkert.org return; 16445807Snate@binkert.org 16455807Snate@binkert.org this->wakeCPU(); 16465807Snate@binkert.org 16475807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 164811151Smitch.hayenga@arm.com this->threadContexts[tid]->activate(); 16495807Snate@binkert.org} 16505807Snate@binkert.org 16512292SN/Atemplate <class Impl> 16526221Snate@binkert.orgThreadID 16532292SN/AFullO3CPU<Impl>::getFreeTid() 16542292SN/A{ 16556221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 16566221Snate@binkert.org if (!tids[tid]) { 16576221Snate@binkert.org tids[tid] = true; 16586221Snate@binkert.org return tid; 16592292SN/A } 16602292SN/A } 16612292SN/A 16626221Snate@binkert.org return InvalidThreadID; 16632292SN/A} 16642292SN/A 16652292SN/Atemplate <class Impl> 16662292SN/Avoid 16672292SN/AFullO3CPU<Impl>::updateThreadPriority() 16682292SN/A{ 16696221Snate@binkert.org if (activeThreads.size() > 1) { 16702292SN/A //DEFAULT TO ROUND ROBIN SCHEME 16712292SN/A //e.g. Move highest priority to end of thread list 16726221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 16732292SN/A 16742292SN/A unsigned high_thread = *list_begin; 16752292SN/A 16762292SN/A activeThreads.erase(list_begin); 16772292SN/A 16782292SN/A activeThreads.push_back(high_thread); 16792292SN/A } 16802292SN/A} 16811060SN/A 16821755SN/A// Forward declaration of FullO3CPU. 16832818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1684