cpu.cc revision 10407
11689SN/A/* 210331Smitch.hayenga@arm.com * Copyright (c) 2011-2012, 2014 ARM Limited 39916Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 152325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 167897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432756Sksewell@umich.edu * Korey Sewell 447897Shestness@cs.utexas.edu * Rick Strong 451689SN/A */ 461689SN/A 478779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 498887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 508887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 518229Snate@binkert.org#include "cpu/o3/cpu.hh" 528229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 538229Snate@binkert.org#include "cpu/o3/thread_context.hh" 544762Snate@binkert.org#include "cpu/activity.hh" 558779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 564762Snate@binkert.org#include "cpu/simple_thread.hh" 574762Snate@binkert.org#include "cpu/thread_context.hh" 588232Snate@binkert.org#include "debug/Activity.hh" 599152Satgutier@umich.edu#include "debug/Drain.hh" 608232Snate@binkert.org#include "debug/O3CPU.hh" 618232Snate@binkert.org#include "debug/Quiesce.hh" 624762Snate@binkert.org#include "enums/MemoryMode.hh" 634762Snate@binkert.org#include "sim/core.hh" 648793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 658779Sgblack@eecs.umich.edu#include "sim/process.hh" 664762Snate@binkert.org#include "sim/stat_control.hh" 678460SAli.Saidi@ARM.com#include "sim/system.hh" 684762Snate@binkert.org 695702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 705702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 718232Snate@binkert.org#include "debug/Activity.hh" 725702Ssaidi@eecs.umich.edu#endif 735702Ssaidi@eecs.umich.edu 748737Skoansin.tan@gmail.comstruct BaseCPUParams; 755529Snate@binkert.org 762669Sktlim@umich.eduusing namespace TheISA; 776221Snate@binkert.orgusing namespace std; 781060SN/A 795529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 805712Shsul@eecs.umich.edu : BaseCPU(params) 811060SN/A{ 821060SN/A} 831060SN/A 842292SN/Avoid 852733Sktlim@umich.eduBaseO3CPU::regStats() 862292SN/A{ 872292SN/A BaseCPU::regStats(); 882292SN/A} 892292SN/A 908707Sandreas.hansson@arm.comtemplate<class Impl> 918707Sandreas.hansson@arm.combool 928975Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 938707Sandreas.hansson@arm.com{ 948707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 958948Sandreas.hansson@arm.com // We shouldn't ever get a block in ownership state 968948Sandreas.hansson@arm.com assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 978948Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 988707Sandreas.hansson@arm.com 998707Sandreas.hansson@arm.com return true; 1008707Sandreas.hansson@arm.com} 1018707Sandreas.hansson@arm.com 1028707Sandreas.hansson@arm.comtemplate<class Impl> 1038707Sandreas.hansson@arm.comvoid 1048707Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvRetry() 1058707Sandreas.hansson@arm.com{ 1068707Sandreas.hansson@arm.com fetch->recvRetry(); 1078707Sandreas.hansson@arm.com} 1088707Sandreas.hansson@arm.com 1098707Sandreas.hansson@arm.comtemplate <class Impl> 1108707Sandreas.hansson@arm.combool 1118975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 1128707Sandreas.hansson@arm.com{ 1138975Sandreas.hansson@arm.com return lsq->recvTimingResp(pkt); 1148707Sandreas.hansson@arm.com} 1158707Sandreas.hansson@arm.com 1168707Sandreas.hansson@arm.comtemplate <class Impl> 1178975Sandreas.hansson@arm.comvoid 1188975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 1198948Sandreas.hansson@arm.com{ 1208975Sandreas.hansson@arm.com lsq->recvTimingSnoopReq(pkt); 1218948Sandreas.hansson@arm.com} 1228948Sandreas.hansson@arm.com 1238948Sandreas.hansson@arm.comtemplate <class Impl> 1248707Sandreas.hansson@arm.comvoid 1258707Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvRetry() 1268707Sandreas.hansson@arm.com{ 1278707Sandreas.hansson@arm.com lsq->recvRetry(); 1288707Sandreas.hansson@arm.com} 1298707Sandreas.hansson@arm.com 1301060SN/Atemplate <class Impl> 1311755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 1325606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 1331060SN/A{ 1341060SN/A} 1351060SN/A 1361060SN/Atemplate <class Impl> 1371060SN/Avoid 1381755SN/AFullO3CPU<Impl>::TickEvent::process() 1391060SN/A{ 1401060SN/A cpu->tick(); 1411060SN/A} 1421060SN/A 1431060SN/Atemplate <class Impl> 1441060SN/Aconst char * 1455336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 1461060SN/A{ 1474873Sstever@eecs.umich.edu return "FullO3CPU tick"; 1481060SN/A} 1491060SN/A 1501060SN/Atemplate <class Impl> 1515595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1522733Sktlim@umich.edu : BaseO3CPU(params), 1533781Sgblack@eecs.umich.edu itb(params->itb), 1543781Sgblack@eecs.umich.edu dtb(params->dtb), 1551060SN/A tickEvent(this), 1565737Scws3k@cs.virginia.edu#ifndef NDEBUG 1575737Scws3k@cs.virginia.edu instcount(0), 1585737Scws3k@cs.virginia.edu#endif 1592292SN/A removeInstsThisCycle(false), 1605595Sgblack@eecs.umich.edu fetch(this, params), 1615595Sgblack@eecs.umich.edu decode(this, params), 1625595Sgblack@eecs.umich.edu rename(this, params), 1635595Sgblack@eecs.umich.edu iew(this, params), 1645595Sgblack@eecs.umich.edu commit(this, params), 1651060SN/A 1669915Ssteve.reinhardt@amd.com regFile(params->numPhysIntRegs, 1679920Syasuko.eckert@amd.com params->numPhysFloatRegs, 1689920Syasuko.eckert@amd.com params->numPhysCCRegs), 1691060SN/A 1709919Ssteve.reinhardt@amd.com freeList(name() + ".freelist", ®File), 1711060SN/A 1729954SFaissal.Sleiman@arm.com rob(this, params), 1731060SN/A 1749916Ssteve.reinhardt@amd.com scoreboard(name() + ".scoreboard", 1759916Ssteve.reinhardt@amd.com regFile.totalNumPhysRegs(), TheISA::NumMiscRegs, 1769916Ssteve.reinhardt@amd.com TheISA::ZeroReg, TheISA::ZeroReg), 1771060SN/A 1789384SAndreas.Sandberg@arm.com isa(numThreads, NULL), 1799384SAndreas.Sandberg@arm.com 1808707Sandreas.hansson@arm.com icachePort(&fetch, this), 1818707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 1828707Sandreas.hansson@arm.com 1832873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1842873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1852873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1862873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1872873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1885804Snate@binkert.org activityRec(name(), NumStages, 1892873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1902873Sktlim@umich.edu params->activity), 1911060SN/A 1921060SN/A globalSeqNum(1), 1932292SN/A system(params->system), 1949444SAndreas.Sandberg@ARM.com drainManager(NULL), 1959180Sandreas.hansson@arm.com lastRunningCycle(curCycle()) 1961060SN/A{ 1979433SAndreas.Sandberg@ARM.com if (!params->switched_out) { 1983221Sktlim@umich.edu _status = Running; 1993221Sktlim@umich.edu } else { 2009152Satgutier@umich.edu _status = SwitchedOut; 2013221Sktlim@umich.edu } 2021681SN/A 2032794Sktlim@umich.edu if (params->checker) { 2042316SN/A BaseCPU *temp_checker = params->checker; 2058733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 2068707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2072316SN/A checker->setSystem(params->system); 2084598Sbinkertn@umich.edu } else { 2094598Sbinkertn@umich.edu checker = NULL; 2104598Sbinkertn@umich.edu } 2112316SN/A 2128793Sgblack@eecs.umich.edu if (!FullSystem) { 2138793Sgblack@eecs.umich.edu thread.resize(numThreads); 2148793Sgblack@eecs.umich.edu tids.resize(numThreads); 2158793Sgblack@eecs.umich.edu } 2161681SN/A 2172325SN/A // The stages also need their CPU pointer setup. However this 2182325SN/A // must be done at the upper level CPU because they have pointers 2192325SN/A // to the upper level CPU, and not this FullO3CPU. 2201060SN/A 2212292SN/A // Set up Pointers to the activeThreads list for each stage 2222292SN/A fetch.setActiveThreads(&activeThreads); 2232292SN/A decode.setActiveThreads(&activeThreads); 2242292SN/A rename.setActiveThreads(&activeThreads); 2252292SN/A iew.setActiveThreads(&activeThreads); 2262292SN/A commit.setActiveThreads(&activeThreads); 2271060SN/A 2281060SN/A // Give each of the stages the time buffer they will use. 2291060SN/A fetch.setTimeBuffer(&timeBuffer); 2301060SN/A decode.setTimeBuffer(&timeBuffer); 2311060SN/A rename.setTimeBuffer(&timeBuffer); 2321060SN/A iew.setTimeBuffer(&timeBuffer); 2331060SN/A commit.setTimeBuffer(&timeBuffer); 2341060SN/A 2351060SN/A // Also setup each of the stages' queues. 2361060SN/A fetch.setFetchQueue(&fetchQueue); 2371060SN/A decode.setFetchQueue(&fetchQueue); 2382292SN/A commit.setFetchQueue(&fetchQueue); 2391060SN/A decode.setDecodeQueue(&decodeQueue); 2401060SN/A rename.setDecodeQueue(&decodeQueue); 2411060SN/A rename.setRenameQueue(&renameQueue); 2421060SN/A iew.setRenameQueue(&renameQueue); 2431060SN/A iew.setIEWQueue(&iewQueue); 2441060SN/A commit.setIEWQueue(&iewQueue); 2451060SN/A commit.setRenameQueue(&renameQueue); 2461060SN/A 2472292SN/A commit.setIEWStage(&iew); 2482292SN/A rename.setIEWStage(&iew); 2492292SN/A rename.setCommitStage(&commit); 2502292SN/A 2518793Sgblack@eecs.umich.edu ThreadID active_threads; 2528793Sgblack@eecs.umich.edu if (FullSystem) { 2538793Sgblack@eecs.umich.edu active_threads = 1; 2548793Sgblack@eecs.umich.edu } else { 2558793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 2562831Sksewell@umich.edu 2578793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 2588793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 2598793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 2608793Sgblack@eecs.umich.edu "or edit your workload size."); 2618793Sgblack@eecs.umich.edu } 2622831Sksewell@umich.edu } 2632292SN/A 2642316SN/A //Make Sure That this a Valid Architeture 2652292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2662292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2679920Syasuko.eckert@amd.com assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs); 2682292SN/A 2692292SN/A rename.setScoreboard(&scoreboard); 2702292SN/A iew.setScoreboard(&scoreboard); 2712292SN/A 2721060SN/A // Setup the rename map for whichever stages need it. 2736221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2749384SAndreas.Sandberg@arm.com isa[tid] = params->isa[tid]; 2759384SAndreas.Sandberg@arm.com 2769919Ssteve.reinhardt@amd.com // Only Alpha has an FP zero register, so for other ISAs we 2779919Ssteve.reinhardt@amd.com // use an invalid FP register index to avoid special treatment 2789919Ssteve.reinhardt@amd.com // of any valid FP reg. 2799919Ssteve.reinhardt@amd.com RegIndex invalidFPReg = TheISA::NumFloatRegs + 1; 2809919Ssteve.reinhardt@amd.com RegIndex fpZeroReg = 2819919Ssteve.reinhardt@amd.com (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg; 2822292SN/A 2839919Ssteve.reinhardt@amd.com commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 2849919Ssteve.reinhardt@amd.com &freeList); 2852292SN/A 2869919Ssteve.reinhardt@amd.com renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 2879919Ssteve.reinhardt@amd.com &freeList); 2882292SN/A } 2892292SN/A 2909919Ssteve.reinhardt@amd.com // Initialize rename map to assign physical registers to the 2919919Ssteve.reinhardt@amd.com // architectural registers for active threads only. 2929919Ssteve.reinhardt@amd.com for (ThreadID tid = 0; tid < active_threads; tid++) { 2939919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) { 2949919Ssteve.reinhardt@amd.com // Note that we can't use the rename() method because we don't 2959919Ssteve.reinhardt@amd.com // want special treatment for the zero register at this point 2969919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = freeList.getIntReg(); 2979919Ssteve.reinhardt@amd.com renameMap[tid].setIntEntry(ridx, phys_reg); 2989919Ssteve.reinhardt@amd.com commitRenameMap[tid].setIntEntry(ridx, phys_reg); 2999919Ssteve.reinhardt@amd.com } 3009919Ssteve.reinhardt@amd.com 3019919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) { 3029919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = freeList.getFloatReg(); 3039919Ssteve.reinhardt@amd.com renameMap[tid].setFloatEntry(ridx, phys_reg); 3049919Ssteve.reinhardt@amd.com commitRenameMap[tid].setFloatEntry(ridx, phys_reg); 3059919Ssteve.reinhardt@amd.com } 3069920Syasuko.eckert@amd.com 3079920Syasuko.eckert@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) { 3089920Syasuko.eckert@amd.com PhysRegIndex phys_reg = freeList.getCCReg(); 3099920Syasuko.eckert@amd.com renameMap[tid].setCCEntry(ridx, phys_reg); 3109920Syasuko.eckert@amd.com commitRenameMap[tid].setCCEntry(ridx, phys_reg); 3119920Syasuko.eckert@amd.com } 3129919Ssteve.reinhardt@amd.com } 3139919Ssteve.reinhardt@amd.com 3142292SN/A rename.setRenameMap(renameMap); 3152292SN/A commit.setRenameMap(commitRenameMap); 3161060SN/A rename.setFreeList(&freeList); 3172292SN/A 3181060SN/A // Setup the ROB for whichever stages need it. 3191060SN/A commit.setROB(&rob); 3202292SN/A 3219158Sandreas.hansson@arm.com lastActivatedCycle = 0; 3226221Snate@binkert.org#if 0 3233093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3246221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3256221Snate@binkert.org globalSeqNum[tid] = 1; 3266221Snate@binkert.org#endif 3273093Sksewell@umich.edu 3285595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3295595Sgblack@eecs.umich.edu 3305595Sgblack@eecs.umich.edu // Setup any thread state. 3315595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3325595Sgblack@eecs.umich.edu 3336221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 3348793Sgblack@eecs.umich.edu if (FullSystem) { 3358793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3368793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3378793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 3388793Sgblack@eecs.umich.edu } else { 3398793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 3408793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3418793Sgblack@eecs.umich.edu tid, this->thread[tid]); 3428793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3438793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3448793Sgblack@eecs.umich.edu tid, params->workload[tid]); 3455595Sgblack@eecs.umich.edu 3468793Sgblack@eecs.umich.edu //usedTids[tid] = true; 3478793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 3488793Sgblack@eecs.umich.edu } else { 3498793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3508793Sgblack@eecs.umich.edu //when scheduling threads to CPU 3518793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3525595Sgblack@eecs.umich.edu 3538793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3548793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3558793Sgblack@eecs.umich.edu tid, dummy_proc); 3568793Sgblack@eecs.umich.edu //usedTids[tid] = false; 3578793Sgblack@eecs.umich.edu } 3585595Sgblack@eecs.umich.edu } 3595595Sgblack@eecs.umich.edu 3605595Sgblack@eecs.umich.edu ThreadContext *tc; 3615595Sgblack@eecs.umich.edu 3625595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3635595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3645595Sgblack@eecs.umich.edu 3655595Sgblack@eecs.umich.edu tc = o3_tc; 3665595Sgblack@eecs.umich.edu 3675595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3685595Sgblack@eecs.umich.edu // CheckerThreadContext. 3695595Sgblack@eecs.umich.edu if (params->checker) { 3705595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3715595Sgblack@eecs.umich.edu o3_tc, this->checker); 3725595Sgblack@eecs.umich.edu } 3735595Sgblack@eecs.umich.edu 3745595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 3755595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 3766221Snate@binkert.org o3_tc->thread = this->thread[tid]; 3775595Sgblack@eecs.umich.edu 3788793Sgblack@eecs.umich.edu if (FullSystem) { 3798793Sgblack@eecs.umich.edu // Setup quiesce event. 3808793Sgblack@eecs.umich.edu this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 3818793Sgblack@eecs.umich.edu } 3825595Sgblack@eecs.umich.edu // Give the thread the TC. 3836221Snate@binkert.org this->thread[tid]->tc = tc; 3845595Sgblack@eecs.umich.edu 3855595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 3865595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 3875595Sgblack@eecs.umich.edu } 3885595Sgblack@eecs.umich.edu 3898876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 3909433SAndreas.Sandberg@ARM.com if (!params->switched_out && !interrupts) { 3918876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 3928876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 3938876Sandreas.hansson@arm.com } 3948876Sandreas.hansson@arm.com 3956221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 3966221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 3971060SN/A} 3981060SN/A 3991060SN/Atemplate <class Impl> 4001755SN/AFullO3CPU<Impl>::~FullO3CPU() 4011060SN/A{ 4021060SN/A} 4031060SN/A 4041060SN/Atemplate <class Impl> 4051060SN/Avoid 40610023Smatt.horsnell@ARM.comFullO3CPU<Impl>::regProbePoints() 40710023Smatt.horsnell@ARM.com{ 40810023Smatt.horsnell@ARM.com ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete"); 40910023Smatt.horsnell@ARM.com ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete"); 41010023Smatt.horsnell@ARM.com fetch.regProbePoints(); 41110023Smatt.horsnell@ARM.com iew.regProbePoints(); 41210023Smatt.horsnell@ARM.com commit.regProbePoints(); 41310023Smatt.horsnell@ARM.com} 41410023Smatt.horsnell@ARM.com 41510023Smatt.horsnell@ARM.comtemplate <class Impl> 41610023Smatt.horsnell@ARM.comvoid 4175595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4181062SN/A{ 4192733Sktlim@umich.edu BaseO3CPU::regStats(); 4202292SN/A 4212733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4222292SN/A timesIdled 4232292SN/A .name(name() + ".timesIdled") 4242292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4252292SN/A " unscheduled itself") 4262292SN/A .prereq(timesIdled); 4272292SN/A 4282292SN/A idleCycles 4292292SN/A .name(name() + ".idleCycles") 4302292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4312292SN/A "to idling") 4322292SN/A .prereq(idleCycles); 4332292SN/A 4348627SAli.Saidi@ARM.com quiesceCycles 4358627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 4368627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 4378627SAli.Saidi@ARM.com "for an interrupt") 4388627SAli.Saidi@ARM.com .prereq(quiesceCycles); 4398627SAli.Saidi@ARM.com 4402292SN/A // Number of Instructions simulated 4412292SN/A // -------------------------------- 4422292SN/A // Should probably be in Base CPU but need templated 4432292SN/A // MaxThreads so put in here instead 4442292SN/A committedInsts 4452292SN/A .init(numThreads) 4462292SN/A .name(name() + ".committedInsts") 44710225Snilay@cs.wisc.edu .desc("Number of Instructions Simulated") 44810225Snilay@cs.wisc.edu .flags(Stats::total); 4492292SN/A 4508834Satgutier@umich.edu committedOps 4518834Satgutier@umich.edu .init(numThreads) 4528834Satgutier@umich.edu .name(name() + ".committedOps") 45310225Snilay@cs.wisc.edu .desc("Number of Ops (including micro ops) Simulated") 45410225Snilay@cs.wisc.edu .flags(Stats::total); 4552292SN/A 4562292SN/A cpi 4572292SN/A .name(name() + ".cpi") 4582292SN/A .desc("CPI: Cycles Per Instruction") 4592292SN/A .precision(6); 4604392Sktlim@umich.edu cpi = numCycles / committedInsts; 4612292SN/A 4622292SN/A totalCpi 4632292SN/A .name(name() + ".cpi_total") 4642292SN/A .desc("CPI: Total CPI of All Threads") 4652292SN/A .precision(6); 46610225Snilay@cs.wisc.edu totalCpi = numCycles / sum(committedInsts); 4672292SN/A 4682292SN/A ipc 4692292SN/A .name(name() + ".ipc") 4702292SN/A .desc("IPC: Instructions Per Cycle") 4712292SN/A .precision(6); 4724392Sktlim@umich.edu ipc = committedInsts / numCycles; 4732292SN/A 4742292SN/A totalIpc 4752292SN/A .name(name() + ".ipc_total") 4762292SN/A .desc("IPC: Total IPC of All Threads") 4772292SN/A .precision(6); 47810225Snilay@cs.wisc.edu totalIpc = sum(committedInsts) / numCycles; 4792292SN/A 4805595Sgblack@eecs.umich.edu this->fetch.regStats(); 4815595Sgblack@eecs.umich.edu this->decode.regStats(); 4825595Sgblack@eecs.umich.edu this->rename.regStats(); 4835595Sgblack@eecs.umich.edu this->iew.regStats(); 4845595Sgblack@eecs.umich.edu this->commit.regStats(); 4857897Shestness@cs.utexas.edu this->rob.regStats(); 4867897Shestness@cs.utexas.edu 4877897Shestness@cs.utexas.edu intRegfileReads 4887897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 4897897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 4907897Shestness@cs.utexas.edu .prereq(intRegfileReads); 4917897Shestness@cs.utexas.edu 4927897Shestness@cs.utexas.edu intRegfileWrites 4937897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 4947897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 4957897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 4967897Shestness@cs.utexas.edu 4977897Shestness@cs.utexas.edu fpRegfileReads 4987897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 4997897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5007897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5017897Shestness@cs.utexas.edu 5027897Shestness@cs.utexas.edu fpRegfileWrites 5037897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5047897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5057897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5067897Shestness@cs.utexas.edu 5079920Syasuko.eckert@amd.com ccRegfileReads 5089920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_reads") 5099920Syasuko.eckert@amd.com .desc("number of cc regfile reads") 5109920Syasuko.eckert@amd.com .prereq(ccRegfileReads); 5119920Syasuko.eckert@amd.com 5129920Syasuko.eckert@amd.com ccRegfileWrites 5139920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_writes") 5149920Syasuko.eckert@amd.com .desc("number of cc regfile writes") 5159920Syasuko.eckert@amd.com .prereq(ccRegfileWrites); 5169920Syasuko.eckert@amd.com 5177897Shestness@cs.utexas.edu miscRegfileReads 5187897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5197897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5207897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5217897Shestness@cs.utexas.edu 5227897Shestness@cs.utexas.edu miscRegfileWrites 5237897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5247897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5257897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5261062SN/A} 5271062SN/A 5281062SN/Atemplate <class Impl> 5291062SN/Avoid 5301755SN/AFullO3CPU<Impl>::tick() 5311060SN/A{ 5322733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5339444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 5349444SAndreas.Sandberg@ARM.com assert(getDrainState() != Drainable::Drained); 5351060SN/A 5362292SN/A ++numCycles; 5372292SN/A 5382325SN/A// activity = false; 5392292SN/A 5402292SN/A //Tick each of the stages 5411060SN/A fetch.tick(); 5421060SN/A 5431060SN/A decode.tick(); 5441060SN/A 5451060SN/A rename.tick(); 5461060SN/A 5471060SN/A iew.tick(); 5481060SN/A 5491060SN/A commit.tick(); 5501060SN/A 5512292SN/A // Now advance the time buffers 5521060SN/A timeBuffer.advance(); 5531060SN/A 5541060SN/A fetchQueue.advance(); 5551060SN/A decodeQueue.advance(); 5561060SN/A renameQueue.advance(); 5571060SN/A iewQueue.advance(); 5581060SN/A 5592325SN/A activityRec.advance(); 5602292SN/A 5612292SN/A if (removeInstsThisCycle) { 5622292SN/A cleanUpRemovedInsts(); 5632292SN/A } 5642292SN/A 5652325SN/A if (!tickEvent.scheduled()) { 5669444SAndreas.Sandberg@ARM.com if (_status == SwitchedOut) { 5673226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 5682325SN/A // increment stat 5699179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 5703221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 5713226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 5729179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 5732325SN/A timesIdled++; 5742325SN/A } else { 5759180Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(Cycles(1))); 5763226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 5772325SN/A } 5782292SN/A } 5792292SN/A 5808793Sgblack@eecs.umich.edu if (!FullSystem) 5818793Sgblack@eecs.umich.edu updateThreadPriority(); 5829444SAndreas.Sandberg@ARM.com 5839444SAndreas.Sandberg@ARM.com tryDrain(); 5841060SN/A} 5851060SN/A 5861060SN/Atemplate <class Impl> 5871060SN/Avoid 5881755SN/AFullO3CPU<Impl>::init() 5891060SN/A{ 5905714Shsul@eecs.umich.edu BaseCPU::init(); 5911060SN/A 5928921Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 5939382SAli.Saidi@ARM.com // Set noSquashFromTC so that the CPU doesn't squash when initially 5948921Sandreas.hansson@arm.com // setting up registers. 5959382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 5968921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 5978921Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 5988921Sandreas.hansson@arm.com } 5992292SN/A 6009433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 6018793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6028793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6038793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6048793Sgblack@eecs.umich.edu } 6056034Ssteve.reinhardt@amd.com } 6062292SN/A 6079382SAli.Saidi@ARM.com // Clear noSquashFromTC. 6086221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6099382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6102292SN/A 6119427SAndreas.Sandberg@ARM.com commit.setThreads(thread); 6129427SAndreas.Sandberg@ARM.com} 6132292SN/A 6149427SAndreas.Sandberg@ARM.comtemplate <class Impl> 6159427SAndreas.Sandberg@ARM.comvoid 6169427SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::startup() 6179427SAndreas.Sandberg@ARM.com{ 6189992Snilay@cs.wisc.edu BaseCPU::startup(); 6199461Snilay@cs.wisc.edu for (int tid = 0; tid < numThreads; ++tid) 6209461Snilay@cs.wisc.edu isa[tid]->startup(threadContexts[tid]); 6219461Snilay@cs.wisc.edu 6229427SAndreas.Sandberg@ARM.com fetch.startupStage(); 6239444SAndreas.Sandberg@ARM.com decode.startupStage(); 6249427SAndreas.Sandberg@ARM.com iew.startupStage(); 6259427SAndreas.Sandberg@ARM.com rename.startupStage(); 6269427SAndreas.Sandberg@ARM.com commit.startupStage(); 6272292SN/A} 6282292SN/A 6292292SN/Atemplate <class Impl> 6302292SN/Avoid 6316221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6322875Sksewell@umich.edu{ 6336221Snate@binkert.org list<ThreadID>::iterator isActive = 6345314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6352875Sksewell@umich.edu 6363226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6379444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6383226Sktlim@umich.edu 6392875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6402875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6412875Sksewell@umich.edu tid); 6422875Sksewell@umich.edu 6432875Sksewell@umich.edu activeThreads.push_back(tid); 6442875Sksewell@umich.edu } 6452875Sksewell@umich.edu} 6462875Sksewell@umich.edu 6472875Sksewell@umich.edutemplate <class Impl> 6482875Sksewell@umich.eduvoid 6496221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 6502875Sksewell@umich.edu{ 6512875Sksewell@umich.edu //Remove From Active List, if Active 6526221Snate@binkert.org list<ThreadID>::iterator thread_it = 6535314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6542875Sksewell@umich.edu 6553226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 6569444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6573226Sktlim@umich.edu 6582875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6592875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6602875Sksewell@umich.edu tid); 6612875Sksewell@umich.edu activeThreads.erase(thread_it); 6622875Sksewell@umich.edu } 66310331Smitch.hayenga@arm.com 66410331Smitch.hayenga@arm.com fetch.deactivateThread(tid); 66510331Smitch.hayenga@arm.com commit.deactivateThread(tid); 6662875Sksewell@umich.edu} 6672875Sksewell@umich.edu 6682875Sksewell@umich.edutemplate <class Impl> 6696221Snate@binkert.orgCounter 6708834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 6716221Snate@binkert.org{ 6726221Snate@binkert.org Counter total(0); 6736221Snate@binkert.org 6746221Snate@binkert.org ThreadID size = thread.size(); 6756221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 6766221Snate@binkert.org total += thread[i]->numInst; 6776221Snate@binkert.org 6786221Snate@binkert.org return total; 6796221Snate@binkert.org} 6806221Snate@binkert.org 6816221Snate@binkert.orgtemplate <class Impl> 6828834Satgutier@umich.eduCounter 6838834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 6848834Satgutier@umich.edu{ 6858834Satgutier@umich.edu Counter total(0); 6868834Satgutier@umich.edu 6878834Satgutier@umich.edu ThreadID size = thread.size(); 6888834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 6898834Satgutier@umich.edu total += thread[i]->numOp; 6908834Satgutier@umich.edu 6918834Satgutier@umich.edu return total; 6928834Satgutier@umich.edu} 6938834Satgutier@umich.edu 6948834Satgutier@umich.edutemplate <class Impl> 6952875Sksewell@umich.eduvoid 69610407Smitch.hayenga@arm.comFullO3CPU<Impl>::activateContext(ThreadID tid) 6972875Sksewell@umich.edu{ 6989444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6999444SAndreas.Sandberg@ARM.com 7002875Sksewell@umich.edu // Needs to set each stage to running as well. 70110407Smitch.hayenga@arm.com activateThread(tid); 7022875Sksewell@umich.edu 7039444SAndreas.Sandberg@ARM.com // We don't want to wake the CPU if it is drained. In that case, 7049444SAndreas.Sandberg@ARM.com // we just want to flag the thread as active and schedule the tick 7059444SAndreas.Sandberg@ARM.com // event from drainResume() instead. 7069444SAndreas.Sandberg@ARM.com if (getDrainState() == Drainable::Drained) 7079444SAndreas.Sandberg@ARM.com return; 7089444SAndreas.Sandberg@ARM.com 7099158Sandreas.hansson@arm.com // If we are time 0 or if the last activation time is in the past, 7109158Sandreas.hansson@arm.com // schedule the next tick and wake up the fetch unit 7119158Sandreas.hansson@arm.com if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 71210407Smitch.hayenga@arm.com scheduleTickEvent(Cycles(0)); 7132875Sksewell@umich.edu 7142875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7152875Sksewell@umich.edu // deschedule itself. 7162875Sksewell@umich.edu activityRec.activity(); 7172875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7182875Sksewell@umich.edu 7199180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 7209180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 7219179Sandreas.hansson@arm.com if (cycles != 0) 7229179Sandreas.hansson@arm.com --cycles; 7239179Sandreas.hansson@arm.com quiesceCycles += cycles; 7248627SAli.Saidi@ARM.com 7257823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7262875Sksewell@umich.edu 7272875Sksewell@umich.edu _status = Running; 7282875Sksewell@umich.edu } 7292875Sksewell@umich.edu} 7302875Sksewell@umich.edu 7312875Sksewell@umich.edutemplate <class Impl> 73210407Smitch.hayenga@arm.comvoid 73310407Smitch.hayenga@arm.comFullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove) 7342875Sksewell@umich.edu{ 73510407Smitch.hayenga@arm.com deactivateThread(tid); 73610407Smitch.hayenga@arm.com if (remove) 73710407Smitch.hayenga@arm.com removeThread(tid); 7382875Sksewell@umich.edu} 7392875Sksewell@umich.edu 7402875Sksewell@umich.edutemplate <class Impl> 7412875Sksewell@umich.eduvoid 7426221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 7432875Sksewell@umich.edu{ 7442875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7459444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 74610407Smitch.hayenga@arm.com deallocateContext(tid, false); 74710407Smitch.hayenga@arm.com 7483221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 74910407Smitch.hayenga@arm.com if (activeThreads.size() == 0) 7502910Sksewell@umich.edu unscheduleTickEvent(); 7518627SAli.Saidi@ARM.com 7528627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 7539179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 7542875Sksewell@umich.edu _status = Idle; 7552875Sksewell@umich.edu} 7562875Sksewell@umich.edu 7572875Sksewell@umich.edutemplate <class Impl> 7582875Sksewell@umich.eduvoid 7596221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 7602875Sksewell@umich.edu{ 7612910Sksewell@umich.edu //For now, this is the same as deallocate 7622910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 7639444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 76410407Smitch.hayenga@arm.com deallocateContext(tid, true); 7652875Sksewell@umich.edu} 7662875Sksewell@umich.edu 7672875Sksewell@umich.edutemplate <class Impl> 7682875Sksewell@umich.eduvoid 7696221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 7702292SN/A{ 7712847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 7722292SN/A // Will change now that the PC and thread state is internal to the CPU 7732683Sktlim@umich.edu // and not in the ThreadContext. 7748793Sgblack@eecs.umich.edu ThreadContext *src_tc; 7758793Sgblack@eecs.umich.edu if (FullSystem) 7768793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 7778793Sgblack@eecs.umich.edu else 7788793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 7792292SN/A 7802292SN/A //Bind Int Regs to Rename Map 7812292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7822292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 7832292SN/A 7842292SN/A renameMap[tid].setEntry(ireg,phys_reg); 7852292SN/A scoreboard.setReg(phys_reg); 7862292SN/A } 7872292SN/A 7882292SN/A //Bind Float Regs to Rename Map 7899920Syasuko.eckert@amd.com int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 7909920Syasuko.eckert@amd.com for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) { 7912292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 7922292SN/A 7932292SN/A renameMap[tid].setEntry(freg,phys_reg); 7942292SN/A scoreboard.setReg(phys_reg); 7952292SN/A } 7962292SN/A 7979920Syasuko.eckert@amd.com //Bind condition-code Regs to Rename Map 7989920Syasuko.eckert@amd.com max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs; 7999920Syasuko.eckert@amd.com for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 8009920Syasuko.eckert@amd.com creg < max_reg; creg++) { 8019920Syasuko.eckert@amd.com PhysRegIndex phys_reg = freeList.getCCReg(); 8029920Syasuko.eckert@amd.com 8039920Syasuko.eckert@amd.com renameMap[tid].setEntry(creg,phys_reg); 8049920Syasuko.eckert@amd.com scoreboard.setReg(phys_reg); 8059920Syasuko.eckert@amd.com } 8069920Syasuko.eckert@amd.com 8072292SN/A //Copy Thread Data Into RegFile 8082847Sksewell@umich.edu //this->copyFromTC(tid); 8092292SN/A 8102847Sksewell@umich.edu //Set PC/NPC/NNPC 8117720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8122292SN/A 8132680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8142292SN/A 81510407Smitch.hayenga@arm.com activateContext(tid); 8162292SN/A 8172292SN/A //Reset ROB/IQ/LSQ Entries 8182292SN/A commit.rob->resetEntries(); 8192292SN/A iew.resetEntries(); 8202292SN/A} 8212292SN/A 8222292SN/Atemplate <class Impl> 8232292SN/Avoid 8246221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8252292SN/A{ 8262877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 8272847Sksewell@umich.edu 8282847Sksewell@umich.edu // Copy Thread Data From RegFile 8292847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 8305364Sksewell@umich.edu // this->copyToTC(tid); 8315364Sksewell@umich.edu 8325364Sksewell@umich.edu 8335364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 8345364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 8355364Sksewell@umich.edu // in SMT workloads. 8362847Sksewell@umich.edu 8372847Sksewell@umich.edu // Unbind Int Regs from Rename Map 8382292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8392292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 8402292SN/A 8412292SN/A scoreboard.unsetReg(phys_reg); 8422292SN/A freeList.addReg(phys_reg); 8432292SN/A } 8442292SN/A 8452847Sksewell@umich.edu // Unbind Float Regs from Rename Map 8469920Syasuko.eckert@amd.com int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 8479920Syasuko.eckert@amd.com for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) { 8482292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 8492292SN/A 8502292SN/A scoreboard.unsetReg(phys_reg); 8512292SN/A freeList.addReg(phys_reg); 8522292SN/A } 8532292SN/A 8549920Syasuko.eckert@amd.com // Unbind condition-code Regs from Rename Map 8559920Syasuko.eckert@amd.com max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs; 8569920Syasuko.eckert@amd.com for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 8579920Syasuko.eckert@amd.com creg < max_reg; creg++) { 8589920Syasuko.eckert@amd.com PhysRegIndex phys_reg = renameMap[tid].lookup(creg); 8599920Syasuko.eckert@amd.com 8609920Syasuko.eckert@amd.com scoreboard.unsetReg(phys_reg); 8619920Syasuko.eckert@amd.com freeList.addReg(phys_reg); 8629920Syasuko.eckert@amd.com } 8639920Syasuko.eckert@amd.com 8642847Sksewell@umich.edu // Squash Throughout Pipeline 8658138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 8668138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 8678138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 8682292SN/A decode.squash(tid); 8692935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 8702875Sksewell@umich.edu iew.squash(tid); 8715363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 8722935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 8732292SN/A 8745362Sksewell@umich.edu 8755362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 8762292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 8772292SN/A 8782847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 8793229Sktlim@umich.edu 8803229Sktlim@umich.edu // Commented out for now. This should be possible to do by 8813229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 8823229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 8833229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 8843229Sktlim@umich.edu/* 8852292SN/A if (activeThreads.size() >= 1) { 8862292SN/A commit.rob->resetEntries(); 8872292SN/A iew.resetEntries(); 8882292SN/A } 8893229Sktlim@umich.edu*/ 8902292SN/A} 8912292SN/A 8924192Sktlim@umich.edutemplate <class Impl> 8935595Sgblack@eecs.umich.eduFault 8946221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 8955702Ssaidi@eecs.umich.edu{ 8965702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 8975702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 8985702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 8995702Ssaidi@eecs.umich.edu 9005702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 9015702Ssaidi@eecs.umich.edu 9025702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9035702Ssaidi@eecs.umich.edu#endif 9045702Ssaidi@eecs.umich.edu return NoFault; 9055702Ssaidi@eecs.umich.edu} 9065702Ssaidi@eecs.umich.edu 9075702Ssaidi@eecs.umich.edutemplate <class Impl> 9085702Ssaidi@eecs.umich.edubool 9096221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 9105702Ssaidi@eecs.umich.edu{ 9115702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9125702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 9135702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 9145702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 9155702Ssaidi@eecs.umich.edu 9165702Ssaidi@eecs.umich.edu switch (palFunc) { 9175702Ssaidi@eecs.umich.edu case PAL::halt: 9185702Ssaidi@eecs.umich.edu halt(); 9195702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 9205702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 9215702Ssaidi@eecs.umich.edu break; 9225702Ssaidi@eecs.umich.edu 9235702Ssaidi@eecs.umich.edu case PAL::bpt: 9245702Ssaidi@eecs.umich.edu case PAL::bugchk: 9255702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 9265702Ssaidi@eecs.umich.edu return false; 9275702Ssaidi@eecs.umich.edu break; 9285702Ssaidi@eecs.umich.edu } 9295702Ssaidi@eecs.umich.edu#endif 9305702Ssaidi@eecs.umich.edu return true; 9315702Ssaidi@eecs.umich.edu} 9325702Ssaidi@eecs.umich.edu 9335702Ssaidi@eecs.umich.edutemplate <class Impl> 9345702Ssaidi@eecs.umich.eduFault 9355595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 9365595Sgblack@eecs.umich.edu{ 9375595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 9385647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 9395595Sgblack@eecs.umich.edu} 9405595Sgblack@eecs.umich.edu 9415595Sgblack@eecs.umich.edutemplate <class Impl> 9425595Sgblack@eecs.umich.eduvoid 94310379Sandreas.hansson@arm.comFullO3CPU<Impl>::processInterrupts(const Fault &interrupt) 9445595Sgblack@eecs.umich.edu{ 9455595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 9465595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 9475595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9485595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9495595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9505595Sgblack@eecs.umich.edu 9515595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 9525647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 9535595Sgblack@eecs.umich.edu 9545595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 9557684Sgblack@eecs.umich.edu this->trap(interrupt, 0, NULL); 9565595Sgblack@eecs.umich.edu} 9575595Sgblack@eecs.umich.edu 9581060SN/Atemplate <class Impl> 9592852Sktlim@umich.eduvoid 96010379Sandreas.hansson@arm.comFullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid, StaticInstPtr inst) 9615595Sgblack@eecs.umich.edu{ 9625595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 9637684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 9645595Sgblack@eecs.umich.edu} 9655595Sgblack@eecs.umich.edu 9665595Sgblack@eecs.umich.edutemplate <class Impl> 9675595Sgblack@eecs.umich.eduvoid 9686221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 9695595Sgblack@eecs.umich.edu{ 9705595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 9715595Sgblack@eecs.umich.edu 9725595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 9735595Sgblack@eecs.umich.edu 9745595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 9755595Sgblack@eecs.umich.edu // instruction. 9765595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 9775595Sgblack@eecs.umich.edu 9785595Sgblack@eecs.umich.edu // Execute the actual syscall. 9795595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 9805595Sgblack@eecs.umich.edu 9815595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 9825595Sgblack@eecs.umich.edu // incrementing it. 9835595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 9845595Sgblack@eecs.umich.edu} 9855595Sgblack@eecs.umich.edu 9865595Sgblack@eecs.umich.edutemplate <class Impl> 9875595Sgblack@eecs.umich.eduvoid 9889448SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::serializeThread(std::ostream &os, ThreadID tid) 9892864Sktlim@umich.edu{ 9909448SAndreas.Sandberg@ARM.com thread[tid]->serialize(os); 9912864Sktlim@umich.edu} 9922864Sktlim@umich.edu 9932864Sktlim@umich.edutemplate <class Impl> 9942864Sktlim@umich.eduvoid 9959448SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::unserializeThread(Checkpoint *cp, const std::string §ion, 9969448SAndreas.Sandberg@ARM.com ThreadID tid) 9972864Sktlim@umich.edu{ 9989448SAndreas.Sandberg@ARM.com thread[tid]->unserialize(cp, section); 9992864Sktlim@umich.edu} 10002864Sktlim@umich.edu 10012864Sktlim@umich.edutemplate <class Impl> 10022905Sktlim@umich.eduunsigned int 10039342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drain(DrainManager *drain_manager) 10041060SN/A{ 10059444SAndreas.Sandberg@ARM.com // If the CPU isn't doing anything, then return immediately. 10069444SAndreas.Sandberg@ARM.com if (switchedOut()) { 10079444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Drained); 10089444SAndreas.Sandberg@ARM.com return 0; 10099444SAndreas.Sandberg@ARM.com } 10103512Sktlim@umich.edu 10119444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Draining...\n"); 10129444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Draining); 10133512Sktlim@umich.edu 10149444SAndreas.Sandberg@ARM.com // We only need to signal a drain to the commit stage as this 10159444SAndreas.Sandberg@ARM.com // initiates squashing controls the draining. Once the commit 10169444SAndreas.Sandberg@ARM.com // stage commits an instruction where it is safe to stop, it'll 10179444SAndreas.Sandberg@ARM.com // squash the rest of the instructions in the pipeline and force 10189444SAndreas.Sandberg@ARM.com // the fetch stage to stall. The pipeline will be drained once all 10199444SAndreas.Sandberg@ARM.com // in-flight instructions have retired. 10202843Sktlim@umich.edu commit.drain(); 10212325SN/A 10222325SN/A // Wake the CPU and record activity so everything can drain out if 10232863Sktlim@umich.edu // the CPU was not able to immediately drain. 10249444SAndreas.Sandberg@ARM.com if (!isDrained()) { 10259342SAndreas.Sandberg@arm.com drainManager = drain_manager; 10262843Sktlim@umich.edu 10272863Sktlim@umich.edu wakeCPU(); 10282863Sktlim@umich.edu activityRec.activity(); 10292852Sktlim@umich.edu 10309152Satgutier@umich.edu DPRINTF(Drain, "CPU not drained\n"); 10319152Satgutier@umich.edu 10322905Sktlim@umich.edu return 1; 10332863Sktlim@umich.edu } else { 10349444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Drained); 10359444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU is already drained\n"); 10369444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 10379444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 10389444SAndreas.Sandberg@ARM.com 10399444SAndreas.Sandberg@ARM.com // Flush out any old data from the time buffers. In 10409444SAndreas.Sandberg@ARM.com // particular, there might be some data in flight from the 10419444SAndreas.Sandberg@ARM.com // fetch stage that isn't visible in any of the CPU buffers we 10429444SAndreas.Sandberg@ARM.com // test in isDrained(). 10439444SAndreas.Sandberg@ARM.com for (int i = 0; i < timeBuffer.getSize(); ++i) { 10449444SAndreas.Sandberg@ARM.com timeBuffer.advance(); 10459444SAndreas.Sandberg@ARM.com fetchQueue.advance(); 10469444SAndreas.Sandberg@ARM.com decodeQueue.advance(); 10479444SAndreas.Sandberg@ARM.com renameQueue.advance(); 10489444SAndreas.Sandberg@ARM.com iewQueue.advance(); 10499444SAndreas.Sandberg@ARM.com } 10509444SAndreas.Sandberg@ARM.com 10519444SAndreas.Sandberg@ARM.com drainSanityCheck(); 10522905Sktlim@umich.edu return 0; 10532863Sktlim@umich.edu } 10542316SN/A} 10552310SN/A 10562316SN/Atemplate <class Impl> 10579444SAndreas.Sandberg@ARM.combool 10589444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::tryDrain() 10599444SAndreas.Sandberg@ARM.com{ 10609444SAndreas.Sandberg@ARM.com if (!drainManager || !isDrained()) 10619444SAndreas.Sandberg@ARM.com return false; 10629444SAndreas.Sandberg@ARM.com 10639444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 10649444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 10659444SAndreas.Sandberg@ARM.com 10669444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 10679444SAndreas.Sandberg@ARM.com drainManager->signalDrainDone(); 10689444SAndreas.Sandberg@ARM.com drainManager = NULL; 10699444SAndreas.Sandberg@ARM.com 10709444SAndreas.Sandberg@ARM.com return true; 10719444SAndreas.Sandberg@ARM.com} 10729444SAndreas.Sandberg@ARM.com 10739444SAndreas.Sandberg@ARM.comtemplate <class Impl> 10749444SAndreas.Sandberg@ARM.comvoid 10759444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::drainSanityCheck() const 10769444SAndreas.Sandberg@ARM.com{ 10779444SAndreas.Sandberg@ARM.com assert(isDrained()); 10789444SAndreas.Sandberg@ARM.com fetch.drainSanityCheck(); 10799444SAndreas.Sandberg@ARM.com decode.drainSanityCheck(); 10809444SAndreas.Sandberg@ARM.com rename.drainSanityCheck(); 10819444SAndreas.Sandberg@ARM.com iew.drainSanityCheck(); 10829444SAndreas.Sandberg@ARM.com commit.drainSanityCheck(); 10839444SAndreas.Sandberg@ARM.com} 10849444SAndreas.Sandberg@ARM.com 10859444SAndreas.Sandberg@ARM.comtemplate <class Impl> 10869444SAndreas.Sandberg@ARM.combool 10879444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::isDrained() const 10889444SAndreas.Sandberg@ARM.com{ 10899444SAndreas.Sandberg@ARM.com bool drained(true); 10909444SAndreas.Sandberg@ARM.com 10919444SAndreas.Sandberg@ARM.com if (!instList.empty() || !removeList.empty()) { 10929444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Main CPU structures not drained.\n"); 10939444SAndreas.Sandberg@ARM.com drained = false; 10949444SAndreas.Sandberg@ARM.com } 10959444SAndreas.Sandberg@ARM.com 10969444SAndreas.Sandberg@ARM.com if (!fetch.isDrained()) { 10979444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Fetch not drained.\n"); 10989444SAndreas.Sandberg@ARM.com drained = false; 10999444SAndreas.Sandberg@ARM.com } 11009444SAndreas.Sandberg@ARM.com 11019444SAndreas.Sandberg@ARM.com if (!decode.isDrained()) { 11029444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Decode not drained.\n"); 11039444SAndreas.Sandberg@ARM.com drained = false; 11049444SAndreas.Sandberg@ARM.com } 11059444SAndreas.Sandberg@ARM.com 11069444SAndreas.Sandberg@ARM.com if (!rename.isDrained()) { 11079444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Rename not drained.\n"); 11089444SAndreas.Sandberg@ARM.com drained = false; 11099444SAndreas.Sandberg@ARM.com } 11109444SAndreas.Sandberg@ARM.com 11119444SAndreas.Sandberg@ARM.com if (!iew.isDrained()) { 11129444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "IEW not drained.\n"); 11139444SAndreas.Sandberg@ARM.com drained = false; 11149444SAndreas.Sandberg@ARM.com } 11159444SAndreas.Sandberg@ARM.com 11169444SAndreas.Sandberg@ARM.com if (!commit.isDrained()) { 11179444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Commit not drained.\n"); 11189444SAndreas.Sandberg@ARM.com drained = false; 11199444SAndreas.Sandberg@ARM.com } 11209444SAndreas.Sandberg@ARM.com 11219444SAndreas.Sandberg@ARM.com return drained; 11229444SAndreas.Sandberg@ARM.com} 11239444SAndreas.Sandberg@ARM.com 11249444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11259444SAndreas.Sandberg@ARM.comvoid 11269444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::commitDrained(ThreadID tid) 11279444SAndreas.Sandberg@ARM.com{ 11289444SAndreas.Sandberg@ARM.com fetch.drainStall(tid); 11299444SAndreas.Sandberg@ARM.com} 11309444SAndreas.Sandberg@ARM.com 11319444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11322316SN/Avoid 11339342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drainResume() 11342316SN/A{ 11359444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Running); 11369444SAndreas.Sandberg@ARM.com if (switchedOut()) 11379444SAndreas.Sandberg@ARM.com return; 11382316SN/A 11399444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Resuming...\n"); 11409523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 11413319Shsul@eecs.umich.edu 11429444SAndreas.Sandberg@ARM.com fetch.drainResume(); 11439444SAndreas.Sandberg@ARM.com commit.drainResume(); 11442316SN/A 11459444SAndreas.Sandberg@ARM.com _status = Idle; 11469444SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); i++) { 11479444SAndreas.Sandberg@ARM.com if (thread[i]->status() == ThreadContext::Active) { 11489444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Activating thread: %i\n", i); 11499444SAndreas.Sandberg@ARM.com activateThread(i); 11509444SAndreas.Sandberg@ARM.com _status = Running; 11512863Sktlim@umich.edu } 11522310SN/A } 11539444SAndreas.Sandberg@ARM.com 11549444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 11559444SAndreas.Sandberg@ARM.com if (_status == Running) 11569444SAndreas.Sandberg@ARM.com schedule(tickEvent, nextCycle()); 11572843Sktlim@umich.edu} 11582843Sktlim@umich.edu 11592843Sktlim@umich.edutemplate <class Impl> 11602843Sktlim@umich.eduvoid 11612843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11622843Sktlim@umich.edu{ 11639444SAndreas.Sandberg@ARM.com DPRINTF(O3CPU, "Switching out\n"); 11649429SAndreas.Sandberg@ARM.com BaseCPU::switchOut(); 11659429SAndreas.Sandberg@ARM.com 11669444SAndreas.Sandberg@ARM.com activityRec.reset(); 11672843Sktlim@umich.edu 11682843Sktlim@umich.edu _status = SwitchedOut; 11698887Sgeoffrey.blake@arm.com 11702843Sktlim@umich.edu if (checker) 11712843Sktlim@umich.edu checker->switchOut(); 11721060SN/A} 11731060SN/A 11741060SN/Atemplate <class Impl> 11751060SN/Avoid 11761755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 11771060SN/A{ 11788737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 11791060SN/A 11802307SN/A fetch.takeOverFrom(); 11812307SN/A decode.takeOverFrom(); 11822307SN/A rename.takeOverFrom(); 11832307SN/A iew.takeOverFrom(); 11842307SN/A commit.takeOverFrom(); 11852307SN/A 11869444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 11871060SN/A 11889152Satgutier@umich.edu FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 11899152Satgutier@umich.edu if (oldO3CPU) 11909152Satgutier@umich.edu globalSeqNum = oldO3CPU->globalSeqNum; 11919152Satgutier@umich.edu 11929179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 11939444SAndreas.Sandberg@ARM.com _status = Idle; 11941060SN/A} 11951060SN/A 11961060SN/Atemplate <class Impl> 11979523SAndreas.Sandberg@ARM.comvoid 11989523SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::verifyMemoryMode() const 11999523SAndreas.Sandberg@ARM.com{ 12009524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 12019523SAndreas.Sandberg@ARM.com fatal("The O3 CPU requires the memory system to be in " 12029523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 12039523SAndreas.Sandberg@ARM.com } 12049523SAndreas.Sandberg@ARM.com} 12059523SAndreas.Sandberg@ARM.com 12069523SAndreas.Sandberg@ARM.comtemplate <class Impl> 12075595Sgblack@eecs.umich.eduTheISA::MiscReg 12086221Snate@binkert.orgFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 12095595Sgblack@eecs.umich.edu{ 12109384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscRegNoEffect(misc_reg); 12115595Sgblack@eecs.umich.edu} 12125595Sgblack@eecs.umich.edu 12135595Sgblack@eecs.umich.edutemplate <class Impl> 12145595Sgblack@eecs.umich.eduTheISA::MiscReg 12156221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 12165595Sgblack@eecs.umich.edu{ 12177897Shestness@cs.utexas.edu miscRegfileReads++; 12189384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 12195595Sgblack@eecs.umich.edu} 12205595Sgblack@eecs.umich.edu 12215595Sgblack@eecs.umich.edutemplate <class Impl> 12225595Sgblack@eecs.umich.eduvoid 12235595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 12246221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12255595Sgblack@eecs.umich.edu{ 12269384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 12275595Sgblack@eecs.umich.edu} 12285595Sgblack@eecs.umich.edu 12295595Sgblack@eecs.umich.edutemplate <class Impl> 12305595Sgblack@eecs.umich.eduvoid 12315595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 12326221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12335595Sgblack@eecs.umich.edu{ 12347897Shestness@cs.utexas.edu miscRegfileWrites++; 12359384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 12365595Sgblack@eecs.umich.edu} 12375595Sgblack@eecs.umich.edu 12385595Sgblack@eecs.umich.edutemplate <class Impl> 12391060SN/Auint64_t 12401755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 12411060SN/A{ 12427897Shestness@cs.utexas.edu intRegfileReads++; 12431060SN/A return regFile.readIntReg(reg_idx); 12441060SN/A} 12451060SN/A 12461060SN/Atemplate <class Impl> 12472455SN/AFloatReg 12482455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 12491060SN/A{ 12507897Shestness@cs.utexas.edu fpRegfileReads++; 12512455SN/A return regFile.readFloatReg(reg_idx); 12521060SN/A} 12531060SN/A 12541060SN/Atemplate <class Impl> 12552455SN/AFloatRegBits 12562455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 12572455SN/A{ 12587897Shestness@cs.utexas.edu fpRegfileReads++; 12592455SN/A return regFile.readFloatRegBits(reg_idx); 12601060SN/A} 12611060SN/A 12621060SN/Atemplate <class Impl> 12639920Syasuko.eckert@amd.comCCReg 12649920Syasuko.eckert@amd.comFullO3CPU<Impl>::readCCReg(int reg_idx) 12659920Syasuko.eckert@amd.com{ 12669920Syasuko.eckert@amd.com ccRegfileReads++; 12679920Syasuko.eckert@amd.com return regFile.readCCReg(reg_idx); 12689920Syasuko.eckert@amd.com} 12699920Syasuko.eckert@amd.com 12709920Syasuko.eckert@amd.comtemplate <class Impl> 12711060SN/Avoid 12721755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 12731060SN/A{ 12747897Shestness@cs.utexas.edu intRegfileWrites++; 12751060SN/A regFile.setIntReg(reg_idx, val); 12761060SN/A} 12771060SN/A 12781060SN/Atemplate <class Impl> 12791060SN/Avoid 12802455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 12811060SN/A{ 12827897Shestness@cs.utexas.edu fpRegfileWrites++; 12832455SN/A regFile.setFloatReg(reg_idx, val); 12841060SN/A} 12851060SN/A 12861060SN/Atemplate <class Impl> 12871060SN/Avoid 12882455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 12892455SN/A{ 12907897Shestness@cs.utexas.edu fpRegfileWrites++; 12912455SN/A regFile.setFloatRegBits(reg_idx, val); 12921060SN/A} 12931060SN/A 12941060SN/Atemplate <class Impl> 12959920Syasuko.eckert@amd.comvoid 12969920Syasuko.eckert@amd.comFullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val) 12979920Syasuko.eckert@amd.com{ 12989920Syasuko.eckert@amd.com ccRegfileWrites++; 12999920Syasuko.eckert@amd.com regFile.setCCReg(reg_idx, val); 13009920Syasuko.eckert@amd.com} 13019920Syasuko.eckert@amd.com 13029920Syasuko.eckert@amd.comtemplate <class Impl> 13031060SN/Auint64_t 13046221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 13051060SN/A{ 13067897Shestness@cs.utexas.edu intRegfileReads++; 13079919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 13082292SN/A 13092292SN/A return regFile.readIntReg(phys_reg); 13102292SN/A} 13112292SN/A 13122292SN/Atemplate <class Impl> 13132292SN/Afloat 13146314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 13152292SN/A{ 13167897Shestness@cs.utexas.edu fpRegfileReads++; 13179919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 13182292SN/A 13192669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 13202292SN/A} 13212292SN/A 13222292SN/Atemplate <class Impl> 13232292SN/Auint64_t 13246221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 13252292SN/A{ 13267897Shestness@cs.utexas.edu fpRegfileReads++; 13279919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 13282292SN/A 13292669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13301060SN/A} 13311060SN/A 13321060SN/Atemplate <class Impl> 13339920Syasuko.eckert@amd.comCCReg 13349920Syasuko.eckert@amd.comFullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid) 13359920Syasuko.eckert@amd.com{ 13369920Syasuko.eckert@amd.com ccRegfileReads++; 13379920Syasuko.eckert@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 13389920Syasuko.eckert@amd.com 13399920Syasuko.eckert@amd.com return regFile.readCCReg(phys_reg); 13409920Syasuko.eckert@amd.com} 13419920Syasuko.eckert@amd.com 13429920Syasuko.eckert@amd.comtemplate <class Impl> 13431060SN/Avoid 13446221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 13451060SN/A{ 13467897Shestness@cs.utexas.edu intRegfileWrites++; 13479919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 13482292SN/A 13492292SN/A regFile.setIntReg(phys_reg, val); 13501060SN/A} 13511060SN/A 13521060SN/Atemplate <class Impl> 13531060SN/Avoid 13546314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 13551060SN/A{ 13567897Shestness@cs.utexas.edu fpRegfileWrites++; 13579919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 13582292SN/A 13592669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 13601060SN/A} 13611060SN/A 13621060SN/Atemplate <class Impl> 13631060SN/Avoid 13646221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 13651060SN/A{ 13667897Shestness@cs.utexas.edu fpRegfileWrites++; 13679919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 13681060SN/A 13692669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 13702292SN/A} 13712292SN/A 13722292SN/Atemplate <class Impl> 13739920Syasuko.eckert@amd.comvoid 13749920Syasuko.eckert@amd.comFullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid) 13759920Syasuko.eckert@amd.com{ 13769920Syasuko.eckert@amd.com ccRegfileWrites++; 13779920Syasuko.eckert@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 13789920Syasuko.eckert@amd.com 13799920Syasuko.eckert@amd.com regFile.setCCReg(phys_reg, val); 13809920Syasuko.eckert@amd.com} 13819920Syasuko.eckert@amd.com 13829920Syasuko.eckert@amd.comtemplate <class Impl> 13837720Sgblack@eecs.umich.eduTheISA::PCState 13847720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 13852292SN/A{ 13867720Sgblack@eecs.umich.edu return commit.pcState(tid); 13871060SN/A} 13881060SN/A 13891060SN/Atemplate <class Impl> 13901060SN/Avoid 13917720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 13921060SN/A{ 13937720Sgblack@eecs.umich.edu commit.pcState(val, tid); 13942292SN/A} 13951060SN/A 13962292SN/Atemplate <class Impl> 13977720Sgblack@eecs.umich.eduAddr 13987720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 13994636Sgblack@eecs.umich.edu{ 14007720Sgblack@eecs.umich.edu return commit.instAddr(tid); 14014636Sgblack@eecs.umich.edu} 14024636Sgblack@eecs.umich.edu 14034636Sgblack@eecs.umich.edutemplate <class Impl> 14047720Sgblack@eecs.umich.eduAddr 14057720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 14064636Sgblack@eecs.umich.edu{ 14077720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 14084636Sgblack@eecs.umich.edu} 14094636Sgblack@eecs.umich.edu 14104636Sgblack@eecs.umich.edutemplate <class Impl> 14117720Sgblack@eecs.umich.eduMicroPC 14127720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 14132292SN/A{ 14147720Sgblack@eecs.umich.edu return commit.microPC(tid); 14154636Sgblack@eecs.umich.edu} 14164636Sgblack@eecs.umich.edu 14174636Sgblack@eecs.umich.edutemplate <class Impl> 14185595Sgblack@eecs.umich.eduvoid 14196221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 14205595Sgblack@eecs.umich.edu{ 14219382SAli.Saidi@ARM.com this->thread[tid]->noSquashFromTC = true; 14225595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 14235595Sgblack@eecs.umich.edu} 14245595Sgblack@eecs.umich.edu 14255595Sgblack@eecs.umich.edutemplate <class Impl> 14262292SN/Atypename FullO3CPU<Impl>::ListIt 14272292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14282292SN/A{ 14292292SN/A instList.push_back(inst); 14301060SN/A 14312292SN/A return --(instList.end()); 14322292SN/A} 14331060SN/A 14342292SN/Atemplate <class Impl> 14352292SN/Avoid 14368834Satgutier@umich.eduFullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 14372292SN/A{ 14382292SN/A // Keep an instruction count. 14398834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 14408834Satgutier@umich.edu thread[tid]->numInst++; 14418834Satgutier@umich.edu thread[tid]->numInsts++; 14428834Satgutier@umich.edu committedInsts[tid]++; 14438834Satgutier@umich.edu } 14448834Satgutier@umich.edu thread[tid]->numOp++; 14458834Satgutier@umich.edu thread[tid]->numOps++; 14468834Satgutier@umich.edu committedOps[tid]++; 14478834Satgutier@umich.edu 14487897Shestness@cs.utexas.edu system->totalNumInsts++; 14492292SN/A // Check for instruction-count-based events. 14502292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 14517897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 14522292SN/A} 14532292SN/A 14542292SN/Atemplate <class Impl> 14552292SN/Avoid 14561755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 14571060SN/A{ 14587720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 14592292SN/A "[sn:%lli]\n", 14607720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 14611060SN/A 14622292SN/A removeInstsThisCycle = true; 14631060SN/A 14641060SN/A // Remove the front instruction. 14652292SN/A removeList.push(inst->getInstListIt()); 14661060SN/A} 14671060SN/A 14681060SN/Atemplate <class Impl> 14691060SN/Avoid 14706221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 14711060SN/A{ 14722733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 14732292SN/A " list.\n", tid); 14741060SN/A 14752292SN/A ListIt end_it; 14761060SN/A 14772292SN/A bool rob_empty = false; 14782292SN/A 14792292SN/A if (instList.empty()) { 14802292SN/A return; 148110164Ssleimanf@umich.edu } else if (rob.isEmpty(tid)) { 14822733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 14832292SN/A end_it = instList.begin(); 14842292SN/A rob_empty = true; 14852292SN/A } else { 14862292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 14872733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 14882292SN/A } 14892292SN/A 14902292SN/A removeInstsThisCycle = true; 14912292SN/A 14922292SN/A ListIt inst_it = instList.end(); 14932292SN/A 14942292SN/A inst_it--; 14952292SN/A 14962292SN/A // Walk through the instruction list, removing any instructions 14972292SN/A // that were inserted after the given instruction iterator, end_it. 14982292SN/A while (inst_it != end_it) { 14992292SN/A assert(!instList.empty()); 15002292SN/A 15012292SN/A squashInstIt(inst_it, tid); 15022292SN/A 15032292SN/A inst_it--; 15042292SN/A } 15052292SN/A 15062292SN/A // If the ROB was empty, then we actually need to remove the first 15072292SN/A // instruction as well. 15082292SN/A if (rob_empty) { 15092292SN/A squashInstIt(inst_it, tid); 15102292SN/A } 15111060SN/A} 15121060SN/A 15131060SN/Atemplate <class Impl> 15141060SN/Avoid 15156221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 15161062SN/A{ 15172292SN/A assert(!instList.empty()); 15182292SN/A 15192292SN/A removeInstsThisCycle = true; 15202292SN/A 15212292SN/A ListIt inst_iter = instList.end(); 15222292SN/A 15232292SN/A inst_iter--; 15242292SN/A 15252733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 15262292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15272292SN/A tid, seq_num, (*inst_iter)->seqNum); 15281062SN/A 15292292SN/A while ((*inst_iter)->seqNum > seq_num) { 15301062SN/A 15312292SN/A bool break_loop = (inst_iter == instList.begin()); 15321062SN/A 15332292SN/A squashInstIt(inst_iter, tid); 15341062SN/A 15352292SN/A inst_iter--; 15361062SN/A 15372292SN/A if (break_loop) 15382292SN/A break; 15392292SN/A } 15402292SN/A} 15412292SN/A 15422292SN/Atemplate <class Impl> 15432292SN/Ainline void 15446221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 15452292SN/A{ 15462292SN/A if ((*instIt)->threadNumber == tid) { 15472733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 15487720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15492292SN/A (*instIt)->threadNumber, 15502292SN/A (*instIt)->seqNum, 15517720Sgblack@eecs.umich.edu (*instIt)->pcState()); 15521062SN/A 15531062SN/A // Mark it as squashed. 15542292SN/A (*instIt)->setSquashed(); 15552292SN/A 15562325SN/A // @todo: Formulate a consistent method for deleting 15572325SN/A // instructions from the instruction list 15582292SN/A // Remove the instruction from the list. 15592292SN/A removeList.push(instIt); 15602292SN/A } 15612292SN/A} 15622292SN/A 15632292SN/Atemplate <class Impl> 15642292SN/Avoid 15652292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 15662292SN/A{ 15672292SN/A while (!removeList.empty()) { 15682733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 15697720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15702292SN/A (*removeList.front())->threadNumber, 15712292SN/A (*removeList.front())->seqNum, 15727720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 15732292SN/A 15742292SN/A instList.erase(removeList.front()); 15752292SN/A 15762292SN/A removeList.pop(); 15771062SN/A } 15781062SN/A 15792292SN/A removeInstsThisCycle = false; 15801062SN/A} 15812325SN/A/* 15821062SN/Atemplate <class Impl> 15831062SN/Avoid 15841755SN/AFullO3CPU<Impl>::removeAllInsts() 15851060SN/A{ 15861060SN/A instList.clear(); 15871060SN/A} 15882325SN/A*/ 15891060SN/Atemplate <class Impl> 15901060SN/Avoid 15911755SN/AFullO3CPU<Impl>::dumpInsts() 15921060SN/A{ 15931060SN/A int num = 0; 15941060SN/A 15952292SN/A ListIt inst_list_it = instList.begin(); 15962292SN/A 15972292SN/A cprintf("Dumping Instruction List\n"); 15982292SN/A 15992292SN/A while (inst_list_it != instList.end()) { 16002292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 16012292SN/A "Squashed:%i\n\n", 16027720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 16032292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16042292SN/A (*inst_list_it)->isSquashed()); 16051060SN/A inst_list_it++; 16061060SN/A ++num; 16071060SN/A } 16081060SN/A} 16092325SN/A/* 16101060SN/Atemplate <class Impl> 16111060SN/Avoid 16121755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 16131060SN/A{ 16141060SN/A iew.wakeDependents(inst); 16151060SN/A} 16162325SN/A*/ 16172292SN/Atemplate <class Impl> 16182292SN/Avoid 16192292SN/AFullO3CPU<Impl>::wakeCPU() 16202292SN/A{ 16212325SN/A if (activityRec.active() || tickEvent.scheduled()) { 16222325SN/A DPRINTF(Activity, "CPU already running.\n"); 16232292SN/A return; 16242292SN/A } 16252292SN/A 16262325SN/A DPRINTF(Activity, "Waking up CPU\n"); 16272325SN/A 16289180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 16299180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 16309179Sandreas.hansson@arm.com if (cycles != 0) 16319179Sandreas.hansson@arm.com --cycles; 16329179Sandreas.hansson@arm.com idleCycles += cycles; 16339179Sandreas.hansson@arm.com numCycles += cycles; 16342292SN/A 16359648Sdam.sunwoo@arm.com schedule(tickEvent, clockEdge()); 16362292SN/A} 16372292SN/A 16385807Snate@binkert.orgtemplate <class Impl> 16395807Snate@binkert.orgvoid 16405807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 16415807Snate@binkert.org{ 16425807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 16435807Snate@binkert.org return; 16445807Snate@binkert.org 16455807Snate@binkert.org this->wakeCPU(); 16465807Snate@binkert.org 16475807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 16485807Snate@binkert.org this->threadContexts[0]->activate(); 16495807Snate@binkert.org} 16505807Snate@binkert.org 16512292SN/Atemplate <class Impl> 16526221Snate@binkert.orgThreadID 16532292SN/AFullO3CPU<Impl>::getFreeTid() 16542292SN/A{ 16556221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 16566221Snate@binkert.org if (!tids[tid]) { 16576221Snate@binkert.org tids[tid] = true; 16586221Snate@binkert.org return tid; 16592292SN/A } 16602292SN/A } 16612292SN/A 16626221Snate@binkert.org return InvalidThreadID; 16632292SN/A} 16642292SN/A 16652292SN/Atemplate <class Impl> 16662292SN/Avoid 16672292SN/AFullO3CPU<Impl>::updateThreadPriority() 16682292SN/A{ 16696221Snate@binkert.org if (activeThreads.size() > 1) { 16702292SN/A //DEFAULT TO ROUND ROBIN SCHEME 16712292SN/A //e.g. Move highest priority to end of thread list 16726221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 16732292SN/A 16742292SN/A unsigned high_thread = *list_begin; 16752292SN/A 16762292SN/A activeThreads.erase(list_begin); 16772292SN/A 16782292SN/A activeThreads.push_back(high_thread); 16792292SN/A } 16802292SN/A} 16811060SN/A 16821755SN/A// Forward declaration of FullO3CPU. 16832818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1684