commit_impl.hh revision 9427:ddf45c1d54d4
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include <algorithm> 45#include <string> 46 47#include "arch/utility.hh" 48#include "base/loader/symtab.hh" 49#include "base/cp_annotate.hh" 50#include "config/the_isa.hh" 51#include "cpu/checker/cpu.hh" 52#include "cpu/o3/commit.hh" 53#include "cpu/o3/thread_state.hh" 54#include "cpu/base.hh" 55#include "cpu/exetrace.hh" 56#include "cpu/timebuf.hh" 57#include "debug/Activity.hh" 58#include "debug/Commit.hh" 59#include "debug/CommitRate.hh" 60#include "debug/ExecFaulting.hh" 61#include "params/DerivO3CPU.hh" 62#include "sim/faults.hh" 63#include "sim/full_system.hh" 64 65using namespace std; 66 67template <class Impl> 68DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 69 ThreadID _tid) 70 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid) 71{ 72} 73 74template <class Impl> 75void 76DefaultCommit<Impl>::TrapEvent::process() 77{ 78 // This will get reset by commit if it was switched out at the 79 // time of this event processing. 80 commit->trapSquash[tid] = true; 81} 82 83template <class Impl> 84const char * 85DefaultCommit<Impl>::TrapEvent::description() const 86{ 87 return "Trap"; 88} 89 90template <class Impl> 91DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 92 : cpu(_cpu), 93 squashCounter(0), 94 iewToCommitDelay(params->iewToCommitDelay), 95 commitToIEWDelay(params->commitToIEWDelay), 96 renameToROBDelay(params->renameToROBDelay), 97 fetchToCommitDelay(params->commitToFetchDelay), 98 renameWidth(params->renameWidth), 99 commitWidth(params->commitWidth), 100 numThreads(params->numThreads), 101 drainPending(false), 102 switchedOut(false), 103 trapLatency(params->trapLatency), 104 canHandleInterrupts(true) 105{ 106 _status = Active; 107 _nextStatus = Inactive; 108 std::string policy = params->smtCommitPolicy; 109 110 //Convert string to lowercase 111 std::transform(policy.begin(), policy.end(), policy.begin(), 112 (int(*)(int)) tolower); 113 114 //Assign commit policy 115 if (policy == "aggressive"){ 116 commitPolicy = Aggressive; 117 118 DPRINTF(Commit,"Commit Policy set to Aggressive.\n"); 119 } else if (policy == "roundrobin"){ 120 commitPolicy = RoundRobin; 121 122 //Set-Up Priority List 123 for (ThreadID tid = 0; tid < numThreads; tid++) { 124 priority_list.push_back(tid); 125 } 126 127 DPRINTF(Commit,"Commit Policy set to Round Robin.\n"); 128 } else if (policy == "oldestready"){ 129 commitPolicy = OldestReady; 130 131 DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 132 } else { 133 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 134 "RoundRobin,OldestReady}"); 135 } 136 137 for (ThreadID tid = 0; tid < numThreads; tid++) { 138 commitStatus[tid] = Idle; 139 changedROBNumEntries[tid] = false; 140 checkEmptyROB[tid] = false; 141 trapInFlight[tid] = false; 142 committedStores[tid] = false; 143 trapSquash[tid] = false; 144 tcSquash[tid] = false; 145 pc[tid].set(0); 146 lastCommitedSeqNum[tid] = 0; 147 } 148 interrupt = NoFault; 149} 150 151template <class Impl> 152std::string 153DefaultCommit<Impl>::name() const 154{ 155 return cpu->name() + ".commit"; 156} 157 158template <class Impl> 159void 160DefaultCommit<Impl>::regStats() 161{ 162 using namespace Stats; 163 commitSquashedInsts 164 .name(name() + ".commitSquashedInsts") 165 .desc("The number of squashed insts skipped by commit") 166 .prereq(commitSquashedInsts); 167 commitSquashEvents 168 .name(name() + ".commitSquashEvents") 169 .desc("The number of times commit is told to squash") 170 .prereq(commitSquashEvents); 171 commitNonSpecStalls 172 .name(name() + ".commitNonSpecStalls") 173 .desc("The number of times commit has been forced to stall to " 174 "communicate backwards") 175 .prereq(commitNonSpecStalls); 176 branchMispredicts 177 .name(name() + ".branchMispredicts") 178 .desc("The number of times a branch was mispredicted") 179 .prereq(branchMispredicts); 180 numCommittedDist 181 .init(0,commitWidth,1) 182 .name(name() + ".committed_per_cycle") 183 .desc("Number of insts commited each cycle") 184 .flags(Stats::pdf) 185 ; 186 187 instsCommitted 188 .init(cpu->numThreads) 189 .name(name() + ".committedInsts") 190 .desc("Number of instructions committed") 191 .flags(total) 192 ; 193 194 opsCommitted 195 .init(cpu->numThreads) 196 .name(name() + ".committedOps") 197 .desc("Number of ops (including micro ops) committed") 198 .flags(total) 199 ; 200 201 statComSwp 202 .init(cpu->numThreads) 203 .name(name() + ".swp_count") 204 .desc("Number of s/w prefetches committed") 205 .flags(total) 206 ; 207 208 statComRefs 209 .init(cpu->numThreads) 210 .name(name() + ".refs") 211 .desc("Number of memory references committed") 212 .flags(total) 213 ; 214 215 statComLoads 216 .init(cpu->numThreads) 217 .name(name() + ".loads") 218 .desc("Number of loads committed") 219 .flags(total) 220 ; 221 222 statComMembars 223 .init(cpu->numThreads) 224 .name(name() + ".membars") 225 .desc("Number of memory barriers committed") 226 .flags(total) 227 ; 228 229 statComBranches 230 .init(cpu->numThreads) 231 .name(name() + ".branches") 232 .desc("Number of branches committed") 233 .flags(total) 234 ; 235 236 statComFloating 237 .init(cpu->numThreads) 238 .name(name() + ".fp_insts") 239 .desc("Number of committed floating point instructions.") 240 .flags(total) 241 ; 242 243 statComInteger 244 .init(cpu->numThreads) 245 .name(name()+".int_insts") 246 .desc("Number of committed integer instructions.") 247 .flags(total) 248 ; 249 250 statComFunctionCalls 251 .init(cpu->numThreads) 252 .name(name()+".function_calls") 253 .desc("Number of function calls committed.") 254 .flags(total) 255 ; 256 257 commitEligible 258 .init(cpu->numThreads) 259 .name(name() + ".bw_limited") 260 .desc("number of insts not committed due to BW limits") 261 .flags(total) 262 ; 263 264 commitEligibleSamples 265 .name(name() + ".bw_lim_events") 266 .desc("number cycles where commit BW limit reached") 267 ; 268} 269 270template <class Impl> 271void 272DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 273{ 274 thread = threads; 275} 276 277template <class Impl> 278void 279DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 280{ 281 timeBuffer = tb_ptr; 282 283 // Setup wire to send information back to IEW. 284 toIEW = timeBuffer->getWire(0); 285 286 // Setup wire to read data from IEW (for the ROB). 287 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 288} 289 290template <class Impl> 291void 292DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 293{ 294 fetchQueue = fq_ptr; 295 296 // Setup wire to get instructions from rename (for the ROB). 297 fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 298} 299 300template <class Impl> 301void 302DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 303{ 304 renameQueue = rq_ptr; 305 306 // Setup wire to get instructions from rename (for the ROB). 307 fromRename = renameQueue->getWire(-renameToROBDelay); 308} 309 310template <class Impl> 311void 312DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 313{ 314 iewQueue = iq_ptr; 315 316 // Setup wire to get instructions from IEW. 317 fromIEW = iewQueue->getWire(-iewToCommitDelay); 318} 319 320template <class Impl> 321void 322DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 323{ 324 iewStage = iew_stage; 325} 326 327template<class Impl> 328void 329DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 330{ 331 activeThreads = at_ptr; 332} 333 334template <class Impl> 335void 336DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 337{ 338 for (ThreadID tid = 0; tid < numThreads; tid++) 339 renameMap[tid] = &rm_ptr[tid]; 340} 341 342template <class Impl> 343void 344DefaultCommit<Impl>::setROB(ROB *rob_ptr) 345{ 346 rob = rob_ptr; 347} 348 349template <class Impl> 350void 351DefaultCommit<Impl>::startupStage() 352{ 353 rob->setActiveThreads(activeThreads); 354 rob->resetEntries(); 355 356 // Broadcast the number of free entries. 357 for (ThreadID tid = 0; tid < numThreads; tid++) { 358 toIEW->commitInfo[tid].usedROB = true; 359 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 360 toIEW->commitInfo[tid].emptyROB = true; 361 } 362 363 // Commit must broadcast the number of free entries it has at the 364 // start of the simulation, so it starts as active. 365 cpu->activateStage(O3CPU::CommitIdx); 366 367 cpu->activityThisCycle(); 368} 369 370template <class Impl> 371bool 372DefaultCommit<Impl>::drain() 373{ 374 drainPending = true; 375 376 return false; 377} 378 379template <class Impl> 380void 381DefaultCommit<Impl>::switchOut() 382{ 383 switchedOut = true; 384 drainPending = false; 385 rob->switchOut(); 386} 387 388template <class Impl> 389void 390DefaultCommit<Impl>::resume() 391{ 392 drainPending = false; 393} 394 395template <class Impl> 396void 397DefaultCommit<Impl>::takeOverFrom() 398{ 399 switchedOut = false; 400 _status = Active; 401 _nextStatus = Inactive; 402 for (ThreadID tid = 0; tid < numThreads; tid++) { 403 commitStatus[tid] = Idle; 404 changedROBNumEntries[tid] = false; 405 trapSquash[tid] = false; 406 tcSquash[tid] = false; 407 } 408 squashCounter = 0; 409 rob->takeOverFrom(); 410} 411 412template <class Impl> 413void 414DefaultCommit<Impl>::updateStatus() 415{ 416 // reset ROB changed variable 417 list<ThreadID>::iterator threads = activeThreads->begin(); 418 list<ThreadID>::iterator end = activeThreads->end(); 419 420 while (threads != end) { 421 ThreadID tid = *threads++; 422 423 changedROBNumEntries[tid] = false; 424 425 // Also check if any of the threads has a trap pending 426 if (commitStatus[tid] == TrapPending || 427 commitStatus[tid] == FetchTrapPending) { 428 _nextStatus = Active; 429 } 430 } 431 432 if (_nextStatus == Inactive && _status == Active) { 433 DPRINTF(Activity, "Deactivating stage.\n"); 434 cpu->deactivateStage(O3CPU::CommitIdx); 435 } else if (_nextStatus == Active && _status == Inactive) { 436 DPRINTF(Activity, "Activating stage.\n"); 437 cpu->activateStage(O3CPU::CommitIdx); 438 } 439 440 _status = _nextStatus; 441} 442 443template <class Impl> 444void 445DefaultCommit<Impl>::setNextStatus() 446{ 447 int squashes = 0; 448 449 list<ThreadID>::iterator threads = activeThreads->begin(); 450 list<ThreadID>::iterator end = activeThreads->end(); 451 452 while (threads != end) { 453 ThreadID tid = *threads++; 454 455 if (commitStatus[tid] == ROBSquashing) { 456 squashes++; 457 } 458 } 459 460 squashCounter = squashes; 461 462 // If commit is currently squashing, then it will have activity for the 463 // next cycle. Set its next status as active. 464 if (squashCounter) { 465 _nextStatus = Active; 466 } 467} 468 469template <class Impl> 470bool 471DefaultCommit<Impl>::changedROBEntries() 472{ 473 list<ThreadID>::iterator threads = activeThreads->begin(); 474 list<ThreadID>::iterator end = activeThreads->end(); 475 476 while (threads != end) { 477 ThreadID tid = *threads++; 478 479 if (changedROBNumEntries[tid]) { 480 return true; 481 } 482 } 483 484 return false; 485} 486 487template <class Impl> 488size_t 489DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 490{ 491 return rob->numFreeEntries(tid); 492} 493 494template <class Impl> 495void 496DefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 497{ 498 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 499 500 TrapEvent *trap = new TrapEvent(this, tid); 501 502 cpu->schedule(trap, cpu->clockEdge(trapLatency)); 503 trapInFlight[tid] = true; 504 thread[tid]->trapPending = true; 505} 506 507template <class Impl> 508void 509DefaultCommit<Impl>::generateTCEvent(ThreadID tid) 510{ 511 assert(!trapInFlight[tid]); 512 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 513 514 tcSquash[tid] = true; 515} 516 517template <class Impl> 518void 519DefaultCommit<Impl>::squashAll(ThreadID tid) 520{ 521 // If we want to include the squashing instruction in the squash, 522 // then use one older sequence number. 523 // Hopefully this doesn't mess things up. Basically I want to squash 524 // all instructions of this thread. 525 InstSeqNum squashed_inst = rob->isEmpty() ? 526 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 527 528 // All younger instructions will be squashed. Set the sequence 529 // number as the youngest instruction in the ROB (0 in this case. 530 // Hopefully nothing breaks.) 531 youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 532 533 rob->squash(squashed_inst, tid); 534 changedROBNumEntries[tid] = true; 535 536 // Send back the sequence number of the squashed instruction. 537 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 538 539 // Send back the squash signal to tell stages that they should 540 // squash. 541 toIEW->commitInfo[tid].squash = true; 542 543 // Send back the rob squashing signal so other stages know that 544 // the ROB is in the process of squashing. 545 toIEW->commitInfo[tid].robSquashing = true; 546 547 toIEW->commitInfo[tid].mispredictInst = NULL; 548 toIEW->commitInfo[tid].squashInst = NULL; 549 550 toIEW->commitInfo[tid].pc = pc[tid]; 551} 552 553template <class Impl> 554void 555DefaultCommit<Impl>::squashFromTrap(ThreadID tid) 556{ 557 squashAll(tid); 558 559 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 560 561 thread[tid]->trapPending = false; 562 thread[tid]->noSquashFromTC = false; 563 trapInFlight[tid] = false; 564 565 trapSquash[tid] = false; 566 567 commitStatus[tid] = ROBSquashing; 568 cpu->activityThisCycle(); 569} 570 571template <class Impl> 572void 573DefaultCommit<Impl>::squashFromTC(ThreadID tid) 574{ 575 squashAll(tid); 576 577 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 578 579 thread[tid]->noSquashFromTC = false; 580 assert(!thread[tid]->trapPending); 581 582 commitStatus[tid] = ROBSquashing; 583 cpu->activityThisCycle(); 584 585 tcSquash[tid] = false; 586} 587 588template <class Impl> 589void 590DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst, 591 uint64_t squash_after_seq_num) 592{ 593 youngestSeqNum[tid] = squash_after_seq_num; 594 595 rob->squash(squash_after_seq_num, tid); 596 changedROBNumEntries[tid] = true; 597 598 // Send back the sequence number of the squashed instruction. 599 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num; 600 601 toIEW->commitInfo[tid].squashInst = head_inst; 602 // Send back the squash signal to tell stages that they should squash. 603 toIEW->commitInfo[tid].squash = true; 604 605 // Send back the rob squashing signal so other stages know that 606 // the ROB is in the process of squashing. 607 toIEW->commitInfo[tid].robSquashing = true; 608 609 toIEW->commitInfo[tid].mispredictInst = NULL; 610 611 toIEW->commitInfo[tid].pc = pc[tid]; 612 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 613 tid, squash_after_seq_num); 614 commitStatus[tid] = ROBSquashing; 615} 616 617template <class Impl> 618void 619DefaultCommit<Impl>::tick() 620{ 621 wroteToTimeBuffer = false; 622 _nextStatus = Inactive; 623 624 if (drainPending && cpu->instList.empty() && !iewStage->hasStoresToWB() && 625 interrupt == NoFault) { 626 cpu->signalDrained(); 627 drainPending = false; 628 return; 629 } 630 631 if (activeThreads->empty()) 632 return; 633 634 list<ThreadID>::iterator threads = activeThreads->begin(); 635 list<ThreadID>::iterator end = activeThreads->end(); 636 637 // Check if any of the threads are done squashing. Change the 638 // status if they are done. 639 while (threads != end) { 640 ThreadID tid = *threads++; 641 642 // Clear the bit saying if the thread has committed stores 643 // this cycle. 644 committedStores[tid] = false; 645 646 if (commitStatus[tid] == ROBSquashing) { 647 648 if (rob->isDoneSquashing(tid)) { 649 commitStatus[tid] = Running; 650 } else { 651 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 652 " insts this cycle.\n", tid); 653 rob->doSquash(tid); 654 toIEW->commitInfo[tid].robSquashing = true; 655 wroteToTimeBuffer = true; 656 } 657 } 658 } 659 660 commit(); 661 662 markCompletedInsts(); 663 664 threads = activeThreads->begin(); 665 666 while (threads != end) { 667 ThreadID tid = *threads++; 668 669 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 670 // The ROB has more instructions it can commit. Its next status 671 // will be active. 672 _nextStatus = Active; 673 674 DynInstPtr inst = rob->readHeadInst(tid); 675 676 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 677 " ROB and ready to commit\n", 678 tid, inst->seqNum, inst->pcState()); 679 680 } else if (!rob->isEmpty(tid)) { 681 DynInstPtr inst = rob->readHeadInst(tid); 682 683 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 684 "%s is head of ROB and not ready\n", 685 tid, inst->seqNum, inst->pcState()); 686 } 687 688 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 689 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 690 } 691 692 693 if (wroteToTimeBuffer) { 694 DPRINTF(Activity, "Activity This Cycle.\n"); 695 cpu->activityThisCycle(); 696 } 697 698 updateStatus(); 699} 700 701template <class Impl> 702void 703DefaultCommit<Impl>::handleInterrupt() 704{ 705 // Verify that we still have an interrupt to handle 706 if (!cpu->checkInterrupts(cpu->tcBase(0))) { 707 DPRINTF(Commit, "Pending interrupt is cleared by master before " 708 "it got handled. Restart fetching from the orig path.\n"); 709 toIEW->commitInfo[0].clearInterrupt = true; 710 interrupt = NoFault; 711 return; 712 } 713 714 // Wait until all in flight instructions are finished before enterring 715 // the interrupt. 716 if (canHandleInterrupts && cpu->instList.empty()) { 717 // Squash or record that I need to squash this cycle if 718 // an interrupt needed to be handled. 719 DPRINTF(Commit, "Interrupt detected.\n"); 720 721 // Clear the interrupt now that it's going to be handled 722 toIEW->commitInfo[0].clearInterrupt = true; 723 724 assert(!thread[0]->noSquashFromTC); 725 thread[0]->noSquashFromTC = true; 726 727 if (cpu->checker) { 728 cpu->checker->handlePendingInt(); 729 } 730 731 // CPU will handle interrupt. 732 cpu->processInterrupts(interrupt); 733 734 thread[0]->noSquashFromTC = false; 735 736 commitStatus[0] = TrapPending; 737 738 // Generate trap squash event. 739 generateTrapEvent(0); 740 741 interrupt = NoFault; 742 } else { 743 DPRINTF(Commit, "Interrupt pending: instruction is %sin " 744 "flight, ROB is %sempty\n", 745 canHandleInterrupts ? "not " : "", 746 cpu->instList.empty() ? "" : "not " ); 747 } 748} 749 750template <class Impl> 751void 752DefaultCommit<Impl>::propagateInterrupt() 753{ 754 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 755 tcSquash[0]) 756 return; 757 758 // Process interrupts if interrupts are enabled, not in PAL 759 // mode, and no other traps or external squashes are currently 760 // pending. 761 // @todo: Allow other threads to handle interrupts. 762 763 // Get any interrupt that happened 764 interrupt = cpu->getInterrupts(); 765 766 // Tell fetch that there is an interrupt pending. This 767 // will make fetch wait until it sees a non PAL-mode PC, 768 // at which point it stops fetching instructions. 769 if (interrupt != NoFault) 770 toIEW->commitInfo[0].interruptPending = true; 771} 772 773template <class Impl> 774void 775DefaultCommit<Impl>::commit() 776{ 777 if (FullSystem) { 778 // Check if we have a interrupt and get read to handle it 779 if (cpu->checkInterrupts(cpu->tcBase(0))) 780 propagateInterrupt(); 781 } 782 783 //////////////////////////////////// 784 // Check for any possible squashes, handle them first 785 //////////////////////////////////// 786 list<ThreadID>::iterator threads = activeThreads->begin(); 787 list<ThreadID>::iterator end = activeThreads->end(); 788 789 while (threads != end) { 790 ThreadID tid = *threads++; 791 792 // Not sure which one takes priority. I think if we have 793 // both, that's a bad sign. 794 if (trapSquash[tid] == true) { 795 assert(!tcSquash[tid]); 796 squashFromTrap(tid); 797 } else if (tcSquash[tid] == true) { 798 assert(commitStatus[tid] != TrapPending); 799 squashFromTC(tid); 800 } 801 802 // Squashed sequence number must be older than youngest valid 803 // instruction in the ROB. This prevents squashes from younger 804 // instructions overriding squashes from older instructions. 805 if (fromIEW->squash[tid] && 806 commitStatus[tid] != TrapPending && 807 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 808 809 if (fromIEW->mispredictInst[tid]) { 810 DPRINTF(Commit, 811 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", 812 tid, 813 fromIEW->mispredictInst[tid]->instAddr(), 814 fromIEW->squashedSeqNum[tid]); 815 } else { 816 DPRINTF(Commit, 817 "[tid:%i]: Squashing due to order violation [sn:%i]\n", 818 tid, fromIEW->squashedSeqNum[tid]); 819 } 820 821 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 822 tid, 823 fromIEW->pc[tid].nextInstAddr()); 824 825 commitStatus[tid] = ROBSquashing; 826 827 // If we want to include the squashing instruction in the squash, 828 // then use one older sequence number. 829 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 830 831 if (fromIEW->includeSquashInst[tid] == true) { 832 squashed_inst--; 833 } 834 835 // All younger instructions will be squashed. Set the sequence 836 // number as the youngest instruction in the ROB. 837 youngestSeqNum[tid] = squashed_inst; 838 839 rob->squash(squashed_inst, tid); 840 changedROBNumEntries[tid] = true; 841 842 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 843 844 toIEW->commitInfo[tid].squash = true; 845 846 // Send back the rob squashing signal so other stages know that 847 // the ROB is in the process of squashing. 848 toIEW->commitInfo[tid].robSquashing = true; 849 850 toIEW->commitInfo[tid].mispredictInst = 851 fromIEW->mispredictInst[tid]; 852 toIEW->commitInfo[tid].branchTaken = 853 fromIEW->branchTaken[tid]; 854 toIEW->commitInfo[tid].squashInst = 855 rob->findInst(tid, squashed_inst); 856 if (toIEW->commitInfo[tid].mispredictInst) { 857 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) { 858 toIEW->commitInfo[tid].branchTaken = true; 859 } 860 } 861 862 toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 863 864 if (toIEW->commitInfo[tid].mispredictInst) { 865 ++branchMispredicts; 866 } 867 } 868 869 } 870 871 setNextStatus(); 872 873 if (squashCounter != numThreads) { 874 // If we're not currently squashing, then get instructions. 875 getInsts(); 876 877 // Try to commit any instructions. 878 commitInsts(); 879 } 880 881 //Check for any activity 882 threads = activeThreads->begin(); 883 884 while (threads != end) { 885 ThreadID tid = *threads++; 886 887 if (changedROBNumEntries[tid]) { 888 toIEW->commitInfo[tid].usedROB = true; 889 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 890 891 wroteToTimeBuffer = true; 892 changedROBNumEntries[tid] = false; 893 if (rob->isEmpty(tid)) 894 checkEmptyROB[tid] = true; 895 } 896 897 // ROB is only considered "empty" for previous stages if: a) 898 // ROB is empty, b) there are no outstanding stores, c) IEW 899 // stage has received any information regarding stores that 900 // committed. 901 // c) is checked by making sure to not consider the ROB empty 902 // on the same cycle as when stores have been committed. 903 // @todo: Make this handle multi-cycle communication between 904 // commit and IEW. 905 if (checkEmptyROB[tid] && rob->isEmpty(tid) && 906 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 907 checkEmptyROB[tid] = false; 908 toIEW->commitInfo[tid].usedROB = true; 909 toIEW->commitInfo[tid].emptyROB = true; 910 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 911 wroteToTimeBuffer = true; 912 } 913 914 } 915} 916 917template <class Impl> 918void 919DefaultCommit<Impl>::commitInsts() 920{ 921 //////////////////////////////////// 922 // Handle commit 923 // Note that commit will be handled prior to putting new 924 // instructions in the ROB so that the ROB only tries to commit 925 // instructions it has in this current cycle, and not instructions 926 // it is writing in during this cycle. Can't commit and squash 927 // things at the same time... 928 //////////////////////////////////// 929 930 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 931 932 unsigned num_committed = 0; 933 934 DynInstPtr head_inst; 935 936 // Commit as many instructions as possible until the commit bandwidth 937 // limit is reached, or it becomes impossible to commit any more. 938 while (num_committed < commitWidth) { 939 // Check for any interrupt that we've already squashed for 940 // and start processing it. 941 if (interrupt != NoFault) 942 handleInterrupt(); 943 944 int commit_thread = getCommittingThread(); 945 946 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 947 break; 948 949 head_inst = rob->readHeadInst(commit_thread); 950 951 ThreadID tid = head_inst->threadNumber; 952 953 assert(tid == commit_thread); 954 955 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 956 head_inst->seqNum, tid); 957 958 // If the head instruction is squashed, it is ready to retire 959 // (be removed from the ROB) at any time. 960 if (head_inst->isSquashed()) { 961 962 DPRINTF(Commit, "Retiring squashed instruction from " 963 "ROB.\n"); 964 965 rob->retireHead(commit_thread); 966 967 ++commitSquashedInsts; 968 969 // Record that the number of ROB entries has changed. 970 changedROBNumEntries[tid] = true; 971 } else { 972 pc[tid] = head_inst->pcState(); 973 974 // Increment the total number of non-speculative instructions 975 // executed. 976 // Hack for now: it really shouldn't happen until after the 977 // commit is deemed to be successful, but this count is needed 978 // for syscalls. 979 thread[tid]->funcExeInst++; 980 981 // Try to commit the head instruction. 982 bool commit_success = commitHead(head_inst, num_committed); 983 984 if (commit_success) { 985 ++num_committed; 986 987 changedROBNumEntries[tid] = true; 988 989 // Set the doneSeqNum to the youngest committed instruction. 990 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 991 992 if (tid == 0) { 993 canHandleInterrupts = (!head_inst->isDelayedCommit()) && 994 ((THE_ISA != ALPHA_ISA) || 995 (!(pc[0].instAddr() & 0x3))); 996 } 997 998 // Updates misc. registers. 999 head_inst->updateMiscRegs(); 1000 1001 cpu->traceFunctions(pc[tid].instAddr()); 1002 1003 TheISA::advancePC(pc[tid], head_inst->staticInst); 1004 1005 // Keep track of the last sequence number commited 1006 lastCommitedSeqNum[tid] = head_inst->seqNum; 1007 1008 // If this is an instruction that doesn't play nicely with 1009 // others squash everything and restart fetch 1010 if (head_inst->isSquashAfter()) 1011 squashAfter(tid, head_inst, head_inst->seqNum); 1012 1013 int count = 0; 1014 Addr oldpc; 1015 // Debug statement. Checks to make sure we're not 1016 // currently updating state while handling PC events. 1017 assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending); 1018 do { 1019 oldpc = pc[tid].instAddr(); 1020 cpu->system->pcEventQueue.service(thread[tid]->getTC()); 1021 count++; 1022 } while (oldpc != pc[tid].instAddr()); 1023 if (count > 1) { 1024 DPRINTF(Commit, 1025 "PC skip function event, stopping commit\n"); 1026 break; 1027 } 1028 } else { 1029 DPRINTF(Commit, "Unable to commit head instruction PC:%s " 1030 "[tid:%i] [sn:%i].\n", 1031 head_inst->pcState(), tid ,head_inst->seqNum); 1032 break; 1033 } 1034 } 1035 } 1036 1037 DPRINTF(CommitRate, "%i\n", num_committed); 1038 numCommittedDist.sample(num_committed); 1039 1040 if (num_committed == commitWidth) { 1041 commitEligibleSamples++; 1042 } 1043} 1044 1045template <class Impl> 1046bool 1047DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 1048{ 1049 assert(head_inst); 1050 1051 ThreadID tid = head_inst->threadNumber; 1052 1053 // If the instruction is not executed yet, then it will need extra 1054 // handling. Signal backwards that it should be executed. 1055 if (!head_inst->isExecuted()) { 1056 // Keep this number correct. We have not yet actually executed 1057 // and committed this instruction. 1058 thread[tid]->funcExeInst--; 1059 1060 if (head_inst->isNonSpeculative() || 1061 head_inst->isStoreConditional() || 1062 head_inst->isMemBarrier() || 1063 head_inst->isWriteBarrier()) { 1064 1065 DPRINTF(Commit, "Encountered a barrier or non-speculative " 1066 "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 1067 head_inst->seqNum, head_inst->pcState()); 1068 1069 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 1070 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1071 return false; 1072 } 1073 1074 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1075 1076 // Change the instruction so it won't try to commit again until 1077 // it is executed. 1078 head_inst->clearCanCommit(); 1079 1080 ++commitNonSpecStalls; 1081 1082 return false; 1083 } else if (head_inst->isLoad()) { 1084 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 1085 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1086 return false; 1087 } 1088 1089 assert(head_inst->uncacheable()); 1090 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 1091 head_inst->seqNum, head_inst->pcState()); 1092 1093 // Send back the non-speculative instruction's sequence 1094 // number. Tell the lsq to re-execute the load. 1095 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1096 toIEW->commitInfo[tid].uncached = true; 1097 toIEW->commitInfo[tid].uncachedLoad = head_inst; 1098 1099 head_inst->clearCanCommit(); 1100 1101 return false; 1102 } else { 1103 panic("Trying to commit un-executed instruction " 1104 "of unknown type!\n"); 1105 } 1106 } 1107 1108 if (head_inst->isThreadSync()) { 1109 // Not handled for now. 1110 panic("Thread sync instructions are not handled yet.\n"); 1111 } 1112 1113 // Check if the instruction caused a fault. If so, trap. 1114 Fault inst_fault = head_inst->getFault(); 1115 1116 // Stores mark themselves as completed. 1117 if (!head_inst->isStore() && inst_fault == NoFault) { 1118 head_inst->setCompleted(); 1119 } 1120 1121 // Use checker prior to updating anything due to traps or PC 1122 // based events. 1123 if (cpu->checker) { 1124 cpu->checker->verify(head_inst); 1125 } 1126 1127 if (inst_fault != NoFault) { 1128 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 1129 head_inst->seqNum, head_inst->pcState()); 1130 1131 if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 1132 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1133 return false; 1134 } 1135 1136 head_inst->setCompleted(); 1137 1138 if (cpu->checker) { 1139 // Need to check the instruction before its fault is processed 1140 cpu->checker->verify(head_inst); 1141 } 1142 1143 assert(!thread[tid]->noSquashFromTC); 1144 1145 // Mark that we're in state update mode so that the trap's 1146 // execution doesn't generate extra squashes. 1147 thread[tid]->noSquashFromTC = true; 1148 1149 // Execute the trap. Although it's slightly unrealistic in 1150 // terms of timing (as it doesn't wait for the full timing of 1151 // the trap event to complete before updating state), it's 1152 // needed to update the state as soon as possible. This 1153 // prevents external agents from changing any specific state 1154 // that the trap need. 1155 cpu->trap(inst_fault, tid, head_inst->staticInst); 1156 1157 // Exit state update mode to avoid accidental updating. 1158 thread[tid]->noSquashFromTC = false; 1159 1160 commitStatus[tid] = TrapPending; 1161 1162 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 1163 head_inst->seqNum); 1164 if (head_inst->traceData) { 1165 if (DTRACE(ExecFaulting)) { 1166 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1167 head_inst->traceData->setCPSeq(thread[tid]->numOp); 1168 head_inst->traceData->dump(); 1169 } 1170 delete head_inst->traceData; 1171 head_inst->traceData = NULL; 1172 } 1173 1174 // Generate trap squash event. 1175 generateTrapEvent(tid); 1176 return false; 1177 } 1178 1179 updateComInstStats(head_inst); 1180 1181 if (FullSystem) { 1182 if (thread[tid]->profile) { 1183 thread[tid]->profilePC = head_inst->instAddr(); 1184 ProfileNode *node = thread[tid]->profile->consume( 1185 thread[tid]->getTC(), head_inst->staticInst); 1186 1187 if (node) 1188 thread[tid]->profileNode = node; 1189 } 1190 if (CPA::available()) { 1191 if (head_inst->isControl()) { 1192 ThreadContext *tc = thread[tid]->getTC(); 1193 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 1194 } 1195 } 1196 } 1197 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", 1198 head_inst->seqNum, head_inst->pcState()); 1199 if (head_inst->traceData) { 1200 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1201 head_inst->traceData->setCPSeq(thread[tid]->numOp); 1202 head_inst->traceData->dump(); 1203 delete head_inst->traceData; 1204 head_inst->traceData = NULL; 1205 } 1206 if (head_inst->isReturn()) { 1207 DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n", 1208 head_inst->seqNum, head_inst->pcState()); 1209 } 1210 1211 // Update the commit rename map 1212 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1213 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 1214 head_inst->renamedDestRegIdx(i)); 1215 } 1216 1217 // Finally clear the head ROB entry. 1218 rob->retireHead(tid); 1219 1220#if TRACING_ON 1221 head_inst->commitTick = curTick() - head_inst->fetchTick; 1222#endif 1223 1224 // If this was a store, record it for this cycle. 1225 if (head_inst->isStore()) 1226 committedStores[tid] = true; 1227 1228 // Return true to indicate that we have committed an instruction. 1229 return true; 1230} 1231 1232template <class Impl> 1233void 1234DefaultCommit<Impl>::getInsts() 1235{ 1236 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1237 1238 // Read any renamed instructions and place them into the ROB. 1239 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1240 1241 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1242 DynInstPtr inst; 1243 1244 inst = fromRename->insts[inst_num]; 1245 ThreadID tid = inst->threadNumber; 1246 1247 if (!inst->isSquashed() && 1248 commitStatus[tid] != ROBSquashing && 1249 commitStatus[tid] != TrapPending) { 1250 changedROBNumEntries[tid] = true; 1251 1252 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 1253 inst->pcState(), inst->seqNum, tid); 1254 1255 rob->insertInst(inst); 1256 1257 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1258 1259 youngestSeqNum[tid] = inst->seqNum; 1260 } else { 1261 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1262 "squashed, skipping.\n", 1263 inst->pcState(), inst->seqNum, tid); 1264 } 1265 } 1266} 1267 1268template <class Impl> 1269void 1270DefaultCommit<Impl>::skidInsert() 1271{ 1272 DPRINTF(Commit, "Attempting to any instructions from rename into " 1273 "skidBuffer.\n"); 1274 1275 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 1276 DynInstPtr inst = fromRename->insts[inst_num]; 1277 1278 if (!inst->isSquashed()) { 1279 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ", 1280 "skidBuffer.\n", inst->pcState(), inst->seqNum, 1281 inst->threadNumber); 1282 skidBuffer.push(inst); 1283 } else { 1284 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1285 "squashed, skipping.\n", 1286 inst->pcState(), inst->seqNum, inst->threadNumber); 1287 } 1288 } 1289} 1290 1291template <class Impl> 1292void 1293DefaultCommit<Impl>::markCompletedInsts() 1294{ 1295 // Grab completed insts out of the IEW instruction queue, and mark 1296 // instructions completed within the ROB. 1297 for (int inst_num = 0; 1298 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1299 ++inst_num) 1300 { 1301 if (!fromIEW->insts[inst_num]->isSquashed()) { 1302 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 1303 "within ROB.\n", 1304 fromIEW->insts[inst_num]->threadNumber, 1305 fromIEW->insts[inst_num]->pcState(), 1306 fromIEW->insts[inst_num]->seqNum); 1307 1308 // Mark the instruction as ready to commit. 1309 fromIEW->insts[inst_num]->setCanCommit(); 1310 } 1311 } 1312} 1313 1314template <class Impl> 1315bool 1316DefaultCommit<Impl>::robDoneSquashing() 1317{ 1318 list<ThreadID>::iterator threads = activeThreads->begin(); 1319 list<ThreadID>::iterator end = activeThreads->end(); 1320 1321 while (threads != end) { 1322 ThreadID tid = *threads++; 1323 1324 if (!rob->isDoneSquashing(tid)) 1325 return false; 1326 } 1327 1328 return true; 1329} 1330 1331template <class Impl> 1332void 1333DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1334{ 1335 ThreadID tid = inst->threadNumber; 1336 1337 if (!inst->isMicroop() || inst->isLastMicroop()) 1338 instsCommitted[tid]++; 1339 opsCommitted[tid]++; 1340 1341 // To match the old model, don't count nops and instruction 1342 // prefetches towards the total commit count. 1343 if (!inst->isNop() && !inst->isInstPrefetch()) { 1344 cpu->instDone(tid, inst); 1345 } 1346 1347 // 1348 // Control Instructions 1349 // 1350 if (inst->isControl()) 1351 statComBranches[tid]++; 1352 1353 // 1354 // Memory references 1355 // 1356 if (inst->isMemRef()) { 1357 statComRefs[tid]++; 1358 1359 if (inst->isLoad()) { 1360 statComLoads[tid]++; 1361 } 1362 } 1363 1364 if (inst->isMemBarrier()) { 1365 statComMembars[tid]++; 1366 } 1367 1368 // Integer Instruction 1369 if (inst->isInteger()) 1370 statComInteger[tid]++; 1371 1372 // Floating Point Instruction 1373 if (inst->isFloating()) 1374 statComFloating[tid]++; 1375 1376 // Function Calls 1377 if (inst->isCall()) 1378 statComFunctionCalls[tid]++; 1379 1380} 1381 1382//////////////////////////////////////// 1383// // 1384// SMT COMMIT POLICY MAINTAINED HERE // 1385// // 1386//////////////////////////////////////// 1387template <class Impl> 1388ThreadID 1389DefaultCommit<Impl>::getCommittingThread() 1390{ 1391 if (numThreads > 1) { 1392 switch (commitPolicy) { 1393 1394 case Aggressive: 1395 //If Policy is Aggressive, commit will call 1396 //this function multiple times per 1397 //cycle 1398 return oldestReady(); 1399 1400 case RoundRobin: 1401 return roundRobin(); 1402 1403 case OldestReady: 1404 return oldestReady(); 1405 1406 default: 1407 return InvalidThreadID; 1408 } 1409 } else { 1410 assert(!activeThreads->empty()); 1411 ThreadID tid = activeThreads->front(); 1412 1413 if (commitStatus[tid] == Running || 1414 commitStatus[tid] == Idle || 1415 commitStatus[tid] == FetchTrapPending) { 1416 return tid; 1417 } else { 1418 return InvalidThreadID; 1419 } 1420 } 1421} 1422 1423template<class Impl> 1424ThreadID 1425DefaultCommit<Impl>::roundRobin() 1426{ 1427 list<ThreadID>::iterator pri_iter = priority_list.begin(); 1428 list<ThreadID>::iterator end = priority_list.end(); 1429 1430 while (pri_iter != end) { 1431 ThreadID tid = *pri_iter; 1432 1433 if (commitStatus[tid] == Running || 1434 commitStatus[tid] == Idle || 1435 commitStatus[tid] == FetchTrapPending) { 1436 1437 if (rob->isHeadReady(tid)) { 1438 priority_list.erase(pri_iter); 1439 priority_list.push_back(tid); 1440 1441 return tid; 1442 } 1443 } 1444 1445 pri_iter++; 1446 } 1447 1448 return InvalidThreadID; 1449} 1450 1451template<class Impl> 1452ThreadID 1453DefaultCommit<Impl>::oldestReady() 1454{ 1455 unsigned oldest = 0; 1456 bool first = true; 1457 1458 list<ThreadID>::iterator threads = activeThreads->begin(); 1459 list<ThreadID>::iterator end = activeThreads->end(); 1460 1461 while (threads != end) { 1462 ThreadID tid = *threads++; 1463 1464 if (!rob->isEmpty(tid) && 1465 (commitStatus[tid] == Running || 1466 commitStatus[tid] == Idle || 1467 commitStatus[tid] == FetchTrapPending)) { 1468 1469 if (rob->isHeadReady(tid)) { 1470 1471 DynInstPtr head_inst = rob->readHeadInst(tid); 1472 1473 if (first) { 1474 oldest = tid; 1475 first = false; 1476 } else if (head_inst->seqNum < oldest) { 1477 oldest = tid; 1478 } 1479 } 1480 } 1481 } 1482 1483 if (!first) { 1484 return oldest; 1485 } else { 1486 return InvalidThreadID; 1487 } 1488} 1489