commit_impl.hh revision 9152:86c0e6ca5e7c
1/* 2 * Copyright (c) 2010-2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include <algorithm> 45#include <string> 46 47#include "arch/utility.hh" 48#include "base/loader/symtab.hh" 49#include "base/cp_annotate.hh" 50#include "config/the_isa.hh" 51#include "cpu/checker/cpu.hh" 52#include "cpu/o3/commit.hh" 53#include "cpu/o3/thread_state.hh" 54#include "cpu/base.hh" 55#include "cpu/exetrace.hh" 56#include "cpu/timebuf.hh" 57#include "debug/Activity.hh" 58#include "debug/Commit.hh" 59#include "debug/CommitRate.hh" 60#include "debug/ExecFaulting.hh" 61#include "debug/O3PipeView.hh" 62#include "params/DerivO3CPU.hh" 63#include "sim/faults.hh" 64#include "sim/full_system.hh" 65 66using namespace std; 67 68template <class Impl> 69DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 70 ThreadID _tid) 71 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid) 72{ 73} 74 75template <class Impl> 76void 77DefaultCommit<Impl>::TrapEvent::process() 78{ 79 // This will get reset by commit if it was switched out at the 80 // time of this event processing. 81 commit->trapSquash[tid] = true; 82} 83 84template <class Impl> 85const char * 86DefaultCommit<Impl>::TrapEvent::description() const 87{ 88 return "Trap"; 89} 90 91template <class Impl> 92DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 93 : cpu(_cpu), 94 squashCounter(0), 95 iewToCommitDelay(params->iewToCommitDelay), 96 commitToIEWDelay(params->commitToIEWDelay), 97 renameToROBDelay(params->renameToROBDelay), 98 fetchToCommitDelay(params->commitToFetchDelay), 99 renameWidth(params->renameWidth), 100 commitWidth(params->commitWidth), 101 numThreads(params->numThreads), 102 drainPending(false), 103 switchedOut(false), 104 trapLatency(params->trapLatency), 105 canHandleInterrupts(true) 106{ 107 _status = Active; 108 _nextStatus = Inactive; 109 std::string policy = params->smtCommitPolicy; 110 111 //Convert string to lowercase 112 std::transform(policy.begin(), policy.end(), policy.begin(), 113 (int(*)(int)) tolower); 114 115 //Assign commit policy 116 if (policy == "aggressive"){ 117 commitPolicy = Aggressive; 118 119 DPRINTF(Commit,"Commit Policy set to Aggressive.\n"); 120 } else if (policy == "roundrobin"){ 121 commitPolicy = RoundRobin; 122 123 //Set-Up Priority List 124 for (ThreadID tid = 0; tid < numThreads; tid++) { 125 priority_list.push_back(tid); 126 } 127 128 DPRINTF(Commit,"Commit Policy set to Round Robin.\n"); 129 } else if (policy == "oldestready"){ 130 commitPolicy = OldestReady; 131 132 DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 133 } else { 134 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 135 "RoundRobin,OldestReady}"); 136 } 137 138 for (ThreadID tid = 0; tid < numThreads; tid++) { 139 commitStatus[tid] = Idle; 140 changedROBNumEntries[tid] = false; 141 checkEmptyROB[tid] = false; 142 trapInFlight[tid] = false; 143 committedStores[tid] = false; 144 trapSquash[tid] = false; 145 tcSquash[tid] = false; 146 pc[tid].set(0); 147 lastCommitedSeqNum[tid] = 0; 148 } 149 interrupt = NoFault; 150} 151 152template <class Impl> 153std::string 154DefaultCommit<Impl>::name() const 155{ 156 return cpu->name() + ".commit"; 157} 158 159template <class Impl> 160void 161DefaultCommit<Impl>::regStats() 162{ 163 using namespace Stats; 164 commitCommittedInsts 165 .name(name() + ".commitCommittedInsts") 166 .desc("The number of committed instructions") 167 .prereq(commitCommittedInsts); 168 commitCommittedOps 169 .name(name() + ".commitCommittedOps") 170 .desc("The number of committed instructions") 171 .prereq(commitCommittedInsts); 172 commitSquashedInsts 173 .name(name() + ".commitSquashedInsts") 174 .desc("The number of squashed insts skipped by commit") 175 .prereq(commitSquashedInsts); 176 commitSquashEvents 177 .name(name() + ".commitSquashEvents") 178 .desc("The number of times commit is told to squash") 179 .prereq(commitSquashEvents); 180 commitNonSpecStalls 181 .name(name() + ".commitNonSpecStalls") 182 .desc("The number of times commit has been forced to stall to " 183 "communicate backwards") 184 .prereq(commitNonSpecStalls); 185 branchMispredicts 186 .name(name() + ".branchMispredicts") 187 .desc("The number of times a branch was mispredicted") 188 .prereq(branchMispredicts); 189 numCommittedDist 190 .init(0,commitWidth,1) 191 .name(name() + ".committed_per_cycle") 192 .desc("Number of insts commited each cycle") 193 .flags(Stats::pdf) 194 ; 195 196 instsCommitted 197 .init(cpu->numThreads) 198 .name(name() + ".committedInsts") 199 .desc("Number of instructions committed") 200 .flags(total) 201 ; 202 203 opsCommitted 204 .init(cpu->numThreads) 205 .name(name() + ".committedOps") 206 .desc("Number of ops (including micro ops) committed") 207 .flags(total) 208 ; 209 210 statComSwp 211 .init(cpu->numThreads) 212 .name(name() + ".swp_count") 213 .desc("Number of s/w prefetches committed") 214 .flags(total) 215 ; 216 217 statComRefs 218 .init(cpu->numThreads) 219 .name(name() + ".refs") 220 .desc("Number of memory references committed") 221 .flags(total) 222 ; 223 224 statComLoads 225 .init(cpu->numThreads) 226 .name(name() + ".loads") 227 .desc("Number of loads committed") 228 .flags(total) 229 ; 230 231 statComMembars 232 .init(cpu->numThreads) 233 .name(name() + ".membars") 234 .desc("Number of memory barriers committed") 235 .flags(total) 236 ; 237 238 statComBranches 239 .init(cpu->numThreads) 240 .name(name() + ".branches") 241 .desc("Number of branches committed") 242 .flags(total) 243 ; 244 245 statComFloating 246 .init(cpu->numThreads) 247 .name(name() + ".fp_insts") 248 .desc("Number of committed floating point instructions.") 249 .flags(total) 250 ; 251 252 statComInteger 253 .init(cpu->numThreads) 254 .name(name()+".int_insts") 255 .desc("Number of committed integer instructions.") 256 .flags(total) 257 ; 258 259 statComFunctionCalls 260 .init(cpu->numThreads) 261 .name(name()+".function_calls") 262 .desc("Number of function calls committed.") 263 .flags(total) 264 ; 265 266 commitEligible 267 .init(cpu->numThreads) 268 .name(name() + ".bw_limited") 269 .desc("number of insts not committed due to BW limits") 270 .flags(total) 271 ; 272 273 commitEligibleSamples 274 .name(name() + ".bw_lim_events") 275 .desc("number cycles where commit BW limit reached") 276 ; 277} 278 279template <class Impl> 280void 281DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 282{ 283 thread = threads; 284} 285 286template <class Impl> 287void 288DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 289{ 290 timeBuffer = tb_ptr; 291 292 // Setup wire to send information back to IEW. 293 toIEW = timeBuffer->getWire(0); 294 295 // Setup wire to read data from IEW (for the ROB). 296 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 297} 298 299template <class Impl> 300void 301DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 302{ 303 fetchQueue = fq_ptr; 304 305 // Setup wire to get instructions from rename (for the ROB). 306 fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 307} 308 309template <class Impl> 310void 311DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 312{ 313 renameQueue = rq_ptr; 314 315 // Setup wire to get instructions from rename (for the ROB). 316 fromRename = renameQueue->getWire(-renameToROBDelay); 317} 318 319template <class Impl> 320void 321DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 322{ 323 iewQueue = iq_ptr; 324 325 // Setup wire to get instructions from IEW. 326 fromIEW = iewQueue->getWire(-iewToCommitDelay); 327} 328 329template <class Impl> 330void 331DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 332{ 333 iewStage = iew_stage; 334} 335 336template<class Impl> 337void 338DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 339{ 340 activeThreads = at_ptr; 341} 342 343template <class Impl> 344void 345DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 346{ 347 for (ThreadID tid = 0; tid < numThreads; tid++) 348 renameMap[tid] = &rm_ptr[tid]; 349} 350 351template <class Impl> 352void 353DefaultCommit<Impl>::setROB(ROB *rob_ptr) 354{ 355 rob = rob_ptr; 356} 357 358template <class Impl> 359void 360DefaultCommit<Impl>::initStage() 361{ 362 rob->setActiveThreads(activeThreads); 363 rob->resetEntries(); 364 365 // Broadcast the number of free entries. 366 for (ThreadID tid = 0; tid < numThreads; tid++) { 367 toIEW->commitInfo[tid].usedROB = true; 368 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 369 toIEW->commitInfo[tid].emptyROB = true; 370 } 371 372 // Commit must broadcast the number of free entries it has at the 373 // start of the simulation, so it starts as active. 374 cpu->activateStage(O3CPU::CommitIdx); 375 376 cpu->activityThisCycle(); 377 trapLatency = cpu->ticks(trapLatency); 378} 379 380template <class Impl> 381bool 382DefaultCommit<Impl>::drain() 383{ 384 drainPending = true; 385 386 return false; 387} 388 389template <class Impl> 390void 391DefaultCommit<Impl>::switchOut() 392{ 393 switchedOut = true; 394 drainPending = false; 395 rob->switchOut(); 396} 397 398template <class Impl> 399void 400DefaultCommit<Impl>::resume() 401{ 402 drainPending = false; 403} 404 405template <class Impl> 406void 407DefaultCommit<Impl>::takeOverFrom() 408{ 409 switchedOut = false; 410 _status = Active; 411 _nextStatus = Inactive; 412 for (ThreadID tid = 0; tid < numThreads; tid++) { 413 commitStatus[tid] = Idle; 414 changedROBNumEntries[tid] = false; 415 trapSquash[tid] = false; 416 tcSquash[tid] = false; 417 } 418 squashCounter = 0; 419 rob->takeOverFrom(); 420} 421 422template <class Impl> 423void 424DefaultCommit<Impl>::updateStatus() 425{ 426 // reset ROB changed variable 427 list<ThreadID>::iterator threads = activeThreads->begin(); 428 list<ThreadID>::iterator end = activeThreads->end(); 429 430 while (threads != end) { 431 ThreadID tid = *threads++; 432 433 changedROBNumEntries[tid] = false; 434 435 // Also check if any of the threads has a trap pending 436 if (commitStatus[tid] == TrapPending || 437 commitStatus[tid] == FetchTrapPending) { 438 _nextStatus = Active; 439 } 440 } 441 442 if (_nextStatus == Inactive && _status == Active) { 443 DPRINTF(Activity, "Deactivating stage.\n"); 444 cpu->deactivateStage(O3CPU::CommitIdx); 445 } else if (_nextStatus == Active && _status == Inactive) { 446 DPRINTF(Activity, "Activating stage.\n"); 447 cpu->activateStage(O3CPU::CommitIdx); 448 } 449 450 _status = _nextStatus; 451} 452 453template <class Impl> 454void 455DefaultCommit<Impl>::setNextStatus() 456{ 457 int squashes = 0; 458 459 list<ThreadID>::iterator threads = activeThreads->begin(); 460 list<ThreadID>::iterator end = activeThreads->end(); 461 462 while (threads != end) { 463 ThreadID tid = *threads++; 464 465 if (commitStatus[tid] == ROBSquashing) { 466 squashes++; 467 } 468 } 469 470 squashCounter = squashes; 471 472 // If commit is currently squashing, then it will have activity for the 473 // next cycle. Set its next status as active. 474 if (squashCounter) { 475 _nextStatus = Active; 476 } 477} 478 479template <class Impl> 480bool 481DefaultCommit<Impl>::changedROBEntries() 482{ 483 list<ThreadID>::iterator threads = activeThreads->begin(); 484 list<ThreadID>::iterator end = activeThreads->end(); 485 486 while (threads != end) { 487 ThreadID tid = *threads++; 488 489 if (changedROBNumEntries[tid]) { 490 return true; 491 } 492 } 493 494 return false; 495} 496 497template <class Impl> 498size_t 499DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 500{ 501 return rob->numFreeEntries(tid); 502} 503 504template <class Impl> 505void 506DefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 507{ 508 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 509 510 TrapEvent *trap = new TrapEvent(this, tid); 511 512 cpu->schedule(trap, curTick() + trapLatency); 513 trapInFlight[tid] = true; 514 thread[tid]->trapPending = true; 515} 516 517template <class Impl> 518void 519DefaultCommit<Impl>::generateTCEvent(ThreadID tid) 520{ 521 assert(!trapInFlight[tid]); 522 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 523 524 tcSquash[tid] = true; 525} 526 527template <class Impl> 528void 529DefaultCommit<Impl>::squashAll(ThreadID tid) 530{ 531 // If we want to include the squashing instruction in the squash, 532 // then use one older sequence number. 533 // Hopefully this doesn't mess things up. Basically I want to squash 534 // all instructions of this thread. 535 InstSeqNum squashed_inst = rob->isEmpty() ? 536 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; 537 538 // All younger instructions will be squashed. Set the sequence 539 // number as the youngest instruction in the ROB (0 in this case. 540 // Hopefully nothing breaks.) 541 youngestSeqNum[tid] = lastCommitedSeqNum[tid]; 542 543 rob->squash(squashed_inst, tid); 544 changedROBNumEntries[tid] = true; 545 546 // Send back the sequence number of the squashed instruction. 547 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 548 549 // Send back the squash signal to tell stages that they should 550 // squash. 551 toIEW->commitInfo[tid].squash = true; 552 553 // Send back the rob squashing signal so other stages know that 554 // the ROB is in the process of squashing. 555 toIEW->commitInfo[tid].robSquashing = true; 556 557 toIEW->commitInfo[tid].mispredictInst = NULL; 558 toIEW->commitInfo[tid].squashInst = NULL; 559 560 toIEW->commitInfo[tid].pc = pc[tid]; 561} 562 563template <class Impl> 564void 565DefaultCommit<Impl>::squashFromTrap(ThreadID tid) 566{ 567 squashAll(tid); 568 569 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 570 571 thread[tid]->trapPending = false; 572 thread[tid]->inSyscall = false; 573 trapInFlight[tid] = false; 574 575 trapSquash[tid] = false; 576 577 commitStatus[tid] = ROBSquashing; 578 cpu->activityThisCycle(); 579} 580 581template <class Impl> 582void 583DefaultCommit<Impl>::squashFromTC(ThreadID tid) 584{ 585 squashAll(tid); 586 587 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 588 589 thread[tid]->inSyscall = false; 590 assert(!thread[tid]->trapPending); 591 592 commitStatus[tid] = ROBSquashing; 593 cpu->activityThisCycle(); 594 595 tcSquash[tid] = false; 596} 597 598template <class Impl> 599void 600DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst, 601 uint64_t squash_after_seq_num) 602{ 603 youngestSeqNum[tid] = squash_after_seq_num; 604 605 rob->squash(squash_after_seq_num, tid); 606 changedROBNumEntries[tid] = true; 607 608 // Send back the sequence number of the squashed instruction. 609 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num; 610 611 toIEW->commitInfo[tid].squashInst = head_inst; 612 // Send back the squash signal to tell stages that they should squash. 613 toIEW->commitInfo[tid].squash = true; 614 615 // Send back the rob squashing signal so other stages know that 616 // the ROB is in the process of squashing. 617 toIEW->commitInfo[tid].robSquashing = true; 618 619 toIEW->commitInfo[tid].mispredictInst = NULL; 620 621 toIEW->commitInfo[tid].pc = pc[tid]; 622 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 623 tid, squash_after_seq_num); 624 commitStatus[tid] = ROBSquashing; 625} 626 627template <class Impl> 628void 629DefaultCommit<Impl>::tick() 630{ 631 wroteToTimeBuffer = false; 632 _nextStatus = Inactive; 633 634 if (drainPending && cpu->instList.empty() && !iewStage->hasStoresToWB() && 635 interrupt == NoFault) { 636 cpu->signalDrained(); 637 drainPending = false; 638 return; 639 } 640 641 if (activeThreads->empty()) 642 return; 643 644 list<ThreadID>::iterator threads = activeThreads->begin(); 645 list<ThreadID>::iterator end = activeThreads->end(); 646 647 // Check if any of the threads are done squashing. Change the 648 // status if they are done. 649 while (threads != end) { 650 ThreadID tid = *threads++; 651 652 // Clear the bit saying if the thread has committed stores 653 // this cycle. 654 committedStores[tid] = false; 655 656 if (commitStatus[tid] == ROBSquashing) { 657 658 if (rob->isDoneSquashing(tid)) { 659 commitStatus[tid] = Running; 660 } else { 661 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 662 " insts this cycle.\n", tid); 663 rob->doSquash(tid); 664 toIEW->commitInfo[tid].robSquashing = true; 665 wroteToTimeBuffer = true; 666 } 667 } 668 } 669 670 commit(); 671 672 markCompletedInsts(); 673 674 threads = activeThreads->begin(); 675 676 while (threads != end) { 677 ThreadID tid = *threads++; 678 679 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 680 // The ROB has more instructions it can commit. Its next status 681 // will be active. 682 _nextStatus = Active; 683 684 DynInstPtr inst = rob->readHeadInst(tid); 685 686 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 687 " ROB and ready to commit\n", 688 tid, inst->seqNum, inst->pcState()); 689 690 } else if (!rob->isEmpty(tid)) { 691 DynInstPtr inst = rob->readHeadInst(tid); 692 693 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 694 "%s is head of ROB and not ready\n", 695 tid, inst->seqNum, inst->pcState()); 696 } 697 698 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 699 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 700 } 701 702 703 if (wroteToTimeBuffer) { 704 DPRINTF(Activity, "Activity This Cycle.\n"); 705 cpu->activityThisCycle(); 706 } 707 708 updateStatus(); 709} 710 711template <class Impl> 712void 713DefaultCommit<Impl>::handleInterrupt() 714{ 715 // Verify that we still have an interrupt to handle 716 if (!cpu->checkInterrupts(cpu->tcBase(0))) { 717 DPRINTF(Commit, "Pending interrupt is cleared by master before " 718 "it got handled. Restart fetching from the orig path.\n"); 719 toIEW->commitInfo[0].clearInterrupt = true; 720 interrupt = NoFault; 721 return; 722 } 723 724 // Wait until all in flight instructions are finished before enterring 725 // the interrupt. 726 if (canHandleInterrupts && cpu->instList.empty()) { 727 // Squash or record that I need to squash this cycle if 728 // an interrupt needed to be handled. 729 DPRINTF(Commit, "Interrupt detected.\n"); 730 731 // Clear the interrupt now that it's going to be handled 732 toIEW->commitInfo[0].clearInterrupt = true; 733 734 assert(!thread[0]->inSyscall); 735 thread[0]->inSyscall = true; 736 737 if (cpu->checker) { 738 cpu->checker->handlePendingInt(); 739 } 740 741 // CPU will handle interrupt. 742 cpu->processInterrupts(interrupt); 743 744 thread[0]->inSyscall = false; 745 746 commitStatus[0] = TrapPending; 747 748 // Generate trap squash event. 749 generateTrapEvent(0); 750 751 interrupt = NoFault; 752 } else { 753 DPRINTF(Commit, "Interrupt pending: instruction is %sin " 754 "flight, ROB is %sempty\n", 755 canHandleInterrupts ? "not " : "", 756 cpu->instList.empty() ? "" : "not " ); 757 } 758} 759 760template <class Impl> 761void 762DefaultCommit<Impl>::propagateInterrupt() 763{ 764 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 765 tcSquash[0]) 766 return; 767 768 // Process interrupts if interrupts are enabled, not in PAL 769 // mode, and no other traps or external squashes are currently 770 // pending. 771 // @todo: Allow other threads to handle interrupts. 772 773 // Get any interrupt that happened 774 interrupt = cpu->getInterrupts(); 775 776 // Tell fetch that there is an interrupt pending. This 777 // will make fetch wait until it sees a non PAL-mode PC, 778 // at which point it stops fetching instructions. 779 if (interrupt != NoFault) 780 toIEW->commitInfo[0].interruptPending = true; 781} 782 783template <class Impl> 784void 785DefaultCommit<Impl>::commit() 786{ 787 if (FullSystem) { 788 // Check if we have a interrupt and get read to handle it 789 if (cpu->checkInterrupts(cpu->tcBase(0))) 790 propagateInterrupt(); 791 } 792 793 //////////////////////////////////// 794 // Check for any possible squashes, handle them first 795 //////////////////////////////////// 796 list<ThreadID>::iterator threads = activeThreads->begin(); 797 list<ThreadID>::iterator end = activeThreads->end(); 798 799 while (threads != end) { 800 ThreadID tid = *threads++; 801 802 // Not sure which one takes priority. I think if we have 803 // both, that's a bad sign. 804 if (trapSquash[tid] == true) { 805 assert(!tcSquash[tid]); 806 squashFromTrap(tid); 807 } else if (tcSquash[tid] == true) { 808 assert(commitStatus[tid] != TrapPending); 809 squashFromTC(tid); 810 } 811 812 // Squashed sequence number must be older than youngest valid 813 // instruction in the ROB. This prevents squashes from younger 814 // instructions overriding squashes from older instructions. 815 if (fromIEW->squash[tid] && 816 commitStatus[tid] != TrapPending && 817 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 818 819 if (fromIEW->mispredictInst[tid]) { 820 DPRINTF(Commit, 821 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", 822 tid, 823 fromIEW->mispredictInst[tid]->instAddr(), 824 fromIEW->squashedSeqNum[tid]); 825 } else { 826 DPRINTF(Commit, 827 "[tid:%i]: Squashing due to order violation [sn:%i]\n", 828 tid, fromIEW->squashedSeqNum[tid]); 829 } 830 831 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 832 tid, 833 fromIEW->pc[tid].nextInstAddr()); 834 835 commitStatus[tid] = ROBSquashing; 836 837 // If we want to include the squashing instruction in the squash, 838 // then use one older sequence number. 839 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 840 841 if (fromIEW->includeSquashInst[tid] == true) { 842 squashed_inst--; 843 } 844 845 // All younger instructions will be squashed. Set the sequence 846 // number as the youngest instruction in the ROB. 847 youngestSeqNum[tid] = squashed_inst; 848 849 rob->squash(squashed_inst, tid); 850 changedROBNumEntries[tid] = true; 851 852 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 853 854 toIEW->commitInfo[tid].squash = true; 855 856 // Send back the rob squashing signal so other stages know that 857 // the ROB is in the process of squashing. 858 toIEW->commitInfo[tid].robSquashing = true; 859 860 toIEW->commitInfo[tid].mispredictInst = 861 fromIEW->mispredictInst[tid]; 862 toIEW->commitInfo[tid].branchTaken = 863 fromIEW->branchTaken[tid]; 864 toIEW->commitInfo[tid].squashInst = 865 rob->findInst(tid, squashed_inst); 866 if (toIEW->commitInfo[tid].mispredictInst) { 867 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) { 868 toIEW->commitInfo[tid].branchTaken = true; 869 } 870 } 871 872 toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 873 874 if (toIEW->commitInfo[tid].mispredictInst) { 875 ++branchMispredicts; 876 } 877 } 878 879 } 880 881 setNextStatus(); 882 883 if (squashCounter != numThreads) { 884 // If we're not currently squashing, then get instructions. 885 getInsts(); 886 887 // Try to commit any instructions. 888 commitInsts(); 889 } 890 891 //Check for any activity 892 threads = activeThreads->begin(); 893 894 while (threads != end) { 895 ThreadID tid = *threads++; 896 897 if (changedROBNumEntries[tid]) { 898 toIEW->commitInfo[tid].usedROB = true; 899 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 900 901 wroteToTimeBuffer = true; 902 changedROBNumEntries[tid] = false; 903 if (rob->isEmpty(tid)) 904 checkEmptyROB[tid] = true; 905 } 906 907 // ROB is only considered "empty" for previous stages if: a) 908 // ROB is empty, b) there are no outstanding stores, c) IEW 909 // stage has received any information regarding stores that 910 // committed. 911 // c) is checked by making sure to not consider the ROB empty 912 // on the same cycle as when stores have been committed. 913 // @todo: Make this handle multi-cycle communication between 914 // commit and IEW. 915 if (checkEmptyROB[tid] && rob->isEmpty(tid) && 916 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 917 checkEmptyROB[tid] = false; 918 toIEW->commitInfo[tid].usedROB = true; 919 toIEW->commitInfo[tid].emptyROB = true; 920 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 921 wroteToTimeBuffer = true; 922 } 923 924 } 925} 926 927template <class Impl> 928void 929DefaultCommit<Impl>::commitInsts() 930{ 931 //////////////////////////////////// 932 // Handle commit 933 // Note that commit will be handled prior to putting new 934 // instructions in the ROB so that the ROB only tries to commit 935 // instructions it has in this current cycle, and not instructions 936 // it is writing in during this cycle. Can't commit and squash 937 // things at the same time... 938 //////////////////////////////////// 939 940 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 941 942 unsigned num_committed = 0; 943 944 DynInstPtr head_inst; 945 946 // Commit as many instructions as possible until the commit bandwidth 947 // limit is reached, or it becomes impossible to commit any more. 948 while (num_committed < commitWidth) { 949 // Check for any interrupt that we've already squashed for 950 // and start processing it. 951 if (interrupt != NoFault) 952 handleInterrupt(); 953 954 int commit_thread = getCommittingThread(); 955 956 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 957 break; 958 959 head_inst = rob->readHeadInst(commit_thread); 960 961 ThreadID tid = head_inst->threadNumber; 962 963 assert(tid == commit_thread); 964 965 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 966 head_inst->seqNum, tid); 967 968 // If the head instruction is squashed, it is ready to retire 969 // (be removed from the ROB) at any time. 970 if (head_inst->isSquashed()) { 971 972 DPRINTF(Commit, "Retiring squashed instruction from " 973 "ROB.\n"); 974 975 rob->retireHead(commit_thread); 976 977 ++commitSquashedInsts; 978 979 // Record that the number of ROB entries has changed. 980 changedROBNumEntries[tid] = true; 981 } else { 982 pc[tid] = head_inst->pcState(); 983 984 // Increment the total number of non-speculative instructions 985 // executed. 986 // Hack for now: it really shouldn't happen until after the 987 // commit is deemed to be successful, but this count is needed 988 // for syscalls. 989 thread[tid]->funcExeInst++; 990 991 // Try to commit the head instruction. 992 bool commit_success = commitHead(head_inst, num_committed); 993 994 if (commit_success) { 995 ++num_committed; 996 997 changedROBNumEntries[tid] = true; 998 999 // Set the doneSeqNum to the youngest committed instruction. 1000 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 1001 1002 if (!head_inst->isMicroop() || head_inst->isLastMicroop()) 1003 ++commitCommittedInsts; 1004 ++commitCommittedOps; 1005 1006 // To match the old model, don't count nops and instruction 1007 // prefetches towards the total commit count. 1008 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 1009 cpu->instDone(tid, head_inst); 1010 } 1011 1012 if (tid == 0) { 1013 canHandleInterrupts = (!head_inst->isDelayedCommit()) && 1014 ((THE_ISA != ALPHA_ISA) || 1015 (!(pc[0].instAddr() & 0x3))); 1016 } 1017 1018 // Updates misc. registers. 1019 head_inst->updateMiscRegs(); 1020 1021 cpu->traceFunctions(pc[tid].instAddr()); 1022 1023 TheISA::advancePC(pc[tid], head_inst->staticInst); 1024 1025 // Keep track of the last sequence number commited 1026 lastCommitedSeqNum[tid] = head_inst->seqNum; 1027 1028 // If this is an instruction that doesn't play nicely with 1029 // others squash everything and restart fetch 1030 if (head_inst->isSquashAfter()) 1031 squashAfter(tid, head_inst, head_inst->seqNum); 1032 1033 int count = 0; 1034 Addr oldpc; 1035 // Debug statement. Checks to make sure we're not 1036 // currently updating state while handling PC events. 1037 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending); 1038 do { 1039 oldpc = pc[tid].instAddr(); 1040 cpu->system->pcEventQueue.service(thread[tid]->getTC()); 1041 count++; 1042 } while (oldpc != pc[tid].instAddr()); 1043 if (count > 1) { 1044 DPRINTF(Commit, 1045 "PC skip function event, stopping commit\n"); 1046 break; 1047 } 1048 } else { 1049 DPRINTF(Commit, "Unable to commit head instruction PC:%s " 1050 "[tid:%i] [sn:%i].\n", 1051 head_inst->pcState(), tid ,head_inst->seqNum); 1052 break; 1053 } 1054 } 1055 } 1056 1057 DPRINTF(CommitRate, "%i\n", num_committed); 1058 numCommittedDist.sample(num_committed); 1059 1060 if (num_committed == commitWidth) { 1061 commitEligibleSamples++; 1062 } 1063} 1064 1065template <class Impl> 1066bool 1067DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 1068{ 1069 assert(head_inst); 1070 1071 ThreadID tid = head_inst->threadNumber; 1072 1073 // If the instruction is not executed yet, then it will need extra 1074 // handling. Signal backwards that it should be executed. 1075 if (!head_inst->isExecuted()) { 1076 // Keep this number correct. We have not yet actually executed 1077 // and committed this instruction. 1078 thread[tid]->funcExeInst--; 1079 1080 if (head_inst->isNonSpeculative() || 1081 head_inst->isStoreConditional() || 1082 head_inst->isMemBarrier() || 1083 head_inst->isWriteBarrier()) { 1084 1085 DPRINTF(Commit, "Encountered a barrier or non-speculative " 1086 "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 1087 head_inst->seqNum, head_inst->pcState()); 1088 1089 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 1090 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1091 return false; 1092 } 1093 1094 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1095 1096 // Change the instruction so it won't try to commit again until 1097 // it is executed. 1098 head_inst->clearCanCommit(); 1099 1100 ++commitNonSpecStalls; 1101 1102 return false; 1103 } else if (head_inst->isLoad()) { 1104 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 1105 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1106 return false; 1107 } 1108 1109 assert(head_inst->uncacheable()); 1110 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 1111 head_inst->seqNum, head_inst->pcState()); 1112 1113 // Send back the non-speculative instruction's sequence 1114 // number. Tell the lsq to re-execute the load. 1115 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1116 toIEW->commitInfo[tid].uncached = true; 1117 toIEW->commitInfo[tid].uncachedLoad = head_inst; 1118 1119 head_inst->clearCanCommit(); 1120 1121 return false; 1122 } else { 1123 panic("Trying to commit un-executed instruction " 1124 "of unknown type!\n"); 1125 } 1126 } 1127 1128 if (head_inst->isThreadSync()) { 1129 // Not handled for now. 1130 panic("Thread sync instructions are not handled yet.\n"); 1131 } 1132 1133 // Check if the instruction caused a fault. If so, trap. 1134 Fault inst_fault = head_inst->getFault(); 1135 1136 // Stores mark themselves as completed. 1137 if (!head_inst->isStore() && inst_fault == NoFault) { 1138 head_inst->setCompleted(); 1139 } 1140 1141 // Use checker prior to updating anything due to traps or PC 1142 // based events. 1143 if (cpu->checker) { 1144 cpu->checker->verify(head_inst); 1145 } 1146 1147 if (inst_fault != NoFault) { 1148 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 1149 head_inst->seqNum, head_inst->pcState()); 1150 1151 if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 1152 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1153 return false; 1154 } 1155 1156 head_inst->setCompleted(); 1157 1158 if (cpu->checker) { 1159 // Need to check the instruction before its fault is processed 1160 cpu->checker->verify(head_inst); 1161 } 1162 1163 assert(!thread[tid]->inSyscall); 1164 1165 // Mark that we're in state update mode so that the trap's 1166 // execution doesn't generate extra squashes. 1167 thread[tid]->inSyscall = true; 1168 1169 // Execute the trap. Although it's slightly unrealistic in 1170 // terms of timing (as it doesn't wait for the full timing of 1171 // the trap event to complete before updating state), it's 1172 // needed to update the state as soon as possible. This 1173 // prevents external agents from changing any specific state 1174 // that the trap need. 1175 cpu->trap(inst_fault, tid, head_inst->staticInst); 1176 1177 // Exit state update mode to avoid accidental updating. 1178 thread[tid]->inSyscall = false; 1179 1180 commitStatus[tid] = TrapPending; 1181 1182 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", 1183 head_inst->seqNum); 1184 if (head_inst->traceData) { 1185 if (DTRACE(ExecFaulting)) { 1186 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1187 head_inst->traceData->setCPSeq(thread[tid]->numOp); 1188 head_inst->traceData->dump(); 1189 } 1190 delete head_inst->traceData; 1191 head_inst->traceData = NULL; 1192 } 1193 1194 // Generate trap squash event. 1195 generateTrapEvent(tid); 1196 return false; 1197 } 1198 1199 updateComInstStats(head_inst); 1200 1201 if (FullSystem) { 1202 if (thread[tid]->profile) { 1203 thread[tid]->profilePC = head_inst->instAddr(); 1204 ProfileNode *node = thread[tid]->profile->consume( 1205 thread[tid]->getTC(), head_inst->staticInst); 1206 1207 if (node) 1208 thread[tid]->profileNode = node; 1209 } 1210 if (CPA::available()) { 1211 if (head_inst->isControl()) { 1212 ThreadContext *tc = thread[tid]->getTC(); 1213 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 1214 } 1215 } 1216 } 1217 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", 1218 head_inst->seqNum, head_inst->pcState()); 1219 if (head_inst->traceData) { 1220 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1221 head_inst->traceData->setCPSeq(thread[tid]->numOp); 1222 head_inst->traceData->dump(); 1223 delete head_inst->traceData; 1224 head_inst->traceData = NULL; 1225 } 1226 if (head_inst->isReturn()) { 1227 DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n", 1228 head_inst->seqNum, head_inst->pcState()); 1229 } 1230 1231 // Update the commit rename map 1232 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1233 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 1234 head_inst->renamedDestRegIdx(i)); 1235 } 1236 1237 // Finally clear the head ROB entry. 1238 rob->retireHead(tid); 1239 1240#if TRACING_ON 1241 // Print info needed by the pipeline activity viewer. 1242 DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n", 1243 head_inst->fetchTick, 1244 head_inst->instAddr(), 1245 head_inst->microPC(), 1246 head_inst->seqNum, 1247 head_inst->staticInst->disassemble(head_inst->instAddr())); 1248 DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->fetchTick + head_inst->decodeTick); 1249 DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->fetchTick + head_inst->renameTick); 1250 DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->fetchTick + head_inst->dispatchTick); 1251 DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->fetchTick + head_inst->issueTick); 1252 DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->fetchTick + head_inst->completeTick); 1253 DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick()); 1254#endif 1255 1256 // If this was a store, record it for this cycle. 1257 if (head_inst->isStore()) 1258 committedStores[tid] = true; 1259 1260 // Return true to indicate that we have committed an instruction. 1261 return true; 1262} 1263 1264template <class Impl> 1265void 1266DefaultCommit<Impl>::getInsts() 1267{ 1268 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1269 1270 // Read any renamed instructions and place them into the ROB. 1271 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1272 1273 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1274 DynInstPtr inst; 1275 1276 inst = fromRename->insts[inst_num]; 1277 ThreadID tid = inst->threadNumber; 1278 1279 if (!inst->isSquashed() && 1280 commitStatus[tid] != ROBSquashing && 1281 commitStatus[tid] != TrapPending) { 1282 changedROBNumEntries[tid] = true; 1283 1284 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 1285 inst->pcState(), inst->seqNum, tid); 1286 1287 rob->insertInst(inst); 1288 1289 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1290 1291 youngestSeqNum[tid] = inst->seqNum; 1292 } else { 1293 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1294 "squashed, skipping.\n", 1295 inst->pcState(), inst->seqNum, tid); 1296 } 1297 } 1298} 1299 1300template <class Impl> 1301void 1302DefaultCommit<Impl>::skidInsert() 1303{ 1304 DPRINTF(Commit, "Attempting to any instructions from rename into " 1305 "skidBuffer.\n"); 1306 1307 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 1308 DynInstPtr inst = fromRename->insts[inst_num]; 1309 1310 if (!inst->isSquashed()) { 1311 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ", 1312 "skidBuffer.\n", inst->pcState(), inst->seqNum, 1313 inst->threadNumber); 1314 skidBuffer.push(inst); 1315 } else { 1316 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1317 "squashed, skipping.\n", 1318 inst->pcState(), inst->seqNum, inst->threadNumber); 1319 } 1320 } 1321} 1322 1323template <class Impl> 1324void 1325DefaultCommit<Impl>::markCompletedInsts() 1326{ 1327 // Grab completed insts out of the IEW instruction queue, and mark 1328 // instructions completed within the ROB. 1329 for (int inst_num = 0; 1330 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1331 ++inst_num) 1332 { 1333 if (!fromIEW->insts[inst_num]->isSquashed()) { 1334 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 1335 "within ROB.\n", 1336 fromIEW->insts[inst_num]->threadNumber, 1337 fromIEW->insts[inst_num]->pcState(), 1338 fromIEW->insts[inst_num]->seqNum); 1339 1340 // Mark the instruction as ready to commit. 1341 fromIEW->insts[inst_num]->setCanCommit(); 1342 } 1343 } 1344} 1345 1346template <class Impl> 1347bool 1348DefaultCommit<Impl>::robDoneSquashing() 1349{ 1350 list<ThreadID>::iterator threads = activeThreads->begin(); 1351 list<ThreadID>::iterator end = activeThreads->end(); 1352 1353 while (threads != end) { 1354 ThreadID tid = *threads++; 1355 1356 if (!rob->isDoneSquashing(tid)) 1357 return false; 1358 } 1359 1360 return true; 1361} 1362 1363template <class Impl> 1364void 1365DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1366{ 1367 ThreadID tid = inst->threadNumber; 1368 1369 if (!inst->isMicroop() || inst->isLastMicroop()) 1370 instsCommitted[tid]++; 1371 opsCommitted[tid]++; 1372 1373 // 1374 // Control Instructions 1375 // 1376 if (inst->isControl()) 1377 statComBranches[tid]++; 1378 1379 // 1380 // Memory references 1381 // 1382 if (inst->isMemRef()) { 1383 statComRefs[tid]++; 1384 1385 if (inst->isLoad()) { 1386 statComLoads[tid]++; 1387 } 1388 } 1389 1390 if (inst->isMemBarrier()) { 1391 statComMembars[tid]++; 1392 } 1393 1394 // Integer Instruction 1395 if (inst->isInteger()) 1396 statComInteger[tid]++; 1397 1398 // Floating Point Instruction 1399 if (inst->isFloating()) 1400 statComFloating[tid]++; 1401 1402 // Function Calls 1403 if (inst->isCall()) 1404 statComFunctionCalls[tid]++; 1405 1406} 1407 1408//////////////////////////////////////// 1409// // 1410// SMT COMMIT POLICY MAINTAINED HERE // 1411// // 1412//////////////////////////////////////// 1413template <class Impl> 1414ThreadID 1415DefaultCommit<Impl>::getCommittingThread() 1416{ 1417 if (numThreads > 1) { 1418 switch (commitPolicy) { 1419 1420 case Aggressive: 1421 //If Policy is Aggressive, commit will call 1422 //this function multiple times per 1423 //cycle 1424 return oldestReady(); 1425 1426 case RoundRobin: 1427 return roundRobin(); 1428 1429 case OldestReady: 1430 return oldestReady(); 1431 1432 default: 1433 return InvalidThreadID; 1434 } 1435 } else { 1436 assert(!activeThreads->empty()); 1437 ThreadID tid = activeThreads->front(); 1438 1439 if (commitStatus[tid] == Running || 1440 commitStatus[tid] == Idle || 1441 commitStatus[tid] == FetchTrapPending) { 1442 return tid; 1443 } else { 1444 return InvalidThreadID; 1445 } 1446 } 1447} 1448 1449template<class Impl> 1450ThreadID 1451DefaultCommit<Impl>::roundRobin() 1452{ 1453 list<ThreadID>::iterator pri_iter = priority_list.begin(); 1454 list<ThreadID>::iterator end = priority_list.end(); 1455 1456 while (pri_iter != end) { 1457 ThreadID tid = *pri_iter; 1458 1459 if (commitStatus[tid] == Running || 1460 commitStatus[tid] == Idle || 1461 commitStatus[tid] == FetchTrapPending) { 1462 1463 if (rob->isHeadReady(tid)) { 1464 priority_list.erase(pri_iter); 1465 priority_list.push_back(tid); 1466 1467 return tid; 1468 } 1469 } 1470 1471 pri_iter++; 1472 } 1473 1474 return InvalidThreadID; 1475} 1476 1477template<class Impl> 1478ThreadID 1479DefaultCommit<Impl>::oldestReady() 1480{ 1481 unsigned oldest = 0; 1482 bool first = true; 1483 1484 list<ThreadID>::iterator threads = activeThreads->begin(); 1485 list<ThreadID>::iterator end = activeThreads->end(); 1486 1487 while (threads != end) { 1488 ThreadID tid = *threads++; 1489 1490 if (!rob->isEmpty(tid) && 1491 (commitStatus[tid] == Running || 1492 commitStatus[tid] == Idle || 1493 commitStatus[tid] == FetchTrapPending)) { 1494 1495 if (rob->isHeadReady(tid)) { 1496 1497 DynInstPtr head_inst = rob->readHeadInst(tid); 1498 1499 if (first) { 1500 oldest = tid; 1501 first = false; 1502 } else if (head_inst->seqNum < oldest) { 1503 oldest = tid; 1504 } 1505 } 1506 } 1507 } 1508 1509 if (!first) { 1510 return oldest; 1511 } else { 1512 return InvalidThreadID; 1513 } 1514} 1515